diff options
Diffstat (limited to 'tests/quick/00.hello/ref')
27 files changed, 1319 insertions, 1403 deletions
diff --git a/tests/quick/00.hello/ref/alpha/linux/inorder-timing/simout b/tests/quick/00.hello/ref/alpha/linux/inorder-timing/simout index 0966923f5..c90d08af7 100755 --- a/tests/quick/00.hello/ref/alpha/linux/inorder-timing/simout +++ b/tests/quick/00.hello/ref/alpha/linux/inorder-timing/simout @@ -1,3 +1,5 @@ +Redirecting stdout to build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/inorder-timing/simout +Redirecting stderr to build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/inorder-timing/simerr M5 Simulator System Copyright (c) 2001-2008 @@ -5,13 +7,13 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Jun 25 2010 15:39:10 -M5 revision 93b1ca421839 7482 default qtip tip update_regr -M5 started Jun 25 2010 15:39:11 -M5 executing on zooks -command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/inorder-timing -re tests/run.py build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/inorder-timing +M5 compiled Aug 26 2010 11:51:59 +M5 revision 85cafc6ccb42 7662 default qtip tip sc-fail-fix +M5 started Aug 26 2010 11:52:02 +M5 executing on zizzer +command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/inorder-timing -re tests/run.py build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/inorder-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. Hello world! -Exiting @ tick 31194000 because target called exit() +Exiting @ tick 30538000 because target called exit() diff --git a/tests/quick/00.hello/ref/alpha/linux/inorder-timing/stats.txt b/tests/quick/00.hello/ref/alpha/linux/inorder-timing/stats.txt index baac829f6..9ad72b38e 100644 --- a/tests/quick/00.hello/ref/alpha/linux/inorder-timing/stats.txt +++ b/tests/quick/00.hello/ref/alpha/linux/inorder-timing/stats.txt @@ -1,13 +1,13 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 22440 # Simulator instruction rate (inst/s) -host_mem_usage 153392 # Number of bytes of host memory used -host_seconds 0.29 # Real time elapsed on the host -host_tick_rate 109185606 # Simulator tick rate (ticks/s) +host_inst_rate 4413 # Simulator instruction rate (inst/s) +host_mem_usage 204480 # Number of bytes of host memory used +host_seconds 1.45 # Real time elapsed on the host +host_tick_rate 21040041 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 6404 # Number of instructions simulated sim_seconds 0.000031 # Number of seconds simulated -sim_ticks 31194000 # Number of ticks simulated +sim_ticks 30538000 # Number of ticks simulated system.cpu.AGEN-Unit.agens 2050 # Number of Address Generations system.cpu.Branch-Predictor.BTBHitPct 29.967427 # BTB Hit Percentage system.cpu.Branch-Predictor.BTBHits 92 # Number of BTB hits @@ -27,11 +27,11 @@ system.cpu.Execution-Unit.predictedNotTakenIncorrect 523 system.cpu.Execution-Unit.predictedTakenIncorrect 6 # Number of Branches Incorrectly Predicted As Taken. system.cpu.Mult-Div-Unit.divides 0 # Number of Divide Operations Executed system.cpu.Mult-Div-Unit.multiplies 1 # Number of Multipy Operations Executed -system.cpu.RegFile-Manager.regFileAccesses 12569 # Number of Total Accesses (Read+Write) to the Register File -system.cpu.RegFile-Manager.regFileReads 7986 # Number of Reads from Register File +system.cpu.RegFile-Manager.regFileAccesses 12573 # Number of Total Accesses (Read+Write) to the Register File +system.cpu.RegFile-Manager.regFileReads 7990 # Number of Reads from Register File system.cpu.RegFile-Manager.regFileWrites 4583 # Number of Writes to Register File -system.cpu.RegFile-Manager.regForwards 315 # Number of Registers Read Through Forwarding Logic -system.cpu.activity 21.904502 # Percentage of cycles cpu is active +system.cpu.RegFile-Manager.regForwards 311 # Number of Registers Read Through Forwarding Logic +system.cpu.activity 22.376672 # Percentage of cycles cpu is active system.cpu.comBranches 1051 # Number of Branches instructions committed system.cpu.comFloats 2 # Number of Floating Point instructions committed system.cpu.comInts 3265 # Number of Integer instructions committed @@ -42,8 +42,8 @@ system.cpu.comStores 865 # Nu system.cpu.committedInsts 6404 # Number of Instructions Simulated (Per-Thread) system.cpu.committedInsts_total 6404 # Number of Instructions Simulated (Total) system.cpu.contextSwitches 1 # Number of context switches -system.cpu.cpi 9.742192 # CPI: Cycles Per Instruction (Per-Thread) -system.cpu.cpi_total 9.742192 # CPI: Total CPI of All Threads +system.cpu.cpi 9.537320 # CPI: Cycles Per Instruction (Per-Thread) +system.cpu.cpi_total 9.537320 # CPI: Total CPI of All Threads system.cpu.dcache.ReadReq_accesses 1185 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_avg_miss_latency 56384.210526 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency 53384.210526 # average ReadReq mshr miss latency @@ -55,15 +55,15 @@ system.cpu.dcache.ReadReq_mshr_miss_latency 5071500 # system.cpu.dcache.ReadReq_mshr_miss_rate 0.080169 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_misses 95 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 865 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 56068.965517 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53068.965517 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 778 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 4878000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.100578 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 87 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_miss_latency 4617000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.100578 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 87 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_avg_miss_latency 56068.493151 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53068.493151 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 792 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 4093000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.084393 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 73 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_miss_latency 3874000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate 0.084393 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses 73 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.dcache.avg_refs 11.202381 # Average number of references to valid blocks. @@ -73,39 +73,39 @@ system.cpu.dcache.blocked_cycles::no_mshrs 0 # system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.demand_accesses 2050 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 56233.516484 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 53233.516484 # average overall mshr miss latency -system.cpu.dcache.demand_hits 1868 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 10234500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.088780 # miss rate for demand accesses -system.cpu.dcache.demand_misses 182 # number of demand (read+write) misses +system.cpu.dcache.demand_avg_miss_latency 56247.023810 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 53247.023810 # average overall mshr miss latency +system.cpu.dcache.demand_hits 1882 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 9449500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.081951 # miss rate for demand accesses +system.cpu.dcache.demand_misses 168 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 9688500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.088780 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 182 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_miss_latency 8945500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.081951 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 168 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_%::0 0.025297 # Average percentage of cache occupancy -system.cpu.dcache.occ_blocks::0 103.617621 # Average occupied blocks per context +system.cpu.dcache.occ_%::0 0.025183 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::0 103.151125 # Average occupied blocks per context system.cpu.dcache.overall_accesses 2050 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 56233.516484 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 53233.516484 # average overall mshr miss latency +system.cpu.dcache.overall_avg_miss_latency 56247.023810 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 53247.023810 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 1868 # number of overall hits -system.cpu.dcache.overall_miss_latency 10234500 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.088780 # miss rate for overall accesses -system.cpu.dcache.overall_misses 182 # number of overall misses +system.cpu.dcache.overall_hits 1882 # number of overall hits +system.cpu.dcache.overall_miss_latency 9449500 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.081951 # miss rate for overall accesses +system.cpu.dcache.overall_misses 168 # number of overall misses system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 9688500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.088780 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 182 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_miss_latency 8945500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.081951 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 168 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.sampled_refs 168 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 103.617621 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 103.151125 # Cycle average of tags in use system.cpu.dcache.total_refs 1882 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 0 # number of writebacks @@ -126,14 +126,14 @@ system.cpu.dtb.write_acv 0 # DT system.cpu.dtb.write_hits 865 # DTB write hits system.cpu.dtb.write_misses 3 # DTB write misses system.cpu.icache.ReadReq_accesses 7169 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 55706.484642 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 52877.192982 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_miss_latency 55703.071672 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 52873.684211 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_hits 6876 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 16322000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency 16321000 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_rate 0.040870 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_misses 293 # number of ReadReq misses system.cpu.icache.ReadReq_mshr_hits 8 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 15070000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 15069000 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.039754 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_misses 285 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked @@ -145,31 +145,31 @@ system.cpu.icache.blocked_cycles::no_mshrs 0 # system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.demand_accesses 7169 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 55706.484642 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 52877.192982 # average overall mshr miss latency +system.cpu.icache.demand_avg_miss_latency 55703.071672 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 52873.684211 # average overall mshr miss latency system.cpu.icache.demand_hits 6876 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 16322000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency 16321000 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_rate 0.040870 # miss rate for demand accesses system.cpu.icache.demand_misses 293 # number of demand (read+write) misses system.cpu.icache.demand_mshr_hits 8 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 15070000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 15069000 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_rate 0.039754 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_misses 285 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_%::0 0.063594 # Average percentage of cache occupancy -system.cpu.icache.occ_blocks::0 130.240724 # Average occupied blocks per context +system.cpu.icache.occ_%::0 0.063218 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::0 129.469682 # Average occupied blocks per context system.cpu.icache.overall_accesses 7169 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 55706.484642 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 52877.192982 # average overall mshr miss latency +system.cpu.icache.overall_avg_miss_latency 55703.071672 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 52873.684211 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.icache.overall_hits 6876 # number of overall hits -system.cpu.icache.overall_miss_latency 16322000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency 16321000 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.040870 # miss rate for overall accesses system.cpu.icache.overall_misses 293 # number of overall misses system.cpu.icache.overall_mshr_hits 8 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 15070000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 15069000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_rate 0.039754 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_misses 285 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -177,13 +177,13 @@ system.cpu.icache.overall_mshr_uncacheable_misses 0 system.cpu.icache.replacements 0 # number of replacements system.cpu.icache.sampled_refs 284 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 130.240724 # Cycle average of tags in use +system.cpu.icache.tagsinuse 129.469682 # Cycle average of tags in use system.cpu.icache.total_refs 6876 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idleCycles 48723 # Number of cycles cpu's stages were not processed -system.cpu.ipc 0.102646 # IPC: Instructions Per Cycle (Per-Thread) -system.cpu.ipc_total 0.102646 # IPC: Total IPC of All Threads +system.cpu.idleCycles 47410 # Number of cycles cpu's stages were not processed +system.cpu.ipc 0.104851 # IPC: Instructions Per Cycle (Per-Thread) +system.cpu.ipc_total 0.104851 # IPC: Total IPC of All Threads system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_hits 0 # DTB hits @@ -201,36 +201,27 @@ system.cpu.itb.write_acv 0 # DT system.cpu.itb.write_hits 0 # DTB write hits system.cpu.itb.write_misses 0 # DTB write misses system.cpu.l2cache.ReadExReq_accesses 73 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency 52075.342466 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency 52068.493151 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40013.698630 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_miss_latency 3801500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency 3801000 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_misses 73 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_mshr_miss_latency 2921000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_misses 73 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadReq_accesses 380 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 52085.751979 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency 52087.071240 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 39947.229551 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_hits 1 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 19740500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency 19741000 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_rate 0.997368 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_misses 379 # number of ReadReq misses system.cpu.l2cache.ReadReq_mshr_miss_latency 15140000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate 0.997368 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_misses 379 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_accesses 14 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_avg_miss_latency 52035.714286 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_miss_latency 728500 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_misses 14 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_mshr_miss_latency 560000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_misses 14 # number of UpgradeReq MSHR misses system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 0.002747 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 0.002646 # Average number of references to valid blocks. system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked @@ -250,8 +241,8 @@ system.cpu.l2cache.demand_mshr_misses 452 # nu system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.occ_%::0 0.005535 # Average percentage of cache occupancy -system.cpu.l2cache.occ_blocks::0 181.374052 # Average occupied blocks per context +system.cpu.l2cache.occ_%::0 0.005668 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::0 185.735123 # Average occupied blocks per context system.cpu.l2cache.overall_accesses 453 # number of overall (read+write) accesses system.cpu.l2cache.overall_avg_miss_latency 52084.070796 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 39957.964602 # average overall mshr miss latency @@ -267,34 +258,34 @@ system.cpu.l2cache.overall_mshr_misses 452 # nu system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.sampled_refs 364 # Sample count of references to valid blocks. +system.cpu.l2cache.sampled_refs 378 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 181.374052 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 185.735123 # Cycle average of tags in use system.cpu.l2cache.total_refs 1 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks -system.cpu.numCycles 62389 # number of cpu cycles simulated -system.cpu.runCycles 13666 # Number of cycles cpu stages are processed. +system.cpu.numCycles 61077 # number of cpu cycles simulated +system.cpu.runCycles 13667 # Number of cycles cpu stages are processed. system.cpu.smtCommittedInsts 0 # Number of SMT Instructions Simulated (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode system.cpu.smt_cpi no_value # CPI: Total SMT-CPI system.cpu.smt_ipc no_value # IPC: Total SMT-IPC -system.cpu.stage-0.idleCycles 55203 # Number of cycles 0 instructions are processed. +system.cpu.stage-0.idleCycles 53891 # Number of cycles 0 instructions are processed. system.cpu.stage-0.runCycles 7186 # Number of cycles 1+ instructions are processed. -system.cpu.stage-0.utilization 11.518056 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage-1.idleCycles 55836 # Number of cycles 0 instructions are processed. -system.cpu.stage-1.runCycles 6553 # Number of cycles 1+ instructions are processed. -system.cpu.stage-1.utilization 10.503454 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage-2.idleCycles 55919 # Number of cycles 0 instructions are processed. +system.cpu.stage-0.utilization 11.765476 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage-1.idleCycles 54525 # Number of cycles 0 instructions are processed. +system.cpu.stage-1.runCycles 6552 # Number of cycles 1+ instructions are processed. +system.cpu.stage-1.utilization 10.727442 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage-2.idleCycles 54607 # Number of cycles 0 instructions are processed. system.cpu.stage-2.runCycles 6470 # Number of cycles 1+ instructions are processed. -system.cpu.stage-2.utilization 10.370418 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage-3.idleCycles 60336 # Number of cycles 0 instructions are processed. +system.cpu.stage-2.utilization 10.593186 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage-3.idleCycles 59024 # Number of cycles 0 instructions are processed. system.cpu.stage-3.runCycles 2053 # Number of cycles 1+ instructions are processed. -system.cpu.stage-3.utilization 3.290644 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage-4.idleCycles 55985 # Number of cycles 0 instructions are processed. +system.cpu.stage-3.utilization 3.361331 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage-4.idleCycles 54673 # Number of cycles 0 instructions are processed. system.cpu.stage-4.runCycles 6404 # Number of cycles 1+ instructions are processed. -system.cpu.stage-4.utilization 10.264630 # Percentage of cycles stage was utilized (processing insts). -system.cpu.threadCycles 62389 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.stage-4.utilization 10.485125 # Percentage of cycles stage was utilized (processing insts). +system.cpu.threadCycles 61077 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.workload.PROG:num_syscalls 17 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/quick/00.hello/ref/alpha/linux/o3-timing/simout b/tests/quick/00.hello/ref/alpha/linux/o3-timing/simout index 4261d2ba3..63bbf8869 100755 --- a/tests/quick/00.hello/ref/alpha/linux/o3-timing/simout +++ b/tests/quick/00.hello/ref/alpha/linux/o3-timing/simout @@ -1,5 +1,5 @@ -Redirecting stdout to build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/o3-timing/simout -Redirecting stderr to build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/o3-timing/simerr +Redirecting stdout to build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/o3-timing/simout +Redirecting stderr to build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/o3-timing/simerr M5 Simulator System Copyright (c) 2001-2008 @@ -7,13 +7,13 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Jun 6 2010 03:04:38 -M5 revision ba1a0193c050 7448 default tip -M5 started Jun 6 2010 03:09:06 +M5 compiled Aug 26 2010 11:51:59 +M5 revision 85cafc6ccb42 7662 default qtip tip sc-fail-fix +M5 started Aug 26 2010 11:52:04 M5 executing on zizzer -command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/o3-timing -re tests/run.py build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/o3-timing +command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/o3-timing -re tests/run.py build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. Hello world! -Exiting @ tick 12497500 because target called exit() +Exiting @ tick 12412500 because target called exit() diff --git a/tests/quick/00.hello/ref/alpha/linux/o3-timing/stats.txt b/tests/quick/00.hello/ref/alpha/linux/o3-timing/stats.txt index fd2b0ddaf..a57aece07 100644 --- a/tests/quick/00.hello/ref/alpha/linux/o3-timing/stats.txt +++ b/tests/quick/00.hello/ref/alpha/linux/o3-timing/stats.txt @@ -1,41 +1,41 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 80384 # Simulator instruction rate (inst/s) -host_mem_usage 204420 # Number of bytes of host memory used -host_seconds 0.08 # Real time elapsed on the host -host_tick_rate 156814646 # Simulator tick rate (ticks/s) +host_inst_rate 44712 # Simulator instruction rate (inst/s) +host_mem_usage 204968 # Number of bytes of host memory used +host_seconds 0.14 # Real time elapsed on the host +host_tick_rate 86758837 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 6386 # Number of instructions simulated sim_seconds 0.000012 # Number of seconds simulated -sim_ticks 12497500 # Number of ticks simulated +sim_ticks 12412500 # Number of ticks simulated system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.BTBHits 692 # Number of BTB hits -system.cpu.BPredUnit.BTBLookups 1820 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 680 # Number of BTB hits +system.cpu.BPredUnit.BTBLookups 1800 # Number of BTB lookups system.cpu.BPredUnit.RASInCorrect 65 # Number of incorrect RAS predictions. system.cpu.BPredUnit.condIncorrect 443 # Number of conditional branches incorrect -system.cpu.BPredUnit.condPredicted 1337 # Number of conditional branches predicted -system.cpu.BPredUnit.lookups 2245 # Number of BP lookups -system.cpu.BPredUnit.usedRAS 315 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.condPredicted 1320 # Number of conditional branches predicted +system.cpu.BPredUnit.lookups 2222 # Number of BP lookups +system.cpu.BPredUnit.usedRAS 313 # Number of times the RAS was used to get a target. system.cpu.commit.COM:branches 1051 # Number of branches committed -system.cpu.commit.COM:bw_lim_events 119 # number cycles where commit BW limit reached +system.cpu.commit.COM:bw_lim_events 117 # number cycles where commit BW limit reached system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits -system.cpu.commit.COM:committed_per_cycle::samples 12431 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::mean 0.515083 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::stdev 1.305811 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::samples 12265 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::mean 0.522055 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::stdev 1.306636 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::0 9528 76.65% 76.65% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::1 1629 13.10% 89.75% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::2 491 3.95% 93.70% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::3 259 2.08% 95.78% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::4 156 1.25% 97.04% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::5 104 0.84% 97.88% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::6 96 0.77% 98.65% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::7 49 0.39% 99.04% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::8 119 0.96% 100.00% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::0 9355 76.27% 76.27% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::1 1631 13.30% 89.57% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::2 489 3.99% 93.56% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::3 266 2.17% 95.73% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::4 144 1.17% 96.90% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::5 131 1.07% 97.97% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::6 95 0.77% 98.74% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::7 37 0.30% 99.05% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::8 117 0.95% 100.00% # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::total 12431 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::total 12265 # Number of insts commited each cycle system.cpu.commit.COM:count 6403 # Number of instructions committed system.cpu.commit.COM:loads 1185 # Number of loads committed system.cpu.commit.COM:membars 0 # Number of memory barriers committed @@ -44,295 +44,295 @@ system.cpu.commit.COM:swp_count 0 # Nu system.cpu.commit.branchMispredicts 369 # The number of times a branch was mispredicted system.cpu.commit.commitCommittedInsts 6403 # The number of committed instructions system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 4622 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 4518 # The number of squashed insts skipped by commit system.cpu.committedInsts 6386 # Number of Instructions Simulated system.cpu.committedInsts_total 6386 # Number of Instructions Simulated -system.cpu.cpi 3.914187 # CPI: Cycles Per Instruction -system.cpu.cpi_total 3.914187 # CPI: Total CPI of All Threads -system.cpu.dcache.ReadReq_accesses 1782 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 34993.902439 # average ReadReq miss latency +system.cpu.cpi 3.887567 # CPI: Cycles Per Instruction +system.cpu.cpi_total 3.887567 # CPI: Total CPI of All Threads +system.cpu.dcache.ReadReq_accesses 1765 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 35761.146497 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency 36257.425743 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 1618 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 5739000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.092031 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 164 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits 63 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_hits 1608 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 5614500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.088952 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 157 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_hits 56 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_miss_latency 3662000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.056678 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate 0.057224 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_misses 101 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 865 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 35082.894737 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35729.885057 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 485 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 13331500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.439306 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 380 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_hits 293 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency 3108500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.100578 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 87 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_avg_miss_latency 34971.751412 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35815.068493 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 511 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 12380000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.409249 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 354 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_hits 281 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_miss_latency 2614500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate 0.084393 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses 73 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 12.275862 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 12.178161 # Average number of references to valid blocks. system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 2647 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 35056.066176 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 36013.297872 # average overall mshr miss latency -system.cpu.dcache.demand_hits 2103 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 19070500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.205516 # miss rate for demand accesses -system.cpu.dcache.demand_misses 544 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 356 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 6770500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.071024 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 188 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_accesses 2630 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 35214.285714 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 36071.839080 # average overall mshr miss latency +system.cpu.dcache.demand_hits 2119 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 17994500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.194297 # miss rate for demand accesses +system.cpu.dcache.demand_misses 511 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 337 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 6276500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.066160 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 174 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.occ_%::0 0.026868 # Average percentage of cache occupancy -system.cpu.dcache.occ_blocks::0 110.050975 # Average occupied blocks per context -system.cpu.dcache.overall_accesses 2647 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 35056.066176 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 36013.297872 # average overall mshr miss latency +system.cpu.dcache.occ_blocks::0 110.049713 # Average occupied blocks per context +system.cpu.dcache.overall_accesses 2630 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 35214.285714 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 36071.839080 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 2103 # number of overall hits -system.cpu.dcache.overall_miss_latency 19070500 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.205516 # miss rate for overall accesses -system.cpu.dcache.overall_misses 544 # number of overall misses -system.cpu.dcache.overall_mshr_hits 356 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 6770500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.071024 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 188 # number of overall MSHR misses +system.cpu.dcache.overall_hits 2119 # number of overall hits +system.cpu.dcache.overall_miss_latency 17994500 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.194297 # miss rate for overall accesses +system.cpu.dcache.overall_misses 511 # number of overall misses +system.cpu.dcache.overall_mshr_hits 337 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 6276500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.066160 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 174 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.sampled_refs 174 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 110.050975 # Cycle average of tags in use -system.cpu.dcache.total_refs 2136 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 110.049713 # Cycle average of tags in use +system.cpu.dcache.total_refs 2119 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 0 # number of writebacks -system.cpu.decode.DECODE:BlockedCycles 1123 # Number of cycles decode is blocked +system.cpu.decode.DECODE:BlockedCycles 1016 # Number of cycles decode is blocked system.cpu.decode.DECODE:BranchMispred 75 # Number of times decode detected a branch misprediction -system.cpu.decode.DECODE:BranchResolved 188 # Number of times decode resolved a branch -system.cpu.decode.DECODE:DecodedInsts 12474 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 8945 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 2313 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 900 # Number of cycles decode is squashing +system.cpu.decode.DECODE:BranchResolved 185 # Number of times decode resolved a branch +system.cpu.decode.DECODE:DecodedInsts 12350 # Number of instructions handled by decode +system.cpu.decode.DECODE:IdleCycles 8913 # Number of cycles decode is idle +system.cpu.decode.DECODE:RunCycles 2277 # Number of cycles decode is running +system.cpu.decode.DECODE:SquashCycles 884 # Number of cycles decode is squashing system.cpu.decode.DECODE:SquashedInsts 209 # Number of squashed instructions handled by decode -system.cpu.decode.DECODE:UnblockCycles 50 # Number of cycles decode is unblocking -system.cpu.dtb.data_accesses 2948 # DTB accesses +system.cpu.decode.DECODE:UnblockCycles 59 # Number of cycles decode is unblocking +system.cpu.dtb.data_accesses 2921 # DTB accesses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_hits 2887 # DTB hits +system.cpu.dtb.data_hits 2860 # DTB hits system.cpu.dtb.data_misses 61 # DTB misses system.cpu.dtb.fetch_accesses 0 # ITB accesses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses -system.cpu.dtb.read_accesses 1865 # DTB read accesses +system.cpu.dtb.read_accesses 1845 # DTB read accesses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_hits 1829 # DTB read hits +system.cpu.dtb.read_hits 1809 # DTB read hits system.cpu.dtb.read_misses 36 # DTB read misses -system.cpu.dtb.write_accesses 1083 # DTB write accesses +system.cpu.dtb.write_accesses 1076 # DTB write accesses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_hits 1058 # DTB write hits +system.cpu.dtb.write_hits 1051 # DTB write hits system.cpu.dtb.write_misses 25 # DTB write misses -system.cpu.fetch.Branches 2245 # Number of branches that fetch encountered -system.cpu.fetch.CacheLines 1792 # Number of cache lines fetched -system.cpu.fetch.Cycles 4238 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.IcacheSquashes 269 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.Insts 13309 # Number of instructions fetch has processed -system.cpu.fetch.SquashCycles 504 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.089814 # Number of branch fetches per cycle -system.cpu.fetch.icacheStallCycles 1792 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.predictedBranches 1007 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 0.532445 # Number of inst fetches per cycle -system.cpu.fetch.rateDist::samples 13331 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.998350 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.390717 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.Branches 2222 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 1774 # Number of cache lines fetched +system.cpu.fetch.Cycles 4193 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 267 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.Insts 13186 # Number of instructions fetch has processed +system.cpu.fetch.SquashCycles 503 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.089503 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 1774 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 993 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 0.531137 # Number of inst fetches per cycle +system.cpu.fetch.rateDist::samples 13149 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.002814 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.396074 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 10920 81.91% 81.91% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 245 1.84% 83.75% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 221 1.66% 85.41% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 185 1.39% 86.80% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 233 1.75% 88.55% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 164 1.23% 89.78% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 228 1.71% 91.49% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 133 1.00% 92.48% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 1002 7.52% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 10764 81.86% 81.86% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 240 1.83% 83.69% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 218 1.66% 85.34% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 183 1.39% 86.74% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 231 1.76% 88.49% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 163 1.24% 89.73% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 224 1.70% 91.44% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 130 0.99% 92.43% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 996 7.57% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 13331 # Number of instructions fetched each cycle (Total) -system.cpu.icache.ReadReq_accesses 1792 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 35303.990610 # average ReadReq miss latency +system.cpu.fetch.rateDist::total 13149 # Number of instructions fetched each cycle (Total) +system.cpu.icache.ReadReq_accesses 1774 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 35292.253521 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency 35283.387622 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 1366 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 15039500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.237723 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_hits 1348 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 15034500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.240135 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_misses 426 # number of ReadReq misses system.cpu.icache.ReadReq_mshr_hits 119 # number of ReadReq MSHR hits system.cpu.icache.ReadReq_mshr_miss_latency 10832000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.171317 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate 0.173055 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_misses 307 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.icache.avg_refs 4.449511 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 4.390879 # Average number of references to valid blocks. system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 1792 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 35303.990610 # average overall miss latency +system.cpu.icache.demand_accesses 1774 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 35292.253521 # average overall miss latency system.cpu.icache.demand_avg_mshr_miss_latency 35283.387622 # average overall mshr miss latency -system.cpu.icache.demand_hits 1366 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 15039500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.237723 # miss rate for demand accesses +system.cpu.icache.demand_hits 1348 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 15034500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.240135 # miss rate for demand accesses system.cpu.icache.demand_misses 426 # number of demand (read+write) misses system.cpu.icache.demand_mshr_hits 119 # number of demand (read+write) MSHR hits system.cpu.icache.demand_mshr_miss_latency 10832000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.171317 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate 0.173055 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_misses 307 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_%::0 0.077094 # Average percentage of cache occupancy -system.cpu.icache.occ_blocks::0 157.888110 # Average occupied blocks per context -system.cpu.icache.overall_accesses 1792 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 35303.990610 # average overall miss latency +system.cpu.icache.occ_%::0 0.077067 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::0 157.832479 # Average occupied blocks per context +system.cpu.icache.overall_accesses 1774 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 35292.253521 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 35283.387622 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 1366 # number of overall hits -system.cpu.icache.overall_miss_latency 15039500 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.237723 # miss rate for overall accesses +system.cpu.icache.overall_hits 1348 # number of overall hits +system.cpu.icache.overall_miss_latency 15034500 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.240135 # miss rate for overall accesses system.cpu.icache.overall_misses 426 # number of overall misses system.cpu.icache.overall_mshr_hits 119 # number of overall MSHR hits system.cpu.icache.overall_mshr_miss_latency 10832000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.171317 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate 0.173055 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_misses 307 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.icache.replacements 0 # number of replacements system.cpu.icache.sampled_refs 307 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 157.888110 # Cycle average of tags in use -system.cpu.icache.total_refs 1366 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 157.832479 # Cycle average of tags in use +system.cpu.icache.total_refs 1348 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idleCycles 11665 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.EXEC:branches 1448 # Number of branches executed -system.cpu.iew.EXEC:nop 83 # number of nop insts executed -system.cpu.iew.EXEC:rate 0.362498 # Inst execution rate -system.cpu.iew.EXEC:refs 2956 # number of memory reference insts executed -system.cpu.iew.EXEC:stores 1085 # Number of stores executed +system.cpu.idleCycles 11677 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.EXEC:branches 1435 # Number of branches executed +system.cpu.iew.EXEC:nop 82 # number of nop insts executed +system.cpu.iew.EXEC:rate 0.361798 # Inst execution rate +system.cpu.iew.EXEC:refs 2929 # number of memory reference insts executed +system.cpu.iew.EXEC:stores 1078 # Number of stores executed system.cpu.iew.EXEC:swp 0 # number of swp insts executed -system.cpu.iew.WB:consumers 6049 # num instructions consuming a value -system.cpu.iew.WB:count 8759 # cumulative count of insts written-back -system.cpu.iew.WB:fanout 0.745247 # average fanout of values written-back +system.cpu.iew.WB:consumers 6007 # num instructions consuming a value +system.cpu.iew.WB:count 8682 # cumulative count of insts written-back +system.cpu.iew.WB:fanout 0.744798 # average fanout of values written-back system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 4508 # num instructions producing a value -system.cpu.iew.WB:rate 0.350416 # insts written-back per cycle -system.cpu.iew.WB:sent 8858 # cumulative count of insts sent to commit -system.cpu.iew.branchMispredicts 427 # Number of branch mispredicts detected at execute -system.cpu.iew.iewBlockCycles 73 # Number of cycles IEW is blocking -system.cpu.iew.iewDispLoadInsts 2269 # Number of dispatched load instructions +system.cpu.iew.WB:producers 4474 # num instructions producing a value +system.cpu.iew.WB:rate 0.349714 # insts written-back per cycle +system.cpu.iew.WB:sent 8783 # cumulative count of insts sent to commit +system.cpu.iew.branchMispredicts 428 # Number of branch mispredicts detected at execute +system.cpu.iew.iewBlockCycles 63 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 2242 # Number of dispatched load instructions system.cpu.iew.iewDispNonSpecInsts 25 # Number of dispatched non-speculative instructions -system.cpu.iew.iewDispSquashedInsts 191 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispStoreInsts 1271 # Number of dispatched store instructions -system.cpu.iew.iewDispatchedInsts 11059 # Number of instructions dispatched to IQ -system.cpu.iew.iewExecLoadInsts 1871 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 304 # Number of squashed instructions skipped in execute -system.cpu.iew.iewExecutedInsts 9061 # Number of executed instructions +system.cpu.iew.iewDispSquashedInsts 193 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 1259 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 10955 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 1851 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 291 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 8982 # Number of executed instructions system.cpu.iew.iewIQFullEvents 7 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.iewSquashCycles 900 # Number of cycles IEW is squashing -system.cpu.iew.iewUnblockCycles 11 # Number of cycles IEW is unblocking +system.cpu.iew.iewSquashCycles 884 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 9 # Number of cycles IEW is unblocking system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread.0.forwLoads 46 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread.0.forwLoads 43 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread.0.ignoredResponses 6 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.0.memOrderViolation 64 # Number of memory ordering violations +system.cpu.iew.lsq.thread.0.memOrderViolation 63 # Number of memory ordering violations system.cpu.iew.lsq.thread.0.rescheduledLoads 1 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 1084 # Number of loads squashed -system.cpu.iew.lsq.thread.0.squashedStores 406 # Number of stores squashed -system.cpu.iew.memOrderViolationEvents 64 # Number of memory order violations -system.cpu.iew.predictedNotTakenIncorrect 302 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.lsq.thread.0.squashedLoads 1057 # Number of loads squashed +system.cpu.iew.lsq.thread.0.squashedStores 394 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 63 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 303 # Number of branches that were predicted not taken incorrectly system.cpu.iew.predictedTakenIncorrect 125 # Number of branches that were predicted taken incorrectly -system.cpu.ipc 0.255481 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.255481 # IPC: Total IPC of All Threads +system.cpu.ipc 0.257230 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.257230 # IPC: Total IPC of All Threads system.cpu.iq.ISSUE:FU_type_0::No_OpClass 2 0.02% 0.02% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntAlu 6287 67.13% 67.15% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntMult 1 0.01% 67.16% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 67.16% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatAdd 2 0.02% 67.19% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 67.19% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 67.19% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 67.19% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 67.19% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 67.19% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::MemRead 1968 21.01% 88.20% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::MemWrite 1105 11.80% 100.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntAlu 6230 67.18% 67.21% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntMult 1 0.01% 67.22% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 67.22% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatAdd 2 0.02% 67.24% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 67.24% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 67.24% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 67.24% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 67.24% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 67.24% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::MemRead 1943 20.95% 88.19% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::MemWrite 1095 11.81% 100.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::total 9365 # Type of FU issued -system.cpu.iq.ISSUE:fu_busy_cnt 92 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_rate 0.009824 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:FU_type_0::total 9273 # Type of FU issued +system.cpu.iq.ISSUE:fu_busy_cnt 91 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_rate 0.009813 # FU busy rate (busy events/executed inst) system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntAlu 1 1.09% 1.09% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 1.09% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 1.09% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 1.09% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 1.09% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 1.09% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 1.09% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 1.09% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 1.09% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::MemRead 56 60.87% 61.96% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::MemWrite 35 38.04% 100.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntAlu 1 1.10% 1.10% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 1.10% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 1.10% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 1.10% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 1.10% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 1.10% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 1.10% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 1.10% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 1.10% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::MemRead 55 60.44% 61.54% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::MemWrite 35 38.46% 100.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:issued_per_cycle::samples 13331 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::mean 0.702498 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.304735 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::samples 13149 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::mean 0.705225 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.302669 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::0 9142 68.58% 68.58% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::1 1697 12.73% 81.31% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::2 1062 7.97% 89.27% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::3 730 5.48% 94.75% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::4 359 2.69% 97.44% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::5 188 1.41% 98.85% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::6 105 0.79% 99.64% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::7 36 0.27% 99.91% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::0 8989 68.36% 68.36% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::1 1668 12.69% 81.05% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::2 1105 8.40% 89.45% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::3 696 5.29% 94.74% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::4 356 2.71% 97.45% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::5 185 1.41% 98.86% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::6 104 0.79% 99.65% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::7 34 0.26% 99.91% # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::8 12 0.09% 100.00% # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::total 13331 # Number of insts issued each cycle -system.cpu.iq.ISSUE:rate 0.374660 # Inst issue rate -system.cpu.iq.iqInstsAdded 10951 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 9365 # Number of instructions issued +system.cpu.iq.ISSUE:issued_per_cycle::total 13149 # Number of insts issued each cycle +system.cpu.iq.ISSUE:rate 0.373520 # Inst issue rate +system.cpu.iq.iqInstsAdded 10848 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 9273 # Number of instructions issued system.cpu.iq.iqNonSpecInstsAdded 25 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 4181 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedInstsIssued 44 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 4076 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 42 # Number of squashed instructions issued system.cpu.iq.iqSquashedNonSpecRemoved 8 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 2504 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedOperandsExamined 2476 # Number of squashed operands that are examined and possibly removed from graph system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_hits 0 # DTB hits system.cpu.itb.data_misses 0 # DTB misses -system.cpu.itb.fetch_accesses 1827 # ITB accesses +system.cpu.itb.fetch_accesses 1808 # ITB accesses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_hits 1792 # ITB hits -system.cpu.itb.fetch_misses 35 # ITB misses +system.cpu.itb.fetch_hits 1774 # ITB hits +system.cpu.itb.fetch_misses 34 # ITB misses system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.read_acv 0 # DTB read access violations system.cpu.itb.read_hits 0 # DTB read hits @@ -342,100 +342,91 @@ system.cpu.itb.write_acv 0 # DT system.cpu.itb.write_hits 0 # DTB write hits system.cpu.itb.write_misses 0 # DTB write misses system.cpu.l2cache.ReadExReq_accesses 73 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency 34465.753425 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31376.712329 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_miss_latency 2516000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_avg_miss_latency 34506.849315 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31424.657534 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_miss_latency 2519000 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_misses 73 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 2290500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency 2294000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_misses 73 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadReq_accesses 408 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 34418.918919 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31239.557740 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency 34420.147420 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31243.243243 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_hits 1 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 14008500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency 14009000 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_rate 0.997549 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_misses 407 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 12714500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency 12716000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate 0.997549 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_misses 407 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_accesses 14 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_avg_miss_latency 34250 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31035.714286 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_miss_latency 479500 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_misses 14 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_mshr_miss_latency 434500 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_misses 14 # number of UpgradeReq MSHR misses system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 0.002545 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 0.002457 # Average number of references to valid blocks. system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.demand_accesses 481 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 34426.041667 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31260.416667 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_miss_latency 34433.333333 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 31270.833333 # average overall mshr miss latency system.cpu.l2cache.demand_hits 1 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 16524500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency 16528000 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_rate 0.997921 # miss rate for demand accesses system.cpu.l2cache.demand_misses 480 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 15005000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 15010000 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_rate 0.997921 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_misses 480 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.occ_%::0 0.006535 # Average percentage of cache occupancy -system.cpu.l2cache.occ_blocks::0 214.135921 # Average occupied blocks per context +system.cpu.l2cache.occ_%::0 0.006704 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::0 219.690126 # Average occupied blocks per context system.cpu.l2cache.overall_accesses 481 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 34426.041667 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31260.416667 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_miss_latency 34433.333333 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 31270.833333 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.l2cache.overall_hits 1 # number of overall hits -system.cpu.l2cache.overall_miss_latency 16524500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency 16528000 # number of overall miss cycles system.cpu.l2cache.overall_miss_rate 0.997921 # miss rate for overall accesses system.cpu.l2cache.overall_misses 480 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 15005000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 15010000 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_rate 0.997921 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_misses 480 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.sampled_refs 393 # Sample count of references to valid blocks. +system.cpu.l2cache.sampled_refs 407 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 214.135921 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 219.690126 # Cycle average of tags in use system.cpu.l2cache.total_refs 1 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks -system.cpu.memDep0.conflictingLoads 36 # Number of conflicting loads. +system.cpu.memDep0.conflictingLoads 34 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 26 # Number of conflicting stores. -system.cpu.memDep0.insertedLoads 2269 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1271 # Number of stores inserted to the mem dependence unit. -system.cpu.numCycles 24996 # number of cpu cycles simulated -system.cpu.rename.RENAME:BlockCycles 340 # Number of cycles rename is blocking +system.cpu.memDep0.insertedLoads 2242 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1259 # Number of stores inserted to the mem dependence unit. +system.cpu.numCycles 24826 # number of cpu cycles simulated +system.cpu.rename.RENAME:BlockCycles 346 # Number of cycles rename is blocking system.cpu.rename.RENAME:CommittedMaps 4583 # Number of HB maps that are committed -system.cpu.rename.RENAME:IQFullEvents 9 # Number of times rename has blocked due to IQ full -system.cpu.rename.RENAME:IdleCycles 9098 # Number of cycles rename is idle -system.cpu.rename.RENAME:LSQFullEvents 255 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RENAME:RenameLookups 15174 # Number of register rename lookups that rename has made -system.cpu.rename.RENAME:RenamedInsts 12043 # Number of instructions processed by rename -system.cpu.rename.RENAME:RenamedOperands 8961 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 2203 # Number of cycles rename is running -system.cpu.rename.RENAME:SquashCycles 900 # Number of cycles rename is squashing -system.cpu.rename.RENAME:UnblockCycles 292 # Number of cycles rename is unblocking -system.cpu.rename.RENAME:UndoneMaps 4378 # Number of HB maps that are undone due to squashing -system.cpu.rename.RENAME:serializeStallCycles 498 # count of cycles rename stalled for serializing inst +system.cpu.rename.RENAME:IQFullEvents 8 # Number of times rename has blocked due to IQ full +system.cpu.rename.RENAME:IdleCycles 9063 # Number of cycles rename is idle +system.cpu.rename.RENAME:LSQFullEvents 234 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RENAME:RenameLookups 15033 # Number of register rename lookups that rename has made +system.cpu.rename.RENAME:RenamedInsts 11933 # Number of instructions processed by rename +system.cpu.rename.RENAME:RenamedOperands 8883 # Number of destination operands rename has renamed +system.cpu.rename.RENAME:RunCycles 2180 # Number of cycles rename is running +system.cpu.rename.RENAME:SquashCycles 884 # Number of cycles rename is squashing +system.cpu.rename.RENAME:UnblockCycles 270 # Number of cycles rename is unblocking +system.cpu.rename.RENAME:UndoneMaps 4300 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:serializeStallCycles 406 # count of cycles rename stalled for serializing inst system.cpu.rename.RENAME:serializingInsts 28 # count of serializing insts renamed -system.cpu.rename.RENAME:skidInsts 750 # count of insts added to the skid buffer +system.cpu.rename.RENAME:skidInsts 694 # count of insts added to the skid buffer system.cpu.rename.RENAME:tempSerializingInsts 22 # count of temporary serializing insts renamed -system.cpu.timesIdled 240 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.timesIdled 239 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.workload.PROG:num_syscalls 17 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing/config.ini b/tests/quick/00.hello/ref/alpha/linux/simple-timing/config.ini index b9c9ec747..17f796bc5 100644 --- a/tests/quick/00.hello/ref/alpha/linux/simple-timing/config.ini +++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing/config.ini @@ -157,7 +157,7 @@ egid=100 env= errout=cerr euid=100 -executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/hello/bin/alpha/linux/hello +executable=/dist/m5/regression/test-progs/hello/bin/alpha/linux/hello gid=100 input=cin max_stack_size=67108864 diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing/simout b/tests/quick/00.hello/ref/alpha/linux/simple-timing/simout index 7ee1b22c1..2df06d2e2 100755 --- a/tests/quick/00.hello/ref/alpha/linux/simple-timing/simout +++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing/simout @@ -1,3 +1,5 @@ +Redirecting stdout to build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/simple-timing/simout +Redirecting stderr to build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/simple-timing/simerr M5 Simulator System Copyright (c) 2001-2008 @@ -5,13 +7,13 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 24 2010 23:12:40 -M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip -M5 started Feb 25 2010 02:20:02 -M5 executing on SC2B0619 -command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/simple-timing -re tests/run.py build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/simple-timing +M5 compiled Aug 26 2010 11:51:59 +M5 revision 85cafc6ccb42 7662 default qtip tip sc-fail-fix +M5 started Aug 26 2010 11:59:22 +M5 executing on zizzer +command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/simple-timing -re tests/run.py build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. Hello world! -Exiting @ tick 33777000 because target called exit() +Exiting @ tick 33007000 because target called exit() diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing/stats.txt b/tests/quick/00.hello/ref/alpha/linux/simple-timing/stats.txt index 998b710c1..0a6e1d861 100644 --- a/tests/quick/00.hello/ref/alpha/linux/simple-timing/stats.txt +++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing/stats.txt @@ -1,13 +1,13 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 605866 # Simulator instruction rate (inst/s) -host_mem_usage 190120 # Number of bytes of host memory used -host_seconds 0.01 # Real time elapsed on the host -host_tick_rate 3109075847 # Simulator tick rate (ticks/s) +host_inst_rate 332796 # Simulator instruction rate (inst/s) +host_mem_usage 204128 # Number of bytes of host memory used +host_seconds 0.02 # Real time elapsed on the host +host_tick_rate 1691799077 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 6404 # Number of instructions simulated -sim_seconds 0.000034 # Number of seconds simulated -sim_ticks 33777000 # Number of ticks simulated +sim_seconds 0.000033 # Number of seconds simulated +sim_ticks 33007000 # Number of ticks simulated system.cpu.dcache.ReadReq_accesses 1185 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_avg_miss_latency 56000 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency 53000 # average ReadReq mshr miss latency @@ -21,13 +21,13 @@ system.cpu.dcache.ReadReq_mshr_misses 95 # nu system.cpu.dcache.WriteReq_accesses 865 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_avg_miss_latency 56000 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53000 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 778 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 4872000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.100578 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 87 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_miss_latency 4611000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.100578 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 87 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_hits 792 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 4088000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.084393 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 73 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_miss_latency 3869000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate 0.084393 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses 73 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.dcache.avg_refs 11.202381 # Average number of references to valid blocks. @@ -39,37 +39,37 @@ system.cpu.dcache.cache_copies 0 # nu system.cpu.dcache.demand_accesses 2050 # number of demand (read+write) accesses system.cpu.dcache.demand_avg_miss_latency 56000 # average overall miss latency system.cpu.dcache.demand_avg_mshr_miss_latency 53000 # average overall mshr miss latency -system.cpu.dcache.demand_hits 1868 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 10192000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.088780 # miss rate for demand accesses -system.cpu.dcache.demand_misses 182 # number of demand (read+write) misses +system.cpu.dcache.demand_hits 1882 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 9408000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.081951 # miss rate for demand accesses +system.cpu.dcache.demand_misses 168 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 9646000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.088780 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 182 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_miss_latency 8904000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.081951 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 168 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_%::0 0.025418 # Average percentage of cache occupancy -system.cpu.dcache.occ_blocks::0 104.111261 # Average occupied blocks per context +system.cpu.dcache.occ_%::0 0.025313 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::0 103.680615 # Average occupied blocks per context system.cpu.dcache.overall_accesses 2050 # number of overall (read+write) accesses system.cpu.dcache.overall_avg_miss_latency 56000 # average overall miss latency system.cpu.dcache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 1868 # number of overall hits -system.cpu.dcache.overall_miss_latency 10192000 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.088780 # miss rate for overall accesses -system.cpu.dcache.overall_misses 182 # number of overall misses +system.cpu.dcache.overall_hits 1882 # number of overall hits +system.cpu.dcache.overall_miss_latency 9408000 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.081951 # miss rate for overall accesses +system.cpu.dcache.overall_misses 168 # number of overall misses system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 9646000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.088780 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 182 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_miss_latency 8904000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.081951 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 168 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.sampled_refs 168 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 104.111261 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 103.680615 # Cycle average of tags in use system.cpu.dcache.total_refs 1882 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 0 # number of writebacks @@ -121,8 +121,8 @@ system.cpu.icache.demand_mshr_misses 279 # nu system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_%::0 0.062817 # Average percentage of cache occupancy -system.cpu.icache.occ_blocks::0 128.649737 # Average occupied blocks per context +system.cpu.icache.occ_%::0 0.062443 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::0 127.883393 # Average occupied blocks per context system.cpu.icache.overall_accesses 6415 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency 55849.462366 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 52849.462366 # average overall mshr miss latency @@ -140,7 +140,7 @@ system.cpu.icache.overall_mshr_uncacheable_misses 0 system.cpu.icache.replacements 0 # number of replacements system.cpu.icache.sampled_refs 279 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 128.649737 # Cycle average of tags in use +system.cpu.icache.tagsinuse 127.883393 # Cycle average of tags in use system.cpu.icache.total_refs 6136 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks @@ -180,18 +180,9 @@ system.cpu.l2cache.ReadReq_misses 373 # nu system.cpu.l2cache.ReadReq_mshr_miss_latency 14920000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate 0.997326 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_misses 373 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_accesses 14 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_avg_miss_latency 52000 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_miss_latency 728000 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_misses 14 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_mshr_miss_latency 560000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_misses 14 # number of UpgradeReq MSHR misses system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 0.002786 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 0.002681 # Average number of references to valid blocks. system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked @@ -211,8 +202,8 @@ system.cpu.l2cache.demand_mshr_misses 446 # nu system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.occ_%::0 0.005491 # Average percentage of cache occupancy -system.cpu.l2cache.occ_blocks::0 179.928092 # Average occupied blocks per context +system.cpu.l2cache.occ_%::0 0.005626 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::0 184.342479 # Average occupied blocks per context system.cpu.l2cache.overall_accesses 447 # number of overall (read+write) accesses system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency @@ -228,14 +219,14 @@ system.cpu.l2cache.overall_mshr_misses 446 # nu system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.sampled_refs 359 # Sample count of references to valid blocks. +system.cpu.l2cache.sampled_refs 373 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 179.928092 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 184.342479 # Cycle average of tags in use system.cpu.l2cache.total_refs 1 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 67554 # number of cpu cycles simulated +system.cpu.numCycles 66014 # number of cpu cycles simulated system.cpu.num_insts 6404 # Number of instructions executed system.cpu.num_refs 2060 # Number of memory references system.cpu.workload.PROG:num_syscalls 17 # Number of system calls diff --git a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/simout b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/simout index a969330c7..621a02c83 100755 --- a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/simout +++ b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/simout @@ -1,5 +1,5 @@ -Redirecting stdout to build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/o3-timing/simout -Redirecting stderr to build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/o3-timing/simerr +Redirecting stdout to build/ALPHA_SE/tests/opt/quick/00.hello/alpha/tru64/o3-timing/simout +Redirecting stderr to build/ALPHA_SE/tests/opt/quick/00.hello/alpha/tru64/o3-timing/simerr M5 Simulator System Copyright (c) 2001-2008 @@ -7,13 +7,13 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Jun 6 2010 03:04:38 -M5 revision ba1a0193c050 7448 default tip -M5 started Jun 6 2010 03:04:41 +M5 compiled Aug 26 2010 11:51:59 +M5 revision 85cafc6ccb42 7662 default qtip tip sc-fail-fix +M5 started Aug 26 2010 11:52:05 M5 executing on zizzer -command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/o3-timing +command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/quick/00.hello/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/opt/quick/00.hello/alpha/tru64/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. Hello world! -Exiting @ tick 7285000 because target called exit() +Exiting @ tick 7300000 because target called exit() diff --git a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stats.txt b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stats.txt index 7aa7cb16b..a87f9a576 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stats.txt @@ -1,41 +1,41 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 8638 # Simulator instruction rate (inst/s) -host_mem_usage 203416 # Number of bytes of host memory used -host_seconds 0.28 # Real time elapsed on the host -host_tick_rate 26335958 # Simulator tick rate (ticks/s) +host_inst_rate 34398 # Simulator instruction rate (inst/s) +host_mem_usage 203876 # Number of bytes of host memory used +host_seconds 0.07 # Real time elapsed on the host +host_tick_rate 104794717 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 2387 # Number of instructions simulated sim_seconds 0.000007 # Number of seconds simulated -sim_ticks 7285000 # Number of ticks simulated +sim_ticks 7300000 # Number of ticks simulated system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.BPredUnit.BTBHits 190 # Number of BTB hits -system.cpu.BPredUnit.BTBLookups 674 # Number of BTB lookups +system.cpu.BPredUnit.BTBLookups 683 # Number of BTB lookups system.cpu.BPredUnit.RASInCorrect 35 # Number of incorrect RAS predictions. system.cpu.BPredUnit.condIncorrect 220 # Number of conditional branches incorrect -system.cpu.BPredUnit.condPredicted 463 # Number of conditional branches predicted -system.cpu.BPredUnit.lookups 916 # Number of BP lookups -system.cpu.BPredUnit.usedRAS 178 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.condPredicted 476 # Number of conditional branches predicted +system.cpu.BPredUnit.lookups 926 # Number of BP lookups +system.cpu.BPredUnit.usedRAS 179 # Number of times the RAS was used to get a target. system.cpu.commit.COM:branches 396 # Number of branches committed -system.cpu.commit.COM:bw_lim_events 39 # number cycles where commit BW limit reached +system.cpu.commit.COM:bw_lim_events 35 # number cycles where commit BW limit reached system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits -system.cpu.commit.COM:committed_per_cycle::samples 6323 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::mean 0.407402 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::stdev 1.198077 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::samples 6328 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::mean 0.407080 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::stdev 1.186255 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::0 5366 84.86% 84.86% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::1 262 4.14% 89.01% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::2 338 5.35% 94.35% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::3 131 2.07% 96.43% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::4 72 1.14% 97.56% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::5 64 1.01% 98.58% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::6 32 0.51% 99.08% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::7 19 0.30% 99.38% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::8 39 0.62% 100.00% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::0 5362 84.73% 84.73% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::1 264 4.17% 88.91% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::2 341 5.39% 94.30% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::3 139 2.20% 96.49% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::4 71 1.12% 97.61% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::5 66 1.04% 98.66% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::6 31 0.49% 99.15% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::7 19 0.30% 99.45% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::8 35 0.55% 100.00% # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::total 6323 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::total 6328 # Number of insts commited each cycle system.cpu.commit.COM:count 2576 # Number of instructions committed system.cpu.commit.COM:loads 415 # Number of loads committed system.cpu.commit.COM:membars 0 # Number of memory barriers committed @@ -44,248 +44,248 @@ system.cpu.commit.COM:swp_count 0 # Nu system.cpu.commit.branchMispredicts 143 # The number of times a branch was mispredicted system.cpu.commit.commitCommittedInsts 2576 # The number of committed instructions system.cpu.commit.commitNonSpecStalls 4 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 1946 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 1998 # The number of squashed insts skipped by commit system.cpu.committedInsts 2387 # Number of Instructions Simulated system.cpu.committedInsts_total 2387 # Number of Instructions Simulated -system.cpu.cpi 6.104315 # CPI: Cycles Per Instruction -system.cpu.cpi_total 6.104315 # CPI: Total CPI of All Threads -system.cpu.dcache.ReadReq_accesses 595 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 35822.222222 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 35663.934426 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 505 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 3224000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.151261 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 90 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits 29 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency 2175500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.102521 # mshr miss rate for ReadReq accesses +system.cpu.cpi 6.116883 # CPI: Cycles Per Instruction +system.cpu.cpi_total 6.116883 # CPI: Total CPI of All Threads +system.cpu.dcache.ReadReq_accesses 599 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 35045 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 35696.721311 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 499 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 3504500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.166945 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 100 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_hits 39 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_miss_latency 2177500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.101836 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_misses 61 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 294 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 37219.626168 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 37702.702703 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 187 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 3982500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.363946 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 107 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_hits 70 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency 1395000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.125850 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 37 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_avg_miss_latency 38819.444444 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 36145.833333 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 222 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 2795000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.244898 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 72 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_hits 48 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_miss_latency 867500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate 0.081633 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses 24 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 8.600000 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 8.482353 # Average number of references to valid blocks. system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 889 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 36581.218274 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 36433.673469 # average overall mshr miss latency -system.cpu.dcache.demand_hits 692 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 7206500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.221597 # miss rate for demand accesses -system.cpu.dcache.demand_misses 197 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 99 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 3570500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.110236 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 98 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_accesses 893 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 36625 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 35823.529412 # average overall mshr miss latency +system.cpu.dcache.demand_hits 721 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 6299500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.192609 # miss rate for demand accesses +system.cpu.dcache.demand_misses 172 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 87 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 3045000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.095185 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 85 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_%::0 0.011290 # Average percentage of cache occupancy -system.cpu.dcache.occ_blocks::0 46.245716 # Average occupied blocks per context -system.cpu.dcache.overall_accesses 889 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 36581.218274 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 36433.673469 # average overall mshr miss latency +system.cpu.dcache.occ_%::0 0.011350 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::0 46.490005 # Average occupied blocks per context +system.cpu.dcache.overall_accesses 893 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 36625 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 35823.529412 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 692 # number of overall hits -system.cpu.dcache.overall_miss_latency 7206500 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.221597 # miss rate for overall accesses -system.cpu.dcache.overall_misses 197 # number of overall misses -system.cpu.dcache.overall_mshr_hits 99 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 3570500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.110236 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 98 # number of overall MSHR misses +system.cpu.dcache.overall_hits 721 # number of overall hits +system.cpu.dcache.overall_miss_latency 6299500 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.192609 # miss rate for overall accesses +system.cpu.dcache.overall_misses 172 # number of overall misses +system.cpu.dcache.overall_mshr_hits 87 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 3045000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.095185 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 85 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.sampled_refs 85 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 46.245716 # Cycle average of tags in use -system.cpu.dcache.total_refs 731 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 46.490005 # Cycle average of tags in use +system.cpu.dcache.total_refs 721 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 0 # number of writebacks -system.cpu.decode.DECODE:BlockedCycles 169 # Number of cycles decode is blocked +system.cpu.decode.DECODE:BlockedCycles 226 # Number of cycles decode is blocked system.cpu.decode.DECODE:BranchMispred 79 # Number of times decode detected a branch misprediction -system.cpu.decode.DECODE:BranchResolved 142 # Number of times decode resolved a branch -system.cpu.decode.DECODE:DecodedInsts 5018 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 5179 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 974 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 367 # Number of cycles decode is squashing +system.cpu.decode.DECODE:BranchResolved 136 # Number of times decode resolved a branch +system.cpu.decode.DECODE:DecodedInsts 5050 # Number of instructions handled by decode +system.cpu.decode.DECODE:IdleCycles 5122 # Number of cycles decode is idle +system.cpu.decode.DECODE:RunCycles 978 # Number of cycles decode is running +system.cpu.decode.DECODE:SquashCycles 373 # Number of cycles decode is squashing system.cpu.decode.DECODE:SquashedInsts 284 # Number of squashed instructions handled by decode -system.cpu.decode.DECODE:UnblockCycles 1 # Number of cycles decode is unblocking -system.cpu.dtb.data_accesses 1010 # DTB accesses +system.cpu.decode.DECODE:UnblockCycles 2 # Number of cycles decode is unblocking +system.cpu.dtb.data_accesses 1016 # DTB accesses system.cpu.dtb.data_acv 1 # DTB access violations -system.cpu.dtb.data_hits 979 # DTB hits -system.cpu.dtb.data_misses 31 # DTB misses +system.cpu.dtb.data_hits 978 # DTB hits +system.cpu.dtb.data_misses 38 # DTB misses system.cpu.dtb.fetch_accesses 0 # ITB accesses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses -system.cpu.dtb.read_accesses 638 # DTB read accesses +system.cpu.dtb.read_accesses 648 # DTB read accesses system.cpu.dtb.read_acv 1 # DTB read access violations -system.cpu.dtb.read_hits 623 # DTB read hits -system.cpu.dtb.read_misses 15 # DTB read misses -system.cpu.dtb.write_accesses 372 # DTB write accesses +system.cpu.dtb.read_hits 627 # DTB read hits +system.cpu.dtb.read_misses 21 # DTB read misses +system.cpu.dtb.write_accesses 368 # DTB write accesses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_hits 356 # DTB write hits -system.cpu.dtb.write_misses 16 # DTB write misses -system.cpu.fetch.Branches 916 # Number of branches that fetch encountered -system.cpu.fetch.CacheLines 789 # Number of cache lines fetched -system.cpu.fetch.Cycles 1801 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.IcacheSquashes 119 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.Insts 5736 # Number of instructions fetch has processed -system.cpu.fetch.SquashCycles 250 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.062865 # Number of branch fetches per cycle -system.cpu.fetch.icacheStallCycles 789 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.predictedBranches 368 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 0.393659 # Number of inst fetches per cycle -system.cpu.fetch.rateDist::samples 6690 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.857399 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.271719 # Number of instructions fetched each cycle (Total) +system.cpu.dtb.write_hits 351 # DTB write hits +system.cpu.dtb.write_misses 17 # DTB write misses +system.cpu.fetch.Branches 926 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 782 # Number of cache lines fetched +system.cpu.fetch.Cycles 1799 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 117 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.Insts 5752 # Number of instructions fetch has processed +system.cpu.fetch.SquashCycles 249 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.063420 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 782 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 369 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 0.393946 # Number of inst fetches per cycle +system.cpu.fetch.rateDist::samples 6701 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.858379 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.271912 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 5707 85.31% 85.31% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 48 0.72% 86.02% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 101 1.51% 87.53% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 74 1.11% 88.64% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 123 1.84% 90.48% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 57 0.85% 91.33% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 51 0.76% 92.09% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 51 0.76% 92.86% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 478 7.14% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 5713 85.26% 85.26% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 53 0.79% 86.05% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 100 1.49% 87.54% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 71 1.06% 88.60% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 125 1.87% 90.46% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 52 0.78% 91.24% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 55 0.82% 92.06% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 60 0.90% 92.96% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 472 7.04% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 6690 # Number of instructions fetched each cycle (Total) -system.cpu.icache.ReadReq_accesses 789 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 36081.196581 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 35312.154696 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 555 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 8443000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.296578 # miss rate for ReadReq accesses +system.cpu.fetch.rateDist::total 6701 # Number of instructions fetched each cycle (Total) +system.cpu.icache.ReadReq_accesses 782 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 36074.786325 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 35303.867403 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 548 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 8441500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.299233 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_misses 234 # number of ReadReq misses system.cpu.icache.ReadReq_mshr_hits 53 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 6391500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.229404 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_latency 6390000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.231458 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_misses 181 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.icache.avg_refs 3.066298 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 3.027624 # Average number of references to valid blocks. system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 789 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 36081.196581 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 35312.154696 # average overall mshr miss latency -system.cpu.icache.demand_hits 555 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 8443000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.296578 # miss rate for demand accesses +system.cpu.icache.demand_accesses 782 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 36074.786325 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 35303.867403 # average overall mshr miss latency +system.cpu.icache.demand_hits 548 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 8441500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.299233 # miss rate for demand accesses system.cpu.icache.demand_misses 234 # number of demand (read+write) misses system.cpu.icache.demand_mshr_hits 53 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 6391500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.229404 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_latency 6390000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0.231458 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_misses 181 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_%::0 0.043805 # Average percentage of cache occupancy -system.cpu.icache.occ_blocks::0 89.711886 # Average occupied blocks per context -system.cpu.icache.overall_accesses 789 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 36081.196581 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 35312.154696 # average overall mshr miss latency +system.cpu.icache.occ_%::0 0.044097 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::0 90.310423 # Average occupied blocks per context +system.cpu.icache.overall_accesses 782 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 36074.786325 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 35303.867403 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 555 # number of overall hits -system.cpu.icache.overall_miss_latency 8443000 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.296578 # miss rate for overall accesses +system.cpu.icache.overall_hits 548 # number of overall hits +system.cpu.icache.overall_miss_latency 8441500 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.299233 # miss rate for overall accesses system.cpu.icache.overall_misses 234 # number of overall misses system.cpu.icache.overall_mshr_hits 53 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 6391500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.229404 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_latency 6390000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0.231458 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_misses 181 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.icache.replacements 0 # number of replacements system.cpu.icache.sampled_refs 181 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 89.711886 # Cycle average of tags in use -system.cpu.icache.total_refs 555 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 90.310423 # Cycle average of tags in use +system.cpu.icache.total_refs 548 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idleCycles 7881 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.EXEC:branches 607 # Number of branches executed -system.cpu.iew.EXEC:nop 310 # number of nop insts executed -system.cpu.iew.EXEC:rate 0.241370 # Inst execution rate -system.cpu.iew.EXEC:refs 1013 # number of memory reference insts executed -system.cpu.iew.EXEC:stores 372 # Number of stores executed +system.cpu.idleCycles 7900 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.EXEC:branches 601 # Number of branches executed +system.cpu.iew.EXEC:nop 306 # number of nop insts executed +system.cpu.iew.EXEC:rate 0.241079 # Inst execution rate +system.cpu.iew.EXEC:refs 1019 # number of memory reference insts executed +system.cpu.iew.EXEC:stores 368 # Number of stores executed system.cpu.iew.EXEC:swp 0 # number of swp insts executed -system.cpu.iew.WB:consumers 1984 # num instructions consuming a value -system.cpu.iew.WB:count 3409 # cumulative count of insts written-back -system.cpu.iew.WB:fanout 0.798891 # average fanout of values written-back +system.cpu.iew.WB:consumers 1981 # num instructions consuming a value +system.cpu.iew.WB:count 3402 # cumulative count of insts written-back +system.cpu.iew.WB:fanout 0.795558 # average fanout of values written-back system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 1585 # num instructions producing a value -system.cpu.iew.WB:rate 0.233958 # insts written-back per cycle +system.cpu.iew.WB:producers 1576 # num instructions producing a value +system.cpu.iew.WB:rate 0.232998 # insts written-back per cycle system.cpu.iew.WB:sent 3452 # cumulative count of insts sent to commit system.cpu.iew.branchMispredicts 164 # Number of branch mispredicts detected at execute -system.cpu.iew.iewBlockCycles 0 # Number of cycles IEW is blocking -system.cpu.iew.iewDispLoadInsts 787 # Number of dispatched load instructions +system.cpu.iew.iewBlockCycles 55 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 795 # Number of dispatched load instructions system.cpu.iew.iewDispNonSpecInsts 6 # Number of dispatched non-speculative instructions -system.cpu.iew.iewDispSquashedInsts 57 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispStoreInsts 432 # Number of dispatched store instructions -system.cpu.iew.iewDispatchedInsts 4536 # Number of instructions dispatched to IQ -system.cpu.iew.iewExecLoadInsts 641 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 117 # Number of squashed instructions skipped in execute -system.cpu.iew.iewExecutedInsts 3517 # Number of executed instructions -system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewDispSquashedInsts 68 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 435 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 4588 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 651 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 111 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 3520 # Number of executed instructions +system.cpu.iew.iewIQFullEvents 3 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.iewSquashCycles 367 # Number of cycles IEW is squashing -system.cpu.iew.iewUnblockCycles 0 # Number of cycles IEW is unblocking +system.cpu.iew.iewSquashCycles 373 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 5 # Number of cycles IEW is unblocking system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.lsq.thread.0.forwLoads 28 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread.0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.0.memOrderViolation 14 # Number of memory ordering violations +system.cpu.iew.lsq.thread.0.memOrderViolation 13 # Number of memory ordering violations system.cpu.iew.lsq.thread.0.rescheduledLoads 0 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 372 # Number of loads squashed -system.cpu.iew.lsq.thread.0.squashedStores 138 # Number of stores squashed -system.cpu.iew.memOrderViolationEvents 14 # Number of memory order violations -system.cpu.iew.predictedNotTakenIncorrect 110 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.predictedTakenIncorrect 54 # Number of branches that were predicted taken incorrectly -system.cpu.ipc 0.163819 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.163819 # IPC: Total IPC of All Threads +system.cpu.iew.lsq.thread.0.squashedLoads 380 # Number of loads squashed +system.cpu.iew.lsq.thread.0.squashedStores 141 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 13 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 109 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 55 # Number of branches that were predicted taken incorrectly +system.cpu.ipc 0.163482 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.163482 # IPC: Total IPC of All Threads system.cpu.iq.ISSUE:FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntAlu 2590 71.27% 71.27% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntMult 1 0.03% 71.30% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 71.30% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatAdd 0 0.00% 71.30% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 71.30% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 71.30% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 71.30% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 71.30% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 71.30% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::MemRead 666 18.33% 89.63% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::MemWrite 377 10.37% 100.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntAlu 2582 71.11% 71.11% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntMult 1 0.03% 71.14% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 71.14% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatAdd 0 0.00% 71.14% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 71.14% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 71.14% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 71.14% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 71.14% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 71.14% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::MemRead 675 18.59% 89.73% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::MemWrite 373 10.27% 100.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::total 3634 # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::total 3631 # Type of FU issued system.cpu.iq.ISSUE:fu_busy_cnt 35 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_rate 0.009631 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:fu_busy_rate 0.009639 # FU busy rate (busy events/executed inst) system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::IntAlu 1 2.86% 2.86% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 2.86% # attempts to use FU when none available @@ -300,38 +300,38 @@ system.cpu.iq.ISSUE:fu_full::MemRead 12 34.29% 37.14% # at system.cpu.iq.ISSUE:fu_full::MemWrite 22 62.86% 100.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:issued_per_cycle::samples 6690 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::mean 0.543199 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.215587 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::samples 6701 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::mean 0.541859 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.220931 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::0 5134 76.74% 76.74% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::1 621 9.28% 86.02% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::2 357 5.34% 91.36% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::3 240 3.59% 94.95% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::4 184 2.75% 97.70% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::5 102 1.52% 99.22% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::6 36 0.54% 99.76% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::7 11 0.16% 99.93% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::8 5 0.07% 100.00% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::0 5144 76.76% 76.76% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::1 631 9.42% 86.18% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::2 352 5.25% 91.43% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::3 241 3.60% 95.03% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::4 180 2.69% 97.72% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::5 94 1.40% 99.12% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::6 38 0.57% 99.69% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::7 13 0.19% 99.88% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::8 8 0.12% 100.00% # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::total 6690 # Number of insts issued each cycle -system.cpu.iq.ISSUE:rate 0.249399 # Inst issue rate -system.cpu.iq.iqInstsAdded 4220 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 3634 # Number of instructions issued +system.cpu.iq.ISSUE:issued_per_cycle::total 6701 # Number of insts issued each cycle +system.cpu.iq.ISSUE:rate 0.248682 # Inst issue rate +system.cpu.iq.iqInstsAdded 4276 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 3631 # Number of instructions issued system.cpu.iq.iqNonSpecInstsAdded 6 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 1660 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedInstsIssued 33 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 1710 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 23 # Number of squashed instructions issued system.cpu.iq.iqSquashedNonSpecRemoved 2 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 874 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedOperandsExamined 972 # Number of squashed operands that are examined and possibly removed from graph system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_hits 0 # DTB hits system.cpu.itb.data_misses 0 # DTB misses -system.cpu.itb.fetch_accesses 818 # ITB accesses +system.cpu.itb.fetch_accesses 811 # ITB accesses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_hits 789 # ITB hits +system.cpu.itb.fetch_hits 782 # ITB hits system.cpu.itb.fetch_misses 29 # ITB misses system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.read_acv 0 # DTB read access violations @@ -351,23 +351,14 @@ system.cpu.l2cache.ReadExReq_mshr_miss_latency 756000 system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_misses 24 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadReq_accesses 242 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 34324.380165 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31130.165289 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_miss_latency 8306500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_avg_miss_latency 34322.314050 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31132.231405 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_miss_latency 8306000 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_rate 1 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_misses 242 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 7533500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency 7534000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_misses 242 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_accesses 14 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_avg_miss_latency 34250 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31107.142857 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_miss_latency 479500 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_misses 14 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_mshr_miss_latency 435500 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_misses 14 # number of UpgradeReq MSHR misses system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.l2cache.avg_refs 0 # Average number of references to valid blocks. @@ -377,63 +368,64 @@ system.cpu.l2cache.blocked_cycles::no_mshrs 0 # system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.demand_accesses 266 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 34349.624060 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31163.533835 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_miss_latency 34347.744361 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 31165.413534 # average overall mshr miss latency system.cpu.l2cache.demand_hits 0 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 9137000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency 9136500 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_rate 1 # miss rate for demand accesses system.cpu.l2cache.demand_misses 266 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 8289500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 8290000 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_rate 1 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_misses 266 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.occ_%::0 0.003416 # Average percentage of cache occupancy -system.cpu.l2cache.occ_blocks::0 111.924793 # Average occupied blocks per context +system.cpu.l2cache.occ_%::0 0.003651 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::0 119.628373 # Average occupied blocks per context system.cpu.l2cache.overall_accesses 266 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 34349.624060 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31163.533835 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_miss_latency 34347.744361 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 31165.413534 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.l2cache.overall_hits 0 # number of overall hits -system.cpu.l2cache.overall_miss_latency 9137000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency 9136500 # number of overall miss cycles system.cpu.l2cache.overall_miss_rate 1 # miss rate for overall accesses system.cpu.l2cache.overall_misses 266 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 8289500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 8290000 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_rate 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_misses 266 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.sampled_refs 228 # Sample count of references to valid blocks. +system.cpu.l2cache.sampled_refs 242 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 111.924793 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 119.628373 # Cycle average of tags in use system.cpu.l2cache.total_refs 0 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks -system.cpu.memDep0.conflictingLoads 12 # Number of conflicting loads. +system.cpu.memDep0.conflictingLoads 16 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 16 # Number of conflicting stores. -system.cpu.memDep0.insertedLoads 787 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 432 # Number of stores inserted to the mem dependence unit. -system.cpu.numCycles 14571 # number of cpu cycles simulated -system.cpu.rename.RENAME:BlockCycles 7 # Number of cycles rename is blocking +system.cpu.memDep0.insertedLoads 795 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 435 # Number of stores inserted to the mem dependence unit. +system.cpu.numCycles 14601 # number of cpu cycles simulated +system.cpu.rename.RENAME:BlockCycles 63 # Number of cycles rename is blocking system.cpu.rename.RENAME:CommittedMaps 1768 # Number of HB maps that are committed -system.cpu.rename.RENAME:IdleCycles 5259 # Number of cycles rename is idle -system.cpu.rename.RENAME:LSQFullEvents 8 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RENAME:RenameLookups 5438 # Number of register rename lookups that rename has made -system.cpu.rename.RENAME:RenamedInsts 4848 # Number of instructions processed by rename -system.cpu.rename.RENAME:RenamedOperands 3462 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 895 # Number of cycles rename is running -system.cpu.rename.RENAME:SquashCycles 367 # Number of cycles rename is squashing -system.cpu.rename.RENAME:UnblockCycles 16 # Number of cycles rename is unblocking -system.cpu.rename.RENAME:UndoneMaps 1694 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:IQFullEvents 3 # Number of times rename has blocked due to IQ full +system.cpu.rename.RENAME:IdleCycles 5203 # Number of cycles rename is idle +system.cpu.rename.RENAME:LSQFullEvents 3 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RENAME:RenameLookups 5514 # Number of register rename lookups that rename has made +system.cpu.rename.RENAME:RenamedInsts 4876 # Number of instructions processed by rename +system.cpu.rename.RENAME:RenamedOperands 3481 # Number of destination operands rename has renamed +system.cpu.rename.RENAME:RunCycles 901 # Number of cycles rename is running +system.cpu.rename.RENAME:SquashCycles 373 # Number of cycles rename is squashing +system.cpu.rename.RENAME:UnblockCycles 15 # Number of cycles rename is unblocking +system.cpu.rename.RENAME:UndoneMaps 1713 # Number of HB maps that are undone due to squashing system.cpu.rename.RENAME:serializeStallCycles 146 # count of cycles rename stalled for serializing inst system.cpu.rename.RENAME:serializingInsts 8 # count of serializing insts renamed -system.cpu.rename.RENAME:skidInsts 80 # count of insts added to the skid buffer +system.cpu.rename.RENAME:skidInsts 78 # count of insts added to the skid buffer system.cpu.rename.RENAME:tempSerializingInsts 6 # count of temporary serializing insts renamed -system.cpu.timesIdled 153 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.timesIdled 152 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.workload.PROG:num_syscalls 4 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.ini b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.ini index ab47c5c67..c142fa659 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.ini +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.ini @@ -157,7 +157,7 @@ egid=100 env= errout=cerr euid=100 -executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/hello/bin/alpha/tru64/hello +executable=/dist/m5/regression/test-progs/hello/bin/alpha/tru64/hello gid=100 input=cin max_stack_size=67108864 diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/simout b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/simout index 2135491a6..6dd6e994b 100755 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/simout +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/simout @@ -1,3 +1,5 @@ +Redirecting stdout to build/ALPHA_SE/tests/opt/quick/00.hello/alpha/tru64/simple-timing/simout +Redirecting stderr to build/ALPHA_SE/tests/opt/quick/00.hello/alpha/tru64/simple-timing/simerr M5 Simulator System Copyright (c) 2001-2008 @@ -5,13 +7,13 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 24 2010 23:12:40 -M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip -M5 started Feb 25 2010 03:11:06 -M5 executing on SC2B0619 -command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/simple-timing -re tests/run.py build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/simple-timing +M5 compiled Aug 26 2010 11:51:59 +M5 revision 85cafc6ccb42 7662 default qtip tip sc-fail-fix +M5 started Aug 26 2010 11:52:05 +M5 executing on zizzer +command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/quick/00.hello/alpha/tru64/simple-timing -re tests/run.py build/ALPHA_SE/tests/opt/quick/00.hello/alpha/tru64/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. Hello world! -Exiting @ tick 17374000 because target called exit() +Exiting @ tick 16769000 because target called exit() diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/stats.txt b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/stats.txt index 3c63125e0..f08ca087e 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/stats.txt @@ -1,13 +1,13 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 400715 # Simulator instruction rate (inst/s) -host_mem_usage 189300 # Number of bytes of host memory used -host_seconds 0.01 # Real time elapsed on the host -host_tick_rate 2582342449 # Simulator tick rate (ticks/s) +host_inst_rate 97740 # Simulator instruction rate (inst/s) +host_mem_usage 203308 # Number of bytes of host memory used +host_seconds 0.03 # Real time elapsed on the host +host_tick_rate 629585132 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 2577 # Number of instructions simulated sim_seconds 0.000017 # Number of seconds simulated -sim_ticks 17374000 # Number of ticks simulated +sim_ticks 16769000 # Number of ticks simulated system.cpu.dcache.ReadReq_accesses 415 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_avg_miss_latency 56000 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency 53000 # average ReadReq mshr miss latency @@ -21,13 +21,13 @@ system.cpu.dcache.ReadReq_mshr_misses 55 # nu system.cpu.dcache.WriteReq_accesses 294 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_avg_miss_latency 56000 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53000 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 256 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 2128000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.129252 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 38 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_miss_latency 2014000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.129252 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 38 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_hits 267 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 1512000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.091837 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 27 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_miss_latency 1431000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate 0.091837 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses 27 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.dcache.avg_refs 7.646341 # Average number of references to valid blocks. @@ -39,37 +39,37 @@ system.cpu.dcache.cache_copies 0 # nu system.cpu.dcache.demand_accesses 709 # number of demand (read+write) accesses system.cpu.dcache.demand_avg_miss_latency 56000 # average overall miss latency system.cpu.dcache.demand_avg_mshr_miss_latency 53000 # average overall mshr miss latency -system.cpu.dcache.demand_hits 616 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 5208000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.131171 # miss rate for demand accesses -system.cpu.dcache.demand_misses 93 # number of demand (read+write) misses +system.cpu.dcache.demand_hits 627 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 4592000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.115656 # miss rate for demand accesses +system.cpu.dcache.demand_misses 82 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 4929000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.131171 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 93 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_miss_latency 4346000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.115656 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 82 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_%::0 0.011615 # Average percentage of cache occupancy -system.cpu.dcache.occ_blocks::0 47.575114 # Average occupied blocks per context +system.cpu.dcache.occ_%::0 0.011577 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::0 47.418751 # Average occupied blocks per context system.cpu.dcache.overall_accesses 709 # number of overall (read+write) accesses system.cpu.dcache.overall_avg_miss_latency 56000 # average overall miss latency system.cpu.dcache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 616 # number of overall hits -system.cpu.dcache.overall_miss_latency 5208000 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.131171 # miss rate for overall accesses -system.cpu.dcache.overall_misses 93 # number of overall misses +system.cpu.dcache.overall_hits 627 # number of overall hits +system.cpu.dcache.overall_miss_latency 4592000 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.115656 # miss rate for overall accesses +system.cpu.dcache.overall_misses 82 # number of overall misses system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 4929000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.131171 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 93 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_miss_latency 4346000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.115656 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 82 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.sampled_refs 82 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 47.575114 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 47.418751 # Cycle average of tags in use system.cpu.dcache.total_refs 627 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 0 # number of writebacks @@ -121,8 +121,8 @@ system.cpu.icache.demand_mshr_misses 163 # nu system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_%::0 0.039276 # Average percentage of cache occupancy -system.cpu.icache.occ_blocks::0 80.437325 # Average occupied blocks per context +system.cpu.icache.occ_%::0 0.039064 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::0 80.003762 # Average occupied blocks per context system.cpu.icache.overall_accesses 2586 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency 56000 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency @@ -140,7 +140,7 @@ system.cpu.icache.overall_mshr_uncacheable_misses 0 system.cpu.icache.replacements 0 # number of replacements system.cpu.icache.sampled_refs 163 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 80.437325 # Cycle average of tags in use +system.cpu.icache.tagsinuse 80.003762 # Cycle average of tags in use system.cpu.icache.total_refs 2423 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks @@ -179,15 +179,6 @@ system.cpu.l2cache.ReadReq_misses 218 # nu system.cpu.l2cache.ReadReq_mshr_miss_latency 8720000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_misses 218 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_accesses 11 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_avg_miss_latency 52000 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_miss_latency 572000 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_misses 11 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_mshr_miss_latency 440000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_misses 11 # number of UpgradeReq MSHR misses system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.l2cache.avg_refs 0 # Average number of references to valid blocks. @@ -210,8 +201,8 @@ system.cpu.l2cache.demand_mshr_misses 245 # nu system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.occ_%::0 0.003139 # Average percentage of cache occupancy -system.cpu.l2cache.occ_blocks::0 102.857609 # Average occupied blocks per context +system.cpu.l2cache.occ_%::0 0.003268 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::0 107.101205 # Average occupied blocks per context system.cpu.l2cache.overall_accesses 245 # number of overall (read+write) accesses system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency @@ -227,14 +218,14 @@ system.cpu.l2cache.overall_mshr_misses 245 # nu system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.sampled_refs 207 # Sample count of references to valid blocks. +system.cpu.l2cache.sampled_refs 218 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 102.857609 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 107.101205 # Cycle average of tags in use system.cpu.l2cache.total_refs 0 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 34748 # number of cpu cycles simulated +system.cpu.numCycles 33538 # number of cpu cycles simulated system.cpu.num_insts 2577 # Number of instructions executed system.cpu.num_refs 717 # Number of memory references system.cpu.workload.PROG:num_syscalls 4 # Number of system calls diff --git a/tests/quick/00.hello/ref/mips/linux/inorder-timing/simout b/tests/quick/00.hello/ref/mips/linux/inorder-timing/simout index 2e799ebf3..4692f4932 100755 --- a/tests/quick/00.hello/ref/mips/linux/inorder-timing/simout +++ b/tests/quick/00.hello/ref/mips/linux/inorder-timing/simout @@ -1,3 +1,5 @@ +Redirecting stdout to build/MIPS_SE/tests/opt/quick/00.hello/mips/linux/inorder-timing/simout +Redirecting stderr to build/MIPS_SE/tests/opt/quick/00.hello/mips/linux/inorder-timing/simerr M5 Simulator System Copyright (c) 2001-2008 @@ -5,13 +7,13 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Jun 25 2010 15:39:33 -M5 revision 93b1ca421839+ 7482+ default qtip tip update_regr -M5 started Jun 25 2010 15:39:34 -M5 executing on zooks -command line: build/MIPS_SE/m5.fast -d build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/inorder-timing -re tests/run.py build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/inorder-timing +M5 compiled Aug 26 2010 12:56:28 +M5 revision 85cafc6ccb42 7662 default qtip tip sc-fail-fix +M5 started Aug 26 2010 12:56:32 +M5 executing on zizzer +command line: build/MIPS_SE/m5.opt -d build/MIPS_SE/tests/opt/quick/00.hello/mips/linux/inorder-timing -re tests/run.py build/MIPS_SE/tests/opt/quick/00.hello/mips/linux/inorder-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. Hello World! -Exiting @ tick 29206500 because target called exit() +Exiting @ tick 28659500 because target called exit() diff --git a/tests/quick/00.hello/ref/mips/linux/inorder-timing/stats.txt b/tests/quick/00.hello/ref/mips/linux/inorder-timing/stats.txt index dd117802e..18095c949 100644 --- a/tests/quick/00.hello/ref/mips/linux/inorder-timing/stats.txt +++ b/tests/quick/00.hello/ref/mips/linux/inorder-timing/stats.txt @@ -1,13 +1,13 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 22033 # Simulator instruction rate (inst/s) -host_mem_usage 154168 # Number of bytes of host memory used -host_seconds 0.26 # Real time elapsed on the host -host_tick_rate 110232758 # Simulator tick rate (ticks/s) +host_inst_rate 16536 # Simulator instruction rate (inst/s) +host_mem_usage 205460 # Number of bytes of host memory used +host_seconds 0.35 # Real time elapsed on the host +host_tick_rate 81268272 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 5827 # Number of instructions simulated sim_seconds 0.000029 # Number of seconds simulated -sim_ticks 29206500 # Number of ticks simulated +sim_ticks 28659500 # Number of ticks simulated system.cpu.AGEN-Unit.agens 2090 # Number of Address Generations system.cpu.Branch-Predictor.BTBHitPct 15.000000 # BTB Hit Percentage system.cpu.Branch-Predictor.BTBHits 24 # Number of BTB hits @@ -27,11 +27,11 @@ system.cpu.Execution-Unit.predictedNotTakenIncorrect 519 system.cpu.Execution-Unit.predictedTakenIncorrect 37 # Number of Branches Incorrectly Predicted As Taken. system.cpu.Mult-Div-Unit.divides 1 # Number of Divide Operations Executed system.cpu.Mult-Div-Unit.multiplies 3 # Number of Multipy Operations Executed -system.cpu.RegFile-Manager.regFileAccesses 10682 # Number of Total Accesses (Read+Write) to the Register File -system.cpu.RegFile-Manager.regFileReads 7272 # Number of Reads from Register File +system.cpu.RegFile-Manager.regFileAccesses 10688 # Number of Total Accesses (Read+Write) to the Register File +system.cpu.RegFile-Manager.regFileReads 7278 # Number of Reads from Register File system.cpu.RegFile-Manager.regFileWrites 3410 # Number of Writes to Register File -system.cpu.RegFile-Manager.regForwards 31 # Number of Registers Read Through Forwarding Logic -system.cpu.activity 20.277673 # Percentage of cycles cpu is active +system.cpu.RegFile-Manager.regForwards 25 # Number of Registers Read Through Forwarding Logic +system.cpu.activity 20.706560 # Percentage of cycles cpu is active system.cpu.comBranches 916 # Number of Branches instructions committed system.cpu.comFloats 0 # Number of Floating Point instructions committed system.cpu.comInts 2155 # Number of Integer instructions committed @@ -42,8 +42,8 @@ system.cpu.comStores 925 # Nu system.cpu.committedInsts 5827 # Number of Instructions Simulated (Per-Thread) system.cpu.committedInsts_total 5827 # Number of Instructions Simulated (Total) system.cpu.contextSwitches 1 # Number of context switches -system.cpu.cpi 10.024713 # CPI: Cycles Per Instruction (Per-Thread) -system.cpu.cpi_total 10.024713 # CPI: Total CPI of All Threads +system.cpu.cpi 9.836966 # CPI: Cycles Per Instruction (Per-Thread) +system.cpu.cpi_total 9.836966 # CPI: Total CPI of All Threads system.cpu.dcache.ReadReq_accesses 1164 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_avg_miss_latency 56229.885057 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency 53229.885057 # average ReadReq mshr miss latency @@ -55,15 +55,15 @@ system.cpu.dcache.ReadReq_mshr_miss_latency 4631000 # system.cpu.dcache.ReadReq_mshr_miss_rate 0.074742 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_misses 87 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 925 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 56265.625000 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53265.625000 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 861 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 3601000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.069189 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 64 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_miss_latency 3409000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.069189 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 64 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_avg_miss_latency 56254.901961 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53254.901961 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 874 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 2869000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.055135 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 51 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_miss_latency 2716000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate 0.055135 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses 51 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.dcache.avg_refs 14.137681 # Average number of references to valid blocks. @@ -73,39 +73,39 @@ system.cpu.dcache.blocked_cycles::no_mshrs 0 # system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.demand_accesses 2089 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 56245.033113 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 53245.033113 # average overall mshr miss latency -system.cpu.dcache.demand_hits 1938 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 8493000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.072283 # miss rate for demand accesses -system.cpu.dcache.demand_misses 151 # number of demand (read+write) misses +system.cpu.dcache.demand_avg_miss_latency 56239.130435 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 53239.130435 # average overall mshr miss latency +system.cpu.dcache.demand_hits 1951 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 7761000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.066060 # miss rate for demand accesses +system.cpu.dcache.demand_misses 138 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 8040000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.072283 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 151 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_miss_latency 7347000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.066060 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 138 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_%::0 0.021604 # Average percentage of cache occupancy -system.cpu.dcache.occ_blocks::0 88.491296 # Average occupied blocks per context +system.cpu.dcache.occ_%::0 0.021533 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::0 88.199028 # Average occupied blocks per context system.cpu.dcache.overall_accesses 2089 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 56245.033113 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 53245.033113 # average overall mshr miss latency +system.cpu.dcache.overall_avg_miss_latency 56239.130435 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 53239.130435 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 1938 # number of overall hits -system.cpu.dcache.overall_miss_latency 8493000 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.072283 # miss rate for overall accesses -system.cpu.dcache.overall_misses 151 # number of overall misses +system.cpu.dcache.overall_hits 1951 # number of overall hits +system.cpu.dcache.overall_miss_latency 7761000 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.066060 # miss rate for overall accesses +system.cpu.dcache.overall_misses 138 # number of overall misses system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 8040000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.072283 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 151 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_miss_latency 7347000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.066060 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 138 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.sampled_refs 138 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 88.491296 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 88.199028 # Cycle average of tags in use system.cpu.dcache.total_refs 1951 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 0 # number of writebacks @@ -118,64 +118,64 @@ system.cpu.dtb.read_misses 0 # DT system.cpu.dtb.write_accesses 0 # DTB write accesses system.cpu.dtb.write_hits 0 # DTB write hits system.cpu.dtb.write_misses 0 # DTB write misses -system.cpu.icache.ReadReq_accesses 5874 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 55801.980198 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 52801.980198 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 5571 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 16908000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.051583 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_accesses 5869 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 55795.379538 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 52795.379538 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 5566 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 16906000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.051627 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_misses 303 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_miss_latency 15999000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.051583 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_latency 15997000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.051627 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_misses 303 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.icache.avg_refs 18.386139 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 18.369637 # Average number of references to valid blocks. system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 5874 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 55801.980198 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 52801.980198 # average overall mshr miss latency -system.cpu.icache.demand_hits 5571 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 16908000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.051583 # miss rate for demand accesses +system.cpu.icache.demand_accesses 5869 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 55795.379538 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 52795.379538 # average overall mshr miss latency +system.cpu.icache.demand_hits 5566 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 16906000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.051627 # miss rate for demand accesses system.cpu.icache.demand_misses 303 # number of demand (read+write) misses system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 15999000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.051583 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_latency 15997000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0.051627 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_misses 303 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_%::0 0.066095 # Average percentage of cache occupancy -system.cpu.icache.occ_blocks::0 135.362853 # Average occupied blocks per context -system.cpu.icache.overall_accesses 5874 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 55801.980198 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 52801.980198 # average overall mshr miss latency +system.cpu.icache.occ_%::0 0.065748 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::0 134.651831 # Average occupied blocks per context +system.cpu.icache.overall_accesses 5869 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 55795.379538 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 52795.379538 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 5571 # number of overall hits -system.cpu.icache.overall_miss_latency 16908000 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.051583 # miss rate for overall accesses +system.cpu.icache.overall_hits 5566 # number of overall hits +system.cpu.icache.overall_miss_latency 16906000 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.051627 # miss rate for overall accesses system.cpu.icache.overall_misses 303 # number of overall misses system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 15999000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.051583 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_latency 15997000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0.051627 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_misses 303 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.icache.replacements 13 # number of replacements system.cpu.icache.sampled_refs 303 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 135.362853 # Cycle average of tags in use -system.cpu.icache.total_refs 5571 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 134.651831 # Cycle average of tags in use +system.cpu.icache.total_refs 5566 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idleCycles 46569 # Number of cycles cpu's stages were not processed -system.cpu.ipc 0.099753 # IPC: Instructions Per Cycle (Per-Thread) -system.cpu.ipc_total 0.099753 # IPC: Total IPC of All Threads +system.cpu.idleCycles 45451 # Number of cycles cpu's stages were not processed +system.cpu.ipc 0.101657 # IPC: Instructions Per Cycle (Per-Thread) +system.cpu.ipc_total 0.101657 # IPC: Total IPC of All Threads system.cpu.itb.accesses 0 # DTB accesses system.cpu.itb.hits 0 # DTB hits system.cpu.itb.misses 0 # DTB misses @@ -186,46 +186,37 @@ system.cpu.itb.write_accesses 0 # DT system.cpu.itb.write_hits 0 # DTB write hits system.cpu.itb.write_misses 0 # DTB write misses system.cpu.l2cache.ReadExReq_accesses 51 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency 52264.705882 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency 52254.901961 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40098.039216 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_miss_latency 2665500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency 2665000 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_misses 51 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_mshr_miss_latency 2045000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_misses 51 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadReq_accesses 390 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 52091.494845 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency 52086.340206 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40048.969072 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_hits 2 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 20211500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency 20209500 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_rate 0.994872 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_misses 388 # number of ReadReq misses system.cpu.l2cache.ReadReq_mshr_miss_latency 15539000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate 0.994872 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_misses 388 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_accesses 13 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_avg_miss_latency 52192.307692 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40153.846154 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_miss_latency 678500 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_misses 13 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_mshr_miss_latency 522000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_misses 13 # number of UpgradeReq MSHR misses system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 0.005333 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 0.005155 # Average number of references to valid blocks. system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.demand_accesses 441 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 52111.617312 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency 52105.922551 # average overall miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency 40054.669704 # average overall mshr miss latency system.cpu.l2cache.demand_hits 2 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 22877000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency 22874500 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_rate 0.995465 # miss rate for demand accesses system.cpu.l2cache.demand_misses 439 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits @@ -235,14 +226,14 @@ system.cpu.l2cache.demand_mshr_misses 439 # nu system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.occ_%::0 0.005708 # Average percentage of cache occupancy -system.cpu.l2cache.occ_blocks::0 187.032260 # Average occupied blocks per context +system.cpu.l2cache.occ_%::0 0.005821 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::0 190.726729 # Average occupied blocks per context system.cpu.l2cache.overall_accesses 441 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 52111.617312 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency 52105.922551 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 40054.669704 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.l2cache.overall_hits 2 # number of overall hits -system.cpu.l2cache.overall_miss_latency 22877000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency 22874500 # number of overall miss cycles system.cpu.l2cache.overall_miss_rate 0.995465 # miss rate for overall accesses system.cpu.l2cache.overall_misses 439 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits @@ -252,34 +243,34 @@ system.cpu.l2cache.overall_mshr_misses 439 # nu system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.sampled_refs 375 # Sample count of references to valid blocks. +system.cpu.l2cache.sampled_refs 388 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 187.032260 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 190.726729 # Cycle average of tags in use system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks -system.cpu.numCycles 58414 # number of cpu cycles simulated -system.cpu.runCycles 11845 # Number of cycles cpu stages are processed. +system.cpu.numCycles 57320 # number of cpu cycles simulated +system.cpu.runCycles 11869 # Number of cycles cpu stages are processed. system.cpu.smtCommittedInsts 0 # Number of SMT Instructions Simulated (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode system.cpu.smt_cpi no_value # CPI: Total SMT-CPI system.cpu.smt_ipc no_value # IPC: Total SMT-IPC -system.cpu.stage-0.idleCycles 52540 # Number of cycles 0 instructions are processed. -system.cpu.stage-0.runCycles 5874 # Number of cycles 1+ instructions are processed. -system.cpu.stage-0.utilization 10.055809 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage-1.idleCycles 52586 # Number of cycles 0 instructions are processed. +system.cpu.stage-0.idleCycles 51451 # Number of cycles 0 instructions are processed. +system.cpu.stage-0.runCycles 5869 # Number of cycles 1+ instructions are processed. +system.cpu.stage-0.utilization 10.239009 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage-1.idleCycles 51492 # Number of cycles 0 instructions are processed. system.cpu.stage-1.runCycles 5828 # Number of cycles 1+ instructions are processed. -system.cpu.stage-1.utilization 9.977060 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage-2.idleCycles 52582 # Number of cycles 0 instructions are processed. +system.cpu.stage-1.utilization 10.167481 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage-2.idleCycles 51488 # Number of cycles 0 instructions are processed. system.cpu.stage-2.runCycles 5832 # Number of cycles 1+ instructions are processed. -system.cpu.stage-2.utilization 9.983908 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage-3.idleCycles 56324 # Number of cycles 0 instructions are processed. +system.cpu.stage-2.utilization 10.174459 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage-3.idleCycles 55230 # Number of cycles 0 instructions are processed. system.cpu.stage-3.runCycles 2090 # Number of cycles 1+ instructions are processed. -system.cpu.stage-3.utilization 3.577909 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage-4.idleCycles 52587 # Number of cycles 0 instructions are processed. +system.cpu.stage-3.utilization 3.646197 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage-4.idleCycles 51493 # Number of cycles 0 instructions are processed. system.cpu.stage-4.runCycles 5827 # Number of cycles 1+ instructions are processed. -system.cpu.stage-4.utilization 9.975348 # Percentage of cycles stage was utilized (processing insts). -system.cpu.threadCycles 58414 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.stage-4.utilization 10.165736 # Percentage of cycles stage was utilized (processing insts). +system.cpu.threadCycles 57320 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.workload.PROG:num_syscalls 8 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/quick/00.hello/ref/mips/linux/o3-timing/simout b/tests/quick/00.hello/ref/mips/linux/o3-timing/simout index 17b9c89ad..5dcdeab67 100755 --- a/tests/quick/00.hello/ref/mips/linux/o3-timing/simout +++ b/tests/quick/00.hello/ref/mips/linux/o3-timing/simout @@ -1,5 +1,5 @@ -Redirecting stdout to build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/o3-timing/simout -Redirecting stderr to build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/o3-timing/simerr +Redirecting stdout to build/MIPS_SE/tests/opt/quick/00.hello/mips/linux/o3-timing/simout +Redirecting stderr to build/MIPS_SE/tests/opt/quick/00.hello/mips/linux/o3-timing/simerr M5 Simulator System Copyright (c) 2001-2008 @@ -7,13 +7,13 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Jun 6 2010 03:55:57 -M5 revision ba1a0193c050 7448 default tip -M5 started Jun 6 2010 03:56:00 +M5 compiled Aug 26 2010 12:56:28 +M5 revision 85cafc6ccb42 7662 default qtip tip sc-fail-fix +M5 started Aug 26 2010 12:56:32 M5 executing on zizzer -command line: build/MIPS_SE/m5.fast -d build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/o3-timing -re tests/run.py build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/o3-timing +command line: build/MIPS_SE/m5.opt -d build/MIPS_SE/tests/opt/quick/00.hello/mips/linux/o3-timing -re tests/run.py build/MIPS_SE/tests/opt/quick/00.hello/mips/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. Hello World! -Exiting @ tick 14021500 because target called exit() +Exiting @ tick 14010500 because target called exit() diff --git a/tests/quick/00.hello/ref/mips/linux/o3-timing/stats.txt b/tests/quick/00.hello/ref/mips/linux/o3-timing/stats.txt index 9cdd99a02..ed89de0db 100644 --- a/tests/quick/00.hello/ref/mips/linux/o3-timing/stats.txt +++ b/tests/quick/00.hello/ref/mips/linux/o3-timing/stats.txt @@ -1,41 +1,41 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 59393 # Simulator instruction rate (inst/s) -host_mem_usage 205240 # Number of bytes of host memory used +host_inst_rate 60755 # Simulator instruction rate (inst/s) +host_mem_usage 205968 # Number of bytes of host memory used host_seconds 0.09 # Real time elapsed on the host -host_tick_rate 160627549 # Simulator tick rate (ticks/s) +host_tick_rate 164238154 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 5169 # Number of instructions simulated sim_seconds 0.000014 # Number of seconds simulated -sim_ticks 14021500 # Number of ticks simulated +sim_ticks 14010500 # Number of ticks simulated system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.BPredUnit.BTBHits 546 # Number of BTB hits -system.cpu.BPredUnit.BTBLookups 1900 # Number of BTB lookups +system.cpu.BPredUnit.BTBLookups 1895 # Number of BTB lookups system.cpu.BPredUnit.RASInCorrect 66 # Number of incorrect RAS predictions. system.cpu.BPredUnit.condIncorrect 747 # Number of conditional branches incorrect -system.cpu.BPredUnit.condPredicted 1589 # Number of conditional branches predicted -system.cpu.BPredUnit.lookups 2405 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 1584 # Number of conditional branches predicted +system.cpu.BPredUnit.lookups 2400 # Number of BP lookups system.cpu.BPredUnit.usedRAS 400 # Number of times the RAS was used to get a target. system.cpu.commit.COM:branches 916 # Number of branches committed -system.cpu.commit.COM:bw_lim_events 69 # number cycles where commit BW limit reached +system.cpu.commit.COM:bw_lim_events 67 # number cycles where commit BW limit reached system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits -system.cpu.commit.COM:committed_per_cycle::samples 14488 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::mean 0.402126 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::stdev 1.127822 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::samples 14458 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::mean 0.402960 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::stdev 1.127371 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::0 11934 82.37% 82.37% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::1 1210 8.35% 90.72% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::2 523 3.61% 94.33% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::3 292 2.02% 96.35% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::4 294 2.03% 98.38% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::5 67 0.46% 98.84% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::0 11898 82.29% 82.29% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::1 1218 8.42% 90.72% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::2 521 3.60% 94.32% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::3 292 2.02% 96.34% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::4 296 2.05% 98.39% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::5 65 0.45% 98.84% # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::6 62 0.43% 99.27% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::7 37 0.26% 99.52% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::8 69 0.48% 100.00% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::7 39 0.27% 99.54% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::8 67 0.46% 100.00% # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::total 14488 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::total 14458 # Number of insts commited each cycle system.cpu.commit.COM:count 5826 # Number of instructions committed system.cpu.commit.COM:loads 1164 # Number of loads committed system.cpu.commit.COM:membars 0 # Number of memory barriers committed @@ -44,85 +44,85 @@ system.cpu.commit.COM:swp_count 0 # Nu system.cpu.commit.branchMispredicts 616 # The number of times a branch was mispredicted system.cpu.commit.commitCommittedInsts 5826 # The number of committed instructions system.cpu.commit.commitNonSpecStalls 10 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 5972 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 5944 # The number of squashed insts skipped by commit system.cpu.committedInsts 5169 # Number of Instructions Simulated system.cpu.committedInsts_total 5169 # Number of Instructions Simulated -system.cpu.cpi 5.425421 # CPI: Cycles Per Instruction -system.cpu.cpi_total 5.425421 # CPI: Total CPI of All Threads -system.cpu.dcache.ReadReq_accesses 2310 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 34156.716418 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 36032.967033 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 2176 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 4577000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.058009 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 134 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits 43 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency 3279000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.039394 # mshr miss rate for ReadReq accesses +system.cpu.cpi 5.421165 # CPI: Cycles Per Instruction +system.cpu.cpi_total 5.421165 # CPI: Total CPI of All Threads +system.cpu.dcache.ReadReq_accesses 2307 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 34750 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 36021.978022 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 2179 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 4448000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.055483 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 128 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_hits 37 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_miss_latency 3278000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.039445 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_misses 91 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 925 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 27570.707071 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 36046.875000 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 628 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 8188500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.321081 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 297 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_hits 233 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency 2307000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.069189 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 64 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_avg_miss_latency 27330.827068 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 36160 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 659 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 7270000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.287568 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 266 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_hits 216 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_miss_latency 1808000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate 0.054054 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses 50 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 20.148936 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 20.127660 # Average number of references to valid blocks. system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 3235 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 29618.329466 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 36038.709677 # average overall mshr miss latency -system.cpu.dcache.demand_hits 2804 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 12765500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.133230 # miss rate for demand accesses -system.cpu.dcache.demand_misses 431 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 276 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 5586000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.047913 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 155 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_accesses 3232 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 29741.116751 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 36070.921986 # average overall mshr miss latency +system.cpu.dcache.demand_hits 2838 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 11718000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.121906 # miss rate for demand accesses +system.cpu.dcache.demand_misses 394 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 253 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 5086000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.043626 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 141 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_%::0 0.022304 # Average percentage of cache occupancy -system.cpu.dcache.occ_blocks::0 91.357241 # Average occupied blocks per context -system.cpu.dcache.overall_accesses 3235 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 29618.329466 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 36038.709677 # average overall mshr miss latency +system.cpu.dcache.occ_%::0 0.022299 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::0 91.337822 # Average occupied blocks per context +system.cpu.dcache.overall_accesses 3232 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 29741.116751 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 36070.921986 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 2804 # number of overall hits -system.cpu.dcache.overall_miss_latency 12765500 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.133230 # miss rate for overall accesses -system.cpu.dcache.overall_misses 431 # number of overall misses -system.cpu.dcache.overall_mshr_hits 276 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 5586000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.047913 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 155 # number of overall MSHR misses +system.cpu.dcache.overall_hits 2838 # number of overall hits +system.cpu.dcache.overall_miss_latency 11718000 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.121906 # miss rate for overall accesses +system.cpu.dcache.overall_misses 394 # number of overall misses +system.cpu.dcache.overall_mshr_hits 253 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 5086000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.043626 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 141 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.sampled_refs 141 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 91.357241 # Cycle average of tags in use -system.cpu.dcache.total_refs 2841 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 91.337822 # Cycle average of tags in use +system.cpu.dcache.total_refs 2838 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 0 # number of writebacks -system.cpu.decode.DECODE:BlockedCycles 521 # Number of cycles decode is blocked +system.cpu.decode.DECODE:BlockedCycles 514 # Number of cycles decode is blocked system.cpu.decode.DECODE:BranchMispred 138 # Number of times decode detected a branch misprediction system.cpu.decode.DECODE:BranchResolved 138 # Number of times decode resolved a branch -system.cpu.decode.DECODE:DecodedInsts 14337 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 10064 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 3903 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 1073 # Number of cycles decode is squashing +system.cpu.decode.DECODE:DecodedInsts 14307 # Number of instructions handled by decode +system.cpu.decode.DECODE:IdleCycles 10045 # Number of cycles decode is idle +system.cpu.decode.DECODE:RunCycles 3899 # Number of cycles decode is running +system.cpu.decode.DECODE:SquashCycles 1070 # Number of cycles decode is squashing system.cpu.decode.DECODE:SquashedInsts 267 # Number of squashed instructions handled by decode system.cpu.dtb.accesses 0 # DTB accesses system.cpu.dtb.hits 0 # DTB hits @@ -133,118 +133,118 @@ system.cpu.dtb.read_misses 0 # DT system.cpu.dtb.write_accesses 0 # DTB write accesses system.cpu.dtb.write_hits 0 # DTB write hits system.cpu.dtb.write_misses 0 # DTB write misses -system.cpu.fetch.Branches 2405 # Number of branches that fetch encountered -system.cpu.fetch.CacheLines 2216 # Number of cache lines fetched -system.cpu.fetch.Cycles 6303 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.IcacheSquashes 358 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.Insts 15547 # Number of instructions fetch has processed -system.cpu.fetch.SquashCycles 763 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.085758 # Number of branch fetches per cycle -system.cpu.fetch.icacheStallCycles 2216 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Branches 2400 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 2213 # Number of cache lines fetched +system.cpu.fetch.Cycles 6297 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 357 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.Insts 15518 # Number of instructions fetch has processed +system.cpu.fetch.SquashCycles 762 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.085647 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 2213 # Number of cycles fetch is stalled on an Icache miss system.cpu.fetch.predictedBranches 946 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 0.554379 # Number of inst fetches per cycle -system.cpu.fetch.rateDist::samples 15561 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.999100 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.261901 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rate 0.553779 # Number of inst fetches per cycle +system.cpu.fetch.rateDist::samples 15528 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.999356 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.261429 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 11491 73.84% 73.84% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1812 11.64% 85.49% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 195 1.25% 86.74% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 11461 73.81% 73.81% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1813 11.68% 85.48% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 195 1.26% 86.74% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::3 140 0.90% 87.64% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::4 320 2.06% 89.70% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 114 0.73% 90.43% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 289 1.86% 92.29% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 259 1.66% 93.95% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 941 6.05% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 114 0.73% 90.44% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 288 1.85% 92.29% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 259 1.67% 93.96% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 938 6.04% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 15561 # Number of instructions fetched each cycle (Total) -system.cpu.icache.ReadReq_accesses 2216 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 35687.203791 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 34908.814590 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 1794 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 15060000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.190433 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 422 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_hits 93 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 11485000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.148466 # mshr miss rate for ReadReq accesses +system.cpu.fetch.rateDist::total 15528 # Number of instructions fetched each cycle (Total) +system.cpu.icache.ReadReq_accesses 2213 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 35692.399050 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 34907.294833 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 1792 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 15026500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.190239 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 421 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_hits 92 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_miss_latency 11484500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.148667 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_misses 329 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.icache.avg_refs 5.452888 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 5.446809 # Average number of references to valid blocks. system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 2216 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 35687.203791 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 34908.814590 # average overall mshr miss latency -system.cpu.icache.demand_hits 1794 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 15060000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.190433 # miss rate for demand accesses -system.cpu.icache.demand_misses 422 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 93 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 11485000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.148466 # mshr miss rate for demand accesses +system.cpu.icache.demand_accesses 2213 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 35692.399050 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 34907.294833 # average overall mshr miss latency +system.cpu.icache.demand_hits 1792 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 15026500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.190239 # miss rate for demand accesses +system.cpu.icache.demand_misses 421 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 92 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 11484500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0.148667 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_misses 329 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_%::0 0.076241 # Average percentage of cache occupancy -system.cpu.icache.occ_blocks::0 156.140617 # Average occupied blocks per context -system.cpu.icache.overall_accesses 2216 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 35687.203791 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 34908.814590 # average overall mshr miss latency +system.cpu.icache.occ_%::0 0.076220 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::0 156.098402 # Average occupied blocks per context +system.cpu.icache.overall_accesses 2213 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 35692.399050 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 34907.294833 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 1794 # number of overall hits -system.cpu.icache.overall_miss_latency 15060000 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.190433 # miss rate for overall accesses -system.cpu.icache.overall_misses 422 # number of overall misses -system.cpu.icache.overall_mshr_hits 93 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 11485000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.148466 # mshr miss rate for overall accesses +system.cpu.icache.overall_hits 1792 # number of overall hits +system.cpu.icache.overall_miss_latency 15026500 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.190239 # miss rate for overall accesses +system.cpu.icache.overall_misses 421 # number of overall misses +system.cpu.icache.overall_mshr_hits 92 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 11484500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0.148667 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_misses 329 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.icache.replacements 16 # number of replacements system.cpu.icache.sampled_refs 329 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 156.140617 # Cycle average of tags in use -system.cpu.icache.total_refs 1794 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 156.098402 # Cycle average of tags in use +system.cpu.icache.total_refs 1792 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idleCycles 12483 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.EXEC:branches 1268 # Number of branches executed -system.cpu.iew.EXEC:nop 1827 # number of nop insts executed -system.cpu.iew.EXEC:rate 0.295643 # Inst execution rate -system.cpu.iew.EXEC:refs 3444 # number of memory reference insts executed -system.cpu.iew.EXEC:stores 1049 # Number of stores executed +system.cpu.idleCycles 12494 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.EXEC:branches 1265 # Number of branches executed +system.cpu.iew.EXEC:nop 1823 # number of nop insts executed +system.cpu.iew.EXEC:rate 0.295232 # Inst execution rate +system.cpu.iew.EXEC:refs 3434 # number of memory reference insts executed +system.cpu.iew.EXEC:stores 1042 # Number of stores executed system.cpu.iew.EXEC:swp 0 # number of swp insts executed -system.cpu.iew.WB:consumers 4139 # num instructions consuming a value -system.cpu.iew.WB:count 7538 # cumulative count of insts written-back -system.cpu.iew.WB:fanout 0.704035 # average fanout of values written-back +system.cpu.iew.WB:consumers 4130 # num instructions consuming a value +system.cpu.iew.WB:count 7520 # cumulative count of insts written-back +system.cpu.iew.WB:fanout 0.704843 # average fanout of values written-back system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 2914 # num instructions producing a value -system.cpu.iew.WB:rate 0.268792 # insts written-back per cycle -system.cpu.iew.WB:sent 7625 # cumulative count of insts sent to commit -system.cpu.iew.branchMispredicts 679 # Number of branch mispredicts detected at execute +system.cpu.iew.WB:producers 2911 # num instructions producing a value +system.cpu.iew.WB:rate 0.268361 # insts written-back per cycle +system.cpu.iew.WB:sent 7608 # cumulative count of insts sent to commit +system.cpu.iew.branchMispredicts 678 # Number of branch mispredicts detected at execute system.cpu.iew.iewBlockCycles 0 # Number of cycles IEW is blocking -system.cpu.iew.iewDispLoadInsts 2797 # Number of dispatched load instructions +system.cpu.iew.iewDispLoadInsts 2792 # Number of dispatched load instructions system.cpu.iew.iewDispNonSpecInsts 12 # Number of dispatched non-speculative instructions system.cpu.iew.iewDispSquashedInsts 953 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispStoreInsts 1159 # Number of dispatched store instructions -system.cpu.iew.iewDispatchedInsts 11802 # Number of instructions dispatched to IQ -system.cpu.iew.iewExecLoadInsts 2395 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 544 # Number of squashed instructions skipped in execute -system.cpu.iew.iewExecutedInsts 8291 # Number of executed instructions +system.cpu.iew.iewDispStoreInsts 1150 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 11774 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 2392 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 540 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 8273 # Number of executed instructions system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.iewSquashCycles 1073 # Number of cycles IEW is squashing +system.cpu.iew.iewSquashCycles 1070 # Number of cycles IEW is squashing system.cpu.iew.iewUnblockCycles 0 # Number of cycles IEW is unblocking system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked @@ -252,71 +252,71 @@ system.cpu.iew.lsq.thread.0.forwLoads 67 # Nu system.cpu.iew.lsq.thread.0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.0.memOrderViolation 22 # Number of memory ordering violations +system.cpu.iew.lsq.thread.0.memOrderViolation 19 # Number of memory ordering violations system.cpu.iew.lsq.thread.0.rescheduledLoads 0 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 1633 # Number of loads squashed -system.cpu.iew.lsq.thread.0.squashedStores 234 # Number of stores squashed -system.cpu.iew.memOrderViolationEvents 22 # Number of memory order violations -system.cpu.iew.predictedNotTakenIncorrect 284 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.lsq.thread.0.squashedLoads 1628 # Number of loads squashed +system.cpu.iew.lsq.thread.0.squashedStores 225 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 19 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 283 # Number of branches that were predicted not taken incorrectly system.cpu.iew.predictedTakenIncorrect 395 # Number of branches that were predicted taken incorrectly -system.cpu.ipc 0.184318 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.184318 # IPC: Total IPC of All Threads +system.cpu.ipc 0.184462 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.184462 # IPC: Total IPC of All Threads system.cpu.iq.ISSUE:FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntAlu 5173 58.55% 58.55% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntMult 5 0.06% 58.61% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntDiv 2 0.02% 58.63% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatAdd 2 0.02% 58.65% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 58.65% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 58.65% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 58.65% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 58.65% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 58.65% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::MemRead 2589 29.30% 87.96% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::MemWrite 1064 12.04% 100.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntAlu 5164 58.60% 58.60% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntMult 5 0.06% 58.65% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntDiv 2 0.02% 58.67% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatAdd 2 0.02% 58.70% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 58.70% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 58.70% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 58.70% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 58.70% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 58.70% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::MemRead 2584 29.32% 88.02% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::MemWrite 1056 11.98% 100.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::total 8835 # Type of FU issued -system.cpu.iq.ISSUE:fu_busy_cnt 162 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_rate 0.018336 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:FU_type_0::total 8813 # Type of FU issued +system.cpu.iq.ISSUE:fu_busy_cnt 160 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_rate 0.018155 # FU busy rate (busy events/executed inst) system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntAlu 8 4.94% 4.94% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 4.94% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 4.94% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 4.94% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 4.94% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 4.94% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 4.94% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 4.94% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 4.94% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::MemRead 100 61.73% 66.67% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::MemWrite 54 33.33% 100.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntAlu 8 5.00% 5.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 5.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 5.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 5.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 5.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 5.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 5.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 5.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 5.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::MemRead 100 62.50% 67.50% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::MemWrite 52 32.50% 100.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:issued_per_cycle::samples 15561 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::mean 0.567766 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.217819 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::samples 15528 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::mean 0.567555 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.215524 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::0 11605 74.58% 74.58% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::1 1745 11.21% 85.79% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::2 791 5.08% 90.87% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::3 727 4.67% 95.55% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::4 340 2.18% 97.73% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::5 213 1.37% 99.10% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::6 93 0.60% 99.70% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::7 32 0.21% 99.90% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::0 11574 74.54% 74.54% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::1 1747 11.25% 85.79% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::2 792 5.10% 90.89% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::3 724 4.66% 95.55% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::4 342 2.20% 97.75% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::5 211 1.36% 99.11% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::6 94 0.61% 99.72% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::7 29 0.19% 99.90% # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::8 15 0.10% 100.00% # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::total 15561 # Number of insts issued each cycle -system.cpu.iq.ISSUE:rate 0.315041 # Inst issue rate -system.cpu.iq.iqInstsAdded 9963 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 8835 # Number of instructions issued +system.cpu.iq.ISSUE:issued_per_cycle::total 15528 # Number of insts issued each cycle +system.cpu.iq.ISSUE:rate 0.314503 # Inst issue rate +system.cpu.iq.iqInstsAdded 9939 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 8813 # Number of instructions issued system.cpu.iq.iqNonSpecInstsAdded 12 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 4119 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsExamined 4094 # Number of squashed instructions iterated over during squash; mainly for profiling system.cpu.iq.iqSquashedInstsIssued 38 # Number of squashed instructions issued system.cpu.iq.iqSquashedNonSpecRemoved 2 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 2680 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedOperandsExamined 2672 # Number of squashed operands that are examined and possibly removed from graph system.cpu.itb.accesses 0 # DTB accesses system.cpu.itb.hits 0 # DTB hits system.cpu.itb.misses 0 # DTB misses @@ -336,37 +336,28 @@ system.cpu.l2cache.ReadExReq_mshr_miss_latency 1568000 system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_misses 50 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadReq_accesses 420 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 34317.307692 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency 34319.711538 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31133.413462 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_hits 4 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 14276000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency 14277000 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_rate 0.990476 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_misses 416 # number of ReadReq misses system.cpu.l2cache.ReadReq_mshr_miss_latency 12951500 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate 0.990476 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_misses 416 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_accesses 14 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_avg_miss_latency 34428.571429 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31178.571429 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_miss_latency 482000 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_misses 14 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_mshr_miss_latency 436500 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_misses 14 # number of UpgradeReq MSHR misses system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 0.009950 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 0.009615 # Average number of references to valid blocks. system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.demand_accesses 470 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 34356.223176 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency 34358.369099 # average overall miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency 31157.725322 # average overall mshr miss latency system.cpu.l2cache.demand_hits 4 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 16010000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency 16011000 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_rate 0.991489 # miss rate for demand accesses system.cpu.l2cache.demand_misses 466 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits @@ -376,14 +367,14 @@ system.cpu.l2cache.demand_mshr_misses 466 # nu system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.occ_%::0 0.006418 # Average percentage of cache occupancy -system.cpu.l2cache.occ_blocks::0 210.308968 # Average occupied blocks per context +system.cpu.l2cache.occ_%::0 0.006586 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::0 215.818258 # Average occupied blocks per context system.cpu.l2cache.overall_accesses 470 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 34356.223176 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency 34358.369099 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 31157.725322 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.l2cache.overall_hits 4 # number of overall hits -system.cpu.l2cache.overall_miss_latency 16010000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency 16011000 # number of overall miss cycles system.cpu.l2cache.overall_miss_rate 0.991489 # miss rate for overall accesses system.cpu.l2cache.overall_misses 466 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits @@ -393,33 +384,33 @@ system.cpu.l2cache.overall_mshr_misses 466 # nu system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.sampled_refs 402 # Sample count of references to valid blocks. +system.cpu.l2cache.sampled_refs 416 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 210.308968 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 215.818258 # Cycle average of tags in use system.cpu.l2cache.total_refs 4 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.memDep0.conflictingLoads 5 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 2 # Number of conflicting stores. -system.cpu.memDep0.insertedLoads 2797 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1159 # Number of stores inserted to the mem dependence unit. -system.cpu.numCycles 28044 # number of cpu cycles simulated -system.cpu.rename.RENAME:BlockCycles 5 # Number of cycles rename is blocking +system.cpu.memDep0.insertedLoads 2792 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1150 # Number of stores inserted to the mem dependence unit. +system.cpu.numCycles 28022 # number of cpu cycles simulated +system.cpu.rename.RENAME:BlockCycles 4 # Number of cycles rename is blocking system.cpu.rename.RENAME:CommittedMaps 3410 # Number of HB maps that are committed -system.cpu.rename.RENAME:IdleCycles 10455 # Number of cycles rename is idle -system.cpu.rename.RENAME:LSQFullEvents 9 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RENAME:RenameLookups 15765 # Number of register rename lookups that rename has made -system.cpu.rename.RENAME:RenamedInsts 13587 # Number of instructions processed by rename -system.cpu.rename.RENAME:RenamedOperands 8333 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 3513 # Number of cycles rename is running -system.cpu.rename.RENAME:SquashCycles 1073 # Number of cycles rename is squashing -system.cpu.rename.RENAME:UnblockCycles 19 # Number of cycles rename is unblocking -system.cpu.rename.RENAME:UndoneMaps 4923 # Number of HB maps that are undone due to squashing -system.cpu.rename.RENAME:serializeStallCycles 496 # count of cycles rename stalled for serializing inst +system.cpu.rename.RENAME:IdleCycles 10436 # Number of cycles rename is idle +system.cpu.rename.RENAME:LSQFullEvents 5 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RENAME:RenameLookups 15725 # Number of register rename lookups that rename has made +system.cpu.rename.RENAME:RenamedInsts 13557 # Number of instructions processed by rename +system.cpu.rename.RENAME:RenamedOperands 8322 # Number of destination operands rename has renamed +system.cpu.rename.RENAME:RunCycles 3509 # Number of cycles rename is running +system.cpu.rename.RENAME:SquashCycles 1070 # Number of cycles rename is squashing +system.cpu.rename.RENAME:UnblockCycles 15 # Number of cycles rename is unblocking +system.cpu.rename.RENAME:UndoneMaps 4912 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:serializeStallCycles 494 # count of cycles rename stalled for serializing inst system.cpu.rename.RENAME:serializingInsts 17 # count of serializing insts renamed -system.cpu.rename.RENAME:skidInsts 111 # count of insts added to the skid buffer +system.cpu.rename.RENAME:skidInsts 104 # count of insts added to the skid buffer system.cpu.rename.RENAME:tempSerializingInsts 11 # count of temporary serializing insts renamed -system.cpu.timesIdled 249 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.timesIdled 247 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.workload.PROG:num_syscalls 8 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/quick/00.hello/ref/mips/linux/simple-timing/config.ini b/tests/quick/00.hello/ref/mips/linux/simple-timing/config.ini index b04189060..e2f4de6ac 100644 --- a/tests/quick/00.hello/ref/mips/linux/simple-timing/config.ini +++ b/tests/quick/00.hello/ref/mips/linux/simple-timing/config.ini @@ -211,7 +211,7 @@ egid=100 env= errout=cerr euid=100 -executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/hello/bin/mips/linux/hello +executable=/dist/m5/regression/test-progs/hello/bin/mips/linux/hello gid=100 input=cin max_stack_size=67108864 diff --git a/tests/quick/00.hello/ref/mips/linux/simple-timing/simout b/tests/quick/00.hello/ref/mips/linux/simple-timing/simout index 31e8564a2..bfd8a31fc 100755 --- a/tests/quick/00.hello/ref/mips/linux/simple-timing/simout +++ b/tests/quick/00.hello/ref/mips/linux/simple-timing/simout @@ -1,3 +1,5 @@ +Redirecting stdout to build/MIPS_SE/tests/opt/quick/00.hello/mips/linux/simple-timing/simout +Redirecting stderr to build/MIPS_SE/tests/opt/quick/00.hello/mips/linux/simple-timing/simerr M5 Simulator System Copyright (c) 2001-2008 @@ -5,13 +7,13 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 24 2010 23:13:04 -M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip -M5 started Feb 25 2010 03:11:22 -M5 executing on SC2B0619 -command line: build/MIPS_SE/m5.fast -d build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/simple-timing -re tests/run.py build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/simple-timing +M5 compiled Aug 26 2010 12:56:28 +M5 revision 85cafc6ccb42 7662 default qtip tip sc-fail-fix +M5 started Aug 26 2010 12:56:30 +M5 executing on zizzer +command line: build/MIPS_SE/m5.opt -d build/MIPS_SE/tests/opt/quick/00.hello/mips/linux/simple-timing -re tests/run.py build/MIPS_SE/tests/opt/quick/00.hello/mips/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. Hello World! -Exiting @ tick 32803000 because target called exit() +Exiting @ tick 32088000 because target called exit() diff --git a/tests/quick/00.hello/ref/mips/linux/simple-timing/stats.txt b/tests/quick/00.hello/ref/mips/linux/simple-timing/stats.txt index 5c8b8dc04..f4ea21892 100644 --- a/tests/quick/00.hello/ref/mips/linux/simple-timing/stats.txt +++ b/tests/quick/00.hello/ref/mips/linux/simple-timing/stats.txt @@ -1,13 +1,13 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 534293 # Simulator instruction rate (inst/s) -host_mem_usage 190944 # Number of bytes of host memory used -host_seconds 0.01 # Real time elapsed on the host -host_tick_rate 2928316372 # Simulator tick rate (ticks/s) +host_inst_rate 5098 # Simulator instruction rate (inst/s) +host_mem_usage 204896 # Number of bytes of host memory used +host_seconds 1.14 # Real time elapsed on the host +host_tick_rate 28066026 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 5827 # Number of instructions simulated -sim_seconds 0.000033 # Number of seconds simulated -sim_ticks 32803000 # Number of ticks simulated +sim_seconds 0.000032 # Number of seconds simulated +sim_ticks 32088000 # Number of ticks simulated system.cpu.dcache.ReadReq_accesses 1164 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_avg_miss_latency 56000 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency 53000 # average ReadReq mshr miss latency @@ -21,13 +21,13 @@ system.cpu.dcache.ReadReq_mshr_misses 87 # nu system.cpu.dcache.WriteReq_accesses 925 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_avg_miss_latency 56000 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53000 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 861 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 3584000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.069189 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 64 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_miss_latency 3392000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.069189 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 64 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_hits 874 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 2856000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.055135 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 51 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_miss_latency 2703000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate 0.055135 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses 51 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.dcache.avg_refs 14.137681 # Average number of references to valid blocks. @@ -39,37 +39,37 @@ system.cpu.dcache.cache_copies 0 # nu system.cpu.dcache.demand_accesses 2089 # number of demand (read+write) accesses system.cpu.dcache.demand_avg_miss_latency 56000 # average overall miss latency system.cpu.dcache.demand_avg_mshr_miss_latency 53000 # average overall mshr miss latency -system.cpu.dcache.demand_hits 1938 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 8456000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.072283 # miss rate for demand accesses -system.cpu.dcache.demand_misses 151 # number of demand (read+write) misses +system.cpu.dcache.demand_hits 1951 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 7728000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.066060 # miss rate for demand accesses +system.cpu.dcache.demand_misses 138 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 8003000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.072283 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 151 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_miss_latency 7314000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.066060 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 138 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_%::0 0.021457 # Average percentage of cache occupancy -system.cpu.dcache.occ_blocks::0 87.887695 # Average occupied blocks per context +system.cpu.dcache.occ_%::0 0.021352 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::0 87.458397 # Average occupied blocks per context system.cpu.dcache.overall_accesses 2089 # number of overall (read+write) accesses system.cpu.dcache.overall_avg_miss_latency 56000 # average overall miss latency system.cpu.dcache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 1938 # number of overall hits -system.cpu.dcache.overall_miss_latency 8456000 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.072283 # miss rate for overall accesses -system.cpu.dcache.overall_misses 151 # number of overall misses +system.cpu.dcache.overall_hits 1951 # number of overall hits +system.cpu.dcache.overall_miss_latency 7728000 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.066060 # miss rate for overall accesses +system.cpu.dcache.overall_misses 138 # number of overall misses system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 8003000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.072283 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 151 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_miss_latency 7314000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.066060 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 138 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.sampled_refs 138 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 87.887695 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 87.458397 # Cycle average of tags in use system.cpu.dcache.total_refs 1951 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 0 # number of writebacks @@ -114,8 +114,8 @@ system.cpu.icache.demand_mshr_misses 303 # nu system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_%::0 0.065174 # Average percentage of cache occupancy -system.cpu.icache.occ_blocks::0 133.475693 # Average occupied blocks per context +system.cpu.icache.occ_%::0 0.064694 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::0 132.493866 # Average occupied blocks per context system.cpu.icache.overall_accesses 5829 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency 55722.772277 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 52722.772277 # average overall mshr miss latency @@ -133,7 +133,7 @@ system.cpu.icache.overall_mshr_uncacheable_misses 0 system.cpu.icache.replacements 13 # number of replacements system.cpu.icache.sampled_refs 303 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 133.475693 # Cycle average of tags in use +system.cpu.icache.tagsinuse 132.493866 # Cycle average of tags in use system.cpu.icache.total_refs 5526 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks @@ -166,18 +166,9 @@ system.cpu.l2cache.ReadReq_misses 388 # nu system.cpu.l2cache.ReadReq_mshr_miss_latency 15520000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate 0.994872 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_misses 388 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_accesses 13 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_avg_miss_latency 52000 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_miss_latency 676000 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_misses 13 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_mshr_miss_latency 520000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_misses 13 # number of UpgradeReq MSHR misses system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 0.005333 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 0.005155 # Average number of references to valid blocks. system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked @@ -197,8 +188,8 @@ system.cpu.l2cache.demand_mshr_misses 439 # nu system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.occ_%::0 0.005638 # Average percentage of cache occupancy -system.cpu.l2cache.occ_blocks::0 184.758016 # Average occupied blocks per context +system.cpu.l2cache.occ_%::0 0.005739 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::0 188.045319 # Average occupied blocks per context system.cpu.l2cache.overall_accesses 441 # number of overall (read+write) accesses system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency @@ -214,14 +205,14 @@ system.cpu.l2cache.overall_mshr_misses 439 # nu system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.sampled_refs 375 # Sample count of references to valid blocks. +system.cpu.l2cache.sampled_refs 388 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 184.758016 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 188.045319 # Cycle average of tags in use system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 65606 # number of cpu cycles simulated +system.cpu.numCycles 64176 # number of cpu cycles simulated system.cpu.num_insts 5827 # Number of instructions executed system.cpu.num_refs 2090 # Number of memory references system.cpu.workload.PROG:num_syscalls 8 # Number of system calls diff --git a/tests/quick/00.hello/ref/power/linux/o3-timing/simerr b/tests/quick/00.hello/ref/power/linux/o3-timing/simerr index 91e0a0356..d552956c6 100755 --- a/tests/quick/00.hello/ref/power/linux/o3-timing/simerr +++ b/tests/quick/00.hello/ref/power/linux/o3-timing/simerr @@ -1,5 +1,5 @@ warn: Sockets disabled, not accepting gdb connections For more information see: http://www.m5sim.org/warn/d946bea6 -warn: allowing mmap of file @ fd 17982776. This will break if not /dev/zero. +warn: allowing mmap of file @ fd 16785032. This will break if not /dev/zero. For more information see: http://www.m5sim.org/warn/3a2134f6 hack: be nice to actually delete the event here diff --git a/tests/quick/00.hello/ref/power/linux/o3-timing/simout b/tests/quick/00.hello/ref/power/linux/o3-timing/simout index b9932c144..f838ffb8f 100755 --- a/tests/quick/00.hello/ref/power/linux/o3-timing/simout +++ b/tests/quick/00.hello/ref/power/linux/o3-timing/simout @@ -1,5 +1,5 @@ -Redirecting stdout to build/POWER_SE/tests/fast/quick/00.hello/power/linux/o3-timing/simout -Redirecting stderr to build/POWER_SE/tests/fast/quick/00.hello/power/linux/o3-timing/simerr +Redirecting stdout to build/POWER_SE/tests/opt/quick/00.hello/power/linux/o3-timing/simout +Redirecting stderr to build/POWER_SE/tests/opt/quick/00.hello/power/linux/o3-timing/simerr M5 Simulator System Copyright (c) 2001-2008 @@ -7,12 +7,12 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Jun 6 2010 03:59:10 -M5 revision ba1a0193c050 7448 default tip -M5 started Jun 6 2010 03:59:12 +M5 compiled Aug 26 2010 12:59:22 +M5 revision 85cafc6ccb42 7662 default qtip tip sc-fail-fix +M5 started Aug 26 2010 12:59:25 M5 executing on zizzer -command line: build/POWER_SE/m5.fast -d build/POWER_SE/tests/fast/quick/00.hello/power/linux/o3-timing -re tests/run.py build/POWER_SE/tests/fast/quick/00.hello/power/linux/o3-timing +command line: build/POWER_SE/m5.opt -d build/POWER_SE/tests/opt/quick/00.hello/power/linux/o3-timing -re tests/run.py build/POWER_SE/tests/opt/quick/00.hello/power/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... Hello world! -Exiting @ tick 11864500 because target called exit() +Exiting @ tick 11733000 because target called exit() diff --git a/tests/quick/00.hello/ref/power/linux/o3-timing/stats.txt b/tests/quick/00.hello/ref/power/linux/o3-timing/stats.txt index e78679f83..914654ad0 100644 --- a/tests/quick/00.hello/ref/power/linux/o3-timing/stats.txt +++ b/tests/quick/00.hello/ref/power/linux/o3-timing/stats.txt @@ -1,13 +1,13 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 82571 # Simulator instruction rate (inst/s) -host_mem_usage 202992 # Number of bytes of host memory used -host_seconds 0.07 # Real time elapsed on the host -host_tick_rate 168278845 # Simulator tick rate (ticks/s) +host_inst_rate 8561 # Simulator instruction rate (inst/s) +host_mem_usage 202624 # Number of bytes of host memory used +host_seconds 0.68 # Real time elapsed on the host +host_tick_rate 17311106 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 5800 # Number of instructions simulated sim_seconds 0.000012 # Number of seconds simulated -sim_ticks 11864500 # Number of ticks simulated +sim_ticks 11733000 # Number of ticks simulated system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.BPredUnit.BTBHits 687 # Number of BTB hits system.cpu.BPredUnit.BTBLookups 1888 # Number of BTB lookups @@ -19,23 +19,23 @@ system.cpu.BPredUnit.usedRAS 189 # Nu system.cpu.commit.COM:branches 1038 # Number of branches committed system.cpu.commit.COM:bw_lim_events 51 # number cycles where commit BW limit reached system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits -system.cpu.commit.COM:committed_per_cycle::samples 10785 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::mean 0.537784 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::stdev 1.251292 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::samples 10473 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::mean 0.553805 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::stdev 1.272090 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::0 8225 76.26% 76.26% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::1 1129 10.47% 86.73% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::2 673 6.24% 92.97% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::3 258 2.39% 95.36% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::4 226 2.10% 97.46% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::5 120 1.11% 98.57% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::6 82 0.76% 99.33% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::7 21 0.19% 99.53% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::8 51 0.47% 100.00% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::0 7930 75.72% 75.72% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::1 1118 10.68% 86.39% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::2 663 6.33% 92.72% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::3 256 2.44% 95.17% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::4 224 2.14% 97.31% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::5 123 1.17% 98.48% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::6 87 0.83% 99.31% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::7 21 0.20% 99.51% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::8 51 0.49% 100.00% # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::total 10785 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::total 10473 # Number of insts commited each cycle system.cpu.commit.COM:count 5800 # Number of instructions committed system.cpu.commit.COM:loads 962 # Number of loads committed system.cpu.commit.COM:membars 7 # Number of memory barriers committed @@ -47,30 +47,30 @@ system.cpu.commit.commitNonSpecStalls 16 # Th system.cpu.commit.commitSquashedInsts 3389 # The number of squashed insts skipped by commit system.cpu.committedInsts 5800 # Number of Instructions Simulated system.cpu.committedInsts_total 5800 # Number of Instructions Simulated -system.cpu.cpi 4.091379 # CPI: Cycles Per Instruction -system.cpu.cpi_total 4.091379 # CPI: Total CPI of All Threads +system.cpu.cpi 4.046034 # CPI: Cycles Per Instruction +system.cpu.cpi_total 4.046034 # CPI: Total CPI of All Threads system.cpu.dcache.ReadReq_accesses 1444 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 33612.359551 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency 33681.818182 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency 34464.285714 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 1355 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 2991500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.061634 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 89 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits 33 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_hits 1356 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 2964000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.060942 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 88 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_hits 32 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_miss_latency 1930000 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.038781 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_misses 56 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 1046 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 33542.735043 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 36053.846154 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 695 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 11773500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.335564 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 351 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_hits 286 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency 2343500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.062141 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 65 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_avg_miss_latency 33737.864078 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 36302.083333 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 737 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 10425000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.295411 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 309 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_hits 261 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_miss_latency 1742500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate 0.045889 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses 48 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.dcache.avg_refs 20.125000 # Average number of references to valid blocks. @@ -80,51 +80,51 @@ system.cpu.dcache.blocked_cycles::no_mshrs 0 # system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.demand_accesses 2490 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 33556.818182 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 35318.181818 # average overall mshr miss latency -system.cpu.dcache.demand_hits 2050 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 14765000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.176707 # miss rate for demand accesses -system.cpu.dcache.demand_misses 440 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 319 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 4273500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.048594 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 121 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_avg_miss_latency 33725.440806 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 35312.500000 # average overall mshr miss latency +system.cpu.dcache.demand_hits 2093 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 13389000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.159438 # miss rate for demand accesses +system.cpu.dcache.demand_misses 397 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 293 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 3672500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.041767 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 104 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_%::0 0.016240 # Average percentage of cache occupancy -system.cpu.dcache.occ_blocks::0 66.517345 # Average occupied blocks per context +system.cpu.dcache.occ_%::0 0.016245 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::0 66.538229 # Average occupied blocks per context system.cpu.dcache.overall_accesses 2490 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 33556.818182 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 35318.181818 # average overall mshr miss latency +system.cpu.dcache.overall_avg_miss_latency 33725.440806 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 35312.500000 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 2050 # number of overall hits -system.cpu.dcache.overall_miss_latency 14765000 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.176707 # miss rate for overall accesses -system.cpu.dcache.overall_misses 440 # number of overall misses -system.cpu.dcache.overall_mshr_hits 319 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 4273500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.048594 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 121 # number of overall MSHR misses +system.cpu.dcache.overall_hits 2093 # number of overall hits +system.cpu.dcache.overall_miss_latency 13389000 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.159438 # miss rate for overall accesses +system.cpu.dcache.overall_misses 397 # number of overall misses +system.cpu.dcache.overall_mshr_hits 293 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 3672500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.041767 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 104 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.sampled_refs 104 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 66.517345 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 66.538229 # Cycle average of tags in use system.cpu.dcache.total_refs 2093 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 0 # number of writebacks -system.cpu.decode.DECODE:BlockedCycles 1153 # Number of cycles decode is blocked +system.cpu.decode.DECODE:BlockedCycles 885 # Number of cycles decode is blocked system.cpu.decode.DECODE:BranchMispred 150 # Number of times decode detected a branch misprediction system.cpu.decode.DECODE:BranchResolved 267 # Number of times decode resolved a branch system.cpu.decode.DECODE:DecodedInsts 10406 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 7618 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 1941 # Number of cycles decode is running +system.cpu.decode.DECODE:IdleCycles 7574 # Number of cycles decode is idle +system.cpu.decode.DECODE:RunCycles 1944 # Number of cycles decode is running system.cpu.decode.DECODE:SquashCycles 570 # Number of cycles decode is squashing system.cpu.decode.DECODE:SquashedInsts 416 # Number of squashed instructions handled by decode -system.cpu.decode.DECODE:UnblockCycles 73 # Number of cycles decode is unblocking +system.cpu.decode.DECODE:UnblockCycles 70 # Number of cycles decode is unblocking system.cpu.dtb.accesses 0 # DTB accesses system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses @@ -140,36 +140,36 @@ system.cpu.fetch.Cycles 3561 # Nu system.cpu.fetch.IcacheSquashes 225 # Number of outstanding Icache misses that were squashed system.cpu.fetch.Insts 11687 # Number of instructions fetch has processed system.cpu.fetch.SquashCycles 410 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.088496 # Number of branch fetches per cycle +system.cpu.fetch.branchRate 0.089487 # Number of branch fetches per cycle system.cpu.fetch.icacheStallCycles 1490 # Number of cycles fetch is stalled on an Icache miss system.cpu.fetch.predictedBranches 876 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 0.492499 # Number of inst fetches per cycle -system.cpu.fetch.rateDist::samples 11355 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.029238 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.423250 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rate 0.498018 # Number of inst fetches per cycle +system.cpu.fetch.rateDist::samples 11043 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.058317 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.450976 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 9285 81.77% 81.77% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 161 1.42% 83.19% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 189 1.66% 84.85% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 155 1.37% 86.22% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 202 1.78% 88.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 136 1.20% 89.19% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 272 2.40% 91.59% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 77 0.68% 92.27% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 878 7.73% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 8973 81.26% 81.26% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 161 1.46% 82.71% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 189 1.71% 84.42% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 155 1.40% 85.83% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 202 1.83% 87.66% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 136 1.23% 88.89% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 272 2.46% 91.35% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 77 0.70% 92.05% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 878 7.95% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 11355 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::total 11043 # Number of instructions fetched each cycle (Total) system.cpu.icache.ReadReq_accesses 1490 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 36423.575130 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 34778.614458 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_miss_latency 36422.279793 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 34777.108434 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_hits 1104 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 14059500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency 14059000 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_rate 0.259060 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_misses 386 # number of ReadReq misses system.cpu.icache.ReadReq_mshr_hits 54 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 11546500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 11546000 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.222819 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_misses 332 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked @@ -181,31 +181,31 @@ system.cpu.icache.blocked_cycles::no_mshrs 0 # system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.demand_accesses 1490 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 36423.575130 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 34778.614458 # average overall mshr miss latency +system.cpu.icache.demand_avg_miss_latency 36422.279793 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 34777.108434 # average overall mshr miss latency system.cpu.icache.demand_hits 1104 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 14059500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency 14059000 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_rate 0.259060 # miss rate for demand accesses system.cpu.icache.demand_misses 386 # number of demand (read+write) misses system.cpu.icache.demand_mshr_hits 54 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 11546500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 11546000 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_rate 0.222819 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_misses 332 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_%::0 0.078771 # Average percentage of cache occupancy -system.cpu.icache.occ_blocks::0 161.323458 # Average occupied blocks per context +system.cpu.icache.occ_%::0 0.078715 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::0 161.207549 # Average occupied blocks per context system.cpu.icache.overall_accesses 1490 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 36423.575130 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 34778.614458 # average overall mshr miss latency +system.cpu.icache.overall_avg_miss_latency 36422.279793 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 34777.108434 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.icache.overall_hits 1104 # number of overall hits -system.cpu.icache.overall_miss_latency 14059500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency 14059000 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.259060 # miss rate for overall accesses system.cpu.icache.overall_misses 386 # number of overall misses system.cpu.icache.overall_mshr_hits 54 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 11546500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 11546000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_rate 0.222819 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_misses 332 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -213,27 +213,27 @@ system.cpu.icache.overall_mshr_uncacheable_misses 0 system.cpu.icache.replacements 0 # number of replacements system.cpu.icache.sampled_refs 332 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 161.323458 # Cycle average of tags in use +system.cpu.icache.tagsinuse 161.207549 # Cycle average of tags in use system.cpu.icache.total_refs 1104 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idleCycles 12375 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.idleCycles 12424 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.iew.EXEC:branches 1261 # Number of branches executed system.cpu.iew.EXEC:nop 0 # number of nop insts executed -system.cpu.iew.EXEC:rate 0.328319 # Inst execution rate +system.cpu.iew.EXEC:rate 0.331998 # Inst execution rate system.cpu.iew.EXEC:refs 2813 # number of memory reference insts executed system.cpu.iew.EXEC:stores 1315 # Number of stores executed system.cpu.iew.EXEC:swp 0 # number of swp insts executed -system.cpu.iew.WB:consumers 5889 # num instructions consuming a value +system.cpu.iew.WB:consumers 5926 # num instructions consuming a value system.cpu.iew.WB:count 7582 # cumulative count of insts written-back -system.cpu.iew.WB:fanout 0.646290 # average fanout of values written-back +system.cpu.iew.WB:fanout 0.645461 # average fanout of values written-back system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 3806 # num instructions producing a value -system.cpu.iew.WB:rate 0.319511 # insts written-back per cycle +system.cpu.iew.WB:producers 3825 # num instructions producing a value +system.cpu.iew.WB:rate 0.323092 # insts written-back per cycle system.cpu.iew.WB:sent 7642 # cumulative count of insts sent to commit system.cpu.iew.branchMispredicts 277 # Number of branch mispredicts detected at execute -system.cpu.iew.iewBlockCycles 117 # Number of cycles IEW is blocking +system.cpu.iew.iewBlockCycles 130 # Number of cycles IEW is blocking system.cpu.iew.iewDispLoadInsts 1681 # Number of dispatched load instructions system.cpu.iew.iewDispNonSpecInsts 14 # Number of dispatched non-speculative instructions system.cpu.iew.iewDispSquashedInsts 97 # Number of squashed instructions skipped by dispatch @@ -246,7 +246,7 @@ system.cpu.iew.iewIQFullEvents 4 # Nu system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall system.cpu.iew.iewSquashCycles 570 # Number of cycles IEW is squashing -system.cpu.iew.iewUnblockCycles 11 # Number of cycles IEW is unblocking +system.cpu.iew.iewUnblockCycles 12 # Number of cycles IEW is unblocking system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.lsq.thread.0.forwLoads 30 # Number of loads that had data forwarded from stores @@ -260,8 +260,8 @@ system.cpu.iew.lsq.thread.0.squashedStores 404 # system.cpu.iew.memOrderViolationEvents 42 # Number of memory order violations system.cpu.iew.predictedNotTakenIncorrect 201 # Number of branches that were predicted not taken incorrectly system.cpu.iew.predictedTakenIncorrect 76 # Number of branches that were predicted taken incorrectly -system.cpu.ipc 0.244416 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.244416 # IPC: Total IPC of All Threads +system.cpu.ipc 0.247156 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.247156 # IPC: Total IPC of All Threads system.cpu.iq.ISSUE:FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::IntAlu 5126 63.37% 63.37% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::IntMult 0 0.00% 63.37% # Type of FU issued @@ -293,24 +293,24 @@ system.cpu.iq.ISSUE:fu_full::MemRead 73 47.71% 54.90% # at system.cpu.iq.ISSUE:fu_full::MemWrite 69 45.10% 100.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:issued_per_cycle::samples 11355 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::mean 0.712373 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.391316 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::samples 11043 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::mean 0.732500 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.410424 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::0 8066 71.03% 71.03% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::1 1182 10.41% 81.44% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::2 820 7.22% 88.67% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::3 507 4.46% 93.13% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::4 388 3.42% 96.55% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::5 218 1.92% 98.47% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::6 121 1.07% 99.53% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::7 46 0.41% 99.94% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::0 7773 70.39% 70.39% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::1 1167 10.57% 80.96% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::2 813 7.36% 88.32% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::3 500 4.53% 92.85% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::4 391 3.54% 96.39% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::5 222 2.01% 98.40% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::6 124 1.12% 99.52% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::7 46 0.42% 99.94% # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::8 7 0.06% 100.00% # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::total 11355 # Number of insts issued each cycle -system.cpu.iq.ISSUE:rate 0.340877 # Inst issue rate +system.cpu.iq.ISSUE:issued_per_cycle::total 11043 # Number of insts issued each cycle +system.cpu.iq.ISSUE:rate 0.344697 # Inst issue rate system.cpu.iq.iqInstsAdded 9163 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqInstsIssued 8089 # Number of instructions issued system.cpu.iq.iqNonSpecInstsAdded 22 # Number of non-speculative instructions added to the IQ @@ -328,46 +328,37 @@ system.cpu.itb.write_accesses 0 # DT system.cpu.itb.write_hits 0 # DTB write hits system.cpu.itb.write_misses 0 # DTB write misses system.cpu.l2cache.ReadExReq_accesses 48 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency 34927.083333 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31750 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_miss_latency 1676500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_avg_miss_latency 34947.916667 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31770.833333 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_miss_latency 1677500 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_misses 48 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 1524000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency 1525000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_misses 48 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadReq_accesses 388 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 34327.631579 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31150 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency 34326.315789 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31147.368421 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_hits 8 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 13044500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency 13044000 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_rate 0.979381 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_misses 380 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 11837000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency 11836000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate 0.979381 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_misses 380 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_accesses 17 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_avg_miss_latency 34264.705882 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31176.470588 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_miss_latency 582500 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_misses 17 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_mshr_miss_latency 530000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_misses 17 # number of UpgradeReq MSHR misses system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 0.022039 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 0.021053 # Average number of references to valid blocks. system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.demand_accesses 436 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 34394.859813 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency 34396.028037 # average overall miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency 31217.289720 # average overall mshr miss latency system.cpu.l2cache.demand_hits 8 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 14721000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency 14721500 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_rate 0.981651 # miss rate for demand accesses system.cpu.l2cache.demand_misses 428 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits @@ -377,14 +368,14 @@ system.cpu.l2cache.demand_mshr_misses 428 # nu system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.occ_%::0 0.005582 # Average percentage of cache occupancy -system.cpu.l2cache.occ_blocks::0 182.925254 # Average occupied blocks per context +system.cpu.l2cache.occ_%::0 0.005863 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::0 192.111326 # Average occupied blocks per context system.cpu.l2cache.overall_accesses 436 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 34394.859813 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency 34396.028037 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 31217.289720 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.l2cache.overall_hits 8 # number of overall hits -system.cpu.l2cache.overall_miss_latency 14721000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency 14721500 # number of overall miss cycles system.cpu.l2cache.overall_miss_rate 0.981651 # miss rate for overall accesses system.cpu.l2cache.overall_misses 428 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits @@ -394,9 +385,9 @@ system.cpu.l2cache.overall_mshr_misses 428 # nu system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.sampled_refs 363 # Sample count of references to valid blocks. +system.cpu.l2cache.sampled_refs 380 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 182.925254 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 192.111326 # Cycle average of tags in use system.cpu.l2cache.total_refs 8 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks @@ -404,24 +395,24 @@ system.cpu.memDep0.conflictingLoads 67 # Nu system.cpu.memDep0.conflictingStores 29 # Number of conflicting stores. system.cpu.memDep0.insertedLoads 1681 # Number of loads inserted to the mem dependence unit. system.cpu.memDep0.insertedStores 1450 # Number of stores inserted to the mem dependence unit. -system.cpu.numCycles 23730 # number of cpu cycles simulated -system.cpu.rename.RENAME:BlockCycles 323 # Number of cycles rename is blocking +system.cpu.numCycles 23467 # number of cpu cycles simulated +system.cpu.rename.RENAME:BlockCycles 312 # Number of cycles rename is blocking system.cpu.rename.RENAME:CommittedMaps 5007 # Number of HB maps that are committed system.cpu.rename.RENAME:IQFullEvents 7 # Number of times rename has blocked due to IQ full -system.cpu.rename.RENAME:IdleCycles 7801 # Number of cycles rename is idle -system.cpu.rename.RENAME:LSQFullEvents 213 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RENAME:IdleCycles 7756 # Number of cycles rename is idle +system.cpu.rename.RENAME:LSQFullEvents 194 # Number of times rename has blocked due to LSQ full system.cpu.rename.RENAME:RenameLookups 16232 # Number of register rename lookups that rename has made system.cpu.rename.RENAME:RenamedInsts 9925 # Number of instructions processed by rename system.cpu.rename.RENAME:RenamedOperands 8708 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 1823 # Number of cycles rename is running +system.cpu.rename.RENAME:RunCycles 1825 # Number of cycles rename is running system.cpu.rename.RENAME:SquashCycles 570 # Number of cycles rename is squashing -system.cpu.rename.RENAME:UnblockCycles 263 # Number of cycles rename is unblocking +system.cpu.rename.RENAME:UnblockCycles 243 # Number of cycles rename is unblocking system.cpu.rename.RENAME:UndoneMaps 3701 # Number of HB maps that are undone due to squashing -system.cpu.rename.RENAME:serializeStallCycles 575 # count of cycles rename stalled for serializing inst +system.cpu.rename.RENAME:serializeStallCycles 337 # count of cycles rename stalled for serializing inst system.cpu.rename.RENAME:serializingInsts 22 # count of serializing insts renamed -system.cpu.rename.RENAME:skidInsts 494 # count of insts added to the skid buffer +system.cpu.rename.RENAME:skidInsts 473 # count of insts added to the skid buffer system.cpu.rename.RENAME:tempSerializingInsts 22 # count of temporary serializing insts renamed -system.cpu.timesIdled 231 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.timesIdled 230 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.workload.PROG:num_syscalls 9 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-timing/config.ini b/tests/quick/00.hello/ref/sparc/linux/simple-timing/config.ini index d91ebcc59..35f8386c3 100644 --- a/tests/quick/00.hello/ref/sparc/linux/simple-timing/config.ini +++ b/tests/quick/00.hello/ref/sparc/linux/simple-timing/config.ini @@ -157,7 +157,7 @@ egid=100 env= errout=cerr euid=100 -executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/hello/bin/sparc/linux/hello +executable=/dist/m5/regression/test-progs/hello/bin/sparc/linux/hello gid=100 input=cin max_stack_size=67108864 diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-timing/simout b/tests/quick/00.hello/ref/sparc/linux/simple-timing/simout index 9485c1bb2..9b5f99faf 100755 --- a/tests/quick/00.hello/ref/sparc/linux/simple-timing/simout +++ b/tests/quick/00.hello/ref/sparc/linux/simple-timing/simout @@ -1,3 +1,5 @@ +Redirecting stdout to build/SPARC_SE/tests/opt/quick/00.hello/sparc/linux/simple-timing/simout +Redirecting stderr to build/SPARC_SE/tests/opt/quick/00.hello/sparc/linux/simple-timing/simerr M5 Simulator System Copyright (c) 2001-2008 @@ -5,11 +7,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 25 2010 03:11:27 -M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip -M5 started Feb 25 2010 03:37:59 -M5 executing on SC2B0619 -command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/00.hello/sparc/linux/simple-timing -re tests/run.py build/SPARC_SE/tests/fast/quick/00.hello/sparc/linux/simple-timing +M5 compiled Aug 26 2010 13:03:41 +M5 revision 85cafc6ccb42 7662 default qtip tip sc-fail-fix +M5 started Aug 26 2010 13:05:08 +M5 executing on zizzer +command line: build/SPARC_SE/m5.opt -d build/SPARC_SE/tests/opt/quick/00.hello/sparc/linux/simple-timing -re tests/run.py build/SPARC_SE/tests/opt/quick/00.hello/sparc/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... -Hello World!Exiting @ tick 29031000 because target called exit() +Hello World!Exiting @ tick 28206000 because target called exit() diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-timing/stats.txt b/tests/quick/00.hello/ref/sparc/linux/simple-timing/stats.txt index 11fb745f1..49d0076df 100644 --- a/tests/quick/00.hello/ref/sparc/linux/simple-timing/stats.txt +++ b/tests/quick/00.hello/ref/sparc/linux/simple-timing/stats.txt @@ -1,13 +1,13 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 462498 # Simulator instruction rate (inst/s) -host_mem_usage 190336 # Number of bytes of host memory used +host_inst_rate 369934 # Simulator instruction rate (inst/s) +host_mem_usage 207380 # Number of bytes of host memory used host_seconds 0.01 # Real time elapsed on the host -host_tick_rate 2452978454 # Simulator tick rate (ticks/s) +host_tick_rate 1923223783 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 5340 # Number of instructions simulated -sim_seconds 0.000029 # Number of seconds simulated -sim_ticks 29031000 # Number of ticks simulated +sim_seconds 0.000028 # Number of seconds simulated +sim_ticks 28206000 # Number of ticks simulated system.cpu.dcache.ReadReq_accesses 716 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_avg_miss_latency 55222.222222 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency 52222.222222 # average ReadReq mshr miss latency @@ -21,13 +21,13 @@ system.cpu.dcache.ReadReq_mshr_misses 54 # nu system.cpu.dcache.WriteReq_accesses 673 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_avg_miss_latency 56000 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53000 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 577 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 5376000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.142645 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 96 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_miss_latency 5088000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.142645 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 96 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_hits 592 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 4536000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.120357 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 81 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_miss_latency 4293000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate 0.120357 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses 81 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.dcache.avg_refs 9.288889 # Average number of references to valid blocks. @@ -37,39 +37,39 @@ system.cpu.dcache.blocked_cycles::no_mshrs 0 # system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.demand_accesses 1389 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 55720 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 52720 # average overall mshr miss latency -system.cpu.dcache.demand_hits 1239 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 8358000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.107991 # miss rate for demand accesses -system.cpu.dcache.demand_misses 150 # number of demand (read+write) misses +system.cpu.dcache.demand_avg_miss_latency 55688.888889 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 52688.888889 # average overall mshr miss latency +system.cpu.dcache.demand_hits 1254 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 7518000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.097192 # miss rate for demand accesses +system.cpu.dcache.demand_misses 135 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 7908000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.107991 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 150 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_miss_latency 7113000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.097192 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 135 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_%::0 0.020107 # Average percentage of cache occupancy -system.cpu.dcache.occ_blocks::0 82.357482 # Average occupied blocks per context +system.cpu.dcache.occ_%::0 0.020036 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::0 82.065697 # Average occupied blocks per context system.cpu.dcache.overall_accesses 1389 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 55720 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 52720 # average overall mshr miss latency +system.cpu.dcache.overall_avg_miss_latency 55688.888889 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 52688.888889 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 1239 # number of overall hits -system.cpu.dcache.overall_miss_latency 8358000 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.107991 # miss rate for overall accesses -system.cpu.dcache.overall_misses 150 # number of overall misses +system.cpu.dcache.overall_hits 1254 # number of overall hits +system.cpu.dcache.overall_miss_latency 7518000 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.097192 # miss rate for overall accesses +system.cpu.dcache.overall_misses 135 # number of overall misses system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 7908000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.107991 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 150 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_miss_latency 7113000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.097192 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 135 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.sampled_refs 135 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 82.357482 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 82.065697 # Cycle average of tags in use system.cpu.dcache.total_refs 1254 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 0 # number of writebacks @@ -105,8 +105,8 @@ system.cpu.icache.demand_mshr_misses 257 # nu system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_%::0 0.057478 # Average percentage of cache occupancy -system.cpu.icache.occ_blocks::0 117.715481 # Average occupied blocks per context +system.cpu.icache.occ_%::0 0.057117 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::0 116.975932 # Average occupied blocks per context system.cpu.icache.overall_accesses 5384 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency 55673.151751 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 52673.151751 # average overall mshr miss latency @@ -124,7 +124,7 @@ system.cpu.icache.overall_mshr_uncacheable_misses 0 system.cpu.icache.replacements 0 # number of replacements system.cpu.icache.sampled_refs 257 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 117.715481 # Cycle average of tags in use +system.cpu.icache.tagsinuse 116.975932 # Cycle average of tags in use system.cpu.icache.total_refs 5127 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks @@ -148,18 +148,9 @@ system.cpu.l2cache.ReadReq_misses 308 # nu system.cpu.l2cache.ReadReq_mshr_miss_latency 12320000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate 0.990354 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_misses 308 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_accesses 15 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_avg_miss_latency 52000 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_miss_latency 780000 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_misses 15 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_mshr_miss_latency 600000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_misses 15 # number of UpgradeReq MSHR misses system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 0.010239 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 0.009740 # Average number of references to valid blocks. system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked @@ -179,8 +170,8 @@ system.cpu.l2cache.demand_mshr_misses 389 # nu system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.occ_%::0 0.004176 # Average percentage of cache occupancy -system.cpu.l2cache.occ_blocks::0 136.844792 # Average occupied blocks per context +system.cpu.l2cache.occ_%::0 0.004337 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::0 142.102892 # Average occupied blocks per context system.cpu.l2cache.overall_accesses 392 # number of overall (read+write) accesses system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency @@ -196,14 +187,14 @@ system.cpu.l2cache.overall_mshr_misses 389 # nu system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.sampled_refs 293 # Sample count of references to valid blocks. +system.cpu.l2cache.sampled_refs 308 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 136.844792 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 142.102892 # Cycle average of tags in use system.cpu.l2cache.total_refs 3 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 58062 # number of cpu cycles simulated +system.cpu.numCycles 56412 # number of cpu cycles simulated system.cpu.num_insts 5340 # Number of instructions executed system.cpu.num_refs 1402 # Number of memory references system.cpu.workload.PROG:num_syscalls 11 # Number of system calls diff --git a/tests/quick/00.hello/ref/x86/linux/simple-timing/simout b/tests/quick/00.hello/ref/x86/linux/simple-timing/simout index 2a02cd35e..f57480110 100755 --- a/tests/quick/00.hello/ref/x86/linux/simple-timing/simout +++ b/tests/quick/00.hello/ref/x86/linux/simple-timing/simout @@ -1,3 +1,5 @@ +Redirecting stdout to build/X86_SE/tests/opt/quick/00.hello/x86/linux/simple-timing/simout +Redirecting stderr to build/X86_SE/tests/opt/quick/00.hello/x86/linux/simple-timing/simerr M5 Simulator System Copyright (c) 2001-2008 @@ -5,12 +7,12 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled May 2 2010 23:23:01 -M5 revision 674289bfe108 7074 default qtip tip updateauxvectorsstats.patch -M5 started May 2 2010 23:23:02 -M5 executing on burrito -command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/quick/00.hello/x86/linux/simple-timing -re tests/run.py build/X86_SE/tests/fast/quick/00.hello/x86/linux/simple-timing +M5 compiled Aug 26 2010 13:20:12 +M5 revision 85cafc6ccb42 7662 default qtip tip sc-fail-fix +M5 started Aug 26 2010 13:33:02 +M5 executing on zizzer +command line: build/X86_SE/m5.opt -d build/X86_SE/tests/opt/quick/00.hello/x86/linux/simple-timing -re tests/run.py build/X86_SE/tests/opt/quick/00.hello/x86/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... Hello world! -Exiting @ tick 29813000 because target called exit() +Exiting @ tick 28768000 because target called exit() diff --git a/tests/quick/00.hello/ref/x86/linux/simple-timing/stats.txt b/tests/quick/00.hello/ref/x86/linux/simple-timing/stats.txt index cc8de12ad..eecf4ab78 100644 --- a/tests/quick/00.hello/ref/x86/linux/simple-timing/stats.txt +++ b/tests/quick/00.hello/ref/x86/linux/simple-timing/stats.txt @@ -1,13 +1,13 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 734670 # Simulator instruction rate (inst/s) -host_mem_usage 220588 # Number of bytes of host memory used -host_seconds 0.01 # Real time elapsed on the host -host_tick_rate 2255655595 # Simulator tick rate (ticks/s) +host_inst_rate 397795 # Simulator instruction rate (inst/s) +host_mem_usage 205892 # Number of bytes of host memory used +host_seconds 0.02 # Real time elapsed on the host +host_tick_rate 1184355702 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 9561 # Number of instructions simulated -sim_seconds 0.000030 # Number of seconds simulated -sim_ticks 29813000 # Number of ticks simulated +sim_seconds 0.000029 # Number of seconds simulated +sim_ticks 28768000 # Number of ticks simulated system.cpu.dcache.ReadReq_accesses 1056 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_avg_miss_latency 56000 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency 53000 # average ReadReq mshr miss latency @@ -21,13 +21,13 @@ system.cpu.dcache.ReadReq_mshr_misses 55 # nu system.cpu.dcache.WriteReq_accesses 934 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_avg_miss_latency 56000 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53000 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 836 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 5488000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.104925 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 98 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_miss_latency 5194000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.104925 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 98 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_hits 855 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 4424000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.084582 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 79 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_miss_latency 4187000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate 0.084582 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses 79 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.dcache.avg_refs 13.850746 # Average number of references to valid blocks. @@ -39,37 +39,37 @@ system.cpu.dcache.cache_copies 0 # nu system.cpu.dcache.demand_accesses 1990 # number of demand (read+write) accesses system.cpu.dcache.demand_avg_miss_latency 56000 # average overall miss latency system.cpu.dcache.demand_avg_mshr_miss_latency 53000 # average overall mshr miss latency -system.cpu.dcache.demand_hits 1837 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 8568000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.076884 # miss rate for demand accesses -system.cpu.dcache.demand_misses 153 # number of demand (read+write) misses +system.cpu.dcache.demand_hits 1856 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 7504000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.067337 # miss rate for demand accesses +system.cpu.dcache.demand_misses 134 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 8109000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.076884 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 153 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_miss_latency 7102000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.067337 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 134 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_%::0 0.019841 # Average percentage of cache occupancy -system.cpu.dcache.occ_blocks::0 81.267134 # Average occupied blocks per context +system.cpu.dcache.occ_%::0 0.019695 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::0 80.668870 # Average occupied blocks per context system.cpu.dcache.overall_accesses 1990 # number of overall (read+write) accesses system.cpu.dcache.overall_avg_miss_latency 56000 # average overall miss latency system.cpu.dcache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 1837 # number of overall hits -system.cpu.dcache.overall_miss_latency 8568000 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.076884 # miss rate for overall accesses -system.cpu.dcache.overall_misses 153 # number of overall misses +system.cpu.dcache.overall_hits 1856 # number of overall hits +system.cpu.dcache.overall_miss_latency 7504000 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.067337 # miss rate for overall accesses +system.cpu.dcache.overall_misses 134 # number of overall misses system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 8109000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.076884 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 153 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_miss_latency 7102000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.067337 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 134 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.sampled_refs 134 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 81.267134 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 80.668870 # Cycle average of tags in use system.cpu.dcache.total_refs 1856 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 0 # number of writebacks @@ -105,8 +105,8 @@ system.cpu.icache.demand_mshr_misses 228 # nu system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_%::0 0.052030 # Average percentage of cache occupancy -system.cpu.icache.occ_blocks::0 106.557747 # Average occupied blocks per context +system.cpu.icache.occ_%::0 0.051447 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::0 105.363985 # Average occupied blocks per context system.cpu.icache.overall_accesses 6911 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency 55815.789474 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 52815.789474 # average overall mshr miss latency @@ -124,7 +124,7 @@ system.cpu.icache.overall_mshr_uncacheable_misses 0 system.cpu.icache.replacements 0 # number of replacements system.cpu.icache.sampled_refs 228 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 106.557747 # Cycle average of tags in use +system.cpu.icache.tagsinuse 105.363985 # Cycle average of tags in use system.cpu.icache.total_refs 6683 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks @@ -148,18 +148,9 @@ system.cpu.l2cache.ReadReq_misses 282 # nu system.cpu.l2cache.ReadReq_mshr_miss_latency 11280000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate 0.996466 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_misses 282 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_accesses 19 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_avg_miss_latency 52000 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_miss_latency 988000 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_misses 19 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_mshr_miss_latency 760000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_misses 19 # number of UpgradeReq MSHR misses system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 0.003802 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 0.003546 # Average number of references to valid blocks. system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked @@ -179,8 +170,8 @@ system.cpu.l2cache.demand_mshr_misses 361 # nu system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.occ_%::0 0.003920 # Average percentage of cache occupancy -system.cpu.l2cache.occ_blocks::0 128.459536 # Average occupied blocks per context +system.cpu.l2cache.occ_%::0 0.004084 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::0 133.809342 # Average occupied blocks per context system.cpu.l2cache.overall_accesses 362 # number of overall (read+write) accesses system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency @@ -196,14 +187,14 @@ system.cpu.l2cache.overall_mshr_misses 361 # nu system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.sampled_refs 263 # Sample count of references to valid blocks. +system.cpu.l2cache.sampled_refs 282 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 128.459536 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 133.809342 # Cycle average of tags in use system.cpu.l2cache.total_refs 1 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 59626 # number of cpu cycles simulated +system.cpu.numCycles 57536 # number of cpu cycles simulated system.cpu.num_insts 9561 # Number of instructions executed system.cpu.num_refs 1990 # Number of memory references system.cpu.workload.PROG:num_syscalls 11 # Number of system calls |