diff options
Diffstat (limited to 'tests/quick/00.hello/ref')
6 files changed, 238 insertions, 205 deletions
diff --git a/tests/quick/00.hello/ref/alpha/linux/inorder-timing/config.ini b/tests/quick/00.hello/ref/alpha/linux/inorder-timing/config.ini index b30560264..5ab5381fc 100644 --- a/tests/quick/00.hello/ref/alpha/linux/inorder-timing/config.ini +++ b/tests/quick/00.hello/ref/alpha/linux/inorder-timing/config.ini @@ -63,6 +63,7 @@ progress_interval=0 stageTracing=false stageWidth=1 system=system +threadModel=SMT tracer=system.cpu.tracer workload=system.cpu.workload dcache_port=system.cpu.dcache.cpu_side @@ -78,7 +79,6 @@ hash_delay=1 latency=1000 max_miss_count=0 mshrs=10 -prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 @@ -113,7 +113,6 @@ hash_delay=1 latency=1000 max_miss_count=0 mshrs=10 -prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 @@ -148,7 +147,6 @@ hash_delay=1 latency=10000 max_miss_count=0 mshrs=10 -prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=100000 @@ -190,7 +188,7 @@ egid=100 env= errout=cerr euid=100 -executable=tests/test-progs/hello/bin/alpha/linux/hello +executable=/dist/m5/regression/test-progs/hello/bin/alpha/linux/hello gid=100 input=cin max_stack_size=67108864 diff --git a/tests/quick/00.hello/ref/alpha/linux/inorder-timing/simout b/tests/quick/00.hello/ref/alpha/linux/inorder-timing/simout index 18efdaa9e..4ad6292c5 100755 --- a/tests/quick/00.hello/ref/alpha/linux/inorder-timing/simout +++ b/tests/quick/00.hello/ref/alpha/linux/inorder-timing/simout @@ -5,13 +5,13 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled May 12 2009 11:18:39 -M5 revision 21550d38f156 6195 default qtip tip inorder-hello-regress -M5 started May 12 2009 11:18:40 +M5 compiled Jan 29 2010 09:13:03 +M5 revision 23ae96d82d21+ 6704+ default qtip tip inorder_hello_alpha +M5 started Jan 29 2010 09:13:04 M5 executing on zooks command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/inorder-timing -re tests/run.py build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/inorder-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. Hello world! -Exiting @ tick 31646000 because target called exit() +Exiting @ tick 31286000 because target called exit() diff --git a/tests/quick/00.hello/ref/alpha/linux/inorder-timing/stats.txt b/tests/quick/00.hello/ref/alpha/linux/inorder-timing/stats.txt index a88b80594..b9a12afbb 100644 --- a/tests/quick/00.hello/ref/alpha/linux/inorder-timing/stats.txt +++ b/tests/quick/00.hello/ref/alpha/linux/inorder-timing/stats.txt @@ -1,53 +1,53 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 23793 # Simulator instruction rate (inst/s) -host_mem_usage 152032 # Number of bytes of host memory used -host_seconds 0.27 # Real time elapsed on the host -host_tick_rate 117464960 # Simulator tick rate (ticks/s) +host_inst_rate 23048 # Simulator instruction rate (inst/s) +host_mem_usage 153228 # Number of bytes of host memory used +host_seconds 0.28 # Real time elapsed on the host +host_tick_rate 112412599 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 6404 # Number of instructions simulated -sim_seconds 0.000032 # Number of seconds simulated -sim_ticks 31646000 # Number of ticks simulated +sim_seconds 0.000031 # Number of seconds simulated +sim_ticks 31286000 # Number of ticks simulated system.cpu.AGEN-Unit.instReqsProcessed 2050 # Number of Instructions Requests that completed in this resource. -system.cpu.Branch-Predictor.instReqsProcessed 6405 # Number of Instructions Requests that completed in this resource. -system.cpu.Branch-Predictor.predictedNotTaken 909 # Number of Branches Predicted As Not Taken (False). -system.cpu.Branch-Predictor.predictedTaken 142 # Number of Branches Predicted As Taken (True). -system.cpu.Decode-Unit.instReqsProcessed 6405 # Number of Instructions Requests that completed in this resource. +system.cpu.Branch-Predictor.instReqsProcessed 6581 # Number of Instructions Requests that completed in this resource. +system.cpu.Branch-Predictor.predictedNotTaken 924 # Number of Branches Predicted As Not Taken (False). +system.cpu.Branch-Predictor.predictedTaken 143 # Number of Branches Predicted As Taken (True). +system.cpu.Decode-Unit.instReqsProcessed 6581 # Number of Instructions Requests that completed in this resource. +system.cpu.Execution-Unit.cyclesExecuted 4340 # Number of Cycles Execution Unit was used. system.cpu.Execution-Unit.instReqsProcessed 4354 # Number of Instructions Requests that completed in this resource. -system.cpu.Execution-Unit.predictedNotTakenIncorrect 607 # Number of Branches Incorrectly Predicted As Not Taken). -system.cpu.Execution-Unit.predictedTakenIncorrect 124 # Number of Branches Incorrectly Predicted As Taken. -system.cpu.Fetch-Buffer-T0.instReqsProcessed 0 # Number of Instructions Requests that completed in this resource. -system.cpu.Fetch-Buffer-T0.instsBypassed 0 # Number of Instructions Bypassed. -system.cpu.Fetch-Buffer-T1.instReqsProcessed 0 # Number of Instructions Requests that completed in this resource. -system.cpu.Fetch-Buffer-T1.instsBypassed 0 # Number of Instructions Bypassed. -system.cpu.Fetch-Seq-Unit.instReqsProcessed 13560 # Number of Instructions Requests that completed in this resource. +system.cpu.Execution-Unit.predictedNotTakenIncorrect 608 # Number of Branches Incorrectly Predicted As Not Taken). +system.cpu.Execution-Unit.predictedTakenIncorrect 123 # Number of Branches Incorrectly Predicted As Taken. +system.cpu.Execution-Unit.utilization 0.069359 # Utilization of Execution Unit (cycles / totalCycles). +system.cpu.Fetch-Seq-Unit.instReqsProcessed 13858 # Number of Instructions Requests that completed in this resource. system.cpu.Graduation-Unit.instReqsProcessed 6404 # Number of Instructions Requests that completed in this resource. system.cpu.Mult-Div-Unit.divInstReqsProcessed 0 # Number of Divide Requests Processed. system.cpu.Mult-Div-Unit.instReqsProcessed 2 # Number of Instructions Requests that completed in this resource. system.cpu.Mult-Div-Unit.multInstReqsProcessed 1 # Number of Multiply Requests Processed. -system.cpu.RegFile-Manager.instReqsProcessed 12884 # Number of Instructions Requests that completed in this resource. +system.cpu.RegFile-Manager.instReqsProcessed 19961 # Number of Instructions Requests that completed in this resource. +system.cpu.activity 22.407428 # Percentage of cycles cpu is active system.cpu.committedInsts 6404 # Number of Instructions Simulated (Per-Thread) system.cpu.committedInsts_total 6404 # Number of Instructions Simulated (Total) -system.cpu.cpi 9.883354 # CPI: Cycles Per Instruction (Per-Thread) -system.cpu.cpi_total 9.883354 # CPI: Total CPI of All Threads +system.cpu.contextSwitches 1 # Number of context switches +system.cpu.cpi 9.770924 # CPI: Cycles Per Instruction (Per-Thread) +system.cpu.cpi_total 9.770924 # CPI: Total CPI of All Threads system.cpu.dcache.ReadReq_accesses 1185 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 56352.631579 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 53352.631579 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_miss_latency 56347.368421 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 53347.368421 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_hits 1090 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 5353500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency 5353000 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_rate 0.080169 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_misses 95 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_miss_latency 5068500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 5068000 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.080169 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_misses 95 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 865 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 56419.540230 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53419.540230 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 56074.712644 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53074.712644 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_hits 778 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 4908500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 4878500 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_rate 0.100578 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_misses 87 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_miss_latency 4647500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 4617500 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate 0.100578 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_misses 87 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked @@ -59,29 +59,29 @@ system.cpu.dcache.blocked_cycles::no_mshrs 0 # system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.demand_accesses 2050 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 56384.615385 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 53384.615385 # average overall mshr miss latency +system.cpu.dcache.demand_avg_miss_latency 56217.032967 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 53217.032967 # average overall mshr miss latency system.cpu.dcache.demand_hits 1868 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 10262000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency 10231500 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_rate 0.088780 # miss rate for demand accesses system.cpu.dcache.demand_misses 182 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 9716000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 9685500 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_rate 0.088780 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_misses 182 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.overall_accesses 2050 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 56384.615385 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 53384.615385 # average overall mshr miss latency +system.cpu.dcache.overall_avg_miss_latency 56217.032967 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 53217.032967 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.dcache.overall_hits 1868 # number of overall hits -system.cpu.dcache.overall_miss_latency 10262000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency 10231500 # number of overall miss cycles system.cpu.dcache.overall_miss_rate 0.088780 # miss rate for overall accesses system.cpu.dcache.overall_misses 182 # number of overall misses system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 9716000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 9685500 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_rate 0.088780 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_misses 182 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -89,7 +89,7 @@ system.cpu.dcache.overall_mshr_uncacheable_misses 0 system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.sampled_refs 168 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 104.325446 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 103.689640 # Cycle average of tags in use system.cpu.dcache.total_refs 1882 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 0 # number of writebacks @@ -110,70 +110,71 @@ system.cpu.dtb.write_accesses 868 # DT system.cpu.dtb.write_acv 0 # DTB write access violations system.cpu.dtb.write_hits 865 # DTB write hits system.cpu.dtb.write_misses 3 # DTB write misses -system.cpu.icache.ReadReq_accesses 7155 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 55763.605442 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 52949.122807 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 6861 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 16394500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.041090 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 294 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_hits 9 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 15090500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.039832 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_accesses 7277 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 55521.594684 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 52863.157895 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 6976 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 16712000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.041363 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 301 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_hits 16 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_miss_latency 15066000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.039164 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_misses 285 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.icache.avg_refs 24.158451 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 24.563380 # Average number of references to valid blocks. system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 7155 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 55763.605442 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 52949.122807 # average overall mshr miss latency -system.cpu.icache.demand_hits 6861 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 16394500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.041090 # miss rate for demand accesses -system.cpu.icache.demand_misses 294 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 9 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 15090500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.039832 # mshr miss rate for demand accesses +system.cpu.icache.demand_accesses 7277 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 55521.594684 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 52863.157895 # average overall mshr miss latency +system.cpu.icache.demand_hits 6976 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 16712000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.041363 # miss rate for demand accesses +system.cpu.icache.demand_misses 301 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 16 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 15066000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0.039164 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_misses 285 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses 7155 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 55763.605442 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 52949.122807 # average overall mshr miss latency +system.cpu.icache.overall_accesses 7277 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 55521.594684 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 52863.157895 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 6861 # number of overall hits -system.cpu.icache.overall_miss_latency 16394500 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.041090 # miss rate for overall accesses -system.cpu.icache.overall_misses 294 # number of overall misses -system.cpu.icache.overall_mshr_hits 9 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 15090500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.039832 # mshr miss rate for overall accesses +system.cpu.icache.overall_hits 6976 # number of overall hits +system.cpu.icache.overall_miss_latency 16712000 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.041363 # miss rate for overall accesses +system.cpu.icache.overall_misses 301 # number of overall misses +system.cpu.icache.overall_mshr_hits 16 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 15066000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0.039164 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_misses 285 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.icache.replacements 0 # number of replacements system.cpu.icache.sampled_refs 284 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 131.383181 # Cycle average of tags in use -system.cpu.icache.total_refs 6861 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 130.373495 # Cycle average of tags in use +system.cpu.icache.total_refs 6976 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.icache_port.instReqsProcessed 7153 # Number of Instructions Requests that completed in this resource. -system.cpu.ipc 0.101180 # IPC: Instructions Per Cycle (Per-Thread) -system.cpu.ipc_total 0.101180 # IPC: Total IPC of All Threads +system.cpu.icache_port.instReqsProcessed 7275 # Number of Instructions Requests that completed in this resource. +system.cpu.idleCycles 48552 # Number of cycles cpu's stages were not processed +system.cpu.ipc 0.102344 # IPC: Instructions Per Cycle (Per-Thread) +system.cpu.ipc_total 0.102344 # IPC: Total IPC of All Threads system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_hits 0 # DTB hits system.cpu.itb.data_misses 0 # DTB misses -system.cpu.itb.fetch_accesses 7172 # ITB accesses +system.cpu.itb.fetch_accesses 7294 # ITB accesses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_hits 7155 # ITB hits +system.cpu.itb.fetch_hits 7277 # ITB hits system.cpu.itb.fetch_misses 17 # ITB misses system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.read_acv 0 # DTB read access violations @@ -184,28 +185,28 @@ system.cpu.itb.write_acv 0 # DT system.cpu.itb.write_hits 0 # DTB write hits system.cpu.itb.write_misses 0 # DTB write misses system.cpu.l2cache.ReadExReq_accesses 73 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency 52424.657534 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency 52075.342466 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40013.698630 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_miss_latency 3827000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency 3801500 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_misses 73 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_mshr_miss_latency 2921000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_misses 73 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadReq_accesses 380 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 52118.733509 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 39944.591029 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency 52068.601583 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 39945.910290 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_hits 1 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 19753000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency 19734000 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_rate 0.997368 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_misses 379 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 15139000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency 15139500 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate 0.997368 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_misses 379 # number of ReadReq MSHR misses system.cpu.l2cache.UpgradeReq_accesses 14 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_avg_miss_latency 52357.142857 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency 52071.428571 # average UpgradeReq miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_miss_latency 733000 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency 729000 # number of UpgradeReq miss cycles system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_misses 14 # number of UpgradeReq misses system.cpu.l2cache.UpgradeReq_mshr_miss_latency 560000 # number of UpgradeReq MSHR miss cycles @@ -220,29 +221,29 @@ system.cpu.l2cache.blocked_cycles::no_mshrs 0 # system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.demand_accesses 453 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 52168.141593 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 39955.752212 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_miss_latency 52069.690265 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 39956.858407 # average overall mshr miss latency system.cpu.l2cache.demand_hits 1 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 23580000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency 23535500 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_rate 0.997792 # miss rate for demand accesses system.cpu.l2cache.demand_misses 452 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 18060000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 18060500 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_rate 0.997792 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_misses 452 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.overall_accesses 453 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 52168.141593 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 39955.752212 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_miss_latency 52069.690265 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 39956.858407 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.l2cache.overall_hits 1 # number of overall hits -system.cpu.l2cache.overall_miss_latency 23580000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency 23535500 # number of overall miss cycles system.cpu.l2cache.overall_miss_rate 0.997792 # miss rate for overall accesses system.cpu.l2cache.overall_misses 452 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 18060000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 18060500 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_rate 0.997792 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_misses 452 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -250,16 +251,32 @@ system.cpu.l2cache.overall_mshr_uncacheable_misses 0 system.cpu.l2cache.replacements 0 # number of replacements system.cpu.l2cache.sampled_refs 364 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 182.840902 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 181.532273 # Cycle average of tags in use system.cpu.l2cache.total_refs 1 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks -system.cpu.numCycles 63293 # number of cpu cycles simulated +system.cpu.numCycles 62573 # number of cpu cycles simulated +system.cpu.runCycles 14021 # Number of cycles cpu stages are processed. system.cpu.smtCommittedInsts 0 # Number of SMT Instructions Simulated (Per-Thread) -system.cpu.smtCycles 0 # Total number of cycles that the CPU was simultaneous multithreading.(SMT) +system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode system.cpu.smt_cpi no_value # CPI: Total SMT-CPI system.cpu.smt_ipc no_value # IPC: Total SMT-IPC -system.cpu.threadCycles 63293 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.stage-0.idleCycles 55279 # Number of cycles 0 instructions are processed. +system.cpu.stage-0.runCycles 7294 # Number of cycles 1+ instructions are processed. +system.cpu.stage-0.utilization 11.656785 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage-1.idleCycles 55992 # Number of cycles 0 instructions are processed. +system.cpu.stage-1.runCycles 6581 # Number of cycles 1+ instructions are processed. +system.cpu.stage-1.utilization 10.517316 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage-2.idleCycles 56103 # Number of cycles 0 instructions are processed. +system.cpu.stage-2.runCycles 6470 # Number of cycles 1+ instructions are processed. +system.cpu.stage-2.utilization 10.339923 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage-3.idleCycles 60520 # Number of cycles 0 instructions are processed. +system.cpu.stage-3.runCycles 2053 # Number of cycles 1+ instructions are processed. +system.cpu.stage-3.utilization 3.280968 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage-4.idleCycles 56169 # Number of cycles 0 instructions are processed. +system.cpu.stage-4.runCycles 6404 # Number of cycles 1+ instructions are processed. +system.cpu.stage-4.utilization 10.234446 # Percentage of cycles stage was utilized (processing insts). +system.cpu.threadCycles 62573 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.workload.PROG:num_syscalls 17 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/quick/00.hello/ref/mips/linux/inorder-timing/config.ini b/tests/quick/00.hello/ref/mips/linux/inorder-timing/config.ini index 78a86bf82..8d2a24508 100644 --- a/tests/quick/00.hello/ref/mips/linux/inorder-timing/config.ini +++ b/tests/quick/00.hello/ref/mips/linux/inorder-timing/config.ini @@ -117,6 +117,7 @@ progress_interval=0 stageTracing=false stageWidth=1 system=system +threadModel=SMT tracer=system.cpu.tracer workload=system.cpu.workload dcache_port=system.cpu.dcache.cpu_side diff --git a/tests/quick/00.hello/ref/mips/linux/inorder-timing/simout b/tests/quick/00.hello/ref/mips/linux/inorder-timing/simout index 581c531f6..ce217f494 100755 --- a/tests/quick/00.hello/ref/mips/linux/inorder-timing/simout +++ b/tests/quick/00.hello/ref/mips/linux/inorder-timing/simout @@ -5,13 +5,13 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Jan 2 2010 07:01:31 -M5 revision a538feb8a617 6813 default qtip tip qbase fixhelp.patch -M5 started Jan 2 2010 07:03:09 -M5 executing on fajita -command line: build/MIPS_SE/m5.opt -d build/MIPS_SE/tests/opt/quick/00.hello/mips/linux/inorder-timing -re tests/run.py build/MIPS_SE/tests/opt/quick/00.hello/mips/linux/inorder-timing +M5 compiled Jan 31 2010 17:08:14 +M5 revision 01508015f86b 6964 default qtip tip inorder_hello_mips +M5 started Jan 31 2010 17:08:15 +M5 executing on zooks +command line: build/MIPS_SE/m5.fast -d build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/inorder-timing -re tests/run.py build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/inorder-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. Hello World! -Exiting @ tick 29940500 because target called exit() +Exiting @ tick 29206500 because target called exit() diff --git a/tests/quick/00.hello/ref/mips/linux/inorder-timing/stats.txt b/tests/quick/00.hello/ref/mips/linux/inorder-timing/stats.txt index d55c721ca..df2d539f4 100644 --- a/tests/quick/00.hello/ref/mips/linux/inorder-timing/stats.txt +++ b/tests/quick/00.hello/ref/mips/linux/inorder-timing/stats.txt @@ -1,96 +1,96 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 10400 # Simulator instruction rate (inst/s) -host_mem_usage 205896 # Number of bytes of host memory used -host_seconds 0.56 # Real time elapsed on the host -host_tick_rate 53415864 # Simulator tick rate (ticks/s) +host_inst_rate 19644 # Simulator instruction rate (inst/s) +host_mem_usage 155856 # Number of bytes of host memory used +host_seconds 0.30 # Real time elapsed on the host +host_tick_rate 98307932 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 5827 # Number of instructions simulated -sim_seconds 0.000030 # Number of seconds simulated -sim_ticks 29940500 # Number of ticks simulated +sim_seconds 0.000029 # Number of seconds simulated +sim_ticks 29206500 # Number of ticks simulated system.cpu.AGEN-Unit.instReqsProcessed 2090 # Number of Instructions Requests that completed in this resource. system.cpu.Branch-Predictor.instReqsProcessed 5828 # Number of Instructions Requests that completed in this resource. system.cpu.Branch-Predictor.predictedNotTaken 826 # Number of Branches Predicted As Not Taken (False). system.cpu.Branch-Predictor.predictedTaken 90 # Number of Branches Predicted As Taken (True). system.cpu.Decode-Unit.instReqsProcessed 5828 # Number of Instructions Requests that completed in this resource. +system.cpu.Execution-Unit.cyclesExecuted 3725 # Number of Cycles Execution Unit was used. system.cpu.Execution-Unit.instReqsProcessed 3734 # Number of Instructions Requests that completed in this resource. system.cpu.Execution-Unit.predictedNotTakenIncorrect 541 # Number of Branches Incorrectly Predicted As Not Taken). system.cpu.Execution-Unit.predictedTakenIncorrect 35 # Number of Branches Incorrectly Predicted As Taken. -system.cpu.Fetch-Buffer-T0.instReqsProcessed 0 # Number of Instructions Requests that completed in this resource. -system.cpu.Fetch-Buffer-T0.instsBypassed 0 # Number of Instructions Bypassed. -system.cpu.Fetch-Buffer-T1.instReqsProcessed 0 # Number of Instructions Requests that completed in this resource. -system.cpu.Fetch-Buffer-T1.instsBypassed 0 # Number of Instructions Bypassed. -system.cpu.Fetch-Seq-Unit.instReqsProcessed 11657 # Number of Instructions Requests that completed in this resource. +system.cpu.Execution-Unit.utilization 0.063769 # Utilization of Execution Unit (cycles / totalCycles). +system.cpu.Fetch-Seq-Unit.instReqsProcessed 11702 # Number of Instructions Requests that completed in this resource. system.cpu.Graduation-Unit.instReqsProcessed 5827 # Number of Instructions Requests that completed in this resource. system.cpu.Mult-Div-Unit.divInstReqsProcessed 1 # Number of Divide Requests Processed. system.cpu.Mult-Div-Unit.instReqsProcessed 8 # Number of Instructions Requests that completed in this resource. system.cpu.Mult-Div-Unit.multInstReqsProcessed 3 # Number of Multiply Requests Processed. system.cpu.RegFile-Manager.instReqsProcessed 10713 # Number of Instructions Requests that completed in this resource. +system.cpu.activity 20.277673 # Percentage of cycles cpu is active system.cpu.committedInsts 5827 # Number of Instructions Simulated (Per-Thread) system.cpu.committedInsts_total 5827 # Number of Instructions Simulated (Total) -system.cpu.cpi 10.276643 # CPI: Cycles Per Instruction (Per-Thread) -system.cpu.cpi_total 10.276643 # CPI: Total CPI of All Threads -system.cpu.dcache.ReadReq_accesses 1165 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 56201.149425 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 53201.149425 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 1078 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 4889500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.074678 # miss rate for ReadReq accesses +system.cpu.contextSwitches 1 # Number of context switches +system.cpu.cpi 10.024713 # CPI: Cycles Per Instruction (Per-Thread) +system.cpu.cpi_total 10.024713 # CPI: Total CPI of All Threads +system.cpu.dcache.ReadReq_accesses 1164 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 56229.885057 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 53229.885057 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 1077 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 4892000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.074742 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_misses 87 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_miss_latency 4628500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.074678 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_latency 4631000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.074742 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_misses 87 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 925 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 56554.687500 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53554.687500 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 56265.625000 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53265.625000 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_hits 861 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 3619500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 3601000 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_rate 0.069189 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_misses 64 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_miss_latency 3427500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 3409000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate 0.069189 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_misses 64 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 14.144928 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 14.137681 # Average number of references to valid blocks. system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 2090 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 56350.993377 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 53350.993377 # average overall mshr miss latency -system.cpu.dcache.demand_hits 1939 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 8509000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.072249 # miss rate for demand accesses +system.cpu.dcache.demand_accesses 2089 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 56245.033113 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 53245.033113 # average overall mshr miss latency +system.cpu.dcache.demand_hits 1938 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 8493000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.072283 # miss rate for demand accesses system.cpu.dcache.demand_misses 151 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 8056000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.072249 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_latency 8040000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.072283 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_misses 151 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.overall_accesses 2090 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 56350.993377 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 53350.993377 # average overall mshr miss latency +system.cpu.dcache.overall_accesses 2089 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 56245.033113 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 53245.033113 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 1939 # number of overall hits -system.cpu.dcache.overall_miss_latency 8509000 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.072249 # miss rate for overall accesses +system.cpu.dcache.overall_hits 1938 # number of overall hits +system.cpu.dcache.overall_miss_latency 8493000 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.072283 # miss rate for overall accesses system.cpu.dcache.overall_misses 151 # number of overall misses system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 8056000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.072249 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_latency 8040000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.072283 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_misses 151 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.sampled_refs 138 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 88.212490 # Cycle average of tags in use -system.cpu.dcache.total_refs 1952 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 88.491296 # Cycle average of tags in use +system.cpu.dcache.total_refs 1951 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 0 # number of writebacks system.cpu.dcache_port.instReqsProcessed 2089 # Number of Instructions Requests that completed in this resource. @@ -103,62 +103,63 @@ system.cpu.dtb.read_misses 0 # DT system.cpu.dtb.write_accesses 0 # DTB write accesses system.cpu.dtb.write_hits 0 # DTB write hits system.cpu.dtb.write_misses 0 # DTB write misses -system.cpu.icache.ReadReq_accesses 5829 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 55765.676568 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 52765.676568 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 5526 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 16897000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.051981 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_accesses 5874 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 55801.980198 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 52801.980198 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 5571 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 16908000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.051583 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_misses 303 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_miss_latency 15988000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.051981 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_latency 15999000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.051583 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_misses 303 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.icache.avg_refs 18.237624 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 18.386139 # Average number of references to valid blocks. system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 5829 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 55765.676568 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 52765.676568 # average overall mshr miss latency -system.cpu.icache.demand_hits 5526 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 16897000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.051981 # miss rate for demand accesses +system.cpu.icache.demand_accesses 5874 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 55801.980198 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 52801.980198 # average overall mshr miss latency +system.cpu.icache.demand_hits 5571 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 16908000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.051583 # miss rate for demand accesses system.cpu.icache.demand_misses 303 # number of demand (read+write) misses system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 15988000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.051981 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_latency 15999000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0.051583 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_misses 303 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses 5829 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 55765.676568 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 52765.676568 # average overall mshr miss latency +system.cpu.icache.overall_accesses 5874 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 55801.980198 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 52801.980198 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 5526 # number of overall hits -system.cpu.icache.overall_miss_latency 16897000 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.051981 # miss rate for overall accesses +system.cpu.icache.overall_hits 5571 # number of overall hits +system.cpu.icache.overall_miss_latency 16908000 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.051583 # miss rate for overall accesses system.cpu.icache.overall_misses 303 # number of overall misses system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 15988000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.051981 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_latency 15999000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0.051583 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_misses 303 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.icache.replacements 13 # number of replacements system.cpu.icache.sampled_refs 303 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 134.267603 # Cycle average of tags in use -system.cpu.icache.total_refs 5526 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 135.362853 # Cycle average of tags in use +system.cpu.icache.total_refs 5571 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.icache_port.instReqsProcessed 5828 # Number of Instructions Requests that completed in this resource. -system.cpu.ipc 0.097308 # IPC: Instructions Per Cycle (Per-Thread) -system.cpu.ipc_total 0.097308 # IPC: Total IPC of All Threads +system.cpu.icache_port.instReqsProcessed 5873 # Number of Instructions Requests that completed in this resource. +system.cpu.idleCycles 46569 # Number of cycles cpu's stages were not processed +system.cpu.ipc 0.099753 # IPC: Instructions Per Cycle (Per-Thread) +system.cpu.ipc_total 0.099753 # IPC: Total IPC of All Threads system.cpu.itb.accesses 0 # DTB accesses system.cpu.itb.hits 0 # DTB hits system.cpu.itb.misses 0 # DTB misses @@ -169,31 +170,31 @@ system.cpu.itb.write_accesses 0 # DT system.cpu.itb.write_hits 0 # DTB write hits system.cpu.itb.write_misses 0 # DTB write misses system.cpu.l2cache.ReadExReq_accesses 51 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency 52500 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency 52264.705882 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40098.039216 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_miss_latency 2677500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency 2665500 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_misses 51 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_mshr_miss_latency 2045000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_misses 51 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadReq_accesses 390 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 52052.835052 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40023.195876 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency 52091.494845 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40048.969072 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_hits 2 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 20196500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency 20211500 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_rate 0.994872 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_misses 388 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 15529000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency 15539000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate 0.994872 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_misses 388 # number of ReadReq MSHR misses system.cpu.l2cache.UpgradeReq_accesses 13 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_avg_miss_latency 52538.461538 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40076.923077 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_miss_latency 683000 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_avg_miss_latency 52192.307692 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40153.846154 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_miss_latency 678500 # number of UpgradeReq miss cycles system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_misses 13 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_mshr_miss_latency 521000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency 522000 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_mshr_misses 13 # number of UpgradeReq MSHR misses system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked @@ -205,29 +206,29 @@ system.cpu.l2cache.blocked_cycles::no_mshrs 0 # system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.demand_accesses 441 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 52104.783599 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 40031.890661 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_miss_latency 52111.617312 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 40054.669704 # average overall mshr miss latency system.cpu.l2cache.demand_hits 2 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 22874000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency 22877000 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_rate 0.995465 # miss rate for demand accesses system.cpu.l2cache.demand_misses 439 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 17574000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 17584000 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_rate 0.995465 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_misses 439 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.overall_accesses 441 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 52104.783599 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 40031.890661 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_miss_latency 52111.617312 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 40054.669704 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.l2cache.overall_hits 2 # number of overall hits -system.cpu.l2cache.overall_miss_latency 22874000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency 22877000 # number of overall miss cycles system.cpu.l2cache.overall_miss_rate 0.995465 # miss rate for overall accesses system.cpu.l2cache.overall_misses 439 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 17574000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 17584000 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_rate 0.995465 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_misses 439 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -235,16 +236,32 @@ system.cpu.l2cache.overall_mshr_uncacheable_misses 0 system.cpu.l2cache.replacements 0 # number of replacements system.cpu.l2cache.sampled_refs 375 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 185.807591 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 187.032260 # Cycle average of tags in use system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks -system.cpu.numCycles 59882 # number of cpu cycles simulated +system.cpu.numCycles 58414 # number of cpu cycles simulated +system.cpu.runCycles 11845 # Number of cycles cpu stages are processed. system.cpu.smtCommittedInsts 0 # Number of SMT Instructions Simulated (Per-Thread) -system.cpu.smtCycles 0 # Total number of cycles that the CPU was simultaneous multithreading.(SMT) +system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode system.cpu.smt_cpi no_value # CPI: Total SMT-CPI system.cpu.smt_ipc no_value # IPC: Total SMT-IPC -system.cpu.threadCycles 59882 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.stage-0.idleCycles 52540 # Number of cycles 0 instructions are processed. +system.cpu.stage-0.runCycles 5874 # Number of cycles 1+ instructions are processed. +system.cpu.stage-0.utilization 10.055809 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage-1.idleCycles 52586 # Number of cycles 0 instructions are processed. +system.cpu.stage-1.runCycles 5828 # Number of cycles 1+ instructions are processed. +system.cpu.stage-1.utilization 9.977060 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage-2.idleCycles 52582 # Number of cycles 0 instructions are processed. +system.cpu.stage-2.runCycles 5832 # Number of cycles 1+ instructions are processed. +system.cpu.stage-2.utilization 9.983908 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage-3.idleCycles 56324 # Number of cycles 0 instructions are processed. +system.cpu.stage-3.runCycles 2090 # Number of cycles 1+ instructions are processed. +system.cpu.stage-3.utilization 3.577909 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage-4.idleCycles 52587 # Number of cycles 0 instructions are processed. +system.cpu.stage-4.runCycles 5827 # Number of cycles 1+ instructions are processed. +system.cpu.stage-4.utilization 9.975348 # Percentage of cycles stage was utilized (processing insts). +system.cpu.threadCycles 58414 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.workload.PROG:num_syscalls 8 # Number of system calls ---------- End Simulation Statistics ---------- |