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-rw-r--r--tests/quick/00.hello/ref/mips/linux/o3-timing/config.ini3
-rwxr-xr-xtests/quick/00.hello/ref/mips/linux/o3-timing/simout6
-rw-r--r--tests/quick/00.hello/ref/mips/linux/o3-timing/stats.txt14
-rw-r--r--tests/quick/00.hello/ref/mips/linux/simple-atomic/config.ini1
-rwxr-xr-xtests/quick/00.hello/ref/mips/linux/simple-atomic/simerr1
-rwxr-xr-xtests/quick/00.hello/ref/mips/linux/simple-atomic/simout16
-rw-r--r--tests/quick/00.hello/ref/mips/linux/simple-atomic/stats.txt60
-rw-r--r--tests/quick/00.hello/ref/mips/linux/simple-timing-ruby/config.ini121
-rwxr-xr-xtests/quick/00.hello/ref/mips/linux/simple-timing-ruby/simerr1
-rwxr-xr-xtests/quick/00.hello/ref/mips/linux/simple-timing-ruby/simout16
-rw-r--r--tests/quick/00.hello/ref/mips/linux/simple-timing-ruby/stats.txt60
-rw-r--r--tests/quick/00.hello/ref/mips/linux/simple-timing/config.ini1
-rwxr-xr-xtests/quick/00.hello/ref/mips/linux/simple-timing/simerr1
-rwxr-xr-xtests/quick/00.hello/ref/mips/linux/simple-timing/simout16
-rw-r--r--tests/quick/00.hello/ref/mips/linux/simple-timing/stats.txt404
15 files changed, 365 insertions, 356 deletions
diff --git a/tests/quick/00.hello/ref/mips/linux/o3-timing/config.ini b/tests/quick/00.hello/ref/mips/linux/o3-timing/config.ini
index 8bda4905e..6a2ff3124 100644
--- a/tests/quick/00.hello/ref/mips/linux/o3-timing/config.ini
+++ b/tests/quick/00.hello/ref/mips/linux/o3-timing/config.ini
@@ -102,6 +102,7 @@ smtNumFetchingThreads=1
smtROBPolicy=Partitioned
smtROBThreshold=100
squashWidth=8
+store_set_clear_period=250000
system=system
tracer=system.cpu.tracer
trapLatency=13
@@ -499,7 +500,7 @@ egid=100
env=
errout=cerr
euid=100
-executable=/chips/pd/randd/dist/test-progs/hello/bin/mips/linux/hello
+executable=/dist/m5/regression/test-progs/hello/bin/mips/linux/hello
gid=100
input=cin
max_stack_size=67108864
diff --git a/tests/quick/00.hello/ref/mips/linux/o3-timing/simout b/tests/quick/00.hello/ref/mips/linux/o3-timing/simout
index cfd15d7a7..a0a2e036e 100755
--- a/tests/quick/00.hello/ref/mips/linux/o3-timing/simout
+++ b/tests/quick/00.hello/ref/mips/linux/o3-timing/simout
@@ -1,9 +1,9 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jul 15 2011 17:48:05
-gem5 started Jul 15 2011 20:13:48
-gem5 executing on u200439-lin.austin.arm.com
+gem5 compiled Sep 9 2011 01:24:08
+gem5 started Sep 9 2011 01:24:15
+gem5 executing on chips
command line: build/MIPS_SE/gem5.opt -d build/MIPS_SE/tests/opt/quick/00.hello/mips/linux/o3-timing -re tests/run.py build/MIPS_SE/tests/opt/quick/00.hello/mips/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
diff --git a/tests/quick/00.hello/ref/mips/linux/o3-timing/stats.txt b/tests/quick/00.hello/ref/mips/linux/o3-timing/stats.txt
index d9d305c59..eb0ece35d 100644
--- a/tests/quick/00.hello/ref/mips/linux/o3-timing/stats.txt
+++ b/tests/quick/00.hello/ref/mips/linux/o3-timing/stats.txt
@@ -3,10 +3,10 @@
sim_seconds 0.000012 # Number of seconds simulated
sim_ticks 12273500 # Number of ticks simulated
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 33014 # Simulator instruction rate (inst/s)
-host_tick_rate 78373339 # Simulator tick rate (ticks/s)
-host_mem_usage 244788 # Number of bytes of host memory used
-host_seconds 0.16 # Real time elapsed on the host
+host_inst_rate 39169 # Simulator instruction rate (inst/s)
+host_tick_rate 92983194 # Simulator tick rate (ticks/s)
+host_mem_usage 242872 # Number of bytes of host memory used
+host_seconds 0.13 # Real time elapsed on the host
sim_insts 5169 # Number of instructions simulated
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.dtb.read_misses 0 # DTB read misses
@@ -86,9 +86,9 @@ system.cpu.rename.UnblockCycles 111 # Nu
system.cpu.rename.RenamedInsts 11017 # Number of instructions processed by rename
system.cpu.rename.LSQFullEvents 101 # Number of times rename has blocked due to LSQ full
system.cpu.rename.RenamedOperands 6705 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 13125 # Number of register rename lookups that rename has made
+system.cpu.rename.RenameLookups 13124 # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups 13120 # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups 5 # Number of floating rename lookups
+system.cpu.rename.fp_rename_lookups 4 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 3410 # Number of HB maps that are committed
system.cpu.rename.UndoneMaps 3295 # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts 18 # count of serializing insts renamed
@@ -290,7 +290,7 @@ system.cpu.int_regfile_reads 10287 # nu
system.cpu.int_regfile_writes 4991 # number of integer regfile writes
system.cpu.fp_regfile_reads 3 # number of floating regfile reads
system.cpu.fp_regfile_writes 1 # number of floating regfile writes
-system.cpu.misc_regfile_reads 154 # number of misc regfile reads
+system.cpu.misc_regfile_reads 153 # number of misc regfile reads
system.cpu.icache.replacements 17 # number of replacements
system.cpu.icache.tagsinuse 161.223747 # Cycle average of tags in use
system.cpu.icache.total_refs 1364 # Total number of references to valid blocks.
diff --git a/tests/quick/00.hello/ref/mips/linux/simple-atomic/config.ini b/tests/quick/00.hello/ref/mips/linux/simple-atomic/config.ini
index 9c80192e1..fda15903b 100644
--- a/tests/quick/00.hello/ref/mips/linux/simple-atomic/config.ini
+++ b/tests/quick/00.hello/ref/mips/linux/simple-atomic/config.ini
@@ -9,6 +9,7 @@ time_sync_spin_threshold=100000000
type=System
children=cpu membus physmem
mem_mode=atomic
+memories=system.physmem
physmem=system.physmem
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
diff --git a/tests/quick/00.hello/ref/mips/linux/simple-atomic/simerr b/tests/quick/00.hello/ref/mips/linux/simple-atomic/simerr
index eabe42249..e45cd058f 100755
--- a/tests/quick/00.hello/ref/mips/linux/simple-atomic/simerr
+++ b/tests/quick/00.hello/ref/mips/linux/simple-atomic/simerr
@@ -1,3 +1,2 @@
warn: Sockets disabled, not accepting gdb connections
-For more information see: http://www.m5sim.org/warn/d946bea6
hack: be nice to actually delete the event here
diff --git a/tests/quick/00.hello/ref/mips/linux/simple-atomic/simout b/tests/quick/00.hello/ref/mips/linux/simple-atomic/simout
index 8a1b8f67f..1b8822a01 100755
--- a/tests/quick/00.hello/ref/mips/linux/simple-atomic/simout
+++ b/tests/quick/00.hello/ref/mips/linux/simple-atomic/simout
@@ -1,14 +1,10 @@
-M5 Simulator System
+gem5 Simulator System. http://gem5.org
+gem5 is copyrighted software; use the --copyright option for details.
-Copyright (c) 2001-2008
-The Regents of The University of Michigan
-All Rights Reserved
-
-
-M5 compiled Apr 19 2011 12:18:54
-M5 started Apr 19 2011 12:18:58
-M5 executing on maize
-command line: build/MIPS_SE/m5.fast -d build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/simple-atomic -re tests/run.py build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/simple-atomic
+gem5 compiled Sep 9 2011 01:24:08
+gem5 started Sep 9 2011 01:24:15
+gem5 executing on chips
+command line: build/MIPS_SE/gem5.opt -d build/MIPS_SE/tests/opt/quick/00.hello/mips/linux/simple-atomic -re tests/run.py build/MIPS_SE/tests/opt/quick/00.hello/mips/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
diff --git a/tests/quick/00.hello/ref/mips/linux/simple-atomic/stats.txt b/tests/quick/00.hello/ref/mips/linux/simple-atomic/stats.txt
index 4243ca997..8495d4b7b 100644
--- a/tests/quick/00.hello/ref/mips/linux/simple-atomic/stats.txt
+++ b/tests/quick/00.hello/ref/mips/linux/simple-atomic/stats.txt
@@ -1,52 +1,52 @@
---------- Begin Simulation Statistics ----------
-host_inst_rate 798153 # Simulator instruction rate (inst/s)
-host_mem_usage 195780 # Number of bytes of host memory used
-host_seconds 0.01 # Real time elapsed on the host
-host_tick_rate 390049435 # Simulator tick rate (ticks/s)
-sim_freq 1000000000000 # Frequency of simulated ticks
-sim_insts 5827 # Number of instructions simulated
sim_seconds 0.000003 # Number of seconds simulated
sim_ticks 2913500 # Number of ticks simulated
-system.cpu.dtb.accesses 0 # DTB accesses
-system.cpu.dtb.hits 0 # DTB hits
-system.cpu.dtb.misses 0 # DTB misses
-system.cpu.dtb.read_accesses 0 # DTB read accesses
+sim_freq 1000000000000 # Frequency of simulated ticks
+host_inst_rate 550881 # Simulator instruction rate (inst/s)
+host_tick_rate 274282730 # Simulator tick rate (ticks/s)
+host_mem_usage 232848 # Number of bytes of host memory used
+host_seconds 0.01 # Real time elapsed on the host
+sim_insts 5827 # Number of instructions simulated
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.dtb.read_misses 0 # DTB read misses
-system.cpu.dtb.write_accesses 0 # DTB write accesses
+system.cpu.dtb.read_accesses 0 # DTB read accesses
system.cpu.dtb.write_hits 0 # DTB write hits
system.cpu.dtb.write_misses 0 # DTB write misses
-system.cpu.idle_fraction 0 # Percentage of idle cycles
-system.cpu.itb.accesses 0 # DTB accesses
-system.cpu.itb.hits 0 # DTB hits
-system.cpu.itb.misses 0 # DTB misses
-system.cpu.itb.read_accesses 0 # DTB read accesses
+system.cpu.dtb.write_accesses 0 # DTB write accesses
+system.cpu.dtb.hits 0 # DTB hits
+system.cpu.dtb.misses 0 # DTB misses
+system.cpu.dtb.accesses 0 # DTB accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
-system.cpu.itb.write_accesses 0 # DTB write accesses
+system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
-system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
+system.cpu.itb.write_accesses 0 # DTB write accesses
+system.cpu.itb.hits 0 # DTB hits
+system.cpu.itb.misses 0 # DTB misses
+system.cpu.itb.accesses 0 # DTB accesses
+system.cpu.workload.num_syscalls 8 # Number of system calls
system.cpu.numCycles 5828 # number of cpu cycles simulated
-system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
-system.cpu.num_busy_cycles 5828 # Number of busy cycles
-system.cpu.num_conditional_control_insts 677 # number of instructions that are conditional controls
-system.cpu.num_fp_alu_accesses 2 # Number of float alu accesses
-system.cpu.num_fp_insts 2 # number of float instructions
-system.cpu.num_fp_register_reads 3 # number of times the floating registers were read
-system.cpu.num_fp_register_writes 1 # number of times the floating registers were written
-system.cpu.num_func_calls 194 # number of times a function call or return occured
-system.cpu.num_idle_cycles 0 # Number of idle cycles
+system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.num_insts 5827 # Number of instructions executed
system.cpu.num_int_alu_accesses 5126 # Number of integer alu accesses
+system.cpu.num_fp_alu_accesses 2 # Number of float alu accesses
+system.cpu.num_func_calls 194 # number of times a function call or return occured
+system.cpu.num_conditional_control_insts 677 # number of instructions that are conditional controls
system.cpu.num_int_insts 5126 # number of integer instructions
-system.cpu.num_int_register_reads 7301 # number of times the integer registers were read
+system.cpu.num_fp_insts 2 # number of float instructions
+system.cpu.num_int_register_reads 7300 # number of times the integer registers were read
system.cpu.num_int_register_writes 3409 # number of times the integer registers were written
-system.cpu.num_load_insts 1164 # Number of load instructions
+system.cpu.num_fp_register_reads 3 # number of times the floating registers were read
+system.cpu.num_fp_register_writes 1 # number of times the floating registers were written
system.cpu.num_mem_refs 2090 # number of memory refs
+system.cpu.num_load_insts 1164 # Number of load instructions
system.cpu.num_store_insts 926 # Number of store instructions
-system.cpu.workload.num_syscalls 8 # Number of system calls
+system.cpu.num_idle_cycles 0 # Number of idle cycles
+system.cpu.num_busy_cycles 5828 # Number of busy cycles
+system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
+system.cpu.idle_fraction 0 # Percentage of idle cycles
---------- End Simulation Statistics ----------
diff --git a/tests/quick/00.hello/ref/mips/linux/simple-timing-ruby/config.ini b/tests/quick/00.hello/ref/mips/linux/simple-timing-ruby/config.ini
index 39758d41d..41938cc87 100644
--- a/tests/quick/00.hello/ref/mips/linux/simple-timing-ruby/config.ini
+++ b/tests/quick/00.hello/ref/mips/linux/simple-timing-ruby/config.ini
@@ -9,6 +9,7 @@ time_sync_spin_threshold=100000
type=System
children=cpu dir_cntrl0 l1_cntrl0 physmem ruby
mem_mode=timing
+memories=system.physmem
physmem=system.physmem
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
@@ -41,8 +42,8 @@ progress_interval=0
system=system
tracer=system.cpu.tracer
workload=system.cpu.workload
-dcache_port=system.ruby.cpu_ruby_ports.port[1]
-icache_port=system.ruby.cpu_ruby_ports.port[0]
+dcache_port=system.l1_cntrl0.sequencer.port[1]
+icache_port=system.l1_cntrl0.sequencer.port[0]
[system.cpu.dtb]
type=MipsTLB
@@ -78,11 +79,13 @@ uid=100
type=Directory_Controller
children=directory memBuffer
buffer_size=0
+cntrl_id=1
directory=system.dir_cntrl0.directory
directory_latency=12
memBuffer=system.dir_cntrl0.memBuffer
number_of_TBEs=256
recycle_latency=10
+ruby_system=system.ruby
transitions_per_cycle=32
version=0
@@ -117,16 +120,42 @@ version=0
[system.l1_cntrl0]
type=L1Cache_Controller
+children=cacheMemory sequencer
buffer_size=0
-cacheMemory=system.ruby.cpu_ruby_ports.dcache
+cacheMemory=system.l1_cntrl0.cacheMemory
cache_response_latency=12
+cntrl_id=0
issue_latency=2
number_of_TBEs=256
recycle_latency=10
-sequencer=system.ruby.cpu_ruby_ports
+ruby_system=system.ruby
+sequencer=system.l1_cntrl0.sequencer
transitions_per_cycle=32
version=0
+[system.l1_cntrl0.cacheMemory]
+type=RubyCache
+assoc=2
+latency=3
+replacement_policy=PSEUDO_LRU
+size=256
+start_index_bit=6
+
+[system.l1_cntrl0.sequencer]
+type=RubySequencer
+access_phys_mem=true
+dcache=system.l1_cntrl0.cacheMemory
+deadlock_threshold=500000
+icache=system.l1_cntrl0.cacheMemory
+max_outstanding_requests=16
+physmem=system.physmem
+ruby_system=system.ruby
+using_network_tester=false
+using_ruby_tester=false
+version=0
+physMemPort=system.physmem.port[0]
+port=system.cpu.icache_port system.cpu.dcache_port
+
[system.physmem]
type=PhysicalMemory
file=
@@ -135,44 +164,18 @@ latency_var=0
null=false
range=0:134217727
zero=false
-port=system.ruby.cpu_ruby_ports.physMemPort
+port=system.l1_cntrl0.sequencer.physMemPort
[system.ruby]
type=RubySystem
-children=cpu_ruby_ports network profiler tracer
+children=network profiler tracer
block_size_bytes=64
clock=1
mem_size=134217728
-network=system.ruby.network
no_mem_vec=false
-profiler=system.ruby.profiler
random_seed=1234
randomization=false
stats_filename=ruby.stats
-tracer=system.ruby.tracer
-
-[system.ruby.cpu_ruby_ports]
-type=RubySequencer
-children=dcache
-access_phys_mem=true
-dcache=system.ruby.cpu_ruby_ports.dcache
-deadlock_threshold=500000
-icache=system.ruby.cpu_ruby_ports.dcache
-max_outstanding_requests=16
-physmem=system.physmem
-using_network_tester=false
-using_ruby_tester=false
-version=0
-physMemPort=system.physmem.port[0]
-port=system.cpu.icache_port system.cpu.dcache_port
-
-[system.ruby.cpu_ruby_ports.dcache]
-type=RubyCache
-assoc=2
-latency=3
-replacement_policy=PSEUDO_LRU
-size=256
-start_index_bit=6
[system.ruby.network]
type=SimpleNetwork
@@ -180,59 +183,77 @@ children=topology
adaptive_routing=false
buffer_size=0
control_msg_size=8
-endpoint_bandwidth=10000
-link_latency=1
+endpoint_bandwidth=1000
number_of_virtual_networks=10
+ruby_system=system.ruby
topology=system.ruby.network.topology
[system.ruby.network.topology]
type=Topology
-children=ext_links0 ext_links1 int_links0 int_links1
+children=ext_links0 ext_links1 int_links0 int_links1 routers0 routers1 routers2
description=Crossbar
ext_links=system.ruby.network.topology.ext_links0 system.ruby.network.topology.ext_links1
int_links=system.ruby.network.topology.int_links0 system.ruby.network.topology.int_links1
-num_int_nodes=3
print_config=false
+routers=system.ruby.network.topology.routers0 system.ruby.network.topology.routers1 system.ruby.network.topology.routers2
[system.ruby.network.topology.ext_links0]
-type=ExtLink
-bw_multiplier=64
+type=SimpleExtLink
+bandwidth_factor=16
ext_node=system.l1_cntrl0
-int_node=0
+int_node=system.ruby.network.topology.routers0
latency=1
+link_id=0
weight=1
[system.ruby.network.topology.ext_links1]
-type=ExtLink
-bw_multiplier=64
+type=SimpleExtLink
+bandwidth_factor=16
ext_node=system.dir_cntrl0
-int_node=1
+int_node=system.ruby.network.topology.routers1
latency=1
+link_id=1
weight=1
[system.ruby.network.topology.int_links0]
-type=IntLink
-bw_multiplier=16
+type=SimpleIntLink
+bandwidth_factor=16
latency=1
-node_a=0
-node_b=2
+link_id=2
+node_a=system.ruby.network.topology.routers0
+node_b=system.ruby.network.topology.routers2
weight=1
[system.ruby.network.topology.int_links1]
-type=IntLink
-bw_multiplier=16
+type=SimpleIntLink
+bandwidth_factor=16
latency=1
-node_a=1
-node_b=2
+link_id=3
+node_a=system.ruby.network.topology.routers1
+node_b=system.ruby.network.topology.routers2
weight=1
+[system.ruby.network.topology.routers0]
+type=BasicRouter
+router_id=0
+
+[system.ruby.network.topology.routers1]
+type=BasicRouter
+router_id=1
+
+[system.ruby.network.topology.routers2]
+type=BasicRouter
+router_id=2
+
[system.ruby.profiler]
type=RubyProfiler
all_instructions=false
hot_lines=false
num_of_sequencers=1
+ruby_system=system.ruby
[system.ruby.tracer]
type=RubyTracer
+ruby_system=system.ruby
warmup_length=100000
diff --git a/tests/quick/00.hello/ref/mips/linux/simple-timing-ruby/simerr b/tests/quick/00.hello/ref/mips/linux/simple-timing-ruby/simerr
index eabe42249..e45cd058f 100755
--- a/tests/quick/00.hello/ref/mips/linux/simple-timing-ruby/simerr
+++ b/tests/quick/00.hello/ref/mips/linux/simple-timing-ruby/simerr
@@ -1,3 +1,2 @@
warn: Sockets disabled, not accepting gdb connections
-For more information see: http://www.m5sim.org/warn/d946bea6
hack: be nice to actually delete the event here
diff --git a/tests/quick/00.hello/ref/mips/linux/simple-timing-ruby/simout b/tests/quick/00.hello/ref/mips/linux/simple-timing-ruby/simout
index e7dec82e9..12fac784c 100755
--- a/tests/quick/00.hello/ref/mips/linux/simple-timing-ruby/simout
+++ b/tests/quick/00.hello/ref/mips/linux/simple-timing-ruby/simout
@@ -1,14 +1,10 @@
-M5 Simulator System
+gem5 Simulator System. http://gem5.org
+gem5 is copyrighted software; use the --copyright option for details.
-Copyright (c) 2001-2008
-The Regents of The University of Michigan
-All Rights Reserved
-
-
-M5 compiled Apr 19 2011 12:18:54
-M5 started Apr 19 2011 12:18:57
-M5 executing on maize
-command line: build/MIPS_SE/m5.fast -d build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/simple-timing-ruby -re tests/run.py build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/simple-timing-ruby
+gem5 compiled Sep 9 2011 01:24:08
+gem5 started Sep 9 2011 01:24:15
+gem5 executing on chips
+command line: build/MIPS_SE/gem5.opt -d build/MIPS_SE/tests/opt/quick/00.hello/mips/linux/simple-timing-ruby -re tests/run.py build/MIPS_SE/tests/opt/quick/00.hello/mips/linux/simple-timing-ruby
Global frequency set at 1000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
diff --git a/tests/quick/00.hello/ref/mips/linux/simple-timing-ruby/stats.txt b/tests/quick/00.hello/ref/mips/linux/simple-timing-ruby/stats.txt
index 12dfdb011..0e750eb72 100644
--- a/tests/quick/00.hello/ref/mips/linux/simple-timing-ruby/stats.txt
+++ b/tests/quick/00.hello/ref/mips/linux/simple-timing-ruby/stats.txt
@@ -1,52 +1,52 @@
---------- Begin Simulation Statistics ----------
-host_inst_rate 81519 # Simulator instruction rate (inst/s)
-host_mem_usage 213976 # Number of bytes of host memory used
-host_seconds 0.07 # Real time elapsed on the host
-host_tick_rate 4090793 # Simulator tick rate (ticks/s)
-sim_freq 1000000000 # Frequency of simulated ticks
-sim_insts 5827 # Number of instructions simulated
sim_seconds 0.000293 # Number of seconds simulated
sim_ticks 292960 # Number of ticks simulated
-system.cpu.dtb.accesses 0 # DTB accesses
-system.cpu.dtb.hits 0 # DTB hits
-system.cpu.dtb.misses 0 # DTB misses
-system.cpu.dtb.read_accesses 0 # DTB read accesses
+sim_freq 1000000000 # Frequency of simulated ticks
+host_inst_rate 24172 # Simulator instruction rate (inst/s)
+host_tick_rate 1215173 # Simulator tick rate (ticks/s)
+host_mem_usage 251116 # Number of bytes of host memory used
+host_seconds 0.24 # Real time elapsed on the host
+sim_insts 5827 # Number of instructions simulated
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.dtb.read_misses 0 # DTB read misses
-system.cpu.dtb.write_accesses 0 # DTB write accesses
+system.cpu.dtb.read_accesses 0 # DTB read accesses
system.cpu.dtb.write_hits 0 # DTB write hits
system.cpu.dtb.write_misses 0 # DTB write misses
-system.cpu.idle_fraction 0 # Percentage of idle cycles
-system.cpu.itb.accesses 0 # DTB accesses
-system.cpu.itb.hits 0 # DTB hits
-system.cpu.itb.misses 0 # DTB misses
-system.cpu.itb.read_accesses 0 # DTB read accesses
+system.cpu.dtb.write_accesses 0 # DTB write accesses
+system.cpu.dtb.hits 0 # DTB hits
+system.cpu.dtb.misses 0 # DTB misses
+system.cpu.dtb.accesses 0 # DTB accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
-system.cpu.itb.write_accesses 0 # DTB write accesses
+system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
-system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
+system.cpu.itb.write_accesses 0 # DTB write accesses
+system.cpu.itb.hits 0 # DTB hits
+system.cpu.itb.misses 0 # DTB misses
+system.cpu.itb.accesses 0 # DTB accesses
+system.cpu.workload.num_syscalls 8 # Number of system calls
system.cpu.numCycles 292960 # number of cpu cycles simulated
-system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
-system.cpu.num_busy_cycles 292960 # Number of busy cycles
-system.cpu.num_conditional_control_insts 677 # number of instructions that are conditional controls
-system.cpu.num_fp_alu_accesses 2 # Number of float alu accesses
-system.cpu.num_fp_insts 2 # number of float instructions
-system.cpu.num_fp_register_reads 3 # number of times the floating registers were read
-system.cpu.num_fp_register_writes 1 # number of times the floating registers were written
-system.cpu.num_func_calls 194 # number of times a function call or return occured
-system.cpu.num_idle_cycles 0 # Number of idle cycles
+system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.num_insts 5827 # Number of instructions executed
system.cpu.num_int_alu_accesses 5126 # Number of integer alu accesses
+system.cpu.num_fp_alu_accesses 2 # Number of float alu accesses
+system.cpu.num_func_calls 194 # number of times a function call or return occured
+system.cpu.num_conditional_control_insts 677 # number of instructions that are conditional controls
system.cpu.num_int_insts 5126 # number of integer instructions
-system.cpu.num_int_register_reads 7301 # number of times the integer registers were read
+system.cpu.num_fp_insts 2 # number of float instructions
+system.cpu.num_int_register_reads 7300 # number of times the integer registers were read
system.cpu.num_int_register_writes 3409 # number of times the integer registers were written
-system.cpu.num_load_insts 1164 # Number of load instructions
+system.cpu.num_fp_register_reads 3 # number of times the floating registers were read
+system.cpu.num_fp_register_writes 1 # number of times the floating registers were written
system.cpu.num_mem_refs 2090 # number of memory refs
+system.cpu.num_load_insts 1164 # Number of load instructions
system.cpu.num_store_insts 926 # Number of store instructions
-system.cpu.workload.num_syscalls 8 # Number of system calls
+system.cpu.num_idle_cycles 0 # Number of idle cycles
+system.cpu.num_busy_cycles 292960 # Number of busy cycles
+system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
+system.cpu.idle_fraction 0 # Percentage of idle cycles
---------- End Simulation Statistics ----------
diff --git a/tests/quick/00.hello/ref/mips/linux/simple-timing/config.ini b/tests/quick/00.hello/ref/mips/linux/simple-timing/config.ini
index 00709865b..383b176d8 100644
--- a/tests/quick/00.hello/ref/mips/linux/simple-timing/config.ini
+++ b/tests/quick/00.hello/ref/mips/linux/simple-timing/config.ini
@@ -9,6 +9,7 @@ time_sync_spin_threshold=100000000
type=System
children=cpu membus physmem
mem_mode=atomic
+memories=system.physmem
physmem=system.physmem
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
diff --git a/tests/quick/00.hello/ref/mips/linux/simple-timing/simerr b/tests/quick/00.hello/ref/mips/linux/simple-timing/simerr
index eabe42249..e45cd058f 100755
--- a/tests/quick/00.hello/ref/mips/linux/simple-timing/simerr
+++ b/tests/quick/00.hello/ref/mips/linux/simple-timing/simerr
@@ -1,3 +1,2 @@
warn: Sockets disabled, not accepting gdb connections
-For more information see: http://www.m5sim.org/warn/d946bea6
hack: be nice to actually delete the event here
diff --git a/tests/quick/00.hello/ref/mips/linux/simple-timing/simout b/tests/quick/00.hello/ref/mips/linux/simple-timing/simout
index 3a1be45f5..6cd1e0d5c 100755
--- a/tests/quick/00.hello/ref/mips/linux/simple-timing/simout
+++ b/tests/quick/00.hello/ref/mips/linux/simple-timing/simout
@@ -1,14 +1,10 @@
-M5 Simulator System
+gem5 Simulator System. http://gem5.org
+gem5 is copyrighted software; use the --copyright option for details.
-Copyright (c) 2001-2008
-The Regents of The University of Michigan
-All Rights Reserved
-
-
-M5 compiled Apr 19 2011 12:18:54
-M5 started Apr 19 2011 12:18:57
-M5 executing on maize
-command line: build/MIPS_SE/m5.fast -d build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/simple-timing -re tests/run.py build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/simple-timing
+gem5 compiled Sep 9 2011 01:24:08
+gem5 started Sep 9 2011 01:24:15
+gem5 executing on chips
+command line: build/MIPS_SE/gem5.opt -d build/MIPS_SE/tests/opt/quick/00.hello/mips/linux/simple-timing -re tests/run.py build/MIPS_SE/tests/opt/quick/00.hello/mips/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
diff --git a/tests/quick/00.hello/ref/mips/linux/simple-timing/stats.txt b/tests/quick/00.hello/ref/mips/linux/simple-timing/stats.txt
index ec5ae032f..d92612e60 100644
--- a/tests/quick/00.hello/ref/mips/linux/simple-timing/stats.txt
+++ b/tests/quick/00.hello/ref/mips/linux/simple-timing/stats.txt
@@ -1,236 +1,236 @@
---------- Begin Simulation Statistics ----------
-host_inst_rate 524923 # Simulator instruction rate (inst/s)
-host_mem_usage 203516 # Number of bytes of host memory used
-host_seconds 0.01 # Real time elapsed on the host
-host_tick_rate 2843944401 # Simulator tick rate (ticks/s)
-sim_freq 1000000000000 # Frequency of simulated ticks
-sim_insts 5827 # Number of instructions simulated
sim_seconds 0.000032 # Number of seconds simulated
sim_ticks 32088000 # Number of ticks simulated
-system.cpu.dcache.ReadReq_accesses 1164 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency 56000 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 53000 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_hits 1077 # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency 4872000 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_rate 0.074742 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_misses 87 # number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_miss_latency 4611000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate 0.074742 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_misses 87 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_accesses 925 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency 56000 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53000 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_hits 874 # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency 2856000 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_rate 0.055135 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses 51 # number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_miss_latency 2703000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_rate 0.055135 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_misses 51 # number of WriteReq MSHR misses
-system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.cpu.dcache.avg_refs 14.137681 # Average number of references to valid blocks.
-system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.demand_accesses 2089 # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency 56000 # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 53000 # average overall mshr miss latency
-system.cpu.dcache.demand_hits 1951 # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency 7728000 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_rate 0.066060 # miss rate for demand accesses
-system.cpu.dcache.demand_misses 138 # number of demand (read+write) misses
-system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency 7314000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_rate 0.066060 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_misses 138 # number of demand (read+write) MSHR misses
-system.cpu.dcache.fast_writes 0 # number of fast writes performed
-system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.occ_blocks::0 87.458397 # Average occupied blocks per context
-system.cpu.dcache.occ_percent::0 0.021352 # Average percentage of cache occupancy
-system.cpu.dcache.overall_accesses 2089 # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency 56000 # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits 1951 # number of overall hits
-system.cpu.dcache.overall_miss_latency 7728000 # number of overall miss cycles
-system.cpu.dcache.overall_miss_rate 0.066060 # miss rate for overall accesses
-system.cpu.dcache.overall_misses 138 # number of overall misses
-system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency 7314000 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_rate 0.066060 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_misses 138 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.dcache.replacements 0 # number of replacements
-system.cpu.dcache.sampled_refs 138 # Sample count of references to valid blocks.
-system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse 87.458397 # Cycle average of tags in use
-system.cpu.dcache.total_refs 1951 # Total number of references to valid blocks.
-system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.writebacks 0 # number of writebacks
-system.cpu.dtb.accesses 0 # DTB accesses
-system.cpu.dtb.hits 0 # DTB hits
-system.cpu.dtb.misses 0 # DTB misses
-system.cpu.dtb.read_accesses 0 # DTB read accesses
+sim_freq 1000000000000 # Frequency of simulated ticks
+host_inst_rate 266984 # Simulator instruction rate (inst/s)
+host_tick_rate 1467506046 # Simulator tick rate (ticks/s)
+host_mem_usage 241568 # Number of bytes of host memory used
+host_seconds 0.02 # Real time elapsed on the host
+sim_insts 5827 # Number of instructions simulated
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.dtb.read_misses 0 # DTB read misses
-system.cpu.dtb.write_accesses 0 # DTB write accesses
+system.cpu.dtb.read_accesses 0 # DTB read accesses
system.cpu.dtb.write_hits 0 # DTB write hits
system.cpu.dtb.write_misses 0 # DTB write misses
-system.cpu.icache.ReadReq_accesses 5829 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_avg_miss_latency 55722.772277 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 52722.772277 # average ReadReq mshr miss latency
+system.cpu.dtb.write_accesses 0 # DTB write accesses
+system.cpu.dtb.hits 0 # DTB hits
+system.cpu.dtb.misses 0 # DTB misses
+system.cpu.dtb.accesses 0 # DTB accesses
+system.cpu.itb.read_hits 0 # DTB read hits
+system.cpu.itb.read_misses 0 # DTB read misses
+system.cpu.itb.read_accesses 0 # DTB read accesses
+system.cpu.itb.write_hits 0 # DTB write hits
+system.cpu.itb.write_misses 0 # DTB write misses
+system.cpu.itb.write_accesses 0 # DTB write accesses
+system.cpu.itb.hits 0 # DTB hits
+system.cpu.itb.misses 0 # DTB misses
+system.cpu.itb.accesses 0 # DTB accesses
+system.cpu.workload.num_syscalls 8 # Number of system calls
+system.cpu.numCycles 64176 # number of cpu cycles simulated
+system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
+system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
+system.cpu.num_insts 5827 # Number of instructions executed
+system.cpu.num_int_alu_accesses 5126 # Number of integer alu accesses
+system.cpu.num_fp_alu_accesses 2 # Number of float alu accesses
+system.cpu.num_func_calls 194 # number of times a function call or return occured
+system.cpu.num_conditional_control_insts 677 # number of instructions that are conditional controls
+system.cpu.num_int_insts 5126 # number of integer instructions
+system.cpu.num_fp_insts 2 # number of float instructions
+system.cpu.num_int_register_reads 7300 # number of times the integer registers were read
+system.cpu.num_int_register_writes 3409 # number of times the integer registers were written
+system.cpu.num_fp_register_reads 3 # number of times the floating registers were read
+system.cpu.num_fp_register_writes 1 # number of times the floating registers were written
+system.cpu.num_mem_refs 2090 # number of memory refs
+system.cpu.num_load_insts 1164 # Number of load instructions
+system.cpu.num_store_insts 926 # Number of store instructions
+system.cpu.num_idle_cycles 0 # Number of idle cycles
+system.cpu.num_busy_cycles 64176 # Number of busy cycles
+system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
+system.cpu.idle_fraction 0 # Percentage of idle cycles
+system.cpu.icache.replacements 13 # number of replacements
+system.cpu.icache.tagsinuse 132.493866 # Cycle average of tags in use
+system.cpu.icache.total_refs 5526 # Total number of references to valid blocks.
+system.cpu.icache.sampled_refs 303 # Sample count of references to valid blocks.
+system.cpu.icache.avg_refs 18.237624 # Average number of references to valid blocks.
+system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu.icache.occ_blocks::0 132.493866 # Average occupied blocks per context
+system.cpu.icache.occ_percent::0 0.064694 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits 5526 # number of ReadReq hits
+system.cpu.icache.demand_hits 5526 # number of demand (read+write) hits
+system.cpu.icache.overall_hits 5526 # number of overall hits
+system.cpu.icache.ReadReq_misses 303 # number of ReadReq misses
+system.cpu.icache.demand_misses 303 # number of demand (read+write) misses
+system.cpu.icache.overall_misses 303 # number of overall misses
system.cpu.icache.ReadReq_miss_latency 16884000 # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency 16884000 # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency 16884000 # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses 5829 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses 5829 # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses 5829 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate 0.051981 # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_misses 303 # number of ReadReq misses
-system.cpu.icache.ReadReq_mshr_miss_latency 15975000 # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate 0.051981 # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_misses 303 # number of ReadReq MSHR misses
-system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.cpu.icache.avg_refs 18.237624 # Average number of references to valid blocks.
-system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu.icache.demand_miss_rate 0.051981 # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate 0.051981 # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency 55722.772277 # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency 55722.772277 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency 55722.772277 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
+system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
+system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.demand_accesses 5829 # number of demand (read+write) accesses
-system.cpu.icache.demand_avg_miss_latency 55722.772277 # average overall miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 52722.772277 # average overall mshr miss latency
-system.cpu.icache.demand_hits 5526 # number of demand (read+write) hits
-system.cpu.icache.demand_miss_latency 16884000 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_rate 0.051981 # miss rate for demand accesses
-system.cpu.icache.demand_misses 303 # number of demand (read+write) misses
+system.cpu.icache.writebacks 0 # number of writebacks
system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses 303 # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses 303 # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses 303 # number of overall MSHR misses
+system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu.icache.ReadReq_mshr_miss_latency 15975000 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency 15975000 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency 15975000 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu.icache.ReadReq_mshr_miss_rate 0.051981 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate 0.051981 # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_misses 303 # number of demand (read+write) MSHR misses
-system.cpu.icache.fast_writes 0 # number of fast writes performed
-system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.icache.occ_blocks::0 132.493866 # Average occupied blocks per context
-system.cpu.icache.occ_percent::0 0.064694 # Average percentage of cache occupancy
-system.cpu.icache.overall_accesses 5829 # number of overall (read+write) accesses
-system.cpu.icache.overall_avg_miss_latency 55722.772277 # average overall miss latency
+system.cpu.icache.overall_mshr_miss_rate 0.051981 # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 52722.772277 # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 52722.772277 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 52722.772277 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.icache.overall_hits 5526 # number of overall hits
-system.cpu.icache.overall_miss_latency 16884000 # number of overall miss cycles
-system.cpu.icache.overall_miss_rate 0.051981 # miss rate for overall accesses
-system.cpu.icache.overall_misses 303 # number of overall misses
-system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.icache.overall_mshr_miss_latency 15975000 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_rate 0.051981 # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_misses 303 # number of overall MSHR misses
-system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.icache.replacements 13 # number of replacements
-system.cpu.icache.sampled_refs 303 # Sample count of references to valid blocks.
+system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse 132.493866 # Cycle average of tags in use
-system.cpu.icache.total_refs 5526 # Total number of references to valid blocks.
-system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.writebacks 0 # number of writebacks
-system.cpu.idle_fraction 0 # Percentage of idle cycles
-system.cpu.itb.accesses 0 # DTB accesses
-system.cpu.itb.hits 0 # DTB hits
-system.cpu.itb.misses 0 # DTB misses
-system.cpu.itb.read_accesses 0 # DTB read accesses
-system.cpu.itb.read_hits 0 # DTB read hits
-system.cpu.itb.read_misses 0 # DTB read misses
-system.cpu.itb.write_accesses 0 # DTB write accesses
-system.cpu.itb.write_hits 0 # DTB write hits
-system.cpu.itb.write_misses 0 # DTB write misses
-system.cpu.l2cache.ReadExReq_accesses 51 # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_miss_latency 2652000 # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_misses 51 # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency 2040000 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_misses 51 # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadReq_accesses 390 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency
+system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.dcache.replacements 0 # number of replacements
+system.cpu.dcache.tagsinuse 87.458397 # Cycle average of tags in use
+system.cpu.dcache.total_refs 1951 # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs 138 # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs 14.137681 # Average number of references to valid blocks.
+system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.occ_blocks::0 87.458397 # Average occupied blocks per context
+system.cpu.dcache.occ_percent::0 0.021352 # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits 1077 # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits 874 # number of WriteReq hits
+system.cpu.dcache.demand_hits 1951 # number of demand (read+write) hits
+system.cpu.dcache.overall_hits 1951 # number of overall hits
+system.cpu.dcache.ReadReq_misses 87 # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses 51 # number of WriteReq misses
+system.cpu.dcache.demand_misses 138 # number of demand (read+write) misses
+system.cpu.dcache.overall_misses 138 # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency 4872000 # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency 2856000 # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency 7728000 # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency 7728000 # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses 1164 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses 925 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses 2089 # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses 2089 # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate 0.074742 # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate 0.055135 # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate 0.066060 # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate 0.066060 # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency 56000 # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency 56000 # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency 56000 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency 56000 # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
+system.cpu.dcache.fast_writes 0 # number of fast writes performed
+system.cpu.dcache.cache_copies 0 # number of cache copies performed
+system.cpu.dcache.writebacks 0 # number of writebacks
+system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses 87 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses 51 # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses 138 # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses 138 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu.dcache.ReadReq_mshr_miss_latency 4611000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency 2703000 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency 7314000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency 7314000 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate 0.074742 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate 0.055135 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate 0.066060 # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate 0.066060 # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 53000 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53000 # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 53000 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
+system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.l2cache.replacements 0 # number of replacements
+system.cpu.l2cache.tagsinuse 188.045319 # Cycle average of tags in use
+system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks.
+system.cpu.l2cache.sampled_refs 388 # Sample count of references to valid blocks.
+system.cpu.l2cache.avg_refs 0.005155 # Average number of references to valid blocks.
+system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.occ_blocks::0 188.045319 # Average occupied blocks per context
+system.cpu.l2cache.occ_percent::0 0.005739 # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits 2 # number of ReadReq hits
+system.cpu.l2cache.demand_hits 2 # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits 2 # number of overall hits
+system.cpu.l2cache.ReadReq_misses 388 # number of ReadReq misses
+system.cpu.l2cache.ReadExReq_misses 51 # number of ReadExReq misses
+system.cpu.l2cache.demand_misses 439 # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses 439 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency 20176000 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency 2652000 # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency 22828000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency 22828000 # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses 390 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses 51 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses 441 # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses 441 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate 0.994872 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_misses 388 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency 15520000 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate 0.994872 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_misses 388 # number of ReadReq MSHR misses
-system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.cpu.l2cache.avg_refs 0.005155 # Average number of references to valid blocks.
-system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate 0.995465 # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate 0.995465 # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
+system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
-system.cpu.l2cache.demand_accesses 441 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency
-system.cpu.l2cache.demand_hits 2 # number of demand (read+write) hits
-system.cpu.l2cache.demand_miss_latency 22828000 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_rate 0.995465 # miss rate for demand accesses
-system.cpu.l2cache.demand_misses 439 # number of demand (read+write) misses
+system.cpu.l2cache.writebacks 0 # number of writebacks
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
+system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
+system.cpu.l2cache.ReadReq_mshr_misses 388 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses 51 # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses 439 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses 439 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency 15520000 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency 2040000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency 17560000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency 17560000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate 0.994872 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate 0.995465 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_misses 439 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.fast_writes 0 # number of fast writes performed
-system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.l2cache.occ_blocks::0 188.045319 # Average occupied blocks per context
-system.cpu.l2cache.occ_percent::0 0.005739 # Average percentage of cache occupancy
-system.cpu.l2cache.overall_accesses 441 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency
+system.cpu.l2cache.overall_mshr_miss_rate 0.995465 # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_hits 2 # number of overall hits
-system.cpu.l2cache.overall_miss_latency 22828000 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_rate 0.995465 # miss rate for overall accesses
-system.cpu.l2cache.overall_misses 439 # number of overall misses
-system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_miss_latency 17560000 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_rate 0.995465 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_misses 439 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.l2cache.replacements 0 # number of replacements
-system.cpu.l2cache.sampled_refs 388 # Sample count of references to valid blocks.
+system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse 188.045319 # Cycle average of tags in use
-system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks.
-system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.writebacks 0 # number of writebacks
-system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
-system.cpu.numCycles 64176 # number of cpu cycles simulated
-system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
-system.cpu.num_busy_cycles 64176 # Number of busy cycles
-system.cpu.num_conditional_control_insts 677 # number of instructions that are conditional controls
-system.cpu.num_fp_alu_accesses 2 # Number of float alu accesses
-system.cpu.num_fp_insts 2 # number of float instructions
-system.cpu.num_fp_register_reads 3 # number of times the floating registers were read
-system.cpu.num_fp_register_writes 1 # number of times the floating registers were written
-system.cpu.num_func_calls 194 # number of times a function call or return occured
-system.cpu.num_idle_cycles 0 # Number of idle cycles
-system.cpu.num_insts 5827 # Number of instructions executed
-system.cpu.num_int_alu_accesses 5126 # Number of integer alu accesses
-system.cpu.num_int_insts 5126 # number of integer instructions
-system.cpu.num_int_register_reads 7301 # number of times the integer registers were read
-system.cpu.num_int_register_writes 3409 # number of times the integer registers were written
-system.cpu.num_load_insts 1164 # Number of load instructions
-system.cpu.num_mem_refs 2090 # number of memory refs
-system.cpu.num_store_insts 926 # Number of store instructions
-system.cpu.workload.num_syscalls 8 # Number of system calls
+system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------