diff options
Diffstat (limited to 'tests/quick/00.hello')
37 files changed, 647 insertions, 3535 deletions
diff --git a/tests/quick/00.hello/ref/alpha/linux/o3-timing/config.ini b/tests/quick/00.hello/ref/alpha/linux/o3-timing/config.ini index c3a59fbce..86e688c3d 100644 --- a/tests/quick/00.hello/ref/alpha/linux/o3-timing/config.ini +++ b/tests/quick/00.hello/ref/alpha/linux/o3-timing/config.ini @@ -110,6 +110,7 @@ numROBEntries=192 numRobs=1 numThreads=1 predType=tournament +progress_interval=0 renameToDecodeDelay=1 renameToFetchDelay=1 renameToIEWDelay=2 @@ -384,20 +385,30 @@ mem_side=system.membus.port[1] [system.cpu.toL2Bus] type=Bus bus_id=0 +clock=1000 +width=64 port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side [system.cpu.workload] type=LiveProcess cmd=hello +egid=100 env= +euid=100 executable=tests/test-progs/hello/bin/alpha/linux/hello +gid=100 input=cin output=cout +pid=100 +ppid=99 system=system +uid=100 [system.membus] type=Bus bus_id=0 +clock=1000 +width=64 port=system.physmem.port system.cpu.l2cache.mem_side [system.physmem] @@ -409,6 +420,7 @@ port=system.membus.port[0] [trace] bufsize=0 +cycle=0 dump_on_exit=false file=cout flags= diff --git a/tests/quick/00.hello/ref/alpha/linux/o3-timing/config.out b/tests/quick/00.hello/ref/alpha/linux/o3-timing/config.out index f491a3081..1b8e6d980 100644 --- a/tests/quick/00.hello/ref/alpha/linux/o3-timing/config.out +++ b/tests/quick/00.hello/ref/alpha/linux/o3-timing/config.out @@ -19,6 +19,8 @@ mem_mode=atomic [system.membus] type=Bus bus_id=0 +clock=1000 +width=64 [system.cpu.workload] type=LiveProcess @@ -28,6 +30,12 @@ input=cin output=cout env= system=system +uid=100 +euid=100 +gid=100 +egid=100 +pid=100 +ppid=99 [system.cpu.dcache] type=BaseCache @@ -208,6 +216,7 @@ max_insts_any_thread=0 max_insts_all_threads=0 max_loads_any_thread=0 max_loads_all_threads=0 +progress_interval=0 cachePorts=200 decodeToFetchDelay=1 renameToFetchDelay=1 @@ -354,10 +363,13 @@ hit_latency=1 [system.cpu.toL2Bus] type=Bus bus_id=0 +clock=1000 +width=64 [trace] flags= start=0 +cycle=0 bufsize=0 file=cout dump_on_exit=false @@ -401,3 +413,6 @@ trace_system=client [debug] break_cycles= +[statsreset] +reset_cycle=0 + diff --git a/tests/quick/00.hello/ref/alpha/linux/o3-timing/m5stats.txt b/tests/quick/00.hello/ref/alpha/linux/o3-timing/m5stats.txt index 5d4f9235a..59cda42d9 100644 --- a/tests/quick/00.hello/ref/alpha/linux/o3-timing/m5stats.txt +++ b/tests/quick/00.hello/ref/alpha/linux/o3-timing/m5stats.txt @@ -2,39 +2,39 @@ ---------- Begin Simulation Statistics ---------- global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. global.BPredUnit.BTBHits 542 # Number of BTB hits -global.BPredUnit.BTBLookups 1938 # Number of BTB lookups +global.BPredUnit.BTBLookups 1936 # Number of BTB lookups global.BPredUnit.RASInCorrect 48 # Number of incorrect RAS predictions. global.BPredUnit.condIncorrect 420 # Number of conditional branches incorrect -global.BPredUnit.condPredicted 1304 # Number of conditional branches predicted -global.BPredUnit.lookups 2256 # Number of BP lookups +global.BPredUnit.condPredicted 1302 # Number of conditional branches predicted +global.BPredUnit.lookups 2254 # Number of BP lookups global.BPredUnit.usedRAS 291 # Number of times the RAS was used to get a target. -host_inst_rate 41797 # Simulator instruction rate (inst/s) -host_mem_usage 160344 # Number of bytes of host memory used -host_seconds 0.13 # Real time elapsed on the host -host_tick_rate 50948 # Simulator tick rate (ticks/s) +host_inst_rate 46995 # Simulator instruction rate (inst/s) +host_mem_usage 160420 # Number of bytes of host memory used +host_seconds 0.12 # Real time elapsed on the host +host_tick_rate 57256 # Simulator tick rate (ticks/s) memdepunit.memDep.conflictingLoads 12 # Number of conflicting loads. memdepunit.memDep.conflictingStores 259 # Number of conflicting stores. -memdepunit.memDep.insertedLoads 2050 # Number of loads inserted to the mem dependence unit. +memdepunit.memDep.insertedLoads 2049 # Number of loads inserted to the mem dependence unit. memdepunit.memDep.insertedStores 1221 # Number of stores inserted to the mem dependence unit. sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 5623 # Number of instructions simulated sim_seconds 0.000000 # Number of seconds simulated -sim_ticks 6870 # Number of ticks simulated +sim_ticks 6868 # Number of ticks simulated system.cpu.commit.COM:branches 862 # Number of branches committed system.cpu.commit.COM:bw_lim_events 74 # number cycles where commit BW limit reached system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle.samples 6116 +system.cpu.commit.COM:committed_per_cycle.samples 6115 system.cpu.commit.COM:committed_per_cycle.min_value 0 - 0 3908 6389.80% - 1 1064 1739.70% - 2 389 636.04% - 3 210 343.36% - 4 153 250.16% - 5 93 152.06% - 6 76 124.26% - 7 149 243.62% - 8 74 120.99% + 0 3908 6390.84% + 1 1063 1738.35% + 2 389 636.14% + 3 210 343.42% + 4 152 248.57% + 5 94 153.72% + 6 76 124.28% + 7 149 243.66% + 8 74 121.01% system.cpu.commit.COM:committed_per_cycle.max_value 8 system.cpu.commit.COM:committed_per_cycle.end_dist @@ -46,67 +46,67 @@ system.cpu.commit.COM:swp_count 0 # Nu system.cpu.commit.branchMispredicts 337 # The number of times a branch was mispredicted system.cpu.commit.commitCommittedInsts 5640 # The number of committed instructions system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 4350 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 4342 # The number of squashed insts skipped by commit system.cpu.committedInsts 5623 # Number of Instructions Simulated system.cpu.committedInsts_total 5623 # Number of Instructions Simulated -system.cpu.cpi 1.221768 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.221768 # CPI: Total CPI of All Threads -system.cpu.dcache.ReadReq_accesses 1538 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 3.072000 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2.240000 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 1413 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 384 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.081274 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 125 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits 25 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency 224 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.065020 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 100 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_accesses 821 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 2.467742 # average WriteReq miss latency +system.cpu.cpi 1.221412 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.221412 # CPI: Total CPI of All Threads +system.cpu.dcache.ReadReq_accesses 1536 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 3.038760 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2.235294 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 1407 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 392 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.083984 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 129 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_hits 27 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_miss_latency 228 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.066406 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_misses 102 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_accesses 812 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_avg_miss_latency 2.564246 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency 2.140845 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 635 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits 633 # number of WriteReq hits system.cpu.dcache.WriteReq_miss_latency 459 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.226553 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 186 # number of WriteReq misses +system.cpu.dcache.WriteReq_miss_rate 0.220443 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 179 # number of WriteReq misses system.cpu.dcache.WriteReq_mshr_hits 108 # number of WriteReq MSHR hits system.cpu.dcache.WriteReq_mshr_miss_latency 152 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.086480 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate 0.087438 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_misses 71 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles_no_targets 0.800000 # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 11.505618 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 11.791908 # Average number of references to valid blocks. system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_no_targets 5 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_targets 4 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 2359 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 2.710611 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 2.198830 # average overall mshr miss latency -system.cpu.dcache.demand_hits 2048 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 843 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.131836 # miss rate for demand accesses -system.cpu.dcache.demand_misses 311 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 133 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 376 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.072488 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 171 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_accesses 2348 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 2.762987 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 2.196532 # average overall mshr miss latency +system.cpu.dcache.demand_hits 2040 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 851 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.131175 # miss rate for demand accesses +system.cpu.dcache.demand_misses 308 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 135 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 380 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.073680 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 173 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.overall_accesses 2359 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 2.710611 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 2.198830 # average overall mshr miss latency +system.cpu.dcache.overall_accesses 2348 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 2.762987 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 2.196532 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 2048 # number of overall hits -system.cpu.dcache.overall_miss_latency 843 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.131836 # miss rate for overall accesses -system.cpu.dcache.overall_misses 311 # number of overall misses -system.cpu.dcache.overall_mshr_hits 133 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 376 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.072488 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 171 # number of overall MSHR misses +system.cpu.dcache.overall_hits 2040 # number of overall hits +system.cpu.dcache.overall_miss_latency 851 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.131175 # miss rate for overall accesses +system.cpu.dcache.overall_misses 308 # number of overall misses +system.cpu.dcache.overall_mshr_hits 135 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 380 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.073680 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 173 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -119,43 +119,43 @@ system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.sampled_refs 178 # Sample count of references to valid blocks. +system.cpu.dcache.sampled_refs 173 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 119.831029 # Cycle average of tags in use -system.cpu.dcache.total_refs 2048 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 114.960547 # Cycle average of tags in use +system.cpu.dcache.total_refs 2040 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 0 # number of writebacks system.cpu.decode.DECODE:BlockedCycles 387 # Number of cycles decode is blocked system.cpu.decode.DECODE:BranchMispred 93 # Number of times decode detected a branch misprediction system.cpu.decode.DECODE:BranchResolved 185 # Number of times decode resolved a branch system.cpu.decode.DECODE:DecodedInsts 12349 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 3542 # Number of cycles decode is idle +system.cpu.decode.DECODE:IdleCycles 3541 # Number of cycles decode is idle system.cpu.decode.DECODE:RunCycles 2158 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 754 # Number of cycles decode is squashing +system.cpu.decode.DECODE:SquashCycles 753 # Number of cycles decode is squashing system.cpu.decode.DECODE:SquashedInsts 286 # Number of squashed instructions handled by decode system.cpu.decode.DECODE:UnblockCycles 30 # Number of cycles decode is unblocking -system.cpu.fetch.Branches 2256 # Number of branches that fetch encountered +system.cpu.fetch.Branches 2254 # Number of branches that fetch encountered system.cpu.fetch.CacheLines 1582 # Number of cache lines fetched -system.cpu.fetch.Cycles 3905 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.Cycles 3904 # Number of cycles fetch has run and was not squashing or blocked system.cpu.fetch.IcacheSquashes 148 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.Insts 13707 # Number of instructions fetch has processed +system.cpu.fetch.Insts 13699 # Number of instructions fetch has processed system.cpu.fetch.SquashCycles 456 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.328336 # Number of branch fetches per cycle +system.cpu.fetch.branchRate 0.328141 # Number of branch fetches per cycle system.cpu.fetch.icacheStallCycles 1582 # Number of cycles fetch is stalled on an Icache miss system.cpu.fetch.predictedBranches 833 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 1.994906 # Number of inst fetches per cycle +system.cpu.fetch.rate 1.994322 # Number of inst fetches per cycle system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist.samples 6871 +system.cpu.fetch.rateDist.samples 6869 system.cpu.fetch.rateDist.min_value 0 - 0 4549 6620.58% - 1 174 253.24% - 2 186 270.70% - 3 157 228.50% - 4 211 307.09% - 5 153 222.68% - 6 171 248.87% - 7 105 152.82% - 8 1165 1695.53% + 0 4548 6621.05% + 1 174 253.31% + 2 186 270.78% + 3 157 228.56% + 4 211 307.18% + 5 153 222.74% + 6 171 248.94% + 7 105 152.86% + 8 1164 1694.57% system.cpu.fetch.rateDist.max_value 8 system.cpu.fetch.rateDist.end_dist @@ -170,8 +170,8 @@ system.cpu.icache.ReadReq_mshr_hits 6 # nu system.cpu.icache.ReadReq_mshr_miss_latency 641 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.202908 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_misses 321 # number of ReadReq MSHR misses -system.cpu.icache.avg_blocked_cycles_no_mshrs no value # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles_no_targets no value # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked system.cpu.icache.avg_refs 3.909657 # Average number of references to valid blocks. system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked @@ -218,38 +218,38 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.icache.replacements 0 # number of replacements system.cpu.icache.sampled_refs 321 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 176.393247 # Cycle average of tags in use +system.cpu.icache.tagsinuse 176.439074 # Cycle average of tags in use system.cpu.icache.total_refs 1255 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks system.cpu.iew.EXEC:branches 1206 # Number of branches executed -system.cpu.iew.EXEC:insts 7969 # Number of executed instructions -system.cpu.iew.EXEC:loads 1610 # Number of load instructions executed system.cpu.iew.EXEC:nop 37 # number of nop insts executed -system.cpu.iew.EXEC:rate 1.159802 # Inst execution rate -system.cpu.iew.EXEC:refs 2599 # number of memory reference insts executed -system.cpu.iew.EXEC:squashedInsts 419 # Number of squashed instructions skipped in execute -system.cpu.iew.EXEC:stores 989 # Number of stores executed +system.cpu.iew.EXEC:rate 1.157374 # Inst execution rate +system.cpu.iew.EXEC:refs 2595 # number of memory reference insts executed +system.cpu.iew.EXEC:stores 985 # Number of stores executed system.cpu.iew.EXEC:swp 0 # number of swp insts executed -system.cpu.iew.WB:consumers 5438 # num instructions consuming a value -system.cpu.iew.WB:count 7722 # cumulative count of insts written-back -system.cpu.iew.WB:fanout 0.744575 # average fanout of values written-back +system.cpu.iew.WB:consumers 5409 # num instructions consuming a value +system.cpu.iew.WB:count 7670 # cumulative count of insts written-back +system.cpu.iew.WB:fanout 0.744130 # average fanout of values written-back system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 4049 # num instructions producing a value -system.cpu.iew.WB:rate 1.123854 # insts written-back per cycle -system.cpu.iew.WB:sent 7762 # cumulative count of insts sent to commit +system.cpu.iew.WB:producers 4025 # num instructions producing a value +system.cpu.iew.WB:rate 1.116611 # insts written-back per cycle +system.cpu.iew.WB:sent 7743 # cumulative count of insts sent to commit system.cpu.iew.branchMispredicts 393 # Number of branch mispredicts detected at execute system.cpu.iew.iewBlockCycles 4 # Number of cycles IEW is blocking -system.cpu.iew.iewDispLoadInsts 2050 # Number of dispatched load instructions +system.cpu.iew.iewDispLoadInsts 2049 # Number of dispatched load instructions system.cpu.iew.iewDispNonSpecInsts 21 # Number of dispatched non-speculative instructions system.cpu.iew.iewDispSquashedInsts 272 # Number of squashed instructions skipped by dispatch system.cpu.iew.iewDispStoreInsts 1221 # Number of dispatched store instructions -system.cpu.iew.iewDispatchedInsts 9990 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispatchedInsts 9982 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 1610 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 409 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 7950 # Number of executed instructions system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.iewSquashCycles 754 # Number of cycles IEW is squashing +system.cpu.iew.iewSquashCycles 753 # Number of cycles IEW is squashing system.cpu.iew.iewUnblockCycles 0 # Number of cycles IEW is unblocking system.cpu.iew.lsq.thread.0.blockedLoads 1 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread.0.cacheBlocked 5 # Number of times an access to memory failed due to the cache being blocked @@ -257,1586 +257,19 @@ system.cpu.iew.lsq.thread.0.forwLoads 55 # Nu system.cpu.iew.lsq.thread.0.ignoredResponses 5 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address +system.cpu.iew.lsq.thread.0.memOrderViolation 41 # Number of memory ordering violations system.cpu.iew.lsq.thread.0.rescheduledLoads 1 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 1071 # Number of loads squashed +system.cpu.iew.lsq.thread.0.squashedLoads 1070 # Number of loads squashed system.cpu.iew.lsq.thread.0.squashedStores 409 # Number of stores squashed system.cpu.iew.memOrderViolationEvents 41 # Number of memory order violations system.cpu.iew.predictedNotTakenIncorrect 296 # Number of branches that were predicted not taken incorrectly system.cpu.iew.predictedTakenIncorrect 97 # Number of branches that were predicted taken incorrectly -system.cpu.ipc 0.818486 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.818486 # IPC: Total IPC of All Threads -system.cpu.iq.IQ:residence:(null).start_dist # cycles from dispatch to issue -system.cpu.iq.IQ:residence:(null).samples 0 -system.cpu.iq.IQ:residence:(null).min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.IQ:residence:(null).max_value 0 -system.cpu.iq.IQ:residence:(null).end_dist - -system.cpu.iq.IQ:residence:IntAlu.start_dist # cycles from dispatch to issue -system.cpu.iq.IQ:residence:IntAlu.samples 0 -system.cpu.iq.IQ:residence:IntAlu.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.IQ:residence:IntAlu.max_value 0 -system.cpu.iq.IQ:residence:IntAlu.end_dist - -system.cpu.iq.IQ:residence:IntMult.start_dist # cycles from dispatch to issue -system.cpu.iq.IQ:residence:IntMult.samples 0 -system.cpu.iq.IQ:residence:IntMult.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.IQ:residence:IntMult.max_value 0 -system.cpu.iq.IQ:residence:IntMult.end_dist - -system.cpu.iq.IQ:residence:IntDiv.start_dist # cycles from dispatch to issue -system.cpu.iq.IQ:residence:IntDiv.samples 0 -system.cpu.iq.IQ:residence:IntDiv.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.IQ:residence:IntDiv.max_value 0 -system.cpu.iq.IQ:residence:IntDiv.end_dist - -system.cpu.iq.IQ:residence:FloatAdd.start_dist # cycles from dispatch to issue -system.cpu.iq.IQ:residence:FloatAdd.samples 0 -system.cpu.iq.IQ:residence:FloatAdd.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.IQ:residence:FloatAdd.max_value 0 -system.cpu.iq.IQ:residence:FloatAdd.end_dist - -system.cpu.iq.IQ:residence:FloatCmp.start_dist # cycles from dispatch to issue -system.cpu.iq.IQ:residence:FloatCmp.samples 0 -system.cpu.iq.IQ:residence:FloatCmp.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.IQ:residence:FloatCmp.max_value 0 -system.cpu.iq.IQ:residence:FloatCmp.end_dist - -system.cpu.iq.IQ:residence:FloatCvt.start_dist # cycles from dispatch to issue -system.cpu.iq.IQ:residence:FloatCvt.samples 0 -system.cpu.iq.IQ:residence:FloatCvt.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.IQ:residence:FloatCvt.max_value 0 -system.cpu.iq.IQ:residence:FloatCvt.end_dist - -system.cpu.iq.IQ:residence:FloatMult.start_dist # cycles from dispatch to issue -system.cpu.iq.IQ:residence:FloatMult.samples 0 -system.cpu.iq.IQ:residence:FloatMult.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.IQ:residence:FloatMult.max_value 0 -system.cpu.iq.IQ:residence:FloatMult.end_dist - -system.cpu.iq.IQ:residence:FloatDiv.start_dist # cycles from dispatch to issue -system.cpu.iq.IQ:residence:FloatDiv.samples 0 -system.cpu.iq.IQ:residence:FloatDiv.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.IQ:residence:FloatDiv.max_value 0 -system.cpu.iq.IQ:residence:FloatDiv.end_dist - -system.cpu.iq.IQ:residence:FloatSqrt.start_dist # cycles from dispatch to issue -system.cpu.iq.IQ:residence:FloatSqrt.samples 0 -system.cpu.iq.IQ:residence:FloatSqrt.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.IQ:residence:FloatSqrt.max_value 0 -system.cpu.iq.IQ:residence:FloatSqrt.end_dist - -system.cpu.iq.IQ:residence:MemRead.start_dist # cycles from dispatch to issue -system.cpu.iq.IQ:residence:MemRead.samples 0 -system.cpu.iq.IQ:residence:MemRead.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.IQ:residence:MemRead.max_value 0 -system.cpu.iq.IQ:residence:MemRead.end_dist - -system.cpu.iq.IQ:residence:MemWrite.start_dist # cycles from dispatch to issue -system.cpu.iq.IQ:residence:MemWrite.samples 0 -system.cpu.iq.IQ:residence:MemWrite.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.IQ:residence:MemWrite.max_value 0 -system.cpu.iq.IQ:residence:MemWrite.end_dist - -system.cpu.iq.IQ:residence:IprAccess.start_dist # cycles from dispatch to issue -system.cpu.iq.IQ:residence:IprAccess.samples 0 -system.cpu.iq.IQ:residence:IprAccess.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.IQ:residence:IprAccess.max_value 0 -system.cpu.iq.IQ:residence:IprAccess.end_dist - -system.cpu.iq.IQ:residence:InstPrefetch.start_dist # cycles from dispatch to issue -system.cpu.iq.IQ:residence:InstPrefetch.samples 0 -system.cpu.iq.IQ:residence:InstPrefetch.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.IQ:residence:InstPrefetch.max_value 0 -system.cpu.iq.IQ:residence:InstPrefetch.end_dist - -system.cpu.iq.ISSUE:(null)_delay.start_dist # cycles from operands ready to issue -system.cpu.iq.ISSUE:(null)_delay.samples 0 -system.cpu.iq.ISSUE:(null)_delay.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.ISSUE:(null)_delay.max_value 0 -system.cpu.iq.ISSUE:(null)_delay.end_dist - -system.cpu.iq.ISSUE:IntAlu_delay.start_dist # cycles from operands ready to issue -system.cpu.iq.ISSUE:IntAlu_delay.samples 0 -system.cpu.iq.ISSUE:IntAlu_delay.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.ISSUE:IntAlu_delay.max_value 0 -system.cpu.iq.ISSUE:IntAlu_delay.end_dist - -system.cpu.iq.ISSUE:IntMult_delay.start_dist # cycles from operands ready to issue -system.cpu.iq.ISSUE:IntMult_delay.samples 0 -system.cpu.iq.ISSUE:IntMult_delay.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.ISSUE:IntMult_delay.max_value 0 -system.cpu.iq.ISSUE:IntMult_delay.end_dist - -system.cpu.iq.ISSUE:IntDiv_delay.start_dist # cycles from operands ready to issue -system.cpu.iq.ISSUE:IntDiv_delay.samples 0 -system.cpu.iq.ISSUE:IntDiv_delay.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.ISSUE:IntDiv_delay.max_value 0 -system.cpu.iq.ISSUE:IntDiv_delay.end_dist - -system.cpu.iq.ISSUE:FloatAdd_delay.start_dist # cycles from operands ready to issue -system.cpu.iq.ISSUE:FloatAdd_delay.samples 0 -system.cpu.iq.ISSUE:FloatAdd_delay.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.ISSUE:FloatAdd_delay.max_value 0 -system.cpu.iq.ISSUE:FloatAdd_delay.end_dist - -system.cpu.iq.ISSUE:FloatCmp_delay.start_dist # cycles from operands ready to issue -system.cpu.iq.ISSUE:FloatCmp_delay.samples 0 -system.cpu.iq.ISSUE:FloatCmp_delay.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.ISSUE:FloatCmp_delay.max_value 0 -system.cpu.iq.ISSUE:FloatCmp_delay.end_dist - -system.cpu.iq.ISSUE:FloatCvt_delay.start_dist # cycles from operands ready to issue -system.cpu.iq.ISSUE:FloatCvt_delay.samples 0 -system.cpu.iq.ISSUE:FloatCvt_delay.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.ISSUE:FloatCvt_delay.max_value 0 -system.cpu.iq.ISSUE:FloatCvt_delay.end_dist - -system.cpu.iq.ISSUE:FloatMult_delay.start_dist # cycles from operands ready to issue -system.cpu.iq.ISSUE:FloatMult_delay.samples 0 -system.cpu.iq.ISSUE:FloatMult_delay.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.ISSUE:FloatMult_delay.max_value 0 -system.cpu.iq.ISSUE:FloatMult_delay.end_dist - -system.cpu.iq.ISSUE:FloatDiv_delay.start_dist # cycles from operands ready to issue -system.cpu.iq.ISSUE:FloatDiv_delay.samples 0 -system.cpu.iq.ISSUE:FloatDiv_delay.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.ISSUE:FloatDiv_delay.max_value 0 -system.cpu.iq.ISSUE:FloatDiv_delay.end_dist - -system.cpu.iq.ISSUE:FloatSqrt_delay.start_dist # cycles from operands ready to issue -system.cpu.iq.ISSUE:FloatSqrt_delay.samples 0 -system.cpu.iq.ISSUE:FloatSqrt_delay.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.ISSUE:FloatSqrt_delay.max_value 0 -system.cpu.iq.ISSUE:FloatSqrt_delay.end_dist - -system.cpu.iq.ISSUE:MemRead_delay.start_dist # cycles from operands ready to issue -system.cpu.iq.ISSUE:MemRead_delay.samples 0 -system.cpu.iq.ISSUE:MemRead_delay.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.ISSUE:MemRead_delay.max_value 0 -system.cpu.iq.ISSUE:MemRead_delay.end_dist - -system.cpu.iq.ISSUE:MemWrite_delay.start_dist # cycles from operands ready to issue -system.cpu.iq.ISSUE:MemWrite_delay.samples 0 -system.cpu.iq.ISSUE:MemWrite_delay.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.ISSUE:MemWrite_delay.max_value 0 -system.cpu.iq.ISSUE:MemWrite_delay.end_dist - -system.cpu.iq.ISSUE:IprAccess_delay.start_dist # cycles from operands ready to issue -system.cpu.iq.ISSUE:IprAccess_delay.samples 0 -system.cpu.iq.ISSUE:IprAccess_delay.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.ISSUE:IprAccess_delay.max_value 0 -system.cpu.iq.ISSUE:IprAccess_delay.end_dist - -system.cpu.iq.ISSUE:InstPrefetch_delay.start_dist # cycles from operands ready to issue -system.cpu.iq.ISSUE:InstPrefetch_delay.samples 0 -system.cpu.iq.ISSUE:InstPrefetch_delay.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.ISSUE:InstPrefetch_delay.max_value 0 -system.cpu.iq.ISSUE:InstPrefetch_delay.end_dist - -system.cpu.iq.ISSUE:FU_type_0 8388 # Type of FU issued +system.cpu.ipc 0.818725 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.818725 # IPC: Total IPC of All Threads +system.cpu.iq.ISSUE:FU_type_0 8359 # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.start_dist (null) 2 0.02% # Type of FU issued - IntAlu 5594 66.69% # Type of FU issued + IntAlu 5573 66.67% # Type of FU issued IntMult 1 0.01% # Type of FU issued IntDiv 0 0.00% # Type of FU issued FloatAdd 2 0.02% # Type of FU issued @@ -1845,13 +278,13 @@ system.cpu.iq.ISSUE:FU_type_0.start_dist FloatMult 0 0.00% # Type of FU issued FloatDiv 0 0.00% # Type of FU issued FloatSqrt 0 0.00% # Type of FU issued - MemRead 1757 20.95% # Type of FU issued - MemWrite 1032 12.30% # Type of FU issued + MemRead 1757 21.02% # Type of FU issued + MemWrite 1024 12.25% # Type of FU issued IprAccess 0 0.00% # Type of FU issued InstPrefetch 0 0.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.end_dist system.cpu.iq.ISSUE:fu_busy_cnt 115 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_rate 0.013710 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:fu_busy_rate 0.013758 # FU busy rate (busy events/executed inst) system.cpu.iq.ISSUE:fu_full.start_dist (null) 0 0.00% # attempts to use FU when none available IntAlu 1 0.87% # attempts to use FU when none available @@ -1869,72 +302,72 @@ system.cpu.iq.ISSUE:fu_full.start_dist InstPrefetch 0 0.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full.end_dist system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle.samples 6871 +system.cpu.iq.ISSUE:issued_per_cycle.samples 6869 system.cpu.iq.ISSUE:issued_per_cycle.min_value 0 - 0 3753 5462.09% - 1 894 1301.12% - 2 723 1052.25% - 3 614 893.61% - 4 451 656.38% - 5 279 406.05% - 6 104 151.36% - 7 41 59.67% - 8 12 17.46% + 0 3761 5475.32% + 1 891 1297.13% + 2 720 1048.19% + 3 617 898.24% + 4 445 647.84% + 5 278 404.72% + 6 104 151.40% + 7 41 59.69% + 8 12 17.47% system.cpu.iq.ISSUE:issued_per_cycle.max_value 8 system.cpu.iq.ISSUE:issued_per_cycle.end_dist -system.cpu.iq.ISSUE:rate 1.220783 # Inst issue rate -system.cpu.iq.iqInstsAdded 9932 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 8388 # Number of instructions issued +system.cpu.iq.ISSUE:rate 1.216917 # Inst issue rate +system.cpu.iq.iqInstsAdded 9924 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 8359 # Number of instructions issued system.cpu.iq.iqNonSpecInstsAdded 21 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 3990 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsExamined 3985 # Number of squashed instructions iterated over during squash; mainly for profiling system.cpu.iq.iqSquashedInstsIssued 21 # Number of squashed instructions issued system.cpu.iq.iqSquashedNonSpecRemoved 4 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 2486 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.l2cache.ReadReq_accesses 499 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 2.042254 # average ReadReq miss latency +system.cpu.iq.iqSquashedOperandsExamined 2568 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.l2cache.ReadReq_accesses 494 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 2.071138 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_hits 2 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 1015 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.995992 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 497 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 490 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.981964 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 490 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_miss_latency 1019 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.995951 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 492 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 492 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.995951 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 492 # number of ReadReq MSHR misses system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 0.004024 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 0.004065 # Average number of references to valid blocks. system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 499 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 2.042254 # average overall miss latency +system.cpu.l2cache.demand_accesses 494 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 2.071138 # average overall miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency 1 # average overall mshr miss latency system.cpu.l2cache.demand_hits 2 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 1015 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.995992 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 497 # number of demand (read+write) misses +system.cpu.l2cache.demand_miss_latency 1019 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.995951 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 492 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 490 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.981964 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 490 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_miss_latency 492 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.995951 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 492 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.overall_accesses 499 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 2.042254 # average overall miss latency +system.cpu.l2cache.overall_accesses 494 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 2.071138 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 1 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.l2cache.overall_hits 2 # number of overall hits -system.cpu.l2cache.overall_miss_latency 1015 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.995992 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 497 # number of overall misses +system.cpu.l2cache.overall_miss_latency 1019 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.995951 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 492 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 490 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.981964 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 490 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_miss_latency 492 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.995951 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 492 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -1947,22 +380,22 @@ system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.sampled_refs 497 # Sample count of references to valid blocks. +system.cpu.l2cache.sampled_refs 492 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 295.773395 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 290.948901 # Cycle average of tags in use system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks -system.cpu.numCycles 6871 # number of cpu cycles simulated +system.cpu.numCycles 6869 # number of cpu cycles simulated system.cpu.rename.RENAME:BlockCycles 4 # Number of cycles rename is blocking system.cpu.rename.RENAME:CommittedMaps 4051 # Number of HB maps that are committed -system.cpu.rename.RENAME:IdleCycles 3758 # Number of cycles rename is idle +system.cpu.rename.RENAME:IdleCycles 3757 # Number of cycles rename is idle system.cpu.rename.RENAME:LSQFullEvents 62 # Number of times rename has blocked due to LSQ full system.cpu.rename.RENAME:RenameLookups 14786 # Number of register rename lookups that rename has made system.cpu.rename.RENAME:RenamedInsts 11555 # Number of instructions processed by rename system.cpu.rename.RENAME:RenamedOperands 8634 # Number of destination operands rename has renamed system.cpu.rename.RENAME:RunCycles 1975 # Number of cycles rename is running -system.cpu.rename.RENAME:SquashCycles 754 # Number of cycles rename is squashing +system.cpu.rename.RENAME:SquashCycles 753 # Number of cycles rename is squashing system.cpu.rename.RENAME:UnblockCycles 111 # Number of cycles rename is unblocking system.cpu.rename.RENAME:UndoneMaps 4583 # Number of HB maps that are undone due to squashing system.cpu.rename.RENAME:serializeStallCycles 269 # count of cycles rename stalled for serializing inst diff --git a/tests/quick/00.hello/ref/alpha/linux/o3-timing/stderr b/tests/quick/00.hello/ref/alpha/linux/o3-timing/stderr index 8893caac8..558105896 100644 --- a/tests/quick/00.hello/ref/alpha/linux/o3-timing/stderr +++ b/tests/quick/00.hello/ref/alpha/linux/o3-timing/stderr @@ -1,3 +1,12 @@ warn: Entering event queue @ 0. Starting simulation... warn: cycle 0: fault (page_table_fault) detected @ PC 0x000000 warn: Increasing stack 0x11ff92000:0x11ff9b000 to 0x11ff90000:0x11ff9b000 because of access to 0x11ff91ff0 +warn: Default fetch doesn't update it's state from a functional call. +warn: Default fetch doesn't update it's state from a functional call. +warn: Default fetch doesn't update it's state from a functional call. +warn: Default fetch doesn't update it's state from a functional call. +warn: Default fetch doesn't update it's state from a functional call. +warn: Default fetch doesn't update it's state from a functional call. +warn: Default fetch doesn't update it's state from a functional call. +warn: Default fetch doesn't update it's state from a functional call. +warn: Default fetch doesn't update it's state from a functional call. diff --git a/tests/quick/00.hello/ref/alpha/linux/o3-timing/stdout b/tests/quick/00.hello/ref/alpha/linux/o3-timing/stdout index fbb329a2f..f2a1151c4 100644 --- a/tests/quick/00.hello/ref/alpha/linux/o3-timing/stdout +++ b/tests/quick/00.hello/ref/alpha/linux/o3-timing/stdout @@ -6,8 +6,8 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Sep 5 2006 15:28:48 -M5 started Tue Sep 5 15:42:12 2006 +M5 compiled Oct 8 2006 20:54:51 +M5 started Sun Oct 8 20:55:10 2006 M5 executing on zizzer.eecs.umich.edu command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/o3-timing tests/run.py quick/00.hello/alpha/linux/o3-timing -Exiting @ tick 6870 because target called exit() +Exiting @ tick 6868 because target called exit() diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-atomic/config.ini b/tests/quick/00.hello/ref/alpha/linux/simple-atomic/config.ini index f84372165..b8aba735a 100644 --- a/tests/quick/00.hello/ref/alpha/linux/simple-atomic/config.ini +++ b/tests/quick/00.hello/ref/alpha/linux/simple-atomic/config.ini @@ -56,6 +56,7 @@ physmem=system.physmem type=AtomicSimpleCPU children=workload clock=1 +cpu_id=0 defer_registration=false function_trace=false function_trace_start=0 @@ -64,6 +65,7 @@ max_insts_any_thread=0 max_loads_all_threads=0 max_loads_any_thread=0 mem=system.physmem +progress_interval=0 simulate_stalls=false system=system width=1 @@ -74,15 +76,23 @@ icache_port=system.membus.port[1] [system.cpu.workload] type=LiveProcess cmd=hello +egid=100 env= +euid=100 executable=tests/test-progs/hello/bin/alpha/linux/hello +gid=100 input=cin output=cout +pid=100 +ppid=99 system=system +uid=100 [system.membus] type=Bus bus_id=0 +clock=1000 +width=64 port=system.physmem.port system.cpu.icache_port system.cpu.dcache_port [system.physmem] @@ -94,6 +104,7 @@ port=system.membus.port[0] [trace] bufsize=0 +cycle=0 dump_on_exit=false file=cout flags= diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-atomic/config.out b/tests/quick/00.hello/ref/alpha/linux/simple-atomic/config.out index a3621a08a..71a43d484 100644 --- a/tests/quick/00.hello/ref/alpha/linux/simple-atomic/config.out +++ b/tests/quick/00.hello/ref/alpha/linux/simple-atomic/config.out @@ -19,6 +19,8 @@ mem_mode=atomic [system.membus] type=Bus bus_id=0 +clock=1000 +width=64 [system.cpu.workload] type=LiveProcess @@ -28,6 +30,12 @@ input=cin output=cout env= system=system +uid=100 +euid=100 +gid=100 +egid=100 +pid=100 +ppid=99 [system.cpu] type=AtomicSimpleCPU @@ -35,8 +43,10 @@ max_insts_any_thread=0 max_insts_all_threads=0 max_loads_any_thread=0 max_loads_all_threads=0 +progress_interval=0 mem=system.physmem system=system +cpu_id=0 workload=system.cpu.workload clock=1 defer_registration=false @@ -48,6 +58,7 @@ simulate_stalls=false [trace] flags= start=0 +cycle=0 bufsize=0 file=cout dump_on_exit=false @@ -91,3 +102,6 @@ trace_system=client [debug] break_cycles= +[statsreset] +reset_cycle=0 + diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-atomic/m5stats.txt b/tests/quick/00.hello/ref/alpha/linux/simple-atomic/m5stats.txt index e3cd05fb0..875e55644 100644 --- a/tests/quick/00.hello/ref/alpha/linux/simple-atomic/m5stats.txt +++ b/tests/quick/00.hello/ref/alpha/linux/simple-atomic/m5stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 74000 # Simulator instruction rate (inst/s) -host_mem_usage 148088 # Number of bytes of host memory used -host_seconds 0.08 # Real time elapsed on the host -host_tick_rate 73591 # Simulator tick rate (ticks/s) +host_inst_rate 172802 # Simulator instruction rate (inst/s) +host_mem_usage 148116 # Number of bytes of host memory used +host_seconds 0.03 # Real time elapsed on the host +host_tick_rate 170614 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 5642 # Number of instructions simulated sim_seconds 0.000000 # Number of seconds simulated diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-atomic/stdout b/tests/quick/00.hello/ref/alpha/linux/simple-atomic/stdout index 17eea9aed..59f571aaf 100644 --- a/tests/quick/00.hello/ref/alpha/linux/simple-atomic/stdout +++ b/tests/quick/00.hello/ref/alpha/linux/simple-atomic/stdout @@ -6,8 +6,8 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Sep 5 2006 15:28:48 -M5 started Tue Sep 5 15:42:14 2006 +M5 compiled Oct 8 2006 14:00:39 +M5 started Sun Oct 8 14:00:50 2006 M5 executing on zizzer.eecs.umich.edu command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/simple-atomic tests/run.py quick/00.hello/alpha/linux/simple-atomic Exiting @ tick 5641 because target called exit() diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing/config.ini b/tests/quick/00.hello/ref/alpha/linux/simple-timing/config.ini index 80d2a27e1..f8e1f1bb0 100644 --- a/tests/quick/00.hello/ref/alpha/linux/simple-timing/config.ini +++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing/config.ini @@ -56,6 +56,7 @@ physmem=system.physmem type=TimingSimpleCPU children=dcache icache l2cache toL2Bus workload clock=1 +cpu_id=0 defer_registration=false function_trace=false function_trace_start=0 @@ -64,6 +65,7 @@ max_insts_any_thread=0 max_loads_all_threads=0 max_loads_any_thread=0 mem=system.cpu.dcache +progress_interval=0 system=system workload=system.cpu.workload dcache_port=system.cpu.dcache.cpu_side @@ -192,20 +194,30 @@ mem_side=system.membus.port[1] [system.cpu.toL2Bus] type=Bus bus_id=0 +clock=1000 +width=64 port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side [system.cpu.workload] type=LiveProcess cmd=hello +egid=100 env= +euid=100 executable=tests/test-progs/hello/bin/alpha/linux/hello +gid=100 input=cin output=cout +pid=100 +ppid=99 system=system +uid=100 [system.membus] type=Bus bus_id=0 +clock=1000 +width=64 port=system.physmem.port system.cpu.l2cache.mem_side [system.physmem] @@ -217,6 +229,7 @@ port=system.membus.port[0] [trace] bufsize=0 +cycle=0 dump_on_exit=false file=cout flags= diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing/config.out b/tests/quick/00.hello/ref/alpha/linux/simple-timing/config.out index 09d8f0c22..2ab7c0150 100644 --- a/tests/quick/00.hello/ref/alpha/linux/simple-timing/config.out +++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing/config.out @@ -19,6 +19,8 @@ mem_mode=atomic [system.membus] type=Bus bus_id=0 +clock=1000 +width=64 [system.cpu.dcache] type=BaseCache @@ -67,6 +69,12 @@ input=cin output=cout env= system=system +uid=100 +euid=100 +gid=100 +egid=100 +pid=100 +ppid=99 [system.cpu] type=TimingSimpleCPU @@ -74,8 +82,10 @@ max_insts_any_thread=0 max_insts_all_threads=0 max_loads_any_thread=0 max_loads_all_threads=0 +progress_interval=0 mem=system.cpu.dcache system=system +cpu_id=0 workload=system.cpu.workload clock=1 defer_registration=false @@ -87,6 +97,8 @@ function_trace_start=0 [system.cpu.toL2Bus] type=Bus bus_id=0 +clock=1000 +width=64 [system.cpu.icache] type=BaseCache @@ -169,6 +181,7 @@ hit_latency=1 [trace] flags= start=0 +cycle=0 bufsize=0 file=cout dump_on_exit=false @@ -212,3 +225,6 @@ trace_system=client [debug] break_cycles= +[statsreset] +reset_cycle=0 + diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing/m5stats.txt b/tests/quick/00.hello/ref/alpha/linux/simple-timing/m5stats.txt index fe2cd43a5..6914938e5 100644 --- a/tests/quick/00.hello/ref/alpha/linux/simple-timing/m5stats.txt +++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing/m5stats.txt @@ -1,67 +1,67 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 113478 # Simulator instruction rate (inst/s) -host_mem_usage 159608 # Number of bytes of host memory used -host_seconds 0.05 # Real time elapsed on the host -host_tick_rate 165749 # Simulator tick rate (ticks/s) +host_inst_rate 152920 # Simulator instruction rate (inst/s) +host_mem_usage 166272 # Number of bytes of host memory used +host_seconds 0.04 # Real time elapsed on the host +host_tick_rate 221766 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 5642 # Number of instructions simulated sim_seconds 0.000000 # Number of seconds simulated -sim_ticks 8312 # Number of ticks simulated -system.cpu.dcache.ReadReq_accesses 981 # number of ReadReq accesses(hits+misses) +sim_ticks 8316 # Number of ticks simulated +system.cpu.dcache.ReadReq_accesses 979 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_avg_miss_latency 3 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 891 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 270 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.091743 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 90 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_miss_latency 180 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.091743 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 90 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_accesses 821 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 2.737500 # average WriteReq miss latency +system.cpu.dcache.ReadReq_hits 887 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 276 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.093973 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 92 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_miss_latency 184 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.093973 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_misses 92 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_accesses 812 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_avg_miss_latency 3 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency 2 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 741 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits 739 # number of WriteReq hits system.cpu.dcache.WriteReq_miss_latency 219 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.097442 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 80 # number of WriteReq misses +system.cpu.dcache.WriteReq_miss_rate 0.089901 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 73 # number of WriteReq misses system.cpu.dcache.WriteReq_mshr_miss_latency 146 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.088916 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate 0.089901 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_misses 73 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 9.600000 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 9.854545 # Average number of references to valid blocks. system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 1802 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 2.876471 # average overall miss latency +system.cpu.dcache.demand_accesses 1791 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 3 # average overall miss latency system.cpu.dcache.demand_avg_mshr_miss_latency 2 # average overall mshr miss latency -system.cpu.dcache.demand_hits 1632 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 489 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.094340 # miss rate for demand accesses -system.cpu.dcache.demand_misses 170 # number of demand (read+write) misses +system.cpu.dcache.demand_hits 1626 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 495 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.092127 # miss rate for demand accesses +system.cpu.dcache.demand_misses 165 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 326 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.090455 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 163 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_miss_latency 330 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.092127 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 165 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.overall_accesses 1802 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 2.876471 # average overall miss latency +system.cpu.dcache.overall_accesses 1791 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 3 # average overall miss latency system.cpu.dcache.overall_avg_mshr_miss_latency 2 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 1632 # number of overall hits -system.cpu.dcache.overall_miss_latency 489 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.094340 # miss rate for overall accesses -system.cpu.dcache.overall_misses 170 # number of overall misses +system.cpu.dcache.overall_hits 1626 # number of overall hits +system.cpu.dcache.overall_miss_latency 495 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.092127 # miss rate for overall accesses +system.cpu.dcache.overall_misses 165 # number of overall misses system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 326 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.090455 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 163 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_miss_latency 330 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.092127 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 165 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -74,10 +74,10 @@ system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.sampled_refs 170 # Sample count of references to valid blocks. +system.cpu.dcache.sampled_refs 165 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 112.055094 # Cycle average of tags in use -system.cpu.dcache.total_refs 1632 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 107.125526 # Cycle average of tags in use +system.cpu.dcache.total_refs 1626 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 0 # number of writebacks system.cpu.icache.ReadReq_accesses 5643 # number of ReadReq accesses(hits+misses) @@ -138,55 +138,55 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.icache.replacements 0 # number of replacements system.cpu.icache.sampled_refs 277 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 133.267292 # Cycle average of tags in use +system.cpu.icache.tagsinuse 133.213539 # Cycle average of tags in use system.cpu.icache.total_refs 5366 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.l2cache.ReadReq_accesses 447 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 1.968610 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_accesses 442 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 2 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_hits 1 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 878 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.997763 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 446 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 439 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.982103 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 439 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_miss_latency 882 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.997738 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 441 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 441 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.997738 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 441 # number of ReadReq MSHR misses system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 0.002242 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 0.002268 # Average number of references to valid blocks. system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 447 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 1.968610 # average overall miss latency +system.cpu.l2cache.demand_accesses 442 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 2 # average overall miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency 1 # average overall mshr miss latency system.cpu.l2cache.demand_hits 1 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 878 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.997763 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 446 # number of demand (read+write) misses +system.cpu.l2cache.demand_miss_latency 882 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.997738 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 441 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 439 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.982103 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 439 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_miss_latency 441 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.997738 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 441 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.overall_accesses 447 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 1.968610 # average overall miss latency +system.cpu.l2cache.overall_accesses 442 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 2 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 1 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no value # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.l2cache.overall_hits 1 # number of overall hits -system.cpu.l2cache.overall_miss_latency 878 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.997763 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 446 # number of overall misses +system.cpu.l2cache.overall_miss_latency 882 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.997738 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 441 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 439 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.982103 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 439 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_miss_latency 441 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.997738 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 441 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -199,14 +199,14 @@ system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.sampled_refs 446 # Sample count of references to valid blocks. +system.cpu.l2cache.sampled_refs 441 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 245.259112 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 240.276061 # Cycle average of tags in use system.cpu.l2cache.total_refs 1 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 0 # number of cpu cycles simulated +system.cpu.numCycles 8316 # number of cpu cycles simulated system.cpu.num_insts 5642 # Number of instructions executed system.cpu.num_refs 1792 # Number of memory references system.cpu.workload.PROG:num_syscalls 17 # Number of system calls diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing/stdout b/tests/quick/00.hello/ref/alpha/linux/simple-timing/stdout index 7104aa0ce..423c0b115 100644 --- a/tests/quick/00.hello/ref/alpha/linux/simple-timing/stdout +++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing/stdout @@ -6,8 +6,8 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Sep 5 2006 15:28:48 -M5 started Tue Sep 5 15:42:15 2006 +M5 compiled Oct 10 2006 01:56:36 +M5 started Tue Oct 10 01:57:04 2006 M5 executing on zizzer.eecs.umich.edu command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/simple-timing tests/run.py quick/00.hello/alpha/linux/simple-timing -Exiting @ tick 8312 because target called exit() +Exiting @ tick 8316 because target called exit() diff --git a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.ini b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.ini index 790ae6ab3..e15dd47b7 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.ini @@ -110,6 +110,7 @@ numROBEntries=192 numRobs=1 numThreads=1 predType=tournament +progress_interval=0 renameToDecodeDelay=1 renameToFetchDelay=1 renameToIEWDelay=2 @@ -384,20 +385,30 @@ mem_side=system.membus.port[1] [system.cpu.toL2Bus] type=Bus bus_id=0 +clock=1000 +width=64 port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side [system.cpu.workload] type=LiveProcess cmd=hello +egid=100 env= +euid=100 executable=tests/test-progs/hello/bin/alpha/tru64/hello +gid=100 input=cin output=cout +pid=100 +ppid=99 system=system +uid=100 [system.membus] type=Bus bus_id=0 +clock=1000 +width=64 port=system.physmem.port system.cpu.l2cache.mem_side [system.physmem] @@ -409,6 +420,7 @@ port=system.membus.port[0] [trace] bufsize=0 +cycle=0 dump_on_exit=false file=cout flags= diff --git a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.out b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.out index 474ea3523..a57dbacf3 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.out +++ b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.out @@ -19,6 +19,8 @@ mem_mode=atomic [system.membus] type=Bus bus_id=0 +clock=1000 +width=64 [system.cpu.workload] type=LiveProcess @@ -28,6 +30,12 @@ input=cin output=cout env= system=system +uid=100 +euid=100 +gid=100 +egid=100 +pid=100 +ppid=99 [system.cpu.dcache] type=BaseCache @@ -208,6 +216,7 @@ max_insts_any_thread=0 max_insts_all_threads=0 max_loads_any_thread=0 max_loads_all_threads=0 +progress_interval=0 cachePorts=200 decodeToFetchDelay=1 renameToFetchDelay=1 @@ -354,10 +363,13 @@ hit_latency=1 [system.cpu.toL2Bus] type=Bus bus_id=0 +clock=1000 +width=64 [trace] flags= start=0 +cycle=0 bufsize=0 file=cout dump_on_exit=false @@ -401,3 +413,6 @@ trace_system=client [debug] break_cycles= +[statsreset] +reset_cycle=0 + diff --git a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/m5stats.txt b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/m5stats.txt index db582e731..41348bbfb 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/m5stats.txt +++ b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/m5stats.txt @@ -8,10 +8,10 @@ global.BPredUnit.condIncorrect 222 # Nu global.BPredUnit.condPredicted 441 # Number of conditional branches predicted global.BPredUnit.lookups 888 # Number of BP lookups global.BPredUnit.usedRAS 160 # Number of times the RAS was used to get a target. -host_inst_rate 26468 # Simulator instruction rate (inst/s) -host_mem_usage 159864 # Number of bytes of host memory used +host_inst_rate 26386 # Simulator instruction rate (inst/s) +host_mem_usage 159884 # Number of bytes of host memory used host_seconds 0.09 # Real time elapsed on the host -host_tick_rate 31894 # Simulator tick rate (ticks/s) +host_tick_rate 31792 # Simulator tick rate (ticks/s) memdepunit.memDep.conflictingLoads 9 # Number of conflicting loads. memdepunit.memDep.conflictingStores 7 # Number of conflicting stores. memdepunit.memDep.insertedLoads 675 # Number of loads inserted to the mem dependence unit. @@ -51,16 +51,16 @@ system.cpu.committedInsts 2387 # Nu system.cpu.committedInsts_total 2387 # Number of Instructions Simulated system.cpu.cpi 1.209049 # CPI: Cycles Per Instruction system.cpu.cpi_total 1.209049 # CPI: Total CPI of All Threads -system.cpu.dcache.ReadReq_accesses 535 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses 534 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_avg_miss_latency 3 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 470 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits 469 # number of ReadReq hits system.cpu.dcache.ReadReq_miss_latency 195 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.121495 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate 0.121723 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_misses 65 # number of ReadReq misses system.cpu.dcache.ReadReq_mshr_hits 4 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_miss_latency 122 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.114019 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate 0.114232 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_misses 61 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 294 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_avg_miss_latency 3.017241 # average WriteReq miss latency @@ -75,37 +75,37 @@ system.cpu.dcache.WriteReq_mshr_miss_rate 0.081633 # m system.cpu.dcache.WriteReq_mshr_misses 24 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles_no_targets 1.500000 # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 8.305882 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 8.294118 # Average number of references to valid blocks. system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_no_targets 2 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_targets 3 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 829 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses 828 # number of demand (read+write) accesses system.cpu.dcache.demand_avg_miss_latency 3.008130 # average overall miss latency system.cpu.dcache.demand_avg_mshr_miss_latency 2.058824 # average overall mshr miss latency -system.cpu.dcache.demand_hits 706 # number of demand (read+write) hits +system.cpu.dcache.demand_hits 705 # number of demand (read+write) hits system.cpu.dcache.demand_miss_latency 370 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.148372 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate 0.148551 # miss rate for demand accesses system.cpu.dcache.demand_misses 123 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 38 # number of demand (read+write) MSHR hits system.cpu.dcache.demand_mshr_miss_latency 175 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.102533 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate 0.102657 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_misses 85 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.overall_accesses 829 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses 828 # number of overall (read+write) accesses system.cpu.dcache.overall_avg_miss_latency 3.008130 # average overall miss latency system.cpu.dcache.overall_avg_mshr_miss_latency 2.058824 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 706 # number of overall hits +system.cpu.dcache.overall_hits 705 # number of overall hits system.cpu.dcache.overall_miss_latency 370 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.148372 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate 0.148551 # miss rate for overall accesses system.cpu.dcache.overall_misses 123 # number of overall misses system.cpu.dcache.overall_mshr_hits 38 # number of overall MSHR hits system.cpu.dcache.overall_mshr_miss_latency 175 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.102533 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate 0.102657 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_misses 85 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses @@ -122,7 +122,7 @@ system.cpu.dcache.replacements 0 # nu system.cpu.dcache.sampled_refs 85 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.dcache.tagsinuse 54.161413 # Cycle average of tags in use -system.cpu.dcache.total_refs 706 # Total number of references to valid blocks. +system.cpu.dcache.total_refs 705 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 0 # number of writebacks system.cpu.decode.DECODE:BlockedCycles 82 # Number of cycles decode is blocked @@ -222,30 +222,30 @@ system.cpu.icache.tagsinuse 115.538968 # Cy system.cpu.icache.total_refs 550 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.iew.EXEC:branches 533 # Number of branches executed -system.cpu.iew.EXEC:insts 3123 # Number of executed instructions -system.cpu.iew.EXEC:loads 578 # Number of load instructions executed +system.cpu.iew.EXEC:branches 532 # Number of branches executed system.cpu.iew.EXEC:nop 247 # number of nop insts executed -system.cpu.iew.EXEC:rate 1.081746 # Inst execution rate -system.cpu.iew.EXEC:refs 914 # number of memory reference insts executed -system.cpu.iew.EXEC:squashedInsts 148 # Number of squashed instructions skipped in execute +system.cpu.iew.EXEC:rate 1.078628 # Inst execution rate +system.cpu.iew.EXEC:refs 910 # number of memory reference insts executed system.cpu.iew.EXEC:stores 336 # Number of stores executed system.cpu.iew.EXEC:swp 0 # number of swp insts executed -system.cpu.iew.WB:consumers 1801 # num instructions consuming a value -system.cpu.iew.WB:count 3070 # cumulative count of insts written-back -system.cpu.iew.WB:fanout 0.791227 # average fanout of values written-back +system.cpu.iew.WB:consumers 1788 # num instructions consuming a value +system.cpu.iew.WB:count 3053 # cumulative count of insts written-back +system.cpu.iew.WB:fanout 0.790828 # average fanout of values written-back system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 1425 # num instructions producing a value -system.cpu.iew.WB:rate 1.063388 # insts written-back per cycle -system.cpu.iew.WB:sent 3076 # cumulative count of insts sent to commit -system.cpu.iew.branchMispredicts 159 # Number of branch mispredicts detected at execute +system.cpu.iew.WB:producers 1414 # num instructions producing a value +system.cpu.iew.WB:rate 1.057499 # insts written-back per cycle +system.cpu.iew.WB:sent 3067 # cumulative count of insts sent to commit +system.cpu.iew.branchMispredicts 158 # Number of branch mispredicts detected at execute system.cpu.iew.iewBlockCycles 0 # Number of cycles IEW is blocking system.cpu.iew.iewDispLoadInsts 675 # Number of dispatched load instructions system.cpu.iew.iewDispNonSpecInsts 7 # Number of dispatched non-speculative instructions system.cpu.iew.iewDispSquashedInsts 127 # Number of squashed instructions skipped by dispatch system.cpu.iew.iewDispStoreInsts 369 # Number of dispatched store instructions system.cpu.iew.iewDispatchedInsts 3835 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 574 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 143 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 3114 # Number of executed instructions system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall @@ -257,1586 +257,19 @@ system.cpu.iew.lsq.thread.0.forwLoads 30 # Nu system.cpu.iew.lsq.thread.0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address +system.cpu.iew.lsq.thread.0.memOrderViolation 11 # Number of memory ordering violations system.cpu.iew.lsq.thread.0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu.iew.lsq.thread.0.squashedLoads 260 # Number of loads squashed system.cpu.iew.lsq.thread.0.squashedStores 75 # Number of stores squashed system.cpu.iew.memOrderViolationEvents 11 # Number of memory order violations -system.cpu.iew.predictedNotTakenIncorrect 106 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 105 # Number of branches that were predicted not taken incorrectly system.cpu.iew.predictedTakenIncorrect 53 # Number of branches that were predicted taken incorrectly system.cpu.ipc 0.827096 # IPC: Instructions Per Cycle system.cpu.ipc_total 0.827096 # IPC: Total IPC of All Threads -system.cpu.iq.IQ:residence:(null).start_dist # cycles from dispatch to issue -system.cpu.iq.IQ:residence:(null).samples 0 -system.cpu.iq.IQ:residence:(null).min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.IQ:residence:(null).max_value 0 -system.cpu.iq.IQ:residence:(null).end_dist - -system.cpu.iq.IQ:residence:IntAlu.start_dist # cycles from dispatch to issue -system.cpu.iq.IQ:residence:IntAlu.samples 0 -system.cpu.iq.IQ:residence:IntAlu.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.IQ:residence:IntAlu.max_value 0 -system.cpu.iq.IQ:residence:IntAlu.end_dist - -system.cpu.iq.IQ:residence:IntMult.start_dist # cycles from dispatch to issue -system.cpu.iq.IQ:residence:IntMult.samples 0 -system.cpu.iq.IQ:residence:IntMult.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.IQ:residence:IntMult.max_value 0 -system.cpu.iq.IQ:residence:IntMult.end_dist - -system.cpu.iq.IQ:residence:IntDiv.start_dist # cycles from dispatch to issue -system.cpu.iq.IQ:residence:IntDiv.samples 0 -system.cpu.iq.IQ:residence:IntDiv.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.IQ:residence:IntDiv.max_value 0 -system.cpu.iq.IQ:residence:IntDiv.end_dist - -system.cpu.iq.IQ:residence:FloatAdd.start_dist # cycles from dispatch to issue -system.cpu.iq.IQ:residence:FloatAdd.samples 0 -system.cpu.iq.IQ:residence:FloatAdd.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.IQ:residence:FloatAdd.max_value 0 -system.cpu.iq.IQ:residence:FloatAdd.end_dist - -system.cpu.iq.IQ:residence:FloatCmp.start_dist # cycles from dispatch to issue -system.cpu.iq.IQ:residence:FloatCmp.samples 0 -system.cpu.iq.IQ:residence:FloatCmp.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.IQ:residence:FloatCmp.max_value 0 -system.cpu.iq.IQ:residence:FloatCmp.end_dist - -system.cpu.iq.IQ:residence:FloatCvt.start_dist # cycles from dispatch to issue -system.cpu.iq.IQ:residence:FloatCvt.samples 0 -system.cpu.iq.IQ:residence:FloatCvt.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.IQ:residence:FloatCvt.max_value 0 -system.cpu.iq.IQ:residence:FloatCvt.end_dist - -system.cpu.iq.IQ:residence:FloatMult.start_dist # cycles from dispatch to issue -system.cpu.iq.IQ:residence:FloatMult.samples 0 -system.cpu.iq.IQ:residence:FloatMult.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.IQ:residence:FloatMult.max_value 0 -system.cpu.iq.IQ:residence:FloatMult.end_dist - -system.cpu.iq.IQ:residence:FloatDiv.start_dist # cycles from dispatch to issue -system.cpu.iq.IQ:residence:FloatDiv.samples 0 -system.cpu.iq.IQ:residence:FloatDiv.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.IQ:residence:FloatDiv.max_value 0 -system.cpu.iq.IQ:residence:FloatDiv.end_dist - -system.cpu.iq.IQ:residence:FloatSqrt.start_dist # cycles from dispatch to issue -system.cpu.iq.IQ:residence:FloatSqrt.samples 0 -system.cpu.iq.IQ:residence:FloatSqrt.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.IQ:residence:FloatSqrt.max_value 0 -system.cpu.iq.IQ:residence:FloatSqrt.end_dist - -system.cpu.iq.IQ:residence:MemRead.start_dist # cycles from dispatch to issue -system.cpu.iq.IQ:residence:MemRead.samples 0 -system.cpu.iq.IQ:residence:MemRead.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.IQ:residence:MemRead.max_value 0 -system.cpu.iq.IQ:residence:MemRead.end_dist - -system.cpu.iq.IQ:residence:MemWrite.start_dist # cycles from dispatch to issue -system.cpu.iq.IQ:residence:MemWrite.samples 0 -system.cpu.iq.IQ:residence:MemWrite.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.IQ:residence:MemWrite.max_value 0 -system.cpu.iq.IQ:residence:MemWrite.end_dist - -system.cpu.iq.IQ:residence:IprAccess.start_dist # cycles from dispatch to issue -system.cpu.iq.IQ:residence:IprAccess.samples 0 -system.cpu.iq.IQ:residence:IprAccess.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.IQ:residence:IprAccess.max_value 0 -system.cpu.iq.IQ:residence:IprAccess.end_dist - -system.cpu.iq.IQ:residence:InstPrefetch.start_dist # cycles from dispatch to issue -system.cpu.iq.IQ:residence:InstPrefetch.samples 0 -system.cpu.iq.IQ:residence:InstPrefetch.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.IQ:residence:InstPrefetch.max_value 0 -system.cpu.iq.IQ:residence:InstPrefetch.end_dist - -system.cpu.iq.ISSUE:(null)_delay.start_dist # cycles from operands ready to issue -system.cpu.iq.ISSUE:(null)_delay.samples 0 -system.cpu.iq.ISSUE:(null)_delay.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.ISSUE:(null)_delay.max_value 0 -system.cpu.iq.ISSUE:(null)_delay.end_dist - -system.cpu.iq.ISSUE:IntAlu_delay.start_dist # cycles from operands ready to issue -system.cpu.iq.ISSUE:IntAlu_delay.samples 0 -system.cpu.iq.ISSUE:IntAlu_delay.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.ISSUE:IntAlu_delay.max_value 0 -system.cpu.iq.ISSUE:IntAlu_delay.end_dist - -system.cpu.iq.ISSUE:IntMult_delay.start_dist # cycles from operands ready to issue -system.cpu.iq.ISSUE:IntMult_delay.samples 0 -system.cpu.iq.ISSUE:IntMult_delay.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.ISSUE:IntMult_delay.max_value 0 -system.cpu.iq.ISSUE:IntMult_delay.end_dist - -system.cpu.iq.ISSUE:IntDiv_delay.start_dist # cycles from operands ready to issue -system.cpu.iq.ISSUE:IntDiv_delay.samples 0 -system.cpu.iq.ISSUE:IntDiv_delay.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.ISSUE:IntDiv_delay.max_value 0 -system.cpu.iq.ISSUE:IntDiv_delay.end_dist - -system.cpu.iq.ISSUE:FloatAdd_delay.start_dist # cycles from operands ready to issue -system.cpu.iq.ISSUE:FloatAdd_delay.samples 0 -system.cpu.iq.ISSUE:FloatAdd_delay.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.ISSUE:FloatAdd_delay.max_value 0 -system.cpu.iq.ISSUE:FloatAdd_delay.end_dist - -system.cpu.iq.ISSUE:FloatCmp_delay.start_dist # cycles from operands ready to issue -system.cpu.iq.ISSUE:FloatCmp_delay.samples 0 -system.cpu.iq.ISSUE:FloatCmp_delay.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.ISSUE:FloatCmp_delay.max_value 0 -system.cpu.iq.ISSUE:FloatCmp_delay.end_dist - -system.cpu.iq.ISSUE:FloatCvt_delay.start_dist # cycles from operands ready to issue -system.cpu.iq.ISSUE:FloatCvt_delay.samples 0 -system.cpu.iq.ISSUE:FloatCvt_delay.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.ISSUE:FloatCvt_delay.max_value 0 -system.cpu.iq.ISSUE:FloatCvt_delay.end_dist - -system.cpu.iq.ISSUE:FloatMult_delay.start_dist # cycles from operands ready to issue -system.cpu.iq.ISSUE:FloatMult_delay.samples 0 -system.cpu.iq.ISSUE:FloatMult_delay.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.ISSUE:FloatMult_delay.max_value 0 -system.cpu.iq.ISSUE:FloatMult_delay.end_dist - -system.cpu.iq.ISSUE:FloatDiv_delay.start_dist # cycles from operands ready to issue -system.cpu.iq.ISSUE:FloatDiv_delay.samples 0 -system.cpu.iq.ISSUE:FloatDiv_delay.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.ISSUE:FloatDiv_delay.max_value 0 -system.cpu.iq.ISSUE:FloatDiv_delay.end_dist - -system.cpu.iq.ISSUE:FloatSqrt_delay.start_dist # cycles from operands ready to issue -system.cpu.iq.ISSUE:FloatSqrt_delay.samples 0 -system.cpu.iq.ISSUE:FloatSqrt_delay.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.ISSUE:FloatSqrt_delay.max_value 0 -system.cpu.iq.ISSUE:FloatSqrt_delay.end_dist - -system.cpu.iq.ISSUE:MemRead_delay.start_dist # cycles from operands ready to issue -system.cpu.iq.ISSUE:MemRead_delay.samples 0 -system.cpu.iq.ISSUE:MemRead_delay.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.ISSUE:MemRead_delay.max_value 0 -system.cpu.iq.ISSUE:MemRead_delay.end_dist - -system.cpu.iq.ISSUE:MemWrite_delay.start_dist # cycles from operands ready to issue -system.cpu.iq.ISSUE:MemWrite_delay.samples 0 -system.cpu.iq.ISSUE:MemWrite_delay.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.ISSUE:MemWrite_delay.max_value 0 -system.cpu.iq.ISSUE:MemWrite_delay.end_dist - -system.cpu.iq.ISSUE:IprAccess_delay.start_dist # cycles from operands ready to issue -system.cpu.iq.ISSUE:IprAccess_delay.samples 0 -system.cpu.iq.ISSUE:IprAccess_delay.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.ISSUE:IprAccess_delay.max_value 0 -system.cpu.iq.ISSUE:IprAccess_delay.end_dist - -system.cpu.iq.ISSUE:InstPrefetch_delay.start_dist # cycles from operands ready to issue -system.cpu.iq.ISSUE:InstPrefetch_delay.samples 0 -system.cpu.iq.ISSUE:InstPrefetch_delay.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.ISSUE:InstPrefetch_delay.max_value 0 -system.cpu.iq.ISSUE:InstPrefetch_delay.end_dist - -system.cpu.iq.ISSUE:FU_type_0 3271 # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0 3257 # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.start_dist (null) 0 0.00% # Type of FU issued - IntAlu 2317 70.83% # Type of FU issued + IntAlu 2308 70.86% # Type of FU issued IntMult 1 0.03% # Type of FU issued IntDiv 0 0.00% # Type of FU issued FloatAdd 0 0.00% # Type of FU issued @@ -1845,13 +278,13 @@ system.cpu.iq.ISSUE:FU_type_0.start_dist FloatMult 0 0.00% # Type of FU issued FloatDiv 0 0.00% # Type of FU issued FloatSqrt 0 0.00% # Type of FU issued - MemRead 609 18.62% # Type of FU issued - MemWrite 344 10.52% # Type of FU issued + MemRead 605 18.58% # Type of FU issued + MemWrite 343 10.53% # Type of FU issued IprAccess 0 0.00% # Type of FU issued InstPrefetch 0 0.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.end_dist system.cpu.iq.ISSUE:fu_busy_cnt 40 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_rate 0.012229 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:fu_busy_rate 0.012281 # FU busy rate (busy events/executed inst) system.cpu.iq.ISSUE:fu_full.start_dist (null) 0 0.00% # attempts to use FU when none available IntAlu 5 12.50% # attempts to use FU when none available @@ -1871,11 +304,11 @@ system.cpu.iq.ISSUE:fu_full.end_dist system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle.samples 2887 system.cpu.iq.ISSUE:issued_per_cycle.min_value 0 - 0 1603 5552.48% - 1 434 1503.29% - 2 301 1042.60% - 3 220 762.04% - 4 167 578.46% + 0 1607 5566.33% + 1 435 1506.75% + 2 298 1032.21% + 3 221 765.50% + 4 164 568.06% 5 94 325.60% 6 46 159.33% 7 15 51.96% @@ -1883,14 +316,14 @@ system.cpu.iq.ISSUE:issued_per_cycle.min_value 0 system.cpu.iq.ISSUE:issued_per_cycle.max_value 8 system.cpu.iq.ISSUE:issued_per_cycle.end_dist -system.cpu.iq.ISSUE:rate 1.133010 # Inst issue rate +system.cpu.iq.ISSUE:rate 1.128161 # Inst issue rate system.cpu.iq.iqInstsAdded 3581 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 3271 # Number of instructions issued +system.cpu.iq.iqInstsIssued 3257 # Number of instructions issued system.cpu.iq.iqNonSpecInstsAdded 7 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 1067 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsExamined 1088 # Number of squashed instructions iterated over during squash; mainly for profiling system.cpu.iq.iqSquashedInstsIssued 1 # Number of squashed instructions issued system.cpu.iq.iqSquashedNonSpecRemoved 3 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 477 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedOperandsExamined 503 # Number of squashed operands that are examined and possibly removed from graph system.cpu.l2cache.ReadReq_accesses 274 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_avg_miss_latency 2.018248 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1 # average ReadReq mshr miss latency diff --git a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stdout b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stdout index 708b9587a..c51631489 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stdout +++ b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stdout @@ -6,8 +6,8 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Sep 5 2006 15:28:48 -M5 started Tue Sep 5 15:42:16 2006 +M5 compiled Oct 8 2006 14:00:39 +M5 started Sun Oct 8 14:00:52 2006 M5 executing on zizzer.eecs.umich.edu command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/quick/00.hello/alpha/tru64/o3-timing tests/run.py quick/00.hello/alpha/tru64/o3-timing Exiting @ tick 2886 because target called exit() diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/config.ini b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/config.ini index 1ec052afb..60783267b 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/config.ini +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/config.ini @@ -56,6 +56,7 @@ physmem=system.physmem type=AtomicSimpleCPU children=workload clock=1 +cpu_id=0 defer_registration=false function_trace=false function_trace_start=0 @@ -64,6 +65,7 @@ max_insts_any_thread=0 max_loads_all_threads=0 max_loads_any_thread=0 mem=system.physmem +progress_interval=0 simulate_stalls=false system=system width=1 @@ -74,15 +76,23 @@ icache_port=system.membus.port[1] [system.cpu.workload] type=LiveProcess cmd=hello +egid=100 env= +euid=100 executable=tests/test-progs/hello/bin/alpha/tru64/hello +gid=100 input=cin output=cout +pid=100 +ppid=99 system=system +uid=100 [system.membus] type=Bus bus_id=0 +clock=1000 +width=64 port=system.physmem.port system.cpu.icache_port system.cpu.dcache_port [system.physmem] @@ -94,6 +104,7 @@ port=system.membus.port[0] [trace] bufsize=0 +cycle=0 dump_on_exit=false file=cout flags= diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/config.out b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/config.out index ae24ae2a8..c8733b8f7 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/config.out +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/config.out @@ -19,6 +19,8 @@ mem_mode=atomic [system.membus] type=Bus bus_id=0 +clock=1000 +width=64 [system.cpu.workload] type=LiveProcess @@ -28,6 +30,12 @@ input=cin output=cout env= system=system +uid=100 +euid=100 +gid=100 +egid=100 +pid=100 +ppid=99 [system.cpu] type=AtomicSimpleCPU @@ -35,8 +43,10 @@ max_insts_any_thread=0 max_insts_all_threads=0 max_loads_any_thread=0 max_loads_all_threads=0 +progress_interval=0 mem=system.physmem system=system +cpu_id=0 workload=system.cpu.workload clock=1 defer_registration=false @@ -48,6 +58,7 @@ simulate_stalls=false [trace] flags= start=0 +cycle=0 bufsize=0 file=cout dump_on_exit=false @@ -91,3 +102,6 @@ trace_system=client [debug] break_cycles= +[statsreset] +reset_cycle=0 + diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/m5stats.txt b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/m5stats.txt index b4747f1f4..e3f845135 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/m5stats.txt +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/m5stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 46556 # Simulator instruction rate (inst/s) -host_mem_usage 147672 # Number of bytes of host memory used -host_seconds 0.06 # Real time elapsed on the host -host_tick_rate 46204 # Simulator tick rate (ticks/s) +host_inst_rate 60702 # Simulator instruction rate (inst/s) +host_mem_usage 147692 # Number of bytes of host memory used +host_seconds 0.04 # Real time elapsed on the host +host_tick_rate 60102 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 2578 # Number of instructions simulated sim_seconds 0.000000 # Number of seconds simulated diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/stdout b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/stdout index 438e330f5..2ee4e0a08 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/stdout +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/stdout @@ -6,8 +6,8 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Sep 5 2006 15:28:48 -M5 started Tue Sep 5 15:42:18 2006 +M5 compiled Oct 8 2006 14:00:39 +M5 started Sun Oct 8 14:00:54 2006 M5 executing on zizzer.eecs.umich.edu command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/quick/00.hello/alpha/tru64/simple-atomic tests/run.py quick/00.hello/alpha/tru64/simple-atomic Exiting @ tick 2577 because target called exit() diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.ini b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.ini index e833d841e..f32654f76 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.ini +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.ini @@ -56,6 +56,7 @@ physmem=system.physmem type=TimingSimpleCPU children=dcache icache l2cache toL2Bus workload clock=1 +cpu_id=0 defer_registration=false function_trace=false function_trace_start=0 @@ -64,6 +65,7 @@ max_insts_any_thread=0 max_loads_all_threads=0 max_loads_any_thread=0 mem=system.cpu.dcache +progress_interval=0 system=system workload=system.cpu.workload dcache_port=system.cpu.dcache.cpu_side @@ -192,20 +194,30 @@ mem_side=system.membus.port[1] [system.cpu.toL2Bus] type=Bus bus_id=0 +clock=1000 +width=64 port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side [system.cpu.workload] type=LiveProcess cmd=hello +egid=100 env= +euid=100 executable=tests/test-progs/hello/bin/alpha/tru64/hello +gid=100 input=cin output=cout +pid=100 +ppid=99 system=system +uid=100 [system.membus] type=Bus bus_id=0 +clock=1000 +width=64 port=system.physmem.port system.cpu.l2cache.mem_side [system.physmem] @@ -217,6 +229,7 @@ port=system.membus.port[0] [trace] bufsize=0 +cycle=0 dump_on_exit=false file=cout flags= diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.out b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.out index 1914b47e7..c45e587d9 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.out +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.out @@ -19,6 +19,8 @@ mem_mode=atomic [system.membus] type=Bus bus_id=0 +clock=1000 +width=64 [system.cpu.dcache] type=BaseCache @@ -67,6 +69,12 @@ input=cin output=cout env= system=system +uid=100 +euid=100 +gid=100 +egid=100 +pid=100 +ppid=99 [system.cpu] type=TimingSimpleCPU @@ -74,8 +82,10 @@ max_insts_any_thread=0 max_insts_all_threads=0 max_loads_any_thread=0 max_loads_all_threads=0 +progress_interval=0 mem=system.cpu.dcache system=system +cpu_id=0 workload=system.cpu.workload clock=1 defer_registration=false @@ -87,6 +97,8 @@ function_trace_start=0 [system.cpu.toL2Bus] type=Bus bus_id=0 +clock=1000 +width=64 [system.cpu.icache] type=BaseCache @@ -169,6 +181,7 @@ hit_latency=1 [trace] flags= start=0 +cycle=0 bufsize=0 file=cout dump_on_exit=false @@ -212,3 +225,6 @@ trace_system=client [debug] break_cycles= +[statsreset] +reset_cycle=0 + diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/m5stats.txt b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/m5stats.txt index 47bcc1b3c..27b01a108 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/m5stats.txt +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/m5stats.txt @@ -1,22 +1,22 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 73626 # Simulator instruction rate (inst/s) -host_mem_usage 159128 # Number of bytes of host memory used -host_seconds 0.04 # Real time elapsed on the host -host_tick_rate 106590 # Simulator tick rate (ticks/s) +host_inst_rate 120829 # Simulator instruction rate (inst/s) +host_mem_usage 165792 # Number of bytes of host memory used +host_seconds 0.02 # Real time elapsed on the host +host_tick_rate 168699 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 2578 # Number of instructions simulated sim_seconds 0.000000 # Number of seconds simulated sim_ticks 3777 # Number of ticks simulated -system.cpu.dcache.ReadReq_accesses 416 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses 415 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_avg_miss_latency 3 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 361 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits 360 # number of ReadReq hits system.cpu.dcache.ReadReq_miss_latency 165 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.132212 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate 0.132530 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_misses 55 # number of ReadReq misses system.cpu.dcache.ReadReq_mshr_miss_latency 110 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.132212 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate 0.132530 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_misses 55 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 294 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_avg_miss_latency 3 # average WriteReq miss latency @@ -30,37 +30,37 @@ system.cpu.dcache.WriteReq_mshr_miss_rate 0.091837 # m system.cpu.dcache.WriteReq_mshr_misses 27 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 7.658537 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 7.646341 # Average number of references to valid blocks. system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 710 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses 709 # number of demand (read+write) accesses system.cpu.dcache.demand_avg_miss_latency 3 # average overall miss latency system.cpu.dcache.demand_avg_mshr_miss_latency 2 # average overall mshr miss latency -system.cpu.dcache.demand_hits 628 # number of demand (read+write) hits +system.cpu.dcache.demand_hits 627 # number of demand (read+write) hits system.cpu.dcache.demand_miss_latency 246 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.115493 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate 0.115656 # miss rate for demand accesses system.cpu.dcache.demand_misses 82 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.cpu.dcache.demand_mshr_miss_latency 164 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.115493 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate 0.115656 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_misses 82 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.overall_accesses 710 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses 709 # number of overall (read+write) accesses system.cpu.dcache.overall_avg_miss_latency 3 # average overall miss latency system.cpu.dcache.overall_avg_mshr_miss_latency 2 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 628 # number of overall hits +system.cpu.dcache.overall_hits 627 # number of overall hits system.cpu.dcache.overall_miss_latency 246 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.115493 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate 0.115656 # miss rate for overall accesses system.cpu.dcache.overall_misses 82 # number of overall misses system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits system.cpu.dcache.overall_mshr_miss_latency 164 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.115493 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate 0.115656 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_misses 82 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses @@ -77,7 +77,7 @@ system.cpu.dcache.replacements 0 # nu system.cpu.dcache.sampled_refs 82 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.dcache.tagsinuse 53.009529 # Cycle average of tags in use -system.cpu.dcache.total_refs 628 # Total number of references to valid blocks. +system.cpu.dcache.total_refs 627 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 0 # number of writebacks system.cpu.icache.ReadReq_accesses 2579 # number of ReadReq accesses(hits+misses) @@ -205,7 +205,7 @@ system.cpu.l2cache.total_refs 0 # To system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 0 # number of cpu cycles simulated +system.cpu.numCycles 3777 # number of cpu cycles simulated system.cpu.num_insts 2578 # Number of instructions executed system.cpu.num_refs 710 # Number of memory references system.cpu.workload.PROG:num_syscalls 4 # Number of system calls diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/stdout b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/stdout index 4a02e57f0..1beab6f4b 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/stdout +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/stdout @@ -6,8 +6,8 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Sep 5 2006 15:28:48 -M5 started Tue Sep 5 15:42:18 2006 +M5 compiled Oct 10 2006 01:56:36 +M5 started Tue Oct 10 01:57:11 2006 M5 executing on zizzer.eecs.umich.edu command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/quick/00.hello/alpha/tru64/simple-timing tests/run.py quick/00.hello/alpha/tru64/simple-timing Exiting @ tick 3777 because target called exit() diff --git a/tests/quick/00.hello/ref/mips/linux/simple-atomic/config.ini b/tests/quick/00.hello/ref/mips/linux/simple-atomic/config.ini index 2c82b8c1a..59cadaa12 100644 --- a/tests/quick/00.hello/ref/mips/linux/simple-atomic/config.ini +++ b/tests/quick/00.hello/ref/mips/linux/simple-atomic/config.ini @@ -56,6 +56,7 @@ physmem=system.physmem type=AtomicSimpleCPU children=workload clock=1 +cpu_id=0 defer_registration=false function_trace=false function_trace_start=0 @@ -64,6 +65,7 @@ max_insts_any_thread=0 max_loads_all_threads=0 max_loads_any_thread=0 mem=system.physmem +progress_interval=0 simulate_stalls=false system=system width=1 @@ -74,15 +76,23 @@ icache_port=system.membus.port[1] [system.cpu.workload] type=LiveProcess cmd=hello +egid=100 env= +euid=100 executable=tests/test-progs/hello/bin/mips/linux/hello +gid=100 input=cin output=cout +pid=100 +ppid=99 system=system +uid=100 [system.membus] type=Bus bus_id=0 +clock=1000 +width=64 port=system.physmem.port system.cpu.icache_port system.cpu.dcache_port [system.physmem] @@ -94,6 +104,7 @@ port=system.membus.port[0] [trace] bufsize=0 +cycle=0 dump_on_exit=false file=cout flags= diff --git a/tests/quick/00.hello/ref/mips/linux/simple-atomic/config.out b/tests/quick/00.hello/ref/mips/linux/simple-atomic/config.out index 8678c0d97..064f467da 100644 --- a/tests/quick/00.hello/ref/mips/linux/simple-atomic/config.out +++ b/tests/quick/00.hello/ref/mips/linux/simple-atomic/config.out @@ -19,6 +19,8 @@ mem_mode=atomic [system.membus] type=Bus bus_id=0 +clock=1000 +width=64 [system.cpu.workload] type=LiveProcess @@ -28,6 +30,12 @@ input=cin output=cout env= system=system +uid=100 +euid=100 +gid=100 +egid=100 +pid=100 +ppid=99 [system.cpu] type=AtomicSimpleCPU @@ -35,8 +43,10 @@ max_insts_any_thread=0 max_insts_all_threads=0 max_loads_any_thread=0 max_loads_all_threads=0 +progress_interval=0 mem=system.physmem system=system +cpu_id=0 workload=system.cpu.workload clock=1 defer_registration=false @@ -48,6 +58,7 @@ simulate_stalls=false [trace] flags= start=0 +cycle=0 bufsize=0 file=cout dump_on_exit=false @@ -91,3 +102,6 @@ trace_system=client [debug] break_cycles= +[statsreset] +reset_cycle=0 + diff --git a/tests/quick/00.hello/ref/mips/linux/simple-atomic/m5stats.txt b/tests/quick/00.hello/ref/mips/linux/simple-atomic/m5stats.txt index b70a6ee17..3b2a2730b 100644 --- a/tests/quick/00.hello/ref/mips/linux/simple-atomic/m5stats.txt +++ b/tests/quick/00.hello/ref/mips/linux/simple-atomic/m5stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 90956 # Simulator instruction rate (inst/s) -host_mem_usage 147380 # Number of bytes of host memory used -host_seconds 0.06 # Real time elapsed on the host -host_tick_rate 90353 # Simulator tick rate (ticks/s) +host_inst_rate 52255 # Simulator instruction rate (inst/s) +host_mem_usage 148024 # Number of bytes of host memory used +host_seconds 0.11 # Real time elapsed on the host +host_tick_rate 52038 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 5657 # Number of instructions simulated sim_seconds 0.000000 # Number of seconds simulated diff --git a/tests/quick/00.hello/ref/mips/linux/simple-atomic/stdout b/tests/quick/00.hello/ref/mips/linux/simple-atomic/stdout index f5b9c8fd7..600b178b3 100644 --- a/tests/quick/00.hello/ref/mips/linux/simple-atomic/stdout +++ b/tests/quick/00.hello/ref/mips/linux/simple-atomic/stdout @@ -6,8 +6,8 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Sep 5 2006 15:37:09 -M5 started Tue Sep 5 15:46:32 2006 +M5 compiled Oct 9 2006 19:28:25 +M5 started Mon Oct 9 19:28:56 2006 M5 executing on zizzer.eecs.umich.edu -command line: build/MIPS_SE/m5.opt -d build/MIPS_SE/tests/opt/quick/00.hello/mips/linux/simple-atomic tests/run.py quick/00.hello/mips/linux/simple-atomic +command line: build/MIPS_SE/m5.debug -d build/MIPS_SE/tests/debug/quick/00.hello/mips/linux/simple-atomic tests/run.py quick/00.hello/mips/linux/simple-atomic Exiting @ tick 5656 because target called exit() diff --git a/tests/quick/00.hello/ref/mips/linux/simple-timing/config.ini b/tests/quick/00.hello/ref/mips/linux/simple-timing/config.ini index 040735f2c..8e1bb0388 100644 --- a/tests/quick/00.hello/ref/mips/linux/simple-timing/config.ini +++ b/tests/quick/00.hello/ref/mips/linux/simple-timing/config.ini @@ -56,6 +56,7 @@ physmem=system.physmem type=TimingSimpleCPU children=dcache icache l2cache toL2Bus workload clock=1 +cpu_id=0 defer_registration=false function_trace=false function_trace_start=0 @@ -64,6 +65,7 @@ max_insts_any_thread=0 max_loads_all_threads=0 max_loads_any_thread=0 mem=system.cpu.dcache +progress_interval=0 system=system workload=system.cpu.workload dcache_port=system.cpu.dcache.cpu_side @@ -192,20 +194,30 @@ mem_side=system.membus.port[1] [system.cpu.toL2Bus] type=Bus bus_id=0 +clock=1000 +width=64 port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side [system.cpu.workload] type=LiveProcess cmd=hello +egid=100 env= +euid=100 executable=tests/test-progs/hello/bin/mips/linux/hello +gid=100 input=cin output=cout +pid=100 +ppid=99 system=system +uid=100 [system.membus] type=Bus bus_id=0 +clock=1000 +width=64 port=system.physmem.port system.cpu.l2cache.mem_side [system.physmem] @@ -217,6 +229,7 @@ port=system.membus.port[0] [trace] bufsize=0 +cycle=0 dump_on_exit=false file=cout flags= diff --git a/tests/quick/00.hello/ref/mips/linux/simple-timing/config.out b/tests/quick/00.hello/ref/mips/linux/simple-timing/config.out index a7270a97e..d683d2355 100644 --- a/tests/quick/00.hello/ref/mips/linux/simple-timing/config.out +++ b/tests/quick/00.hello/ref/mips/linux/simple-timing/config.out @@ -19,6 +19,8 @@ mem_mode=atomic [system.membus] type=Bus bus_id=0 +clock=1000 +width=64 [system.cpu.dcache] type=BaseCache @@ -67,6 +69,12 @@ input=cin output=cout env= system=system +uid=100 +euid=100 +gid=100 +egid=100 +pid=100 +ppid=99 [system.cpu] type=TimingSimpleCPU @@ -74,8 +82,10 @@ max_insts_any_thread=0 max_insts_all_threads=0 max_loads_any_thread=0 max_loads_all_threads=0 +progress_interval=0 mem=system.cpu.dcache system=system +cpu_id=0 workload=system.cpu.workload clock=1 defer_registration=false @@ -87,6 +97,8 @@ function_trace_start=0 [system.cpu.toL2Bus] type=Bus bus_id=0 +clock=1000 +width=64 [system.cpu.icache] type=BaseCache @@ -169,6 +181,7 @@ hit_latency=1 [trace] flags= start=0 +cycle=0 bufsize=0 file=cout dump_on_exit=false @@ -212,3 +225,6 @@ trace_system=client [debug] break_cycles= +[statsreset] +reset_cycle=0 + diff --git a/tests/quick/00.hello/ref/mips/linux/simple-timing/m5stats.txt b/tests/quick/00.hello/ref/mips/linux/simple-timing/m5stats.txt index 5d054b950..ab86ba509 100644 --- a/tests/quick/00.hello/ref/mips/linux/simple-timing/m5stats.txt +++ b/tests/quick/00.hello/ref/mips/linux/simple-timing/m5stats.txt @@ -1,67 +1,67 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 129834 # Simulator instruction rate (inst/s) -host_mem_usage 158964 # Number of bytes of host memory used -host_seconds 0.04 # Real time elapsed on the host -host_tick_rate 194881 # Simulator tick rate (ticks/s) +host_inst_rate 68704 # Simulator instruction rate (inst/s) +host_mem_usage 166092 # Number of bytes of host memory used +host_seconds 0.08 # Real time elapsed on the host +host_tick_rate 103651 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 5657 # Number of instructions simulated sim_seconds 0.000000 # Number of seconds simulated -sim_ticks 8573 # Number of ticks simulated -system.cpu.dcache.ReadReq_accesses 1131 # number of ReadReq accesses(hits+misses) +sim_ticks 8579 # Number of ticks simulated +system.cpu.dcache.ReadReq_accesses 1130 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_avg_miss_latency 3 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 1052 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 237 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.069850 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 79 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_miss_latency 158 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.069850 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 79 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_accesses 933 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 2.586207 # average WriteReq miss latency +system.cpu.dcache.ReadReq_hits 1048 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 246 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.072566 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 82 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_miss_latency 164 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.072566 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_misses 82 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_accesses 924 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_avg_miss_latency 3 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency 2 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 875 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits 874 # number of WriteReq hits system.cpu.dcache.WriteReq_miss_latency 150 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.062165 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 58 # number of WriteReq misses +system.cpu.dcache.WriteReq_miss_rate 0.054113 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 50 # number of WriteReq misses system.cpu.dcache.WriteReq_mshr_miss_latency 100 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.053591 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate 0.054113 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_misses 50 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 14.065693 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 14.560606 # Average number of references to valid blocks. system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 2064 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 2.824818 # average overall miss latency +system.cpu.dcache.demand_accesses 2054 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 3 # average overall miss latency system.cpu.dcache.demand_avg_mshr_miss_latency 2 # average overall mshr miss latency -system.cpu.dcache.demand_hits 1927 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 387 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.066376 # miss rate for demand accesses -system.cpu.dcache.demand_misses 137 # number of demand (read+write) misses +system.cpu.dcache.demand_hits 1922 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 396 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.064265 # miss rate for demand accesses +system.cpu.dcache.demand_misses 132 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 258 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.062500 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 129 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_miss_latency 264 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.064265 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 132 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.overall_accesses 2064 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 2.824818 # average overall miss latency +system.cpu.dcache.overall_accesses 2054 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 3 # average overall miss latency system.cpu.dcache.overall_avg_mshr_miss_latency 2 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 1927 # number of overall hits -system.cpu.dcache.overall_miss_latency 387 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.066376 # miss rate for overall accesses -system.cpu.dcache.overall_misses 137 # number of overall misses +system.cpu.dcache.overall_avg_mshr_uncacheable_latency no value # average overall mshr uncacheable latency +system.cpu.dcache.overall_hits 1922 # number of overall hits +system.cpu.dcache.overall_miss_latency 396 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.064265 # miss rate for overall accesses +system.cpu.dcache.overall_misses 132 # number of overall misses system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 258 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.062500 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 129 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_miss_latency 264 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.064265 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 132 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -74,10 +74,10 @@ system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.sampled_refs 137 # Sample count of references to valid blocks. +system.cpu.dcache.sampled_refs 132 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 91.822487 # Cycle average of tags in use -system.cpu.dcache.total_refs 1927 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 86.924009 # Cycle average of tags in use +system.cpu.dcache.total_refs 1922 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 0 # number of writebacks system.cpu.icache.ReadReq_accesses 5658 # number of ReadReq accesses(hits+misses) @@ -115,7 +115,7 @@ system.cpu.icache.no_allocate_misses 0 # Nu system.cpu.icache.overall_accesses 5658 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency 2.993399 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 1.993399 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency no value # average overall mshr uncacheable latency system.cpu.icache.overall_hits 5355 # number of overall hits system.cpu.icache.overall_miss_latency 907 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.053552 # miss rate for overall accesses @@ -138,55 +138,55 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.icache.replacements 13 # number of replacements system.cpu.icache.sampled_refs 303 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 138.188010 # Cycle average of tags in use +system.cpu.icache.tagsinuse 138.192774 # Cycle average of tags in use system.cpu.icache.total_refs 5355 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.l2cache.ReadReq_accesses 440 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 1.963470 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_accesses 435 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 2 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_hits 2 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 860 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.995455 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 438 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 430 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.977273 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 430 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_miss_latency 866 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.995402 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 433 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 433 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.995402 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 433 # number of ReadReq MSHR misses system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 0.004566 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 0.004619 # Average number of references to valid blocks. system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 440 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 1.963470 # average overall miss latency +system.cpu.l2cache.demand_accesses 435 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 2 # average overall miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency 1 # average overall mshr miss latency system.cpu.l2cache.demand_hits 2 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 860 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.995455 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 438 # number of demand (read+write) misses +system.cpu.l2cache.demand_miss_latency 866 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.995402 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 433 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 430 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.977273 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 430 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_miss_latency 433 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.995402 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 433 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.overall_accesses 440 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 1.963470 # average overall miss latency +system.cpu.l2cache.overall_accesses 435 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 2 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 1 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no value # average overall mshr uncacheable latency system.cpu.l2cache.overall_hits 2 # number of overall hits -system.cpu.l2cache.overall_miss_latency 860 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.995455 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 438 # number of overall misses +system.cpu.l2cache.overall_miss_latency 866 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.995402 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 433 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 430 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.977273 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 430 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_miss_latency 433 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.995402 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 433 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -199,9 +199,9 @@ system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.sampled_refs 438 # Sample count of references to valid blocks. +system.cpu.l2cache.sampled_refs 433 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 231.300093 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 226.406294 # Cycle average of tags in use system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks diff --git a/tests/quick/00.hello/ref/mips/linux/simple-timing/stdout b/tests/quick/00.hello/ref/mips/linux/simple-timing/stdout index 11009935d..4acd2a2e5 100644 --- a/tests/quick/00.hello/ref/mips/linux/simple-timing/stdout +++ b/tests/quick/00.hello/ref/mips/linux/simple-timing/stdout @@ -6,8 +6,8 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Sep 5 2006 15:37:09 -M5 started Tue Sep 5 15:46:32 2006 +M5 compiled Oct 9 2006 19:28:25 +M5 started Mon Oct 9 19:28:56 2006 M5 executing on zizzer.eecs.umich.edu -command line: build/MIPS_SE/m5.opt -d build/MIPS_SE/tests/opt/quick/00.hello/mips/linux/simple-timing tests/run.py quick/00.hello/mips/linux/simple-timing -Exiting @ tick 8573 because target called exit() +command line: build/MIPS_SE/m5.debug -d build/MIPS_SE/tests/debug/quick/00.hello/mips/linux/simple-timing tests/run.py quick/00.hello/mips/linux/simple-timing +Exiting @ tick 8579 because target called exit() diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-atomic/config.ini b/tests/quick/00.hello/ref/sparc/linux/simple-atomic/config.ini index 082415a7f..21028fa63 100644 --- a/tests/quick/00.hello/ref/sparc/linux/simple-atomic/config.ini +++ b/tests/quick/00.hello/ref/sparc/linux/simple-atomic/config.ini @@ -56,6 +56,7 @@ physmem=system.physmem type=AtomicSimpleCPU children=workload clock=1 +cpu_id=0 defer_registration=false function_trace=false function_trace_start=0 @@ -64,6 +65,7 @@ max_insts_any_thread=0 max_loads_all_threads=0 max_loads_any_thread=0 mem=system.physmem +progress_interval=0 simulate_stalls=false system=system width=1 @@ -74,11 +76,17 @@ icache_port=system.membus.port[1] [system.cpu.workload] type=LiveProcess cmd=hello +egid=100 env= +euid=100 executable=tests/test-progs/hello/bin/sparc/linux/hello +gid=100 input=cin output=cout +pid=100 +ppid=99 system=system +uid=100 [system.membus] type=Bus @@ -94,6 +102,7 @@ port=system.membus.port[0] [trace] bufsize=0 +cycle=0 dump_on_exit=false file=cout flags= diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-atomic/config.out b/tests/quick/00.hello/ref/sparc/linux/simple-atomic/config.out index 45412a511..f5be4e3bd 100644 --- a/tests/quick/00.hello/ref/sparc/linux/simple-atomic/config.out +++ b/tests/quick/00.hello/ref/sparc/linux/simple-atomic/config.out @@ -28,6 +28,12 @@ input=cin output=cout env= system=system +uid=100 +euid=100 +gid=100 +egid=100 +pid=100 +ppid=99 [system.cpu] type=AtomicSimpleCPU @@ -35,8 +41,10 @@ max_insts_any_thread=0 max_insts_all_threads=0 max_loads_any_thread=0 max_loads_all_threads=0 +progress_interval=0 mem=system.physmem system=system +cpu_id=0 workload=system.cpu.workload clock=1 defer_registration=false @@ -48,6 +56,7 @@ simulate_stalls=false [trace] flags= start=0 +cycle=0 bufsize=0 file=cout dump_on_exit=false @@ -91,3 +100,6 @@ trace_system=client [debug] break_cycles= +[statsreset] +reset_cycle=0 + diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-atomic/m5stats.txt b/tests/quick/00.hello/ref/sparc/linux/simple-atomic/m5stats.txt index 9bfb2fec9..e87e77b8f 100644 --- a/tests/quick/00.hello/ref/sparc/linux/simple-atomic/m5stats.txt +++ b/tests/quick/00.hello/ref/sparc/linux/simple-atomic/m5stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 61348 # Simulator instruction rate (inst/s) -host_mem_usage 147288 # Number of bytes of host memory used -host_seconds 0.07 # Real time elapsed on the host -host_tick_rate 60991 # Simulator tick rate (ticks/s) +host_inst_rate 2175 # Simulator instruction rate (inst/s) +host_mem_usage 147292 # Number of bytes of host memory used +host_seconds 2.06 # Real time elapsed on the host +host_tick_rate 2174 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 4483 # Number of instructions simulated sim_seconds 0.000000 # Number of seconds simulated diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-atomic/stdout b/tests/quick/00.hello/ref/sparc/linux/simple-atomic/stdout index 38eb82c8b..c9df3a17c 100644 --- a/tests/quick/00.hello/ref/sparc/linux/simple-atomic/stdout +++ b/tests/quick/00.hello/ref/sparc/linux/simple-atomic/stdout @@ -5,8 +5,8 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Sep 5 2006 15:39:50 -M5 started Tue Sep 5 15:49:24 2006 +M5 compiled Oct 8 2006 14:19:59 +M5 started Sun Oct 8 14:20:03 2006 M5 executing on zizzer.eecs.umich.edu command line: build/SPARC_SE/m5.opt -d build/SPARC_SE/tests/opt/quick/00.hello/sparc/linux/simple-atomic tests/run.py quick/00.hello/sparc/linux/simple-atomic Exiting @ tick 4482 because target called exit() |