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-rw-r--r--tests/quick/00.hello/ref/alpha/linux/o3-timing/config.ini6
-rw-r--r--tests/quick/00.hello/ref/alpha/linux/o3-timing/m5stats.txt482
-rw-r--r--tests/quick/00.hello/ref/alpha/linux/o3-timing/stdout8
-rw-r--r--tests/quick/00.hello/ref/alpha/linux/simple-timing/config.ini6
-rw-r--r--tests/quick/00.hello/ref/alpha/linux/simple-timing/m5stats.txt96
-rw-r--r--tests/quick/00.hello/ref/alpha/linux/simple-timing/stdout8
-rw-r--r--tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.ini6
-rw-r--r--tests/quick/00.hello/ref/alpha/tru64/o3-timing/m5stats.txt432
-rw-r--r--tests/quick/00.hello/ref/alpha/tru64/o3-timing/stdout8
-rw-r--r--tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.ini6
-rw-r--r--tests/quick/00.hello/ref/alpha/tru64/simple-timing/m5stats.txt96
-rw-r--r--tests/quick/00.hello/ref/alpha/tru64/simple-timing/stdout8
-rw-r--r--tests/quick/00.hello/ref/mips/linux/simple-timing/config.ini6
-rw-r--r--tests/quick/00.hello/ref/mips/linux/simple-timing/m5stats.txt96
-rw-r--r--tests/quick/00.hello/ref/mips/linux/simple-timing/stdout8
-rw-r--r--tests/quick/00.hello/ref/sparc/linux/simple-timing/config.ini6
-rw-r--r--tests/quick/00.hello/ref/sparc/linux/simple-timing/m5stats.txt96
-rw-r--r--tests/quick/00.hello/ref/sparc/linux/simple-timing/stdout8
18 files changed, 709 insertions, 673 deletions
diff --git a/tests/quick/00.hello/ref/alpha/linux/o3-timing/config.ini b/tests/quick/00.hello/ref/alpha/linux/o3-timing/config.ini
index f145eee43..1a19512dc 100644
--- a/tests/quick/00.hello/ref/alpha/linux/o3-timing/config.ini
+++ b/tests/quick/00.hello/ref/alpha/linux/o3-timing/config.ini
@@ -99,10 +99,12 @@ type=BaseCache
addr_range=0:18446744073709551615
assoc=2
block_size=64
+cpu_side_filter_ranges=
hash_delay=1
latency=1000
lifo=false
max_miss_count=0
+mem_side_filter_ranges=
mshrs=10
prefetch_access=false
prefetch_cache_check_push=true
@@ -270,10 +272,12 @@ type=BaseCache
addr_range=0:18446744073709551615
assoc=2
block_size=64
+cpu_side_filter_ranges=
hash_delay=1
latency=1000
lifo=false
max_miss_count=0
+mem_side_filter_ranges=
mshrs=10
prefetch_access=false
prefetch_cache_check_push=true
@@ -304,10 +308,12 @@ type=BaseCache
addr_range=0:18446744073709551615
assoc=2
block_size=64
+cpu_side_filter_ranges=
hash_delay=1
latency=1000
lifo=false
max_miss_count=0
+mem_side_filter_ranges=
mshrs=10
prefetch_access=false
prefetch_cache_check_push=true
diff --git a/tests/quick/00.hello/ref/alpha/linux/o3-timing/m5stats.txt b/tests/quick/00.hello/ref/alpha/linux/o3-timing/m5stats.txt
index 02095a557..35d6ad747 100644
--- a/tests/quick/00.hello/ref/alpha/linux/o3-timing/m5stats.txt
+++ b/tests/quick/00.hello/ref/alpha/linux/o3-timing/m5stats.txt
@@ -1,40 +1,40 @@
---------- Begin Simulation Statistics ----------
global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-global.BPredUnit.BTBHits 543 # Number of BTB hits
-global.BPredUnit.BTBLookups 1720 # Number of BTB lookups
-global.BPredUnit.RASInCorrect 59 # Number of incorrect RAS predictions.
-global.BPredUnit.condIncorrect 423 # Number of conditional branches incorrect
-global.BPredUnit.condPredicted 1175 # Number of conditional branches predicted
-global.BPredUnit.lookups 2025 # Number of BP lookups
-global.BPredUnit.usedRAS 277 # Number of times the RAS was used to get a target.
-host_inst_rate 29843 # Simulator instruction rate (inst/s)
-host_mem_usage 154572 # Number of bytes of host memory used
-host_seconds 0.19 # Real time elapsed on the host
-host_tick_rate 22095832 # Simulator tick rate (ticks/s)
-memdepunit.memDep.conflictingLoads 31 # Number of conflicting loads.
-memdepunit.memDep.conflictingStores 133 # Number of conflicting stores.
-memdepunit.memDep.insertedLoads 1967 # Number of loads inserted to the mem dependence unit.
-memdepunit.memDep.insertedStores 1200 # Number of stores inserted to the mem dependence unit.
+global.BPredUnit.BTBHits 538 # Number of BTB hits
+global.BPredUnit.BTBLookups 1681 # Number of BTB lookups
+global.BPredUnit.RASInCorrect 51 # Number of incorrect RAS predictions.
+global.BPredUnit.condIncorrect 412 # Number of conditional branches incorrect
+global.BPredUnit.condPredicted 1149 # Number of conditional branches predicted
+global.BPredUnit.lookups 1984 # Number of BP lookups
+global.BPredUnit.usedRAS 275 # Number of times the RAS was used to get a target.
+host_inst_rate 62494 # Simulator instruction rate (inst/s)
+host_mem_usage 196896 # Number of bytes of host memory used
+host_seconds 0.09 # Real time elapsed on the host
+host_tick_rate 50069310 # Simulator tick rate (ticks/s)
+memdepunit.memDep.conflictingLoads 10 # Number of conflicting loads.
+memdepunit.memDep.conflictingStores 121 # Number of conflicting stores.
+memdepunit.memDep.insertedLoads 1979 # Number of loads inserted to the mem dependence unit.
+memdepunit.memDep.insertedStores 1190 # Number of stores inserted to the mem dependence unit.
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 5623 # Number of instructions simulated
-sim_seconds 0.000004 # Number of seconds simulated
-sim_ticks 4170500 # Number of ticks simulated
+sim_seconds 0.000005 # Number of seconds simulated
+sim_ticks 4515000 # Number of ticks simulated
system.cpu.commit.COM:branches 862 # Number of branches committed
-system.cpu.commit.COM:bw_lim_events 105 # number cycles where commit BW limit reached
+system.cpu.commit.COM:bw_lim_events 81 # number cycles where commit BW limit reached
system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle.samples 7614
+system.cpu.commit.COM:committed_per_cycle.samples 8177
system.cpu.commit.COM:committed_per_cycle.min_value 0
- 0 5315 6980.56%
- 1 1182 1552.40%
- 2 399 524.03%
- 3 192 252.17%
- 4 125 164.17%
- 5 99 130.02%
- 6 130 170.74%
- 7 67 88.00%
- 8 105 137.90%
+ 0 5854 7159.10%
+ 1 1205 1473.65%
+ 2 403 492.85%
+ 3 188 229.91%
+ 4 133 162.65%
+ 5 98 119.85%
+ 6 110 134.52%
+ 7 105 128.41%
+ 8 81 99.06%
system.cpu.commit.COM:committed_per_cycle.max_value 8
system.cpu.commit.COM:committed_per_cycle.end_dist
@@ -43,70 +43,70 @@ system.cpu.commit.COM:loads 979 # Nu
system.cpu.commit.COM:membars 0 # Number of memory barriers committed
system.cpu.commit.COM:refs 1791 # Number of memory references committed
system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed
-system.cpu.commit.branchMispredicts 349 # The number of times a branch was mispredicted
+system.cpu.commit.branchMispredicts 339 # The number of times a branch was mispredicted
system.cpu.commit.commitCommittedInsts 5640 # The number of committed instructions
system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.commitSquashedInsts 3957 # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts 4015 # The number of squashed insts skipped by commit
system.cpu.committedInsts 5623 # Number of Instructions Simulated
system.cpu.committedInsts_total 5623 # Number of Instructions Simulated
-system.cpu.cpi 1.483372 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 1.483372 # CPI: Total CPI of All Threads
-system.cpu.dcache.ReadReq_accesses 1487 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency 8188.118812 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 5495.049505 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_hits 1386 # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency 827000 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_rate 0.067922 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_misses 101 # number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_hits 34 # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_miss_latency 555000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate 0.067922 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_misses 101 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_accesses 561 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency 18316.091954 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 5068.965517 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_hits 474 # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency 1593500 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_rate 0.155080 # miss rate for WriteReq accesses
+system.cpu.cpi 1.584030 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 1.584030 # CPI: Total CPI of All Threads
+system.cpu.dcache.ReadReq_accesses 1516 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_avg_miss_latency 10550 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 6350 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_hits 1416 # number of ReadReq hits
+system.cpu.dcache.ReadReq_miss_latency 1055000 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_rate 0.065963 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_misses 100 # number of ReadReq misses
+system.cpu.dcache.ReadReq_mshr_hits 32 # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_miss_latency 635000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate 0.065963 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_misses 100 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_accesses 533 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_avg_miss_latency 26660.919540 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 5781.609195 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_hits 446 # number of WriteReq hits
+system.cpu.dcache.WriteReq_miss_latency 2319500 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_rate 0.163227 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_misses 87 # number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_hits 251 # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_miss_latency 441000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_rate 0.155080 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_hits 279 # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_miss_latency 503000 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_rate 0.163227 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_misses 87 # number of WriteReq MSHR misses
system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
-system.cpu.dcache.avg_refs 10.770115 # Average number of references to valid blocks.
+system.cpu.dcache.avg_refs 10.843931 # Average number of references to valid blocks.
system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.demand_accesses 2048 # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency 12875 # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 5297.872340 # average overall mshr miss latency
-system.cpu.dcache.demand_hits 1860 # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency 2420500 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_rate 0.091797 # miss rate for demand accesses
-system.cpu.dcache.demand_misses 188 # number of demand (read+write) misses
-system.cpu.dcache.demand_mshr_hits 285 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency 996000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_rate 0.091797 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_misses 188 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_accesses 2049 # number of demand (read+write) accesses
+system.cpu.dcache.demand_avg_miss_latency 18045.454545 # average overall miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 6085.561497 # average overall mshr miss latency
+system.cpu.dcache.demand_hits 1862 # number of demand (read+write) hits
+system.cpu.dcache.demand_miss_latency 3374500 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_rate 0.091264 # miss rate for demand accesses
+system.cpu.dcache.demand_misses 187 # number of demand (read+write) misses
+system.cpu.dcache.demand_mshr_hits 311 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_miss_latency 1138000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_rate 0.091264 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_misses 187 # number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.overall_accesses 2048 # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency 12875 # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 5297.872340 # average overall mshr miss latency
+system.cpu.dcache.overall_accesses 2049 # number of overall (read+write) accesses
+system.cpu.dcache.overall_avg_miss_latency 18045.454545 # average overall miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 6085.561497 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits 1860 # number of overall hits
-system.cpu.dcache.overall_miss_latency 2420500 # number of overall miss cycles
-system.cpu.dcache.overall_miss_rate 0.091797 # miss rate for overall accesses
-system.cpu.dcache.overall_misses 188 # number of overall misses
-system.cpu.dcache.overall_mshr_hits 285 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency 996000 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_rate 0.091797 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_misses 188 # number of overall MSHR misses
+system.cpu.dcache.overall_hits 1862 # number of overall hits
+system.cpu.dcache.overall_miss_latency 3374500 # number of overall miss cycles
+system.cpu.dcache.overall_miss_rate 0.091264 # miss rate for overall accesses
+system.cpu.dcache.overall_misses 187 # number of overall misses
+system.cpu.dcache.overall_mshr_hits 311 # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_miss_latency 1138000 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_rate 0.091264 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_misses 187 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
@@ -119,90 +119,90 @@ system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0
system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
system.cpu.dcache.replacements 0 # number of replacements
-system.cpu.dcache.sampled_refs 174 # Sample count of references to valid blocks.
+system.cpu.dcache.sampled_refs 173 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse 112.600183 # Cycle average of tags in use
-system.cpu.dcache.total_refs 1874 # Total number of references to valid blocks.
+system.cpu.dcache.tagsinuse 111.683956 # Cycle average of tags in use
+system.cpu.dcache.total_refs 1876 # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 0 # number of writebacks
-system.cpu.decode.DECODE:BlockedCycles 391 # Number of cycles decode is blocked
-system.cpu.decode.DECODE:BranchMispred 82 # Number of times decode detected a branch misprediction
+system.cpu.decode.DECODE:BlockedCycles 428 # Number of cycles decode is blocked
+system.cpu.decode.DECODE:BranchMispred 81 # Number of times decode detected a branch misprediction
system.cpu.decode.DECODE:BranchResolved 164 # Number of times decode resolved a branch
-system.cpu.decode.DECODE:DecodedInsts 11387 # Number of instructions handled by decode
-system.cpu.decode.DECODE:IdleCycles 5174 # Number of cycles decode is idle
-system.cpu.decode.DECODE:RunCycles 2002 # Number of cycles decode is running
-system.cpu.decode.DECODE:SquashCycles 726 # Number of cycles decode is squashing
-system.cpu.decode.DECODE:SquashedInsts 244 # Number of squashed instructions handled by decode
-system.cpu.decode.DECODE:UnblockCycles 48 # Number of cycles decode is unblocking
-system.cpu.fetch.Branches 2025 # Number of branches that fetch encountered
-system.cpu.fetch.CacheLines 1529 # Number of cache lines fetched
-system.cpu.fetch.Cycles 3690 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.IcacheSquashes 212 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.Insts 12463 # Number of instructions fetch has processed
-system.cpu.fetch.SquashCycles 457 # Number of cycles fetch has spent squashing
-system.cpu.fetch.branchRate 0.242777 # Number of branch fetches per cycle
-system.cpu.fetch.icacheStallCycles 1529 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.predictedBranches 820 # Number of branches that fetch has predicted taken
-system.cpu.fetch.rate 1.494185 # Number of inst fetches per cycle
+system.cpu.decode.DECODE:DecodedInsts 11204 # Number of instructions handled by decode
+system.cpu.decode.DECODE:IdleCycles 5725 # Number of cycles decode is idle
+system.cpu.decode.DECODE:RunCycles 1989 # Number of cycles decode is running
+system.cpu.decode.DECODE:SquashCycles 729 # Number of cycles decode is squashing
+system.cpu.decode.DECODE:SquashedInsts 235 # Number of squashed instructions handled by decode
+system.cpu.decode.DECODE:UnblockCycles 36 # Number of cycles decode is unblocking
+system.cpu.fetch.Branches 1984 # Number of branches that fetch encountered
+system.cpu.fetch.CacheLines 1520 # Number of cache lines fetched
+system.cpu.fetch.Cycles 3641 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.IcacheSquashes 230 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.Insts 12195 # Number of instructions fetch has processed
+system.cpu.fetch.SquashCycles 444 # Number of cycles fetch has spent squashing
+system.cpu.fetch.branchRate 0.222746 # Number of branch fetches per cycle
+system.cpu.fetch.icacheStallCycles 1520 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.predictedBranches 813 # Number of branches that fetch has predicted taken
+system.cpu.fetch.rate 1.369148 # Number of inst fetches per cycle
system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist.samples 8341
+system.cpu.fetch.rateDist.samples 8907
system.cpu.fetch.rateDist.min_value 0
- 0 6181 7410.38%
- 1 173 207.41%
- 2 174 208.61%
- 3 151 181.03%
- 4 219 262.56%
- 5 157 188.23%
- 6 179 214.60%
- 7 102 122.29%
- 8 1005 1204.89%
+ 0 6787 7619.85%
+ 1 178 199.84%
+ 2 167 187.49%
+ 3 149 167.28%
+ 4 210 235.77%
+ 5 157 176.27%
+ 6 180 202.09%
+ 7 101 113.39%
+ 8 978 1098.01%
system.cpu.fetch.rateDist.max_value 8
system.cpu.fetch.rateDist.end_dist
-system.cpu.icache.ReadReq_accesses 1511 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_avg_miss_latency 5621.019108 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 4464.968153 # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_hits 1197 # number of ReadReq hits
-system.cpu.icache.ReadReq_miss_latency 1765000 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_rate 0.207809 # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_accesses 1497 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_avg_miss_latency 7812.101911 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 5500 # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_hits 1183 # number of ReadReq hits
+system.cpu.icache.ReadReq_miss_latency 2453000 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_rate 0.209753 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_misses 314 # number of ReadReq misses
-system.cpu.icache.ReadReq_mshr_hits 18 # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_miss_latency 1402000 # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate 0.207809 # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_hits 23 # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_miss_latency 1727000 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate 0.209753 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_misses 314 # number of ReadReq MSHR misses
system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
-system.cpu.icache.avg_refs 3.812102 # Average number of references to valid blocks.
+system.cpu.icache.avg_refs 3.767516 # Average number of references to valid blocks.
system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.demand_accesses 1511 # number of demand (read+write) accesses
-system.cpu.icache.demand_avg_miss_latency 5621.019108 # average overall miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 4464.968153 # average overall mshr miss latency
-system.cpu.icache.demand_hits 1197 # number of demand (read+write) hits
-system.cpu.icache.demand_miss_latency 1765000 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_rate 0.207809 # miss rate for demand accesses
+system.cpu.icache.demand_accesses 1497 # number of demand (read+write) accesses
+system.cpu.icache.demand_avg_miss_latency 7812.101911 # average overall miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 5500 # average overall mshr miss latency
+system.cpu.icache.demand_hits 1183 # number of demand (read+write) hits
+system.cpu.icache.demand_miss_latency 2453000 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_rate 0.209753 # miss rate for demand accesses
system.cpu.icache.demand_misses 314 # number of demand (read+write) misses
-system.cpu.icache.demand_mshr_hits 18 # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_miss_latency 1402000 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_rate 0.207809 # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_hits 23 # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_miss_latency 1727000 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_rate 0.209753 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_misses 314 # number of demand (read+write) MSHR misses
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.icache.overall_accesses 1511 # number of overall (read+write) accesses
-system.cpu.icache.overall_avg_miss_latency 5621.019108 # average overall miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 4464.968153 # average overall mshr miss latency
+system.cpu.icache.overall_accesses 1497 # number of overall (read+write) accesses
+system.cpu.icache.overall_avg_miss_latency 7812.101911 # average overall miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 5500 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
-system.cpu.icache.overall_hits 1197 # number of overall hits
-system.cpu.icache.overall_miss_latency 1765000 # number of overall miss cycles
-system.cpu.icache.overall_miss_rate 0.207809 # miss rate for overall accesses
+system.cpu.icache.overall_hits 1183 # number of overall hits
+system.cpu.icache.overall_miss_latency 2453000 # number of overall miss cycles
+system.cpu.icache.overall_miss_rate 0.209753 # miss rate for overall accesses
system.cpu.icache.overall_misses 314 # number of overall misses
-system.cpu.icache.overall_mshr_hits 18 # number of overall MSHR hits
-system.cpu.icache.overall_mshr_miss_latency 1402000 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_rate 0.207809 # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_hits 23 # number of overall MSHR hits
+system.cpu.icache.overall_mshr_miss_latency 1727000 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_rate 0.209753 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_misses 314 # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
@@ -218,59 +218,59 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0
system.cpu.icache.replacements 0 # number of replacements
system.cpu.icache.sampled_refs 314 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse 167.838424 # Cycle average of tags in use
-system.cpu.icache.total_refs 1197 # Total number of references to valid blocks.
+system.cpu.icache.tagsinuse 165.376334 # Cycle average of tags in use
+system.cpu.icache.total_refs 1183 # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks
-system.cpu.idleCycles 1997 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.iew.EXEC:branches 1159 # Number of branches executed
-system.cpu.iew.EXEC:nop 43 # number of nop insts executed
-system.cpu.iew.EXEC:rate 0.933581 # Inst execution rate
-system.cpu.iew.EXEC:refs 2561 # number of memory reference insts executed
-system.cpu.iew.EXEC:stores 971 # Number of stores executed
+system.cpu.idleCycles 88946 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.iew.EXEC:branches 1172 # Number of branches executed
+system.cpu.iew.EXEC:nop 45 # number of nop insts executed
+system.cpu.iew.EXEC:rate 0.880207 # Inst execution rate
+system.cpu.iew.EXEC:refs 2591 # number of memory reference insts executed
+system.cpu.iew.EXEC:stores 974 # Number of stores executed
system.cpu.iew.EXEC:swp 0 # number of swp insts executed
-system.cpu.iew.WB:consumers 5329 # num instructions consuming a value
-system.cpu.iew.WB:count 7480 # cumulative count of insts written-back
-system.cpu.iew.WB:fanout 0.739351 # average fanout of values written-back
+system.cpu.iew.WB:consumers 5292 # num instructions consuming a value
+system.cpu.iew.WB:count 7505 # cumulative count of insts written-back
+system.cpu.iew.WB:fanout 0.745276 # average fanout of values written-back
system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.iew.WB:producers 3940 # num instructions producing a value
-system.cpu.iew.WB:rate 0.896775 # insts written-back per cycle
-system.cpu.iew.WB:sent 7559 # cumulative count of insts sent to commit
-system.cpu.iew.branchMispredicts 402 # Number of branch mispredicts detected at execute
+system.cpu.iew.WB:producers 3944 # num instructions producing a value
+system.cpu.iew.WB:rate 0.842596 # insts written-back per cycle
+system.cpu.iew.WB:sent 7591 # cumulative count of insts sent to commit
+system.cpu.iew.branchMispredicts 401 # Number of branch mispredicts detected at execute
system.cpu.iew.iewBlockCycles 4 # Number of cycles IEW is blocking
-system.cpu.iew.iewDispLoadInsts 1967 # Number of dispatched load instructions
+system.cpu.iew.iewDispLoadInsts 1979 # Number of dispatched load instructions
system.cpu.iew.iewDispNonSpecInsts 23 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewDispSquashedInsts 240 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispStoreInsts 1200 # Number of dispatched store instructions
-system.cpu.iew.iewDispatchedInsts 9614 # Number of instructions dispatched to IQ
-system.cpu.iew.iewExecLoadInsts 1590 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 364 # Number of squashed instructions skipped in execute
-system.cpu.iew.iewExecutedInsts 7787 # Number of executed instructions
+system.cpu.iew.iewDispSquashedInsts 194 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispStoreInsts 1190 # Number of dispatched store instructions
+system.cpu.iew.iewDispatchedInsts 9672 # Number of instructions dispatched to IQ
+system.cpu.iew.iewExecLoadInsts 1617 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 358 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewExecutedInsts 7840 # Number of executed instructions
system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.iewSquashCycles 726 # Number of cycles IEW is squashing
+system.cpu.iew.iewSquashCycles 729 # Number of cycles IEW is squashing
system.cpu.iew.iewUnblockCycles 0 # Number of cycles IEW is unblocking
system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
-system.cpu.iew.lsq.thread.0.forwLoads 48 # Number of loads that had data forwarded from stores
+system.cpu.iew.lsq.thread.0.forwLoads 47 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread.0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
-system.cpu.iew.lsq.thread.0.memOrderViolation 70 # Number of memory ordering violations
+system.cpu.iew.lsq.thread.0.memOrderViolation 66 # Number of memory ordering violations
system.cpu.iew.lsq.thread.0.rescheduledLoads 1 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread.0.squashedLoads 988 # Number of loads squashed
-system.cpu.iew.lsq.thread.0.squashedStores 388 # Number of stores squashed
-system.cpu.iew.memOrderViolationEvents 70 # Number of memory order violations
-system.cpu.iew.predictedNotTakenIncorrect 287 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.predictedTakenIncorrect 115 # Number of branches that were predicted taken incorrectly
-system.cpu.ipc 0.674140 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 0.674140 # IPC: Total IPC of All Threads
-system.cpu.iq.ISSUE:FU_type_0 8151 # Type of FU issued
+system.cpu.iew.lsq.thread.0.squashedLoads 1000 # Number of loads squashed
+system.cpu.iew.lsq.thread.0.squashedStores 378 # Number of stores squashed
+system.cpu.iew.memOrderViolationEvents 66 # Number of memory order violations
+system.cpu.iew.predictedNotTakenIncorrect 294 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.predictedTakenIncorrect 107 # Number of branches that were predicted taken incorrectly
+system.cpu.ipc 0.631301 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 0.631301 # IPC: Total IPC of All Threads
+system.cpu.iq.ISSUE:FU_type_0 8198 # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0.start_dist
No_OpClass 2 0.02% # Type of FU issued
- IntAlu 5422 66.52% # Type of FU issued
+ IntAlu 5452 66.50% # Type of FU issued
IntMult 1 0.01% # Type of FU issued
IntDiv 0 0.00% # Type of FU issued
FloatAdd 2 0.02% # Type of FU issued
@@ -279,13 +279,13 @@ system.cpu.iq.ISSUE:FU_type_0.start_dist
FloatMult 0 0.00% # Type of FU issued
FloatDiv 0 0.00% # Type of FU issued
FloatSqrt 0 0.00% # Type of FU issued
- MemRead 1720 21.10% # Type of FU issued
- MemWrite 1004 12.32% # Type of FU issued
+ MemRead 1744 21.27% # Type of FU issued
+ MemWrite 997 12.16% # Type of FU issued
IprAccess 0 0.00% # Type of FU issued
InstPrefetch 0 0.00% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0.end_dist
-system.cpu.iq.ISSUE:fu_busy_cnt 104 # FU busy when requested
-system.cpu.iq.ISSUE:fu_busy_rate 0.012759 # FU busy rate (busy events/executed inst)
+system.cpu.iq.ISSUE:fu_busy_cnt 102 # FU busy when requested
+system.cpu.iq.ISSUE:fu_busy_rate 0.012442 # FU busy rate (busy events/executed inst)
system.cpu.iq.ISSUE:fu_full.start_dist
No_OpClass 0 0.00% # attempts to use FU when none available
IntAlu 0 0.00% # attempts to use FU when none available
@@ -297,96 +297,96 @@ system.cpu.iq.ISSUE:fu_full.start_dist
FloatMult 0 0.00% # attempts to use FU when none available
FloatDiv 0 0.00% # attempts to use FU when none available
FloatSqrt 0 0.00% # attempts to use FU when none available
- MemRead 70 67.31% # attempts to use FU when none available
- MemWrite 34 32.69% # attempts to use FU when none available
+ MemRead 67 65.69% # attempts to use FU when none available
+ MemWrite 35 34.31% # attempts to use FU when none available
IprAccess 0 0.00% # attempts to use FU when none available
InstPrefetch 0 0.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full.end_dist
system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle.samples 8341
+system.cpu.iq.ISSUE:issued_per_cycle.samples 8907
system.cpu.iq.ISSUE:issued_per_cycle.min_value 0
- 0 5104 6119.17%
- 1 1084 1299.60%
- 2 829 993.89%
- 3 533 639.01%
- 4 366 438.80%
- 5 258 309.32%
- 6 126 151.06%
- 7 28 33.57%
- 8 13 15.59%
+ 0 5630 6320.87%
+ 1 1096 1230.49%
+ 2 792 889.19%
+ 3 582 653.42%
+ 4 464 520.94%
+ 5 200 224.54%
+ 6 99 111.15%
+ 7 30 33.68%
+ 8 14 15.72%
system.cpu.iq.ISSUE:issued_per_cycle.max_value 8
system.cpu.iq.ISSUE:issued_per_cycle.end_dist
-system.cpu.iq.ISSUE:rate 0.977221 # Inst issue rate
-system.cpu.iq.iqInstsAdded 9548 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqInstsIssued 8151 # Number of instructions issued
+system.cpu.iq.ISSUE:rate 0.920400 # Inst issue rate
+system.cpu.iq.iqInstsAdded 9604 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqInstsIssued 8198 # Number of instructions issued
system.cpu.iq.iqNonSpecInstsAdded 23 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqSquashedInstsExamined 3578 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedInstsExamined 3664 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedInstsIssued 22 # Number of squashed instructions issued
system.cpu.iq.iqSquashedNonSpecRemoved 6 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.iqSquashedOperandsExamined 2360 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedOperandsExamined 2365 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.l2cache.ReadExReq_accesses 73 # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_avg_miss_latency 3643.835616 # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 2643.835616 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_miss_latency 266000 # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_avg_miss_latency 4486.301370 # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 2486.301370 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_miss_latency 327500 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_misses 73 # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency 193000 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency 181500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_misses 73 # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadReq_accesses 415 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_avg_miss_latency 3406.779661 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2406.779661 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_accesses 414 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_avg_miss_latency 4450.242718 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2450.242718 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_hits 2 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_miss_latency 1407000 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_rate 0.995181 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_misses 413 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency 994000 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate 0.995181 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_misses 413 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_miss_latency 1833500 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_rate 0.995169 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_misses 412 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency 1009500 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate 0.995169 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_misses 412 # number of ReadReq MSHR misses
system.cpu.l2cache.UpgradeReq_accesses 14 # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_avg_miss_latency 3392.857143 # average UpgradeReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 2392.857143 # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_miss_latency 47500 # number of UpgradeReq miss cycles
+system.cpu.l2cache.UpgradeReq_avg_miss_latency 4214.285714 # average UpgradeReq miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 2214.285714 # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_miss_latency 59000 # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_misses 14 # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency 33500 # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency 31000 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_misses 14 # number of UpgradeReq MSHR misses
system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
-system.cpu.l2cache.avg_refs 0.005013 # Average number of references to valid blocks.
+system.cpu.l2cache.avg_refs 0.005025 # Average number of references to valid blocks.
system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
-system.cpu.l2cache.demand_accesses 488 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_avg_miss_latency 3442.386831 # average overall miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency 2442.386831 # average overall mshr miss latency
+system.cpu.l2cache.demand_accesses 487 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_avg_miss_latency 4455.670103 # average overall miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency 2455.670103 # average overall mshr miss latency
system.cpu.l2cache.demand_hits 2 # number of demand (read+write) hits
-system.cpu.l2cache.demand_miss_latency 1673000 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_rate 0.995902 # miss rate for demand accesses
-system.cpu.l2cache.demand_misses 486 # number of demand (read+write) misses
+system.cpu.l2cache.demand_miss_latency 2161000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_rate 0.995893 # miss rate for demand accesses
+system.cpu.l2cache.demand_misses 485 # number of demand (read+write) misses
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_miss_latency 1187000 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_rate 0.995902 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_misses 486 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_miss_latency 1191000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_rate 0.995893 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_misses 485 # number of demand (read+write) MSHR misses
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.l2cache.overall_accesses 488 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_avg_miss_latency 3442.386831 # average overall miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency 2442.386831 # average overall mshr miss latency
+system.cpu.l2cache.overall_accesses 487 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_avg_miss_latency 4455.670103 # average overall miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency 2455.670103 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.cpu.l2cache.overall_hits 2 # number of overall hits
-system.cpu.l2cache.overall_miss_latency 1673000 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_rate 0.995902 # miss rate for overall accesses
-system.cpu.l2cache.overall_misses 486 # number of overall misses
+system.cpu.l2cache.overall_miss_latency 2161000 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_rate 0.995893 # miss rate for overall accesses
+system.cpu.l2cache.overall_misses 485 # number of overall misses
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_miss_latency 1187000 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_rate 0.995902 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_misses 486 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_miss_latency 1191000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_rate 0.995893 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_misses 485 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
@@ -399,29 +399,29 @@ system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0
system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
system.cpu.l2cache.replacements 0 # number of replacements
-system.cpu.l2cache.sampled_refs 399 # Sample count of references to valid blocks.
+system.cpu.l2cache.sampled_refs 398 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse 223.758944 # Cycle average of tags in use
+system.cpu.l2cache.tagsinuse 221.319862 # Cycle average of tags in use
system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.writebacks 0 # number of writebacks
-system.cpu.numCycles 8341 # number of cpu cycles simulated
-system.cpu.rename.RENAME:BlockCycles 14 # Number of cycles rename is blocking
+system.cpu.numCycles 8907 # number of cpu cycles simulated
+system.cpu.rename.RENAME:BlockCycles 50 # Number of cycles rename is blocking
system.cpu.rename.RENAME:CommittedMaps 4051 # Number of HB maps that are committed
-system.cpu.rename.RENAME:IdleCycles 5339 # Number of cycles rename is idle
+system.cpu.rename.RENAME:IdleCycles 5884 # Number of cycles rename is idle
system.cpu.rename.RENAME:LSQFullEvents 71 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RENAME:RenameLookups 13891 # Number of register rename lookups that rename has made
-system.cpu.rename.RENAME:RenamedInsts 10852 # Number of instructions processed by rename
-system.cpu.rename.RENAME:RenamedOperands 8114 # Number of destination operands rename has renamed
-system.cpu.rename.RENAME:RunCycles 1888 # Number of cycles rename is running
-system.cpu.rename.RENAME:SquashCycles 726 # Number of cycles rename is squashing
-system.cpu.rename.RENAME:UnblockCycles 102 # Number of cycles rename is unblocking
-system.cpu.rename.RENAME:UndoneMaps 4063 # Number of HB maps that are undone due to squashing
-system.cpu.rename.RENAME:serializeStallCycles 272 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RENAME:RenameLookups 13715 # Number of register rename lookups that rename has made
+system.cpu.rename.RENAME:RenamedInsts 10735 # Number of instructions processed by rename
+system.cpu.rename.RENAME:RenamedOperands 8030 # Number of destination operands rename has renamed
+system.cpu.rename.RENAME:RunCycles 1846 # Number of cycles rename is running
+system.cpu.rename.RENAME:SquashCycles 729 # Number of cycles rename is squashing
+system.cpu.rename.RENAME:UnblockCycles 122 # Number of cycles rename is unblocking
+system.cpu.rename.RENAME:UndoneMaps 3979 # Number of HB maps that are undone due to squashing
+system.cpu.rename.RENAME:serializeStallCycles 276 # count of cycles rename stalled for serializing inst
system.cpu.rename.RENAME:serializingInsts 26 # count of serializing insts renamed
-system.cpu.rename.RENAME:skidInsts 382 # count of insts added to the skid buffer
-system.cpu.rename.RENAME:tempSerializingInsts 21 # count of temporary serializing insts renamed
-system.cpu.timesIdled 3 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.rename.RENAME:skidInsts 532 # count of insts added to the skid buffer
+system.cpu.rename.RENAME:tempSerializingInsts 20 # count of temporary serializing insts renamed
+system.cpu.timesIdled 54 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.workload.PROG:num_syscalls 17 # Number of system calls
---------- End Simulation Statistics ----------
diff --git a/tests/quick/00.hello/ref/alpha/linux/o3-timing/stdout b/tests/quick/00.hello/ref/alpha/linux/o3-timing/stdout
index 22c3e0435..fe297b10e 100644
--- a/tests/quick/00.hello/ref/alpha/linux/o3-timing/stdout
+++ b/tests/quick/00.hello/ref/alpha/linux/o3-timing/stdout
@@ -6,9 +6,9 @@ The Regents of The University of Michigan
All Rights Reserved
-M5 compiled Aug 3 2007 03:56:47
-M5 started Fri Aug 3 04:17:12 2007
-M5 executing on zizzer.eecs.umich.edu
+M5 compiled Aug 12 2007 00:26:55
+M5 started Sun Aug 12 00:29:40 2007
+M5 executing on zeep
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/o3-timing tests/run.py quick/00.hello/alpha/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
-Exiting @ tick 4170500 because target called exit()
+Exiting @ tick 4515000 because target called exit()
diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing/config.ini b/tests/quick/00.hello/ref/alpha/linux/simple-timing/config.ini
index 5ae318852..c95e2e383 100644
--- a/tests/quick/00.hello/ref/alpha/linux/simple-timing/config.ini
+++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing/config.ini
@@ -34,10 +34,12 @@ type=BaseCache
addr_range=0:18446744073709551615
assoc=2
block_size=64
+cpu_side_filter_ranges=
hash_delay=1
latency=1000
lifo=false
max_miss_count=0
+mem_side_filter_ranges=
mshrs=10
prefetch_access=false
prefetch_cache_check_push=true
@@ -68,10 +70,12 @@ type=BaseCache
addr_range=0:18446744073709551615
assoc=2
block_size=64
+cpu_side_filter_ranges=
hash_delay=1
latency=1000
lifo=false
max_miss_count=0
+mem_side_filter_ranges=
mshrs=10
prefetch_access=false
prefetch_cache_check_push=true
@@ -102,10 +106,12 @@ type=BaseCache
addr_range=0:18446744073709551615
assoc=2
block_size=64
+cpu_side_filter_ranges=
hash_delay=1
latency=10000
lifo=false
max_miss_count=0
+mem_side_filter_ranges=
mshrs=10
prefetch_access=false
prefetch_cache_check_push=true
diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing/m5stats.txt b/tests/quick/00.hello/ref/alpha/linux/simple-timing/m5stats.txt
index db7224c2e..3c7a26090 100644
--- a/tests/quick/00.hello/ref/alpha/linux/simple-timing/m5stats.txt
+++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing/m5stats.txt
@@ -1,31 +1,31 @@
---------- Begin Simulation Statistics ----------
-host_inst_rate 65923 # Simulator instruction rate (inst/s)
-host_mem_usage 154180 # Number of bytes of host memory used
-host_seconds 0.09 # Real time elapsed on the host
-host_tick_rate 155349854 # Simulator tick rate (ticks/s)
+host_inst_rate 334797 # Simulator instruction rate (inst/s)
+host_mem_usage 196348 # Number of bytes of host memory used
+host_seconds 0.02 # Real time elapsed on the host
+host_tick_rate 1064082508 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 5642 # Number of instructions simulated
-sim_seconds 0.000013 # Number of seconds simulated
-sim_ticks 13359000 # Number of ticks simulated
+sim_seconds 0.000018 # Number of seconds simulated
+sim_ticks 18365000 # Number of ticks simulated
system.cpu.dcache.ReadReq_accesses 979 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency 14000 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 13000 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency 25000 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 23000 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_hits 887 # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency 1288000 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency 2300000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_rate 0.093973 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_misses 92 # number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_miss_latency 1196000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency 2116000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate 0.093973 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_misses 92 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_accesses 812 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency 14000 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 13000 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency 25000 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 23000 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_hits 725 # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency 1218000 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency 2175000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_rate 0.107143 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_misses 87 # number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_miss_latency 1131000 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency 2001000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_rate 0.107143 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_misses 87 # number of WriteReq MSHR misses
system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
@@ -37,29 +37,29 @@ system.cpu.dcache.blocked_cycles_no_mshrs 0 # n
system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.demand_accesses 1791 # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency 14000 # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 13000 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_miss_latency 25000 # average overall miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 23000 # average overall mshr miss latency
system.cpu.dcache.demand_hits 1612 # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency 2506000 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency 4475000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_rate 0.099944 # miss rate for demand accesses
system.cpu.dcache.demand_misses 179 # number of demand (read+write) misses
system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency 2327000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency 4117000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_rate 0.099944 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_misses 179 # number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.overall_accesses 1791 # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency 14000 # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 13000 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_miss_latency 25000 # average overall miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 23000 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.cpu.dcache.overall_hits 1612 # number of overall hits
-system.cpu.dcache.overall_miss_latency 2506000 # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency 4475000 # number of overall miss cycles
system.cpu.dcache.overall_miss_rate 0.099944 # miss rate for overall accesses
system.cpu.dcache.overall_misses 179 # number of overall misses
system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency 2327000 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency 4117000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_rate 0.099944 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_misses 179 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
@@ -76,18 +76,18 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0
system.cpu.dcache.replacements 0 # number of replacements
system.cpu.dcache.sampled_refs 165 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse 103.895955 # Cycle average of tags in use
+system.cpu.dcache.tagsinuse 102.396682 # Cycle average of tags in use
system.cpu.dcache.total_refs 1626 # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 0 # number of writebacks
system.cpu.icache.ReadReq_accesses 5643 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_avg_miss_latency 13992.779783 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 12992.779783 # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_miss_latency 24956.678700 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 22956.678700 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_hits 5366 # number of ReadReq hits
-system.cpu.icache.ReadReq_miss_latency 3876000 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency 6913000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_rate 0.049087 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_misses 277 # number of ReadReq misses
-system.cpu.icache.ReadReq_mshr_miss_latency 3599000 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency 6359000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate 0.049087 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_misses 277 # number of ReadReq MSHR misses
system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
@@ -99,29 +99,29 @@ system.cpu.icache.blocked_cycles_no_mshrs 0 # n
system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.demand_accesses 5643 # number of demand (read+write) accesses
-system.cpu.icache.demand_avg_miss_latency 13992.779783 # average overall miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 12992.779783 # average overall mshr miss latency
+system.cpu.icache.demand_avg_miss_latency 24956.678700 # average overall miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 22956.678700 # average overall mshr miss latency
system.cpu.icache.demand_hits 5366 # number of demand (read+write) hits
-system.cpu.icache.demand_miss_latency 3876000 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency 6913000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_rate 0.049087 # miss rate for demand accesses
system.cpu.icache.demand_misses 277 # number of demand (read+write) misses
system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_miss_latency 3599000 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency 6359000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_rate 0.049087 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_misses 277 # number of demand (read+write) MSHR misses
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.icache.overall_accesses 5643 # number of overall (read+write) accesses
-system.cpu.icache.overall_avg_miss_latency 13992.779783 # average overall miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 12992.779783 # average overall mshr miss latency
+system.cpu.icache.overall_avg_miss_latency 24956.678700 # average overall miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 22956.678700 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.cpu.icache.overall_hits 5366 # number of overall hits
-system.cpu.icache.overall_miss_latency 3876000 # number of overall miss cycles
+system.cpu.icache.overall_miss_latency 6913000 # number of overall miss cycles
system.cpu.icache.overall_miss_rate 0.049087 # miss rate for overall accesses
system.cpu.icache.overall_misses 277 # number of overall misses
system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.icache.overall_mshr_miss_latency 3599000 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency 6359000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_rate 0.049087 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_misses 277 # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
@@ -138,34 +138,34 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0
system.cpu.icache.replacements 0 # number of replacements
system.cpu.icache.sampled_refs 277 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse 129.745202 # Cycle average of tags in use
+system.cpu.icache.tagsinuse 128.096333 # Cycle average of tags in use
system.cpu.icache.total_refs 5366 # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks
system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.l2cache.ReadExReq_accesses 73 # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_avg_miss_latency 12000 # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency 22000 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 11000 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_miss_latency 876000 # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency 1606000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_misses 73 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_mshr_miss_latency 803000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_misses 73 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadReq_accesses 369 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_avg_miss_latency 12000 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency 22000 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 11000 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_hits 1 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_miss_latency 4416000 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency 8096000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_rate 0.997290 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_misses 368 # number of ReadReq misses
system.cpu.l2cache.ReadReq_mshr_miss_latency 4048000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.997290 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_misses 368 # number of ReadReq MSHR misses
system.cpu.l2cache.UpgradeReq_accesses 14 # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_avg_miss_latency 12000 # average UpgradeReq miss latency
+system.cpu.l2cache.UpgradeReq_avg_miss_latency 22000 # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 11000 # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_miss_latency 168000 # number of UpgradeReq miss cycles
+system.cpu.l2cache.UpgradeReq_miss_latency 308000 # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_misses 14 # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 154000 # number of UpgradeReq MSHR miss cycles
@@ -180,10 +180,10 @@ system.cpu.l2cache.blocked_cycles_no_mshrs 0 #
system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.demand_accesses 442 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_avg_miss_latency 12000 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency 22000 # average overall miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency 11000 # average overall mshr miss latency
system.cpu.l2cache.demand_hits 1 # number of demand (read+write) hits
-system.cpu.l2cache.demand_miss_latency 5292000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency 9702000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_rate 0.997738 # miss rate for demand accesses
system.cpu.l2cache.demand_misses 441 # number of demand (read+write) misses
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
@@ -194,11 +194,11 @@ system.cpu.l2cache.fast_writes 0 # nu
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.overall_accesses 442 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_avg_miss_latency 12000 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency 22000 # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 11000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.cpu.l2cache.overall_hits 1 # number of overall hits
-system.cpu.l2cache.overall_miss_latency 5292000 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency 9702000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_rate 0.997738 # miss rate for overall accesses
system.cpu.l2cache.overall_misses 441 # number of overall misses
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
@@ -219,12 +219,12 @@ system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0
system.cpu.l2cache.replacements 0 # number of replacements
system.cpu.l2cache.sampled_refs 354 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse 179.464793 # Cycle average of tags in use
+system.cpu.l2cache.tagsinuse 177.517189 # Cycle average of tags in use
system.cpu.l2cache.total_refs 1 # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.writebacks 0 # number of writebacks
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
-system.cpu.numCycles 13359000 # number of cpu cycles simulated
+system.cpu.numCycles 18365000 # number of cpu cycles simulated
system.cpu.num_insts 5642 # Number of instructions executed
system.cpu.num_refs 1792 # Number of memory references
system.cpu.workload.PROG:num_syscalls 17 # Number of system calls
diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing/stdout b/tests/quick/00.hello/ref/alpha/linux/simple-timing/stdout
index d25a0624e..940c4ad1c 100644
--- a/tests/quick/00.hello/ref/alpha/linux/simple-timing/stdout
+++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing/stdout
@@ -6,9 +6,9 @@ The Regents of The University of Michigan
All Rights Reserved
-M5 compiled Aug 3 2007 03:56:47
-M5 started Fri Aug 3 04:17:13 2007
-M5 executing on zizzer.eecs.umich.edu
+M5 compiled Aug 12 2007 00:26:55
+M5 started Sun Aug 12 00:29:41 2007
+M5 executing on zeep
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/simple-timing tests/run.py quick/00.hello/alpha/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
-Exiting @ tick 13359000 because target called exit()
+Exiting @ tick 18365000 because target called exit()
diff --git a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.ini b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.ini
index ca7690f17..f5eb9b8b9 100644
--- a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.ini
+++ b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.ini
@@ -99,10 +99,12 @@ type=BaseCache
addr_range=0:18446744073709551615
assoc=2
block_size=64
+cpu_side_filter_ranges=
hash_delay=1
latency=1000
lifo=false
max_miss_count=0
+mem_side_filter_ranges=
mshrs=10
prefetch_access=false
prefetch_cache_check_push=true
@@ -270,10 +272,12 @@ type=BaseCache
addr_range=0:18446744073709551615
assoc=2
block_size=64
+cpu_side_filter_ranges=
hash_delay=1
latency=1000
lifo=false
max_miss_count=0
+mem_side_filter_ranges=
mshrs=10
prefetch_access=false
prefetch_cache_check_push=true
@@ -304,10 +308,12 @@ type=BaseCache
addr_range=0:18446744073709551615
assoc=2
block_size=64
+cpu_side_filter_ranges=
hash_delay=1
latency=1000
lifo=false
max_miss_count=0
+mem_side_filter_ranges=
mshrs=10
prefetch_access=false
prefetch_cache_check_push=true
diff --git a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/m5stats.txt b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/m5stats.txt
index f575843e4..536bed0d1 100644
--- a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/m5stats.txt
+++ b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/m5stats.txt
@@ -1,40 +1,40 @@
---------- Begin Simulation Statistics ----------
global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-global.BPredUnit.BTBHits 146 # Number of BTB hits
-global.BPredUnit.BTBLookups 613 # Number of BTB lookups
+global.BPredUnit.BTBHits 143 # Number of BTB hits
+global.BPredUnit.BTBLookups 610 # Number of BTB lookups
global.BPredUnit.RASInCorrect 32 # Number of incorrect RAS predictions.
global.BPredUnit.condIncorrect 212 # Number of conditional branches incorrect
-global.BPredUnit.condPredicted 393 # Number of conditional branches predicted
-global.BPredUnit.lookups 777 # Number of BP lookups
-global.BPredUnit.usedRAS 153 # Number of times the RAS was used to get a target.
-host_inst_rate 24407 # Simulator instruction rate (inst/s)
-host_mem_usage 153952 # Number of bytes of host memory used
-host_seconds 0.10 # Real time elapsed on the host
-host_tick_rate 19202153 # Simulator tick rate (ticks/s)
-memdepunit.memDep.conflictingLoads 7 # Number of conflicting loads.
+global.BPredUnit.condPredicted 394 # Number of conditional branches predicted
+global.BPredUnit.lookups 779 # Number of BP lookups
+global.BPredUnit.usedRAS 155 # Number of times the RAS was used to get a target.
+host_inst_rate 72558 # Simulator instruction rate (inst/s)
+host_mem_usage 196048 # Number of bytes of host memory used
+host_seconds 0.03 # Real time elapsed on the host
+host_tick_rate 63572637 # Simulator tick rate (ticks/s)
+memdepunit.memDep.conflictingLoads 8 # Number of conflicting loads.
memdepunit.memDep.conflictingStores 7 # Number of conflicting stores.
-memdepunit.memDep.insertedLoads 635 # Number of loads inserted to the mem dependence unit.
-memdepunit.memDep.insertedStores 367 # Number of stores inserted to the mem dependence unit.
+memdepunit.memDep.insertedLoads 636 # Number of loads inserted to the mem dependence unit.
+memdepunit.memDep.insertedStores 369 # Number of stores inserted to the mem dependence unit.
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 2387 # Number of instructions simulated
sim_seconds 0.000002 # Number of seconds simulated
-sim_ticks 1884000 # Number of ticks simulated
+sim_ticks 2104000 # Number of ticks simulated
system.cpu.commit.COM:branches 396 # Number of branches committed
-system.cpu.commit.COM:bw_lim_events 33 # number cycles where commit BW limit reached
+system.cpu.commit.COM:bw_lim_events 35 # number cycles where commit BW limit reached
system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle.samples 3543
+system.cpu.commit.COM:committed_per_cycle.samples 3945
system.cpu.commit.COM:committed_per_cycle.min_value 0
- 0 2580 7281.96%
- 1 265 747.95%
- 2 337 951.17%
- 3 138 389.50%
- 4 67 189.11%
- 5 69 194.75%
- 6 32 90.32%
- 7 22 62.09%
- 8 33 93.14%
+ 0 2992 7584.28%
+ 1 255 646.39%
+ 2 335 849.18%
+ 3 139 352.34%
+ 4 66 167.30%
+ 5 69 174.90%
+ 6 33 83.65%
+ 7 21 53.23%
+ 8 35 88.72%
system.cpu.commit.COM:committed_per_cycle.max_value 8
system.cpu.commit.COM:committed_per_cycle.end_dist
@@ -46,67 +46,67 @@ system.cpu.commit.COM:swp_count 0 # Nu
system.cpu.commit.branchMispredicts 131 # The number of times a branch was mispredicted
system.cpu.commit.commitCommittedInsts 2576 # The number of committed instructions
system.cpu.commit.commitNonSpecStalls 4 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.commitSquashedInsts 1118 # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts 1134 # The number of squashed insts skipped by commit
system.cpu.committedInsts 2387 # Number of Instructions Simulated
system.cpu.committedInsts_total 2387 # Number of Instructions Simulated
-system.cpu.cpi 1.578969 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 1.578969 # CPI: Total CPI of All Threads
-system.cpu.dcache.ReadReq_accesses 518 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency 6583.333333 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 4891.666667 # average ReadReq mshr miss latency
+system.cpu.cpi 1.747382 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 1.747382 # CPI: Total CPI of All Threads
+system.cpu.dcache.ReadReq_accesses 519 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_avg_miss_latency 8729.508197 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 5745.901639 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_hits 458 # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency 395000 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_rate 0.115830 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_misses 60 # number of ReadReq misses
+system.cpu.dcache.ReadReq_miss_latency 532500 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_rate 0.117534 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_misses 61 # number of ReadReq misses
system.cpu.dcache.ReadReq_mshr_hits 10 # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_miss_latency 293500 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate 0.115830 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_misses 60 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_accesses 239 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency 14216.216216 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 5202.702703 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_hits 202 # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency 526000 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_rate 0.154812 # miss rate for WriteReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_latency 350500 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate 0.117534 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_misses 61 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_accesses 240 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_avg_miss_latency 18810.810811 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 6202.702703 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_hits 203 # number of WriteReq hits
+system.cpu.dcache.WriteReq_miss_latency 696000 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_rate 0.154167 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_misses 37 # number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_hits 55 # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_miss_latency 192500 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_rate 0.154812 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_hits 54 # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_miss_latency 229500 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_rate 0.154167 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_misses 37 # number of WriteReq MSHR misses
system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
-system.cpu.dcache.avg_refs 7.905882 # Average number of references to valid blocks.
+system.cpu.dcache.avg_refs 7.929412 # Average number of references to valid blocks.
system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.demand_accesses 757 # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency 9494.845361 # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 5010.309278 # average overall mshr miss latency
-system.cpu.dcache.demand_hits 660 # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency 921000 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_rate 0.128137 # miss rate for demand accesses
-system.cpu.dcache.demand_misses 97 # number of demand (read+write) misses
-system.cpu.dcache.demand_mshr_hits 65 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency 486000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_rate 0.128137 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_misses 97 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_accesses 759 # number of demand (read+write) accesses
+system.cpu.dcache.demand_avg_miss_latency 12535.714286 # average overall miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 5918.367347 # average overall mshr miss latency
+system.cpu.dcache.demand_hits 661 # number of demand (read+write) hits
+system.cpu.dcache.demand_miss_latency 1228500 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_rate 0.129117 # miss rate for demand accesses
+system.cpu.dcache.demand_misses 98 # number of demand (read+write) misses
+system.cpu.dcache.demand_mshr_hits 64 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_miss_latency 580000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_rate 0.129117 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_misses 98 # number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.overall_accesses 757 # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency 9494.845361 # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 5010.309278 # average overall mshr miss latency
+system.cpu.dcache.overall_accesses 759 # number of overall (read+write) accesses
+system.cpu.dcache.overall_avg_miss_latency 12535.714286 # average overall miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 5918.367347 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits 660 # number of overall hits
-system.cpu.dcache.overall_miss_latency 921000 # number of overall miss cycles
-system.cpu.dcache.overall_miss_rate 0.128137 # miss rate for overall accesses
-system.cpu.dcache.overall_misses 97 # number of overall misses
-system.cpu.dcache.overall_mshr_hits 65 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency 486000 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_rate 0.128137 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_misses 97 # number of overall MSHR misses
+system.cpu.dcache.overall_hits 661 # number of overall hits
+system.cpu.dcache.overall_miss_latency 1228500 # number of overall miss cycles
+system.cpu.dcache.overall_miss_rate 0.129117 # miss rate for overall accesses
+system.cpu.dcache.overall_misses 98 # number of overall misses
+system.cpu.dcache.overall_mshr_hits 64 # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_miss_latency 580000 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_rate 0.129117 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_misses 98 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
@@ -121,88 +121,88 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0
system.cpu.dcache.replacements 0 # number of replacements
system.cpu.dcache.sampled_refs 85 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse 51.399169 # Cycle average of tags in use
-system.cpu.dcache.total_refs 672 # Total number of references to valid blocks.
+system.cpu.dcache.tagsinuse 50.690606 # Cycle average of tags in use
+system.cpu.dcache.total_refs 674 # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 0 # number of writebacks
-system.cpu.decode.DECODE:BlockedCycles 87 # Number of cycles decode is blocked
+system.cpu.decode.DECODE:BlockedCycles 91 # Number of cycles decode is blocked
system.cpu.decode.DECODE:BranchMispred 83 # Number of times decode detected a branch misprediction
-system.cpu.decode.DECODE:BranchResolved 125 # Number of times decode resolved a branch
-system.cpu.decode.DECODE:DecodedInsts 4218 # Number of instructions handled by decode
-system.cpu.decode.DECODE:IdleCycles 2648 # Number of cycles decode is idle
-system.cpu.decode.DECODE:RunCycles 808 # Number of cycles decode is running
+system.cpu.decode.DECODE:BranchResolved 126 # Number of times decode resolved a branch
+system.cpu.decode.DECODE:DecodedInsts 4236 # Number of instructions handled by decode
+system.cpu.decode.DECODE:IdleCycles 3045 # Number of cycles decode is idle
+system.cpu.decode.DECODE:RunCycles 809 # Number of cycles decode is running
system.cpu.decode.DECODE:SquashCycles 225 # Number of cycles decode is squashing
system.cpu.decode.DECODE:SquashedInsts 304 # Number of squashed instructions handled by decode
system.cpu.decode.DECODE:UnblockCycles 1 # Number of cycles decode is unblocking
-system.cpu.fetch.Branches 777 # Number of branches that fetch encountered
-system.cpu.fetch.CacheLines 686 # Number of cache lines fetched
-system.cpu.fetch.Cycles 1528 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.IcacheSquashes 107 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.Insts 4951 # Number of instructions fetch has processed
+system.cpu.fetch.Branches 779 # Number of branches that fetch encountered
+system.cpu.fetch.CacheLines 691 # Number of cache lines fetched
+system.cpu.fetch.Cycles 1534 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.IcacheSquashes 112 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.Insts 4961 # Number of instructions fetch has processed
system.cpu.fetch.SquashCycles 223 # Number of cycles fetch has spent squashing
-system.cpu.fetch.branchRate 0.206155 # Number of branch fetches per cycle
-system.cpu.fetch.icacheStallCycles 686 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.predictedBranches 299 # Number of branches that fetch has predicted taken
-system.cpu.fetch.rate 1.313611 # Number of inst fetches per cycle
+system.cpu.fetch.branchRate 0.186766 # Number of branch fetches per cycle
+system.cpu.fetch.icacheStallCycles 691 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.predictedBranches 298 # Number of branches that fetch has predicted taken
+system.cpu.fetch.rate 1.189403 # Number of inst fetches per cycle
system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist.samples 3769
+system.cpu.fetch.rateDist.samples 4171
system.cpu.fetch.rateDist.min_value 0
- 0 2929 7771.29%
- 1 36 95.52%
- 2 88 233.48%
- 3 54 143.27%
- 4 108 286.55%
- 5 55 145.93%
- 6 40 106.13%
- 7 42 111.44%
- 8 417 1106.39%
+ 0 3330 7983.70%
+ 1 36 86.31%
+ 2 85 203.79%
+ 3 57 136.66%
+ 4 109 261.33%
+ 5 54 129.47%
+ 6 40 95.90%
+ 7 42 100.70%
+ 8 418 1002.16%
system.cpu.fetch.rateDist.max_value 8
system.cpu.fetch.rateDist.end_dist
-system.cpu.icache.ReadReq_accesses 676 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_avg_miss_latency 5629.032258 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 4489.247312 # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_hits 490 # number of ReadReq hits
-system.cpu.icache.ReadReq_miss_latency 1047000 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_rate 0.275148 # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_accesses 674 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_avg_miss_latency 7774.193548 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 5451.612903 # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_hits 488 # number of ReadReq hits
+system.cpu.icache.ReadReq_miss_latency 1446000 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_rate 0.275964 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_misses 186 # number of ReadReq misses
-system.cpu.icache.ReadReq_mshr_hits 10 # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_miss_latency 835000 # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate 0.275148 # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_hits 17 # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_miss_latency 1014000 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate 0.275964 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_misses 186 # number of ReadReq MSHR misses
system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
-system.cpu.icache.avg_refs 2.634409 # Average number of references to valid blocks.
+system.cpu.icache.avg_refs 2.623656 # Average number of references to valid blocks.
system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.demand_accesses 676 # number of demand (read+write) accesses
-system.cpu.icache.demand_avg_miss_latency 5629.032258 # average overall miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 4489.247312 # average overall mshr miss latency
-system.cpu.icache.demand_hits 490 # number of demand (read+write) hits
-system.cpu.icache.demand_miss_latency 1047000 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_rate 0.275148 # miss rate for demand accesses
+system.cpu.icache.demand_accesses 674 # number of demand (read+write) accesses
+system.cpu.icache.demand_avg_miss_latency 7774.193548 # average overall miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 5451.612903 # average overall mshr miss latency
+system.cpu.icache.demand_hits 488 # number of demand (read+write) hits
+system.cpu.icache.demand_miss_latency 1446000 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_rate 0.275964 # miss rate for demand accesses
system.cpu.icache.demand_misses 186 # number of demand (read+write) misses
-system.cpu.icache.demand_mshr_hits 10 # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_miss_latency 835000 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_rate 0.275148 # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_hits 17 # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_miss_latency 1014000 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_rate 0.275964 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_misses 186 # number of demand (read+write) MSHR misses
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.icache.overall_accesses 676 # number of overall (read+write) accesses
-system.cpu.icache.overall_avg_miss_latency 5629.032258 # average overall miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 4489.247312 # average overall mshr miss latency
+system.cpu.icache.overall_accesses 674 # number of overall (read+write) accesses
+system.cpu.icache.overall_avg_miss_latency 7774.193548 # average overall miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 5451.612903 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
-system.cpu.icache.overall_hits 490 # number of overall hits
-system.cpu.icache.overall_miss_latency 1047000 # number of overall miss cycles
-system.cpu.icache.overall_miss_rate 0.275148 # miss rate for overall accesses
+system.cpu.icache.overall_hits 488 # number of overall hits
+system.cpu.icache.overall_miss_latency 1446000 # number of overall miss cycles
+system.cpu.icache.overall_miss_rate 0.275964 # miss rate for overall accesses
system.cpu.icache.overall_misses 186 # number of overall misses
-system.cpu.icache.overall_mshr_hits 10 # number of overall MSHR hits
-system.cpu.icache.overall_mshr_miss_latency 835000 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_rate 0.275148 # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_hits 17 # number of overall MSHR hits
+system.cpu.icache.overall_mshr_miss_latency 1014000 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_rate 0.275964 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_misses 186 # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
@@ -218,35 +218,35 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0
system.cpu.icache.replacements 0 # number of replacements
system.cpu.icache.sampled_refs 186 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse 104.691657 # Cycle average of tags in use
-system.cpu.icache.total_refs 490 # Total number of references to valid blocks.
+system.cpu.icache.tagsinuse 102.643576 # Cycle average of tags in use
+system.cpu.icache.total_refs 488 # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks
-system.cpu.idleCycles 998 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.iew.EXEC:branches 516 # Number of branches executed
+system.cpu.idleCycles 26984 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.iew.EXEC:branches 522 # Number of branches executed
system.cpu.iew.EXEC:nop 242 # number of nop insts executed
-system.cpu.iew.EXEC:rate 0.810295 # Inst execution rate
-system.cpu.iew.EXEC:refs 894 # number of memory reference insts executed
-system.cpu.iew.EXEC:stores 334 # Number of stores executed
+system.cpu.iew.EXEC:rate 0.736514 # Inst execution rate
+system.cpu.iew.EXEC:refs 896 # number of memory reference insts executed
+system.cpu.iew.EXEC:stores 333 # Number of stores executed
system.cpu.iew.EXEC:swp 0 # number of swp insts executed
-system.cpu.iew.WB:consumers 1725 # num instructions consuming a value
-system.cpu.iew.WB:count 2987 # cumulative count of insts written-back
-system.cpu.iew.WB:fanout 0.794203 # average fanout of values written-back
+system.cpu.iew.WB:consumers 1736 # num instructions consuming a value
+system.cpu.iew.WB:count 3002 # cumulative count of insts written-back
+system.cpu.iew.WB:fanout 0.793779 # average fanout of values written-back
system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.iew.WB:producers 1370 # num instructions producing a value
-system.cpu.iew.WB:rate 0.792518 # insts written-back per cycle
-system.cpu.iew.WB:sent 3007 # cumulative count of insts sent to commit
-system.cpu.iew.branchMispredicts 146 # Number of branch mispredicts detected at execute
+system.cpu.iew.WB:producers 1378 # num instructions producing a value
+system.cpu.iew.WB:rate 0.719731 # insts written-back per cycle
+system.cpu.iew.WB:sent 3020 # cumulative count of insts sent to commit
+system.cpu.iew.branchMispredicts 147 # Number of branch mispredicts detected at execute
system.cpu.iew.iewBlockCycles 0 # Number of cycles IEW is blocking
-system.cpu.iew.iewDispLoadInsts 635 # Number of dispatched load instructions
+system.cpu.iew.iewDispLoadInsts 636 # Number of dispatched load instructions
system.cpu.iew.iewDispNonSpecInsts 6 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewDispSquashedInsts 92 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispStoreInsts 367 # Number of dispatched store instructions
-system.cpu.iew.iewDispatchedInsts 3711 # Number of instructions dispatched to IQ
-system.cpu.iew.iewExecLoadInsts 560 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 111 # Number of squashed instructions skipped in execute
-system.cpu.iew.iewExecutedInsts 3054 # Number of executed instructions
+system.cpu.iew.iewDispSquashedInsts 85 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispStoreInsts 369 # Number of dispatched store instructions
+system.cpu.iew.iewDispatchedInsts 3727 # Number of instructions dispatched to IQ
+system.cpu.iew.iewExecLoadInsts 563 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 108 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewExecutedInsts 3072 # Number of executed instructions
system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
@@ -254,23 +254,23 @@ system.cpu.iew.iewSquashCycles 225 # Nu
system.cpu.iew.iewUnblockCycles 0 # Number of cycles IEW is unblocking
system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
-system.cpu.iew.lsq.thread.0.forwLoads 24 # Number of loads that had data forwarded from stores
-system.cpu.iew.lsq.thread.0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread.0.forwLoads 25 # Number of loads that had data forwarded from stores
+system.cpu.iew.lsq.thread.0.ignoredResponses 1 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
-system.cpu.iew.lsq.thread.0.memOrderViolation 12 # Number of memory ordering violations
+system.cpu.iew.lsq.thread.0.memOrderViolation 13 # Number of memory ordering violations
system.cpu.iew.lsq.thread.0.rescheduledLoads 0 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread.0.squashedLoads 220 # Number of loads squashed
-system.cpu.iew.lsq.thread.0.squashedStores 73 # Number of stores squashed
-system.cpu.iew.memOrderViolationEvents 12 # Number of memory order violations
-system.cpu.iew.predictedNotTakenIncorrect 98 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.lsq.thread.0.squashedLoads 221 # Number of loads squashed
+system.cpu.iew.lsq.thread.0.squashedStores 75 # Number of stores squashed
+system.cpu.iew.memOrderViolationEvents 13 # Number of memory order violations
+system.cpu.iew.predictedNotTakenIncorrect 99 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.predictedTakenIncorrect 48 # Number of branches that were predicted taken incorrectly
-system.cpu.ipc 0.633324 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 0.633324 # IPC: Total IPC of All Threads
-system.cpu.iq.ISSUE:FU_type_0 3165 # Type of FU issued
+system.cpu.ipc 0.572285 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 0.572285 # IPC: Total IPC of All Threads
+system.cpu.iq.ISSUE:FU_type_0 3180 # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0.start_dist
No_OpClass 0 0.00% # Type of FU issued
- IntAlu 2243 70.87% # Type of FU issued
+ IntAlu 2258 71.01% # Type of FU issued
IntMult 1 0.03% # Type of FU issued
IntDiv 0 0.00% # Type of FU issued
FloatAdd 0 0.00% # Type of FU issued
@@ -279,16 +279,16 @@ system.cpu.iq.ISSUE:FU_type_0.start_dist
FloatMult 0 0.00% # Type of FU issued
FloatDiv 0 0.00% # Type of FU issued
FloatSqrt 0 0.00% # Type of FU issued
- MemRead 581 18.36% # Type of FU issued
- MemWrite 340 10.74% # Type of FU issued
+ MemRead 581 18.27% # Type of FU issued
+ MemWrite 340 10.69% # Type of FU issued
IprAccess 0 0.00% # Type of FU issued
InstPrefetch 0 0.00% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0.end_dist
-system.cpu.iq.ISSUE:fu_busy_cnt 35 # FU busy when requested
-system.cpu.iq.ISSUE:fu_busy_rate 0.011058 # FU busy rate (busy events/executed inst)
+system.cpu.iq.ISSUE:fu_busy_cnt 36 # FU busy when requested
+system.cpu.iq.ISSUE:fu_busy_rate 0.011321 # FU busy rate (busy events/executed inst)
system.cpu.iq.ISSUE:fu_full.start_dist
No_OpClass 0 0.00% # attempts to use FU when none available
- IntAlu 1 2.86% # attempts to use FU when none available
+ IntAlu 2 5.56% # attempts to use FU when none available
IntMult 0 0.00% # attempts to use FU when none available
IntDiv 0 0.00% # attempts to use FU when none available
FloatAdd 0 0.00% # attempts to use FU when none available
@@ -297,61 +297,61 @@ system.cpu.iq.ISSUE:fu_full.start_dist
FloatMult 0 0.00% # attempts to use FU when none available
FloatDiv 0 0.00% # attempts to use FU when none available
FloatSqrt 0 0.00% # attempts to use FU when none available
- MemRead 12 34.29% # attempts to use FU when none available
- MemWrite 22 62.86% # attempts to use FU when none available
+ MemRead 12 33.33% # attempts to use FU when none available
+ MemWrite 22 61.11% # attempts to use FU when none available
IprAccess 0 0.00% # attempts to use FU when none available
InstPrefetch 0 0.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full.end_dist
system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle.samples 3769
+system.cpu.iq.ISSUE:issued_per_cycle.samples 4171
system.cpu.iq.ISSUE:issued_per_cycle.min_value 0
- 0 2469 6550.81%
- 1 494 1310.69%
- 2 274 726.98%
- 3 234 620.85%
- 4 152 403.29%
- 5 87 230.83%
- 6 40 106.13%
- 7 14 37.15%
- 8 5 13.27%
+ 0 2877 6897.63%
+ 1 465 1114.84%
+ 2 300 719.25%
+ 3 228 546.63%
+ 4 154 369.22%
+ 5 89 213.38%
+ 6 40 95.90%
+ 7 14 33.57%
+ 8 4 9.59%
system.cpu.iq.ISSUE:issued_per_cycle.max_value 8
system.cpu.iq.ISSUE:issued_per_cycle.end_dist
-system.cpu.iq.ISSUE:rate 0.839745 # Inst issue rate
-system.cpu.iq.iqInstsAdded 3463 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqInstsIssued 3165 # Number of instructions issued
+system.cpu.iq.ISSUE:rate 0.762407 # Inst issue rate
+system.cpu.iq.iqInstsAdded 3479 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqInstsIssued 3180 # Number of instructions issued
system.cpu.iq.iqNonSpecInstsAdded 6 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqSquashedInstsExamined 947 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedInstsExamined 944 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedInstsIssued 1 # Number of squashed instructions issued
system.cpu.iq.iqSquashedNonSpecRemoved 2 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.iqSquashedOperandsExamined 468 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.l2cache.ReadExReq_accesses 25 # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_avg_miss_latency 3720 # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 2720 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_miss_latency 93000 # number of ReadExReq miss cycles
+system.cpu.iq.iqSquashedOperandsExamined 473 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.l2cache.ReadExReq_accesses 24 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_avg_miss_latency 4750 # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 2750 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_miss_latency 114000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_misses 25 # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency 68000 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_misses 24 # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_mshr_miss_latency 66000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_misses 25 # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadReq_accesses 246 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_avg_miss_latency 3357.723577 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2357.723577 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_miss_latency 826000 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_mshr_misses 24 # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadReq_accesses 247 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_avg_miss_latency 4354.251012 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2354.251012 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_miss_latency 1075500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_rate 1 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_misses 246 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency 580000 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_misses 247 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency 581500 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate 1 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_misses 246 # number of ReadReq MSHR misses
-system.cpu.l2cache.UpgradeReq_accesses 13 # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_avg_miss_latency 3230.769231 # average UpgradeReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 2230.769231 # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_miss_latency 42000 # number of UpgradeReq miss cycles
+system.cpu.l2cache.ReadReq_mshr_misses 247 # number of ReadReq MSHR misses
+system.cpu.l2cache.UpgradeReq_accesses 14 # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_avg_miss_latency 4250 # average UpgradeReq miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 2250 # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_miss_latency 59500 # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_misses 13 # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency 29000 # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_misses 14 # number of UpgradeReq misses
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency 31500 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_misses 13 # number of UpgradeReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses 14 # number of UpgradeReq MSHR misses
system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
system.cpu.l2cache.avg_refs 0 # Average number of references to valid blocks.
@@ -361,29 +361,29 @@ system.cpu.l2cache.blocked_cycles_no_mshrs 0 #
system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.demand_accesses 271 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_avg_miss_latency 3391.143911 # average overall miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency 2391.143911 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_miss_latency 4389.298893 # average overall miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency 2389.298893 # average overall mshr miss latency
system.cpu.l2cache.demand_hits 0 # number of demand (read+write) hits
-system.cpu.l2cache.demand_miss_latency 919000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency 1189500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_rate 1 # miss rate for demand accesses
system.cpu.l2cache.demand_misses 271 # number of demand (read+write) misses
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_miss_latency 648000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency 647500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_rate 1 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_misses 271 # number of demand (read+write) MSHR misses
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.overall_accesses 271 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_avg_miss_latency 3391.143911 # average overall miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency 2391.143911 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_miss_latency 4389.298893 # average overall miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency 2389.298893 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.cpu.l2cache.overall_hits 0 # number of overall hits
-system.cpu.l2cache.overall_miss_latency 919000 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency 1189500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_rate 1 # miss rate for overall accesses
system.cpu.l2cache.overall_misses 271 # number of overall misses
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_miss_latency 648000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency 647500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_rate 1 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_misses 271 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
@@ -400,26 +400,26 @@ system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0
system.cpu.l2cache.replacements 0 # number of replacements
system.cpu.l2cache.sampled_refs 233 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse 129.636467 # Cycle average of tags in use
+system.cpu.l2cache.tagsinuse 127.304233 # Cycle average of tags in use
system.cpu.l2cache.total_refs 0 # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.writebacks 0 # number of writebacks
-system.cpu.numCycles 3769 # number of cpu cycles simulated
+system.cpu.numCycles 4171 # number of cpu cycles simulated
system.cpu.rename.RENAME:CommittedMaps 1768 # Number of HB maps that are committed
-system.cpu.rename.RENAME:IdleCycles 2724 # Number of cycles rename is idle
+system.cpu.rename.RENAME:IdleCycles 3117 # Number of cycles rename is idle
system.cpu.rename.RENAME:LSQFullEvents 1 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RENAME:RenameLookups 4613 # Number of register rename lookups that rename has made
-system.cpu.rename.RENAME:RenamedInsts 4068 # Number of instructions processed by rename
-system.cpu.rename.RENAME:RenamedOperands 2909 # Number of destination operands rename has renamed
-system.cpu.rename.RENAME:RunCycles 733 # Number of cycles rename is running
+system.cpu.rename.RENAME:RenameLookups 4657 # Number of register rename lookups that rename has made
+system.cpu.rename.RENAME:RenamedInsts 4106 # Number of instructions processed by rename
+system.cpu.rename.RENAME:RenamedOperands 2936 # Number of destination operands rename has renamed
+system.cpu.rename.RENAME:RunCycles 738 # Number of cycles rename is running
system.cpu.rename.RENAME:SquashCycles 225 # Number of cycles rename is squashing
system.cpu.rename.RENAME:UnblockCycles 7 # Number of cycles rename is unblocking
-system.cpu.rename.RENAME:UndoneMaps 1141 # Number of HB maps that are undone due to squashing
-system.cpu.rename.RENAME:serializeStallCycles 80 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RENAME:UndoneMaps 1168 # Number of HB maps that are undone due to squashing
+system.cpu.rename.RENAME:serializeStallCycles 84 # count of cycles rename stalled for serializing inst
system.cpu.rename.RENAME:serializingInsts 8 # count of serializing insts renamed
-system.cpu.rename.RENAME:skidInsts 52 # count of insts added to the skid buffer
+system.cpu.rename.RENAME:skidInsts 50 # count of insts added to the skid buffer
system.cpu.rename.RENAME:tempSerializingInsts 6 # count of temporary serializing insts renamed
-system.cpu.timesIdled 2 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.timesIdled 16 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.workload.PROG:num_syscalls 4 # Number of system calls
---------- End Simulation Statistics ----------
diff --git a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stdout b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stdout
index 79e638bb8..57159efac 100644
--- a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stdout
+++ b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stdout
@@ -6,9 +6,9 @@ The Regents of The University of Michigan
All Rights Reserved
-M5 compiled Aug 3 2007 03:56:47
-M5 started Fri Aug 3 04:17:13 2007
-M5 executing on zizzer.eecs.umich.edu
+M5 compiled Aug 12 2007 00:26:55
+M5 started Sun Aug 12 00:29:41 2007
+M5 executing on zeep
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/o3-timing tests/run.py quick/00.hello/alpha/tru64/o3-timing
Global frequency set at 1000000000000 ticks per second
-Exiting @ tick 1884000 because target called exit()
+Exiting @ tick 2104000 because target called exit()
diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.ini b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.ini
index a9adf07b9..f8e125ea1 100644
--- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.ini
+++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.ini
@@ -34,10 +34,12 @@ type=BaseCache
addr_range=0:18446744073709551615
assoc=2
block_size=64
+cpu_side_filter_ranges=
hash_delay=1
latency=1000
lifo=false
max_miss_count=0
+mem_side_filter_ranges=
mshrs=10
prefetch_access=false
prefetch_cache_check_push=true
@@ -68,10 +70,12 @@ type=BaseCache
addr_range=0:18446744073709551615
assoc=2
block_size=64
+cpu_side_filter_ranges=
hash_delay=1
latency=1000
lifo=false
max_miss_count=0
+mem_side_filter_ranges=
mshrs=10
prefetch_access=false
prefetch_cache_check_push=true
@@ -102,10 +106,12 @@ type=BaseCache
addr_range=0:18446744073709551615
assoc=2
block_size=64
+cpu_side_filter_ranges=
hash_delay=1
latency=10000
lifo=false
max_miss_count=0
+mem_side_filter_ranges=
mshrs=10
prefetch_access=false
prefetch_cache_check_push=true
diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/m5stats.txt b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/m5stats.txt
index 56479827d..23e886f55 100644
--- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/m5stats.txt
+++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/m5stats.txt
@@ -1,31 +1,31 @@
---------- Begin Simulation Statistics ----------
-host_inst_rate 43962 # Simulator instruction rate (inst/s)
-host_mem_usage 153564 # Number of bytes of host memory used
-host_seconds 0.06 # Real time elapsed on the host
-host_tick_rate 112042683 # Simulator tick rate (ticks/s)
+host_inst_rate 196854 # Simulator instruction rate (inst/s)
+host_mem_usage 195480 # Number of bytes of host memory used
+host_seconds 0.01 # Real time elapsed on the host
+host_tick_rate 706389035 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 2578 # Number of instructions simulated
-sim_seconds 0.000007 # Number of seconds simulated
-sim_ticks 6615000 # Number of ticks simulated
+sim_seconds 0.000009 # Number of seconds simulated
+sim_ticks 9431000 # Number of ticks simulated
system.cpu.dcache.ReadReq_accesses 415 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency 14000 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 13000 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency 25000 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 23000 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_hits 360 # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency 770000 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency 1375000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_rate 0.132530 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_misses 55 # number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_miss_latency 715000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency 1265000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate 0.132530 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_misses 55 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_accesses 294 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency 14000 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 13000 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency 25000 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 23000 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_hits 256 # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency 532000 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency 950000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_rate 0.129252 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_misses 38 # number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_miss_latency 494000 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency 874000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_rate 0.129252 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_misses 38 # number of WriteReq MSHR misses
system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
@@ -37,29 +37,29 @@ system.cpu.dcache.blocked_cycles_no_mshrs 0 # n
system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.demand_accesses 709 # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency 14000 # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 13000 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_miss_latency 25000 # average overall miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 23000 # average overall mshr miss latency
system.cpu.dcache.demand_hits 616 # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency 1302000 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency 2325000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_rate 0.131171 # miss rate for demand accesses
system.cpu.dcache.demand_misses 93 # number of demand (read+write) misses
system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency 1209000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency 2139000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_rate 0.131171 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_misses 93 # number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.overall_accesses 709 # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency 14000 # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 13000 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_miss_latency 25000 # average overall miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 23000 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.cpu.dcache.overall_hits 616 # number of overall hits
-system.cpu.dcache.overall_miss_latency 1302000 # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency 2325000 # number of overall miss cycles
system.cpu.dcache.overall_miss_rate 0.131171 # miss rate for overall accesses
system.cpu.dcache.overall_misses 93 # number of overall misses
system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency 1209000 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency 2139000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_rate 0.131171 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_misses 93 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
@@ -76,18 +76,18 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0
system.cpu.dcache.replacements 0 # number of replacements
system.cpu.dcache.sampled_refs 82 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse 50.044147 # Cycle average of tags in use
+system.cpu.dcache.tagsinuse 48.863963 # Cycle average of tags in use
system.cpu.dcache.total_refs 627 # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 0 # number of writebacks
system.cpu.icache.ReadReq_accesses 2579 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_avg_miss_latency 14000 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 13000 # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_miss_latency 25000 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 23000 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_hits 2416 # number of ReadReq hits
-system.cpu.icache.ReadReq_miss_latency 2282000 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency 4075000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_rate 0.063203 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_misses 163 # number of ReadReq misses
-system.cpu.icache.ReadReq_mshr_miss_latency 2119000 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency 3749000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate 0.063203 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_misses 163 # number of ReadReq MSHR misses
system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
@@ -99,29 +99,29 @@ system.cpu.icache.blocked_cycles_no_mshrs 0 # n
system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.demand_accesses 2579 # number of demand (read+write) accesses
-system.cpu.icache.demand_avg_miss_latency 14000 # average overall miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 13000 # average overall mshr miss latency
+system.cpu.icache.demand_avg_miss_latency 25000 # average overall miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 23000 # average overall mshr miss latency
system.cpu.icache.demand_hits 2416 # number of demand (read+write) hits
-system.cpu.icache.demand_miss_latency 2282000 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency 4075000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_rate 0.063203 # miss rate for demand accesses
system.cpu.icache.demand_misses 163 # number of demand (read+write) misses
system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_miss_latency 2119000 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency 3749000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_rate 0.063203 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_misses 163 # number of demand (read+write) MSHR misses
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.icache.overall_accesses 2579 # number of overall (read+write) accesses
-system.cpu.icache.overall_avg_miss_latency 14000 # average overall miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 13000 # average overall mshr miss latency
+system.cpu.icache.overall_avg_miss_latency 25000 # average overall miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 23000 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.cpu.icache.overall_hits 2416 # number of overall hits
-system.cpu.icache.overall_miss_latency 2282000 # number of overall miss cycles
+system.cpu.icache.overall_miss_latency 4075000 # number of overall miss cycles
system.cpu.icache.overall_miss_rate 0.063203 # miss rate for overall accesses
system.cpu.icache.overall_misses 163 # number of overall misses
system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.icache.overall_mshr_miss_latency 2119000 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency 3749000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_rate 0.063203 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_misses 163 # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
@@ -138,33 +138,33 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0
system.cpu.icache.replacements 0 # number of replacements
system.cpu.icache.sampled_refs 163 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse 86.205303 # Cycle average of tags in use
+system.cpu.icache.tagsinuse 83.443652 # Cycle average of tags in use
system.cpu.icache.total_refs 2416 # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks
system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.l2cache.ReadExReq_accesses 27 # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_avg_miss_latency 12000 # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency 22000 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 11000 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_miss_latency 324000 # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency 594000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_misses 27 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_mshr_miss_latency 297000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_misses 27 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadReq_accesses 218 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_avg_miss_latency 12000 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency 22000 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 11000 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_miss_latency 2616000 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency 4796000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_rate 1 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_misses 218 # number of ReadReq misses
system.cpu.l2cache.ReadReq_mshr_miss_latency 2398000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate 1 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_misses 218 # number of ReadReq MSHR misses
system.cpu.l2cache.UpgradeReq_accesses 11 # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_avg_miss_latency 12000 # average UpgradeReq miss latency
+system.cpu.l2cache.UpgradeReq_avg_miss_latency 22000 # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 11000 # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_miss_latency 132000 # number of UpgradeReq miss cycles
+system.cpu.l2cache.UpgradeReq_miss_latency 242000 # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_misses 11 # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 121000 # number of UpgradeReq MSHR miss cycles
@@ -179,10 +179,10 @@ system.cpu.l2cache.blocked_cycles_no_mshrs 0 #
system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.demand_accesses 245 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_avg_miss_latency 12000 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency 22000 # average overall miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency 11000 # average overall mshr miss latency
system.cpu.l2cache.demand_hits 0 # number of demand (read+write) hits
-system.cpu.l2cache.demand_miss_latency 2940000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency 5390000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_rate 1 # miss rate for demand accesses
system.cpu.l2cache.demand_misses 245 # number of demand (read+write) misses
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
@@ -193,11 +193,11 @@ system.cpu.l2cache.fast_writes 0 # nu
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.overall_accesses 245 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_avg_miss_latency 12000 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency 22000 # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 11000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.cpu.l2cache.overall_hits 0 # number of overall hits
-system.cpu.l2cache.overall_miss_latency 2940000 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency 5390000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_rate 1 # miss rate for overall accesses
system.cpu.l2cache.overall_misses 245 # number of overall misses
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
@@ -218,12 +218,12 @@ system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0
system.cpu.l2cache.replacements 0 # number of replacements
system.cpu.l2cache.sampled_refs 207 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse 109.774164 # Cycle average of tags in use
+system.cpu.l2cache.tagsinuse 106.620093 # Cycle average of tags in use
system.cpu.l2cache.total_refs 0 # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.writebacks 0 # number of writebacks
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
-system.cpu.numCycles 6615000 # number of cpu cycles simulated
+system.cpu.numCycles 9431000 # number of cpu cycles simulated
system.cpu.num_insts 2578 # Number of instructions executed
system.cpu.num_refs 710 # Number of memory references
system.cpu.workload.PROG:num_syscalls 4 # Number of system calls
diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/stdout b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/stdout
index 47fca6faf..eb8910969 100644
--- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/stdout
+++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/stdout
@@ -6,9 +6,9 @@ The Regents of The University of Michigan
All Rights Reserved
-M5 compiled Aug 3 2007 03:56:47
-M5 started Fri Aug 3 04:17:14 2007
-M5 executing on zizzer.eecs.umich.edu
+M5 compiled Aug 12 2007 00:26:55
+M5 started Sun Aug 12 00:29:42 2007
+M5 executing on zeep
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/simple-timing tests/run.py quick/00.hello/alpha/tru64/simple-timing
Global frequency set at 1000000000000 ticks per second
-Exiting @ tick 6615000 because target called exit()
+Exiting @ tick 9431000 because target called exit()
diff --git a/tests/quick/00.hello/ref/mips/linux/simple-timing/config.ini b/tests/quick/00.hello/ref/mips/linux/simple-timing/config.ini
index c52036289..f2dee3856 100644
--- a/tests/quick/00.hello/ref/mips/linux/simple-timing/config.ini
+++ b/tests/quick/00.hello/ref/mips/linux/simple-timing/config.ini
@@ -34,10 +34,12 @@ type=BaseCache
addr_range=0:18446744073709551615
assoc=2
block_size=64
+cpu_side_filter_ranges=
hash_delay=1
latency=1000
lifo=false
max_miss_count=0
+mem_side_filter_ranges=
mshrs=10
prefetch_access=false
prefetch_cache_check_push=true
@@ -68,10 +70,12 @@ type=BaseCache
addr_range=0:18446744073709551615
assoc=2
block_size=64
+cpu_side_filter_ranges=
hash_delay=1
latency=1000
lifo=false
max_miss_count=0
+mem_side_filter_ranges=
mshrs=10
prefetch_access=false
prefetch_cache_check_push=true
@@ -102,10 +106,12 @@ type=BaseCache
addr_range=0:18446744073709551615
assoc=2
block_size=64
+cpu_side_filter_ranges=
hash_delay=1
latency=10000
lifo=false
max_miss_count=0
+mem_side_filter_ranges=
mshrs=10
prefetch_access=false
prefetch_cache_check_push=true
diff --git a/tests/quick/00.hello/ref/mips/linux/simple-timing/m5stats.txt b/tests/quick/00.hello/ref/mips/linux/simple-timing/m5stats.txt
index 985175cad..a9c46636a 100644
--- a/tests/quick/00.hello/ref/mips/linux/simple-timing/m5stats.txt
+++ b/tests/quick/00.hello/ref/mips/linux/simple-timing/m5stats.txt
@@ -1,31 +1,31 @@
---------- Begin Simulation Statistics ----------
-host_inst_rate 45085 # Simulator instruction rate (inst/s)
-host_mem_usage 155088 # Number of bytes of host memory used
-host_seconds 0.13 # Real time elapsed on the host
-host_tick_rate 101545982 # Simulator tick rate (ticks/s)
+host_inst_rate 269189 # Simulator instruction rate (inst/s)
+host_mem_usage 197500 # Number of bytes of host memory used
+host_seconds 0.02 # Real time elapsed on the host
+host_tick_rate 866482072 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 5657 # Number of instructions simulated
-sim_seconds 0.000014 # Number of seconds simulated
-sim_ticks 13544000 # Number of ticks simulated
+sim_seconds 0.000018 # Number of seconds simulated
+sim_ticks 18463000 # Number of ticks simulated
system.cpu.dcache.ReadReq_accesses 1130 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency 14000 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 13000 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency 25000 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 23000 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_hits 1048 # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency 1148000 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency 2050000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_rate 0.072566 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_misses 82 # number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_miss_latency 1066000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency 1886000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate 0.072566 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_misses 82 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_accesses 924 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency 14000 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 13000 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency 25000 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 23000 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_hits 860 # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency 896000 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency 1600000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_rate 0.069264 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_misses 64 # number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_miss_latency 832000 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency 1472000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_rate 0.069264 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_misses 64 # number of WriteReq MSHR misses
system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
@@ -37,29 +37,29 @@ system.cpu.dcache.blocked_cycles_no_mshrs 0 # n
system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.demand_accesses 2054 # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency 14000 # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 13000 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_miss_latency 25000 # average overall miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 23000 # average overall mshr miss latency
system.cpu.dcache.demand_hits 1908 # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency 2044000 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency 3650000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_rate 0.071081 # miss rate for demand accesses
system.cpu.dcache.demand_misses 146 # number of demand (read+write) misses
system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency 1898000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency 3358000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_rate 0.071081 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_misses 146 # number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.overall_accesses 2054 # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency 14000 # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 13000 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_miss_latency 25000 # average overall miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 23000 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.cpu.dcache.overall_hits 1908 # number of overall hits
-system.cpu.dcache.overall_miss_latency 2044000 # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency 3650000 # number of overall miss cycles
system.cpu.dcache.overall_miss_rate 0.071081 # miss rate for overall accesses
system.cpu.dcache.overall_misses 146 # number of overall misses
system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency 1898000 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency 3358000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_rate 0.071081 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_misses 146 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
@@ -76,18 +76,18 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0
system.cpu.dcache.replacements 0 # number of replacements
system.cpu.dcache.sampled_refs 132 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse 85.440937 # Cycle average of tags in use
+system.cpu.dcache.tagsinuse 84.706280 # Cycle average of tags in use
system.cpu.dcache.total_refs 1922 # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 0 # number of writebacks
system.cpu.icache.ReadReq_accesses 5658 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_avg_miss_latency 13986.798680 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 12986.798680 # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_miss_latency 24920.792079 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 22920.792079 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_hits 5355 # number of ReadReq hits
-system.cpu.icache.ReadReq_miss_latency 4238000 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency 7551000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_rate 0.053552 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_misses 303 # number of ReadReq misses
-system.cpu.icache.ReadReq_mshr_miss_latency 3935000 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency 6945000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate 0.053552 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_misses 303 # number of ReadReq MSHR misses
system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
@@ -99,29 +99,29 @@ system.cpu.icache.blocked_cycles_no_mshrs 0 # n
system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.demand_accesses 5658 # number of demand (read+write) accesses
-system.cpu.icache.demand_avg_miss_latency 13986.798680 # average overall miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 12986.798680 # average overall mshr miss latency
+system.cpu.icache.demand_avg_miss_latency 24920.792079 # average overall miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 22920.792079 # average overall mshr miss latency
system.cpu.icache.demand_hits 5355 # number of demand (read+write) hits
-system.cpu.icache.demand_miss_latency 4238000 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency 7551000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_rate 0.053552 # miss rate for demand accesses
system.cpu.icache.demand_misses 303 # number of demand (read+write) misses
system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_miss_latency 3935000 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency 6945000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_rate 0.053552 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_misses 303 # number of demand (read+write) MSHR misses
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.icache.overall_accesses 5658 # number of overall (read+write) accesses
-system.cpu.icache.overall_avg_miss_latency 13986.798680 # average overall miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 12986.798680 # average overall mshr miss latency
+system.cpu.icache.overall_avg_miss_latency 24920.792079 # average overall miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 22920.792079 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.cpu.icache.overall_hits 5355 # number of overall hits
-system.cpu.icache.overall_miss_latency 4238000 # number of overall miss cycles
+system.cpu.icache.overall_miss_latency 7551000 # number of overall miss cycles
system.cpu.icache.overall_miss_rate 0.053552 # miss rate for overall accesses
system.cpu.icache.overall_misses 303 # number of overall misses
system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.icache.overall_mshr_miss_latency 3935000 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency 6945000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_rate 0.053552 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_misses 303 # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
@@ -138,34 +138,34 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0
system.cpu.icache.replacements 13 # number of replacements
system.cpu.icache.sampled_refs 303 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse 136.727640 # Cycle average of tags in use
+system.cpu.icache.tagsinuse 135.936693 # Cycle average of tags in use
system.cpu.icache.total_refs 5355 # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks
system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.l2cache.ReadExReq_accesses 50 # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_avg_miss_latency 12000 # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency 22000 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 11000 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_miss_latency 600000 # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency 1100000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_misses 50 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_mshr_miss_latency 550000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_misses 50 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadReq_accesses 385 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_avg_miss_latency 12000 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency 22000 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 11000 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_hits 2 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_miss_latency 4596000 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency 8426000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_rate 0.994805 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_misses 383 # number of ReadReq misses
system.cpu.l2cache.ReadReq_mshr_miss_latency 4213000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.994805 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_misses 383 # number of ReadReq MSHR misses
system.cpu.l2cache.UpgradeReq_accesses 14 # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_avg_miss_latency 12000 # average UpgradeReq miss latency
+system.cpu.l2cache.UpgradeReq_avg_miss_latency 22000 # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 11000 # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_miss_latency 168000 # number of UpgradeReq miss cycles
+system.cpu.l2cache.UpgradeReq_miss_latency 308000 # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_misses 14 # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 154000 # number of UpgradeReq MSHR miss cycles
@@ -180,10 +180,10 @@ system.cpu.l2cache.blocked_cycles_no_mshrs 0 #
system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.demand_accesses 435 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_avg_miss_latency 12000 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency 22000 # average overall miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency 11000 # average overall mshr miss latency
system.cpu.l2cache.demand_hits 2 # number of demand (read+write) hits
-system.cpu.l2cache.demand_miss_latency 5196000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency 9526000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_rate 0.995402 # miss rate for demand accesses
system.cpu.l2cache.demand_misses 433 # number of demand (read+write) misses
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
@@ -194,11 +194,11 @@ system.cpu.l2cache.fast_writes 0 # nu
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.overall_accesses 435 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_avg_miss_latency 12000 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency 22000 # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 11000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.cpu.l2cache.overall_hits 2 # number of overall hits
-system.cpu.l2cache.overall_miss_latency 5196000 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency 9526000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_rate 0.995402 # miss rate for overall accesses
system.cpu.l2cache.overall_misses 433 # number of overall misses
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
@@ -219,12 +219,12 @@ system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0
system.cpu.l2cache.replacements 0 # number of replacements
system.cpu.l2cache.sampled_refs 369 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse 184.077317 # Cycle average of tags in use
+system.cpu.l2cache.tagsinuse 183.281817 # Cycle average of tags in use
system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.writebacks 0 # number of writebacks
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
-system.cpu.numCycles 13544000 # number of cpu cycles simulated
+system.cpu.numCycles 18463000 # number of cpu cycles simulated
system.cpu.num_insts 5657 # Number of instructions executed
system.cpu.num_refs 2055 # Number of memory references
system.cpu.workload.PROG:num_syscalls 13 # Number of system calls
diff --git a/tests/quick/00.hello/ref/mips/linux/simple-timing/stdout b/tests/quick/00.hello/ref/mips/linux/simple-timing/stdout
index c24f82c4f..ad6e002b5 100644
--- a/tests/quick/00.hello/ref/mips/linux/simple-timing/stdout
+++ b/tests/quick/00.hello/ref/mips/linux/simple-timing/stdout
@@ -6,9 +6,9 @@ The Regents of The University of Michigan
All Rights Reserved
-M5 compiled Aug 3 2007 04:06:41
-M5 started Fri Aug 3 04:31:10 2007
-M5 executing on zizzer.eecs.umich.edu
+M5 compiled Aug 12 2007 17:11:48
+M5 started Sun Aug 12 17:11:50 2007
+M5 executing on zeep
command line: build/MIPS_SE/m5.fast -d build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/simple-timing tests/run.py quick/00.hello/mips/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
-Exiting @ tick 13544000 because target called exit()
+Exiting @ tick 18463000 because target called exit()
diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-timing/config.ini b/tests/quick/00.hello/ref/sparc/linux/simple-timing/config.ini
index 4a945c9a3..719701ccd 100644
--- a/tests/quick/00.hello/ref/sparc/linux/simple-timing/config.ini
+++ b/tests/quick/00.hello/ref/sparc/linux/simple-timing/config.ini
@@ -34,10 +34,12 @@ type=BaseCache
addr_range=0:18446744073709551615
assoc=2
block_size=64
+cpu_side_filter_ranges=
hash_delay=1
latency=1000
lifo=false
max_miss_count=0
+mem_side_filter_ranges=
mshrs=10
prefetch_access=false
prefetch_cache_check_push=true
@@ -68,10 +70,12 @@ type=BaseCache
addr_range=0:18446744073709551615
assoc=2
block_size=64
+cpu_side_filter_ranges=
hash_delay=1
latency=1000
lifo=false
max_miss_count=0
+mem_side_filter_ranges=
mshrs=10
prefetch_access=false
prefetch_cache_check_push=true
@@ -102,10 +106,12 @@ type=BaseCache
addr_range=0:18446744073709551615
assoc=2
block_size=64
+cpu_side_filter_ranges=
hash_delay=1
latency=10000
lifo=false
max_miss_count=0
+mem_side_filter_ranges=
mshrs=10
prefetch_access=false
prefetch_cache_check_push=true
diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-timing/m5stats.txt b/tests/quick/00.hello/ref/sparc/linux/simple-timing/m5stats.txt
index 7810c3335..8907d716d 100644
--- a/tests/quick/00.hello/ref/sparc/linux/simple-timing/m5stats.txt
+++ b/tests/quick/00.hello/ref/sparc/linux/simple-timing/m5stats.txt
@@ -1,31 +1,31 @@
---------- Begin Simulation Statistics ----------
-host_inst_rate 36222 # Simulator instruction rate (inst/s)
-host_mem_usage 155556 # Number of bytes of host memory used
-host_seconds 0.13 # Real time elapsed on the host
-host_tick_rate 84966253 # Simulator tick rate (ticks/s)
+host_inst_rate 277220 # Simulator instruction rate (inst/s)
+host_mem_usage 197684 # Number of bytes of host memory used
+host_seconds 0.02 # Real time elapsed on the host
+host_tick_rate 892278360 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 4863 # Number of instructions simulated
-sim_seconds 0.000011 # Number of seconds simulated
-sim_ticks 11443000 # Number of ticks simulated
+sim_seconds 0.000016 # Number of seconds simulated
+sim_ticks 15912000 # Number of ticks simulated
system.cpu.dcache.ReadReq_accesses 608 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency 13962.962963 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 12962.962963 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency 24777.777778 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 22777.777778 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_hits 554 # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency 754000 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency 1338000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_rate 0.088816 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_misses 54 # number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_miss_latency 700000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency 1230000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate 0.088816 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_misses 54 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_accesses 661 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency 14000 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 13000 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency 25000 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 23000 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_hits 562 # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency 1386000 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency 2475000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_rate 0.149773 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_misses 99 # number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_miss_latency 1287000 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency 2277000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_rate 0.149773 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_misses 99 # number of WriteReq MSHR misses
system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
@@ -37,29 +37,29 @@ system.cpu.dcache.blocked_cycles_no_mshrs 0 # n
system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.demand_accesses 1269 # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency 13986.928105 # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 12986.928105 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_miss_latency 24921.568627 # average overall miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 22921.568627 # average overall mshr miss latency
system.cpu.dcache.demand_hits 1116 # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency 2140000 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency 3813000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_rate 0.120567 # miss rate for demand accesses
system.cpu.dcache.demand_misses 153 # number of demand (read+write) misses
system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency 1987000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency 3507000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_rate 0.120567 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_misses 153 # number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.overall_accesses 1269 # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency 13986.928105 # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 12986.928105 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_miss_latency 24921.568627 # average overall miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 22921.568627 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.cpu.dcache.overall_hits 1116 # number of overall hits
-system.cpu.dcache.overall_miss_latency 2140000 # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency 3813000 # number of overall miss cycles
system.cpu.dcache.overall_miss_rate 0.120567 # miss rate for overall accesses
system.cpu.dcache.overall_misses 153 # number of overall misses
system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency 1987000 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency 3507000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_rate 0.120567 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_misses 153 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
@@ -76,18 +76,18 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0
system.cpu.dcache.replacements 0 # number of replacements
system.cpu.dcache.sampled_refs 138 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse 83.865949 # Cycle average of tags in use
+system.cpu.dcache.tagsinuse 83.464621 # Cycle average of tags in use
system.cpu.dcache.total_refs 1131 # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 0 # number of writebacks
system.cpu.icache.ReadReq_accesses 4864 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_avg_miss_latency 13984.375000 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 12984.375000 # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_miss_latency 24906.250000 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 22906.250000 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_hits 4608 # number of ReadReq hits
-system.cpu.icache.ReadReq_miss_latency 3580000 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency 6376000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_rate 0.052632 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_misses 256 # number of ReadReq misses
-system.cpu.icache.ReadReq_mshr_miss_latency 3324000 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency 5864000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate 0.052632 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_misses 256 # number of ReadReq MSHR misses
system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
@@ -99,29 +99,29 @@ system.cpu.icache.blocked_cycles_no_mshrs 0 # n
system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.demand_accesses 4864 # number of demand (read+write) accesses
-system.cpu.icache.demand_avg_miss_latency 13984.375000 # average overall miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 12984.375000 # average overall mshr miss latency
+system.cpu.icache.demand_avg_miss_latency 24906.250000 # average overall miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 22906.250000 # average overall mshr miss latency
system.cpu.icache.demand_hits 4608 # number of demand (read+write) hits
-system.cpu.icache.demand_miss_latency 3580000 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency 6376000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_rate 0.052632 # miss rate for demand accesses
system.cpu.icache.demand_misses 256 # number of demand (read+write) misses
system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_miss_latency 3324000 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency 5864000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_rate 0.052632 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_misses 256 # number of demand (read+write) MSHR misses
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.icache.overall_accesses 4864 # number of overall (read+write) accesses
-system.cpu.icache.overall_avg_miss_latency 13984.375000 # average overall miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 12984.375000 # average overall mshr miss latency
+system.cpu.icache.overall_avg_miss_latency 24906.250000 # average overall miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 22906.250000 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.cpu.icache.overall_hits 4608 # number of overall hits
-system.cpu.icache.overall_miss_latency 3580000 # number of overall miss cycles
+system.cpu.icache.overall_miss_latency 6376000 # number of overall miss cycles
system.cpu.icache.overall_miss_rate 0.052632 # miss rate for overall accesses
system.cpu.icache.overall_misses 256 # number of overall misses
system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.icache.overall_mshr_miss_latency 3324000 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency 5864000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_rate 0.052632 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_misses 256 # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
@@ -138,34 +138,34 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0
system.cpu.icache.replacements 0 # number of replacements
system.cpu.icache.sampled_refs 256 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse 114.646434 # Cycle average of tags in use
+system.cpu.icache.tagsinuse 114.953503 # Cycle average of tags in use
system.cpu.icache.total_refs 4608 # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks
system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.l2cache.ReadExReq_accesses 84 # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_avg_miss_latency 12000 # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency 22000 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 11000 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_miss_latency 1008000 # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency 1848000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_misses 84 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_mshr_miss_latency 924000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_misses 84 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadReq_accesses 310 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_avg_miss_latency 12000 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency 22000 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 11000 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_hits 3 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_miss_latency 3684000 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency 6754000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_rate 0.990323 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_misses 307 # number of ReadReq misses
system.cpu.l2cache.ReadReq_mshr_miss_latency 3377000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.990323 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_misses 307 # number of ReadReq MSHR misses
system.cpu.l2cache.UpgradeReq_accesses 15 # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_avg_miss_latency 12000 # average UpgradeReq miss latency
+system.cpu.l2cache.UpgradeReq_avg_miss_latency 22000 # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 11000 # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_miss_latency 180000 # number of UpgradeReq miss cycles
+system.cpu.l2cache.UpgradeReq_miss_latency 330000 # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_misses 15 # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 165000 # number of UpgradeReq MSHR miss cycles
@@ -180,10 +180,10 @@ system.cpu.l2cache.blocked_cycles_no_mshrs 0 #
system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.demand_accesses 394 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_avg_miss_latency 12000 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency 22000 # average overall miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency 11000 # average overall mshr miss latency
system.cpu.l2cache.demand_hits 3 # number of demand (read+write) hits
-system.cpu.l2cache.demand_miss_latency 4692000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency 8602000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_rate 0.992386 # miss rate for demand accesses
system.cpu.l2cache.demand_misses 391 # number of demand (read+write) misses
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
@@ -194,11 +194,11 @@ system.cpu.l2cache.fast_writes 0 # nu
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.overall_accesses 394 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_avg_miss_latency 12000 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency 22000 # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 11000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.cpu.l2cache.overall_hits 3 # number of overall hits
-system.cpu.l2cache.overall_miss_latency 4692000 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency 8602000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_rate 0.992386 # miss rate for overall accesses
system.cpu.l2cache.overall_misses 391 # number of overall misses
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
@@ -219,12 +219,12 @@ system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0
system.cpu.l2cache.replacements 0 # number of replacements
system.cpu.l2cache.sampled_refs 292 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse 133.135118 # Cycle average of tags in use
+system.cpu.l2cache.tagsinuse 133.743977 # Cycle average of tags in use
system.cpu.l2cache.total_refs 3 # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.writebacks 0 # number of writebacks
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
-system.cpu.numCycles 11443000 # number of cpu cycles simulated
+system.cpu.numCycles 15912000 # number of cpu cycles simulated
system.cpu.num_insts 4863 # Number of instructions executed
system.cpu.num_refs 1269 # Number of memory references
system.cpu.workload.PROG:num_syscalls 11 # Number of system calls
diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-timing/stdout b/tests/quick/00.hello/ref/sparc/linux/simple-timing/stdout
index 1b34d79bb..85df476d4 100644
--- a/tests/quick/00.hello/ref/sparc/linux/simple-timing/stdout
+++ b/tests/quick/00.hello/ref/sparc/linux/simple-timing/stdout
@@ -5,9 +5,9 @@ The Regents of The University of Michigan
All Rights Reserved
-M5 compiled Aug 3 2007 04:11:25
-M5 started Fri Aug 3 04:31:19 2007
-M5 executing on zizzer.eecs.umich.edu
+M5 compiled Aug 12 2007 12:23:15
+M5 started Sun Aug 12 16:58:40 2007
+M5 executing on zeep
command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/00.hello/sparc/linux/simple-timing tests/run.py quick/00.hello/sparc/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
-Exiting @ tick 11443000 because target called exit()
+Exiting @ tick 15912000 because target called exit()