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-rw-r--r--tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/config.ini233
-rw-r--r--tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/ruby.stats848
-rwxr-xr-xtests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/simout8
-rw-r--r--tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/stats.txt8
-rw-r--r--tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/config.ini225
-rw-r--r--tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/ruby.stats2364
-rwxr-xr-xtests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/simout8
-rw-r--r--tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/stats.txt8
-rw-r--r--tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/config.ini246
-rw-r--r--tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/ruby.stats1697
-rwxr-xr-xtests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/simout10
-rw-r--r--tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/stats.txt14
-rw-r--r--tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/config.ini209
-rw-r--r--tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/ruby.stats1137
-rwxr-xr-xtests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/simout12
-rw-r--r--tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/stats.txt14
-rw-r--r--tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/config.ini233
-rw-r--r--tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/ruby.stats848
-rwxr-xr-xtests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/simout8
-rw-r--r--tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/stats.txt8
-rw-r--r--tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/config.ini225
-rw-r--r--tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/ruby.stats2356
-rwxr-xr-xtests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/simout8
-rw-r--r--tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/stats.txt8
-rw-r--r--tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/config.ini246
-rw-r--r--tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/ruby.stats1693
-rwxr-xr-xtests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/simout10
-rw-r--r--tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/stats.txt14
-rw-r--r--tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/config.ini211
-rw-r--r--tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/ruby.stats1131
-rwxr-xr-xtests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/simout10
-rw-r--r--tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/stats.txt14
32 files changed, 7418 insertions, 6646 deletions
diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/config.ini b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/config.ini
index f712efbf6..588a2547e 100644
--- a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/config.ini
+++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/config.ini
@@ -5,7 +5,7 @@ dummy=0
[system]
type=System
-children=cpu physmem ruby
+children=cpu dir_cntrl0 l1_cntrl0 l2_cntrl0 physmem ruby
mem_mode=timing
physmem=system.physmem
@@ -32,8 +32,8 @@ progress_interval=0
system=system
tracer=system.cpu.tracer
workload=system.cpu.workload
-dcache_port=system.ruby.network.topology.ext_links0.ext_node.sequencer.port[1]
-icache_port=system.ruby.network.topology.ext_links0.ext_node.sequencer.port[0]
+dcache_port=system.l1_cntrl0.sequencer.port[1]
+icache_port=system.l1_cntrl0.sequencer.port[0]
[system.cpu.dtb]
type=AlphaTLB
@@ -54,7 +54,7 @@ egid=100
env=
errout=cerr
euid=100
-executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/hello/bin/alpha/linux/hello
+executable=tests/test-progs/hello/bin/alpha/linux/hello
gid=100
input=cin
max_stack_size=67108864
@@ -65,6 +65,114 @@ simpoint=0
system=system
uid=100
+[system.dir_cntrl0]
+type=Directory_Controller
+children=directory memBuffer
+buffer_size=0
+directory=system.dir_cntrl0.directory
+directory_latency=6
+memBuffer=system.dir_cntrl0.memBuffer
+number_of_TBEs=256
+recycle_latency=10
+to_mem_ctrl_latency=1
+transitions_per_cycle=32
+version=0
+
+[system.dir_cntrl0.directory]
+type=RubyDirectoryMemory
+map_levels=4
+numa_high_bit=6
+size=134217728
+use_map=false
+version=0
+
+[system.dir_cntrl0.memBuffer]
+type=RubyMemoryControl
+bank_bit_0=8
+bank_busy_time=11
+bank_queue_size=12
+banks_per_rank=8
+basic_bus_busy_time=2
+dimm_bit_0=12
+dimms_per_channel=2
+mem_bus_cycle_multiplier=10
+mem_ctl_latency=12
+mem_fixed_delay=0
+mem_random_arbitrate=0
+rank_bit_0=11
+rank_rank_delay=1
+ranks_per_dimm=2
+read_write_delay=2
+refresh_period=1560
+tFaw=0
+version=0
+
+[system.l1_cntrl0]
+type=L1Cache_Controller
+children=sequencer
+L1DcacheMemory=system.l1_cntrl0.sequencer.dcache
+L1IcacheMemory=system.l1_cntrl0.sequencer.icache
+buffer_size=0
+l1_request_latency=2
+l1_response_latency=2
+l2_select_num_bits=0
+number_of_TBEs=256
+recycle_latency=10
+sequencer=system.l1_cntrl0.sequencer
+to_l2_latency=1
+transitions_per_cycle=32
+version=0
+
+[system.l1_cntrl0.sequencer]
+type=RubySequencer
+children=dcache icache
+dcache=system.l1_cntrl0.sequencer.dcache
+deadlock_threshold=500000
+icache=system.l1_cntrl0.sequencer.icache
+max_outstanding_requests=16
+physmem=system.physmem
+using_ruby_tester=false
+version=0
+physMemPort=system.physmem.port[0]
+port=system.cpu.icache_port system.cpu.dcache_port
+
+[system.l1_cntrl0.sequencer.dcache]
+type=RubyCache
+assoc=2
+latency=3
+replacement_policy=PSEUDO_LRU
+size=256
+start_index_bit=6
+
+[system.l1_cntrl0.sequencer.icache]
+type=RubyCache
+assoc=2
+latency=3
+replacement_policy=PSEUDO_LRU
+size=256
+start_index_bit=6
+
+[system.l2_cntrl0]
+type=L2Cache_Controller
+children=L2cacheMemory
+L2cacheMemory=system.l2_cntrl0.L2cacheMemory
+buffer_size=0
+l2_request_latency=2
+l2_response_latency=2
+number_of_TBEs=256
+recycle_latency=10
+to_l1_latency=1
+transitions_per_cycle=32
+version=0
+
+[system.l2_cntrl0.L2cacheMemory]
+type=RubyCache
+assoc=2
+latency=15
+replacement_policy=PSEUDO_LRU
+size=512
+start_index_bit=6
+
[system.physmem]
type=PhysicalMemory
file=
@@ -73,7 +181,7 @@ latency_var=0
null=false
range=0:134217727
zero=false
-port=system.ruby.network.topology.ext_links0.ext_node.sequencer.physMemPort
+port=system.l1_cntrl0.sequencer.physMemPort
[system.ruby]
type=RubySystem
@@ -83,6 +191,7 @@ clock=1
debug=system.ruby.debug
mem_size=134217728
network=system.ruby.network
+no_mem_vec=false
profiler=system.ruby.profiler
random_seed=1234
randomization=false
@@ -100,7 +209,7 @@ verbosity_string=none
[system.ruby.network]
type=SimpleNetwork
children=topology
-adaptive_routing=true
+adaptive_routing=false
buffer_size=0
control_msg_size=8
endpoint_bandwidth=10000
@@ -113,138 +222,34 @@ type=Topology
children=ext_links0 ext_links1 ext_links2 int_links0 int_links1 int_links2
ext_links=system.ruby.network.topology.ext_links0 system.ruby.network.topology.ext_links1 system.ruby.network.topology.ext_links2
int_links=system.ruby.network.topology.int_links0 system.ruby.network.topology.int_links1 system.ruby.network.topology.int_links2
+name=Crossbar
num_int_nodes=4
print_config=false
[system.ruby.network.topology.ext_links0]
type=ExtLink
-children=ext_node
bw_multiplier=64
-ext_node=system.ruby.network.topology.ext_links0.ext_node
+ext_node=system.l1_cntrl0
int_node=0
latency=1
weight=1
-[system.ruby.network.topology.ext_links0.ext_node]
-type=L1Cache_Controller
-children=sequencer
-L1DcacheMemory=system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache
-L1IcacheMemory=system.ruby.network.topology.ext_links0.ext_node.sequencer.icache
-buffer_size=0
-l1_request_latency=2
-l1_response_latency=2
-l2_select_num_bits=0
-number_of_TBEs=256
-recycle_latency=10
-sequencer=system.ruby.network.topology.ext_links0.ext_node.sequencer
-to_l2_latency=1
-transitions_per_cycle=32
-version=0
-
-[system.ruby.network.topology.ext_links0.ext_node.sequencer]
-type=RubySequencer
-children=dcache icache
-dcache=system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache
-deadlock_threshold=500000
-icache=system.ruby.network.topology.ext_links0.ext_node.sequencer.icache
-max_outstanding_requests=16
-physmem=system.physmem
-using_ruby_tester=false
-version=0
-physMemPort=system.physmem.port[0]
-port=system.cpu.icache_port system.cpu.dcache_port
-
-[system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache]
-type=RubyCache
-assoc=2
-latency=3
-replacement_policy=PSEUDO_LRU
-size=256
-
-[system.ruby.network.topology.ext_links0.ext_node.sequencer.icache]
-type=RubyCache
-assoc=2
-latency=3
-replacement_policy=PSEUDO_LRU
-size=256
-
[system.ruby.network.topology.ext_links1]
type=ExtLink
-children=ext_node
bw_multiplier=64
-ext_node=system.ruby.network.topology.ext_links1.ext_node
+ext_node=system.l2_cntrl0
int_node=1
latency=1
weight=1
-[system.ruby.network.topology.ext_links1.ext_node]
-type=L2Cache_Controller
-children=L2cacheMemory
-L2cacheMemory=system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory
-buffer_size=0
-l2_request_latency=2
-l2_response_latency=2
-number_of_TBEs=256
-recycle_latency=10
-to_l1_latency=1
-transitions_per_cycle=32
-version=0
-
-[system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory]
-type=RubyCache
-assoc=2
-latency=15
-replacement_policy=PSEUDO_LRU
-size=512
-
[system.ruby.network.topology.ext_links2]
type=ExtLink
-children=ext_node
bw_multiplier=64
-ext_node=system.ruby.network.topology.ext_links2.ext_node
+ext_node=system.dir_cntrl0
int_node=2
latency=1
weight=1
-[system.ruby.network.topology.ext_links2.ext_node]
-type=Directory_Controller
-children=directory memBuffer
-buffer_size=0
-directory=system.ruby.network.topology.ext_links2.ext_node.directory
-directory_latency=6
-memBuffer=system.ruby.network.topology.ext_links2.ext_node.memBuffer
-number_of_TBEs=256
-recycle_latency=10
-to_mem_ctrl_latency=1
-transitions_per_cycle=32
-version=0
-
-[system.ruby.network.topology.ext_links2.ext_node.directory]
-type=RubyDirectoryMemory
-size=134217728
-version=0
-
-[system.ruby.network.topology.ext_links2.ext_node.memBuffer]
-type=RubyMemoryControl
-bank_bit_0=8
-bank_busy_time=11
-bank_queue_size=12
-banks_per_rank=8
-basic_bus_busy_time=2
-dimm_bit_0=12
-dimms_per_channel=2
-mem_bus_cycle_multiplier=10
-mem_ctl_latency=12
-mem_fixed_delay=0
-mem_random_arbitrate=0
-rank_bit_0=11
-rank_rank_delay=1
-ranks_per_dimm=2
-read_write_delay=2
-refresh_period=1560
-tFaw=0
-version=0
-
[system.ruby.network.topology.int_links0]
type=IntLink
bw_multiplier=16
diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/ruby.stats b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/ruby.stats
index 0defa99bd..347214713 100644
--- a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/ruby.stats
+++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/ruby.stats
@@ -13,7 +13,7 @@ RubySystem config:
Network Configuration
---------------------
network: SIMPLE_NETWORK
-topology:
+topology: Crossbar
virtual_net_0: active, unordered
virtual_net_1: active, unordered
@@ -34,7 +34,7 @@ periodic_stats_period: 1000000
================ End RubySystem Configuration Print ================
-Real time: Jan/28/2010 13:57:44
+Real time: Aug/05/2010 10:23:43
Profiler Stats
--------------
@@ -43,31 +43,20 @@ Elapsed_time_in_minutes: 0.0166667
Elapsed_time_in_hours: 0.000277778
Elapsed_time_in_days: 1.15741e-05
-Virtual_time_in_seconds: 0.95
-Virtual_time_in_minutes: 0.0158333
-Virtual_time_in_hours: 0.000263889
-Virtual_time_in_days: 1.09954e-05
+Virtual_time_in_seconds: 0.32
+Virtual_time_in_minutes: 0.00533333
+Virtual_time_in_hours: 8.88889e-05
+Virtual_time_in_days: 3.7037e-06
Ruby_current_time: 275313
Ruby_start_time: 0
Ruby_cycles: 275313
-mbytes_resident: 34.4609
-mbytes_total: 34.4688
+mbytes_resident: 34.8867
+mbytes_total: 34.8945
resident_ratio: 1
-Total_misses: 0
-total_misses: 0 [ 0 ]
-user_misses: 0 [ 0 ]
-supervisor_misses: 0 [ 0 ]
-
-ruby_cycles_executed: 275314 [ 275314 ]
-
-transactions_started: 0 [ 0 ]
-transactions_ended: 0 [ 0 ]
-cycles_per_transaction: 0 [ 0 ]
-misses_per_transaction: 0 [ 0 ]
-
+ruby_cycles_executed: [ 275314 ]
Busy Controller Counts:
L1Cache-0:0
@@ -82,9 +71,23 @@ sequencer_requests_outstanding: [binsize: 1 max: 1 count: 8465 average: 1 |
All Non-Zero Cycle Demand Cache Accesses
----------------------------------------
miss_latency: [binsize: 2 max: 281 count: 8464 average: 31.5275 | standard deviation: 62.4195 | 0 6974 0 0 0 0 0 0 0 30 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 156 439 246 330 220 8 7 9 11 3 2 9 4 5 1 0 0 1 1 0 0 0 0 0 0 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 0 0 1 0 0 0 0 1 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
-miss_latency_1: [binsize: 2 max: 269 count: 6414 average: 20.6784 | standard deviation: 51.1007 | 0 5723 0 0 0 0 0 0 0 5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 59 203 95 191 106 4 5 4 6 2 1 1 1 4 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
-miss_latency_2: [binsize: 2 max: 281 count: 1185 average: 82.5848 | standard deviation: 82.5677 | 0 602 0 0 0 0 0 0 0 13 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 64 191 73 123 92 4 2 3 3 1 1 7 2 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
-miss_latency_3: [binsize: 2 max: 215 count: 865 average: 42.0289 | standard deviation: 69.8546 | 0 649 0 0 0 0 0 0 0 12 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 33 45 78 16 22 0 0 2 2 0 0 1 1 1 0 0 0 1 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency_IFETCH: [binsize: 2 max: 269 count: 6414 average: 20.6784 | standard deviation: 51.1007 | 0 5723 0 0 0 0 0 0 0 5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 59 203 95 191 106 4 5 4 6 2 1 1 1 4 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency_LD: [binsize: 2 max: 281 count: 1185 average: 82.5848 | standard deviation: 82.5677 | 0 602 0 0 0 0 0 0 0 13 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 64 191 73 123 92 4 2 3 3 1 1 7 2 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency_ST: [binsize: 2 max: 215 count: 865 average: 42.0289 | standard deviation: 69.8546 | 0 649 0 0 0 0 0 0 0 12 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 33 45 78 16 22 0 0 2 2 0 0 1 1 1 0 0 0 1 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency_NULL: [binsize: 2 max: 281 count: 8464 average: 31.5275 | standard deviation: 62.4195 | 0 6974 0 0 0 0 0 0 0 30 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 156 439 246 330 220 8 7 9 11 3 2 9 4 5 1 0 0 1 1 0 0 0 0 0 0 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 0 0 1 0 0 0 0 1 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency_wCC_issue_to_initial_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+miss_latency_wCC_initial_forward_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+miss_latency_wCC_forward_to_first_response: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+miss_latency_wCC_first_response_to_completion: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+imcomplete_wCC_Times: 0
+miss_latency_dir_issue_to_initial_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+miss_latency_dir_initial_forward_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+miss_latency_dir_forward_to_first_response: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+miss_latency_dir_first_response_to_completion: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+imcomplete_dir_Times: 0
+miss_latency_IFETCH_NULL: [binsize: 2 max: 269 count: 6414 average: 20.6784 | standard deviation: 51.1007 | 0 5723 0 0 0 0 0 0 0 5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 59 203 95 191 106 4 5 4 6 2 1 1 1 4 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency_LD_NULL: [binsize: 2 max: 281 count: 1185 average: 82.5848 | standard deviation: 82.5677 | 0 602 0 0 0 0 0 0 0 13 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 64 191 73 123 92 4 2 3 3 1 1 7 2 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency_ST_NULL: [binsize: 2 max: 215 count: 865 average: 42.0289 | standard deviation: 69.8546 | 0 649 0 0 0 0 0 0 0 12 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 33 45 78 16 22 0 0 2 2 0 0 1 1 1 0 0 0 1 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
All Non-Zero Cycle SW Prefetch Requests
------------------------------------
@@ -116,8 +119,8 @@ Resource Usage
page_size: 4096
user_time: 0
system_time: 0
-page_reclaims: 7392
-page_faults: 2212
+page_reclaims: 7576
+page_faults: 2166
swaps: 0
block_inputs: 0
block_outputs: 0
@@ -125,6 +128,14 @@ block_outputs: 0
Network Stats
-------------
+total_msg_count_Control: 8850 70800
+total_msg_count_Request_Control: 3123 24984
+total_msg_count_Response_Data: 9681 697032
+total_msg_count_Response_Control: 14286 114288
+total_msg_count_Writeback_Data: 864 62208
+total_msg_count_Writeback_Control: 867 6936
+total_msgs: 37671 total_bytes: 976248
+
switch_0_inlinks: 2
switch_0_outlinks: 2
links_utilized_percent_switch_0: 0.0889147
@@ -186,352 +197,346 @@ links_utilized_percent_switch_3: 0.246247
outgoing_messages_switch_3_link_2_Response_Data: 277 19944 [ 0 277 0 0 0 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_3_link_2_Response_Control: 1175 9400 [ 0 1175 0 0 0 0 0 0 0 0 ] base_latency: 1
-Cache Stats: system.ruby.network.topology.ext_links0.ext_node.sequencer.icache
- system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_misses: 0
- system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_demand_misses: 0
- system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_prefetches: 0
- system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_sw_prefetches: 0
- system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_hw_prefetches: 0
- system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_misses_per_transaction: nan
+Cache Stats: system.l1_cntrl0.sequencer.icache
+ system.l1_cntrl0.sequencer.icache_total_misses: 0
+ system.l1_cntrl0.sequencer.icache_total_demand_misses: 0
+ system.l1_cntrl0.sequencer.icache_total_prefetches: 0
+ system.l1_cntrl0.sequencer.icache_total_sw_prefetches: 0
+ system.l1_cntrl0.sequencer.icache_total_hw_prefetches: 0
- system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
-Cache Stats: system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache
- system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_misses: 0
- system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_demand_misses: 0
- system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_prefetches: 0
- system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_sw_prefetches: 0
- system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_hw_prefetches: 0
- system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_misses_per_transaction: nan
+Cache Stats: system.l1_cntrl0.sequencer.dcache
+ system.l1_cntrl0.sequencer.dcache_total_misses: 0
+ system.l1_cntrl0.sequencer.dcache_total_demand_misses: 0
+ system.l1_cntrl0.sequencer.dcache_total_prefetches: 0
+ system.l1_cntrl0.sequencer.dcache_total_sw_prefetches: 0
+ system.l1_cntrl0.sequencer.dcache_total_hw_prefetches: 0
- system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
- --- L1Cache 0 ---
+ --- L1Cache ---
- Event Counts -
-Load 1185
-Ifetch 6414
-Store 865
-Inv 1041
-L1_Replacement 1354
-Fwd_GETX 0
-Fwd_GETS 0
-Fwd_GET_INSTR 0
-Data 0
-Data_Exclusive 583
-DataS_fromL1 0
-Data_all_Acks 907
-Ack 0
-Ack_all 0
-WB_Ack 436
+Load [1185 ] 1185
+Ifetch [6414 ] 6414
+Store [865 ] 865
+Inv [1041 ] 1041
+L1_Replacement [1354 ] 1354
+Fwd_GETX [0 ] 0
+Fwd_GETS [0 ] 0
+Fwd_GET_INSTR [0 ] 0
+Data [0 ] 0
+Data_Exclusive [583 ] 583
+DataS_fromL1 [0 ] 0
+Data_all_Acks [907 ] 907
+Ack [0 ] 0
+Ack_all [0 ] 0
+WB_Ack [436 ] 436
- Transitions -
-NP Load 525
-NP Ifetch 646
-NP Store 191
-NP Inv 356
-NP L1_Replacement 0 <--
-
-I Load 58
-I Ifetch 45
-I Store 25
-I Inv 0 <--
-I L1_Replacement 556
-
-S Load 0 <--
-S Ifetch 5723
-S Store 0 <--
-S Inv 325
-S L1_Replacement 362
-
-E Load 454
-E Ifetch 0 <--
-E Store 71
-E Inv 219
-E L1_Replacement 291
-E Fwd_GETX 0 <--
-E Fwd_GETS 0 <--
-E Fwd_GET_INSTR 0 <--
-
-M Load 148
-M Ifetch 0 <--
-M Store 578
-M Inv 141
-M L1_Replacement 145
-M Fwd_GETX 0 <--
-M Fwd_GETS 0 <--
-M Fwd_GET_INSTR 0 <--
-
-IS Load 0 <--
-IS Ifetch 0 <--
-IS Store 0 <--
-IS Inv 0 <--
-IS L1_Replacement 0 <--
-IS Data_Exclusive 583
-IS DataS_fromL1 0 <--
-IS Data_all_Acks 691
-
-IM Load 0 <--
-IM Ifetch 0 <--
-IM Store 0 <--
-IM Inv 0 <--
-IM L1_Replacement 0 <--
-IM Data 0 <--
-IM Data_all_Acks 216
-IM Ack 0 <--
-
-SM Load 0 <--
-SM Ifetch 0 <--
-SM Store 0 <--
-SM Inv 0 <--
-SM L1_Replacement 0 <--
-SM Ack 0 <--
-SM Ack_all 0 <--
-
-IS_I Load 0 <--
-IS_I Ifetch 0 <--
-IS_I Store 0 <--
-IS_I Inv 0 <--
-IS_I L1_Replacement 0 <--
-IS_I Data_Exclusive 0 <--
-IS_I DataS_fromL1 0 <--
-IS_I Data_all_Acks 0 <--
-
-M_I Load 0 <--
-M_I Ifetch 0 <--
-M_I Store 0 <--
-M_I Inv 0 <--
-M_I L1_Replacement 0 <--
-M_I Fwd_GETX 0 <--
-M_I Fwd_GETS 0 <--
-M_I Fwd_GET_INSTR 0 <--
-M_I WB_Ack 436
-
-E_I Load 0 <--
-E_I Ifetch 0 <--
-E_I Store 0 <--
-E_I L1_Replacement 0 <--
-
-Cache Stats: system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory
- system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_total_misses: 0
- system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_total_demand_misses: 0
- system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_total_prefetches: 0
- system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_total_sw_prefetches: 0
- system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_total_hw_prefetches: 0
- system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_misses_per_transaction: nan
-
- system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
-
- --- L2Cache 0 ---
+NP Load [525 ] 525
+NP Ifetch [646 ] 646
+NP Store [191 ] 191
+NP Inv [356 ] 356
+NP L1_Replacement [0 ] 0
+
+I Load [58 ] 58
+I Ifetch [45 ] 45
+I Store [25 ] 25
+I Inv [0 ] 0
+I L1_Replacement [556 ] 556
+
+S Load [0 ] 0
+S Ifetch [5723 ] 5723
+S Store [0 ] 0
+S Inv [325 ] 325
+S L1_Replacement [362 ] 362
+
+E Load [454 ] 454
+E Ifetch [0 ] 0
+E Store [71 ] 71
+E Inv [219 ] 219
+E L1_Replacement [291 ] 291
+E Fwd_GETX [0 ] 0
+E Fwd_GETS [0 ] 0
+E Fwd_GET_INSTR [0 ] 0
+
+M Load [148 ] 148
+M Ifetch [0 ] 0
+M Store [578 ] 578
+M Inv [141 ] 141
+M L1_Replacement [145 ] 145
+M Fwd_GETX [0 ] 0
+M Fwd_GETS [0 ] 0
+M Fwd_GET_INSTR [0 ] 0
+
+IS Load [0 ] 0
+IS Ifetch [0 ] 0
+IS Store [0 ] 0
+IS Inv [0 ] 0
+IS L1_Replacement [0 ] 0
+IS Data_Exclusive [583 ] 583
+IS DataS_fromL1 [0 ] 0
+IS Data_all_Acks [691 ] 691
+
+IM Load [0 ] 0
+IM Ifetch [0 ] 0
+IM Store [0 ] 0
+IM Inv [0 ] 0
+IM L1_Replacement [0 ] 0
+IM Data [0 ] 0
+IM Data_all_Acks [216 ] 216
+IM Ack [0 ] 0
+
+SM Load [0 ] 0
+SM Ifetch [0 ] 0
+SM Store [0 ] 0
+SM Inv [0 ] 0
+SM L1_Replacement [0 ] 0
+SM Ack [0 ] 0
+SM Ack_all [0 ] 0
+
+IS_I Load [0 ] 0
+IS_I Ifetch [0 ] 0
+IS_I Store [0 ] 0
+IS_I Inv [0 ] 0
+IS_I L1_Replacement [0 ] 0
+IS_I Data_Exclusive [0 ] 0
+IS_I DataS_fromL1 [0 ] 0
+IS_I Data_all_Acks [0 ] 0
+
+M_I Load [0 ] 0
+M_I Ifetch [0 ] 0
+M_I Store [0 ] 0
+M_I Inv [0 ] 0
+M_I L1_Replacement [0 ] 0
+M_I Fwd_GETX [0 ] 0
+M_I Fwd_GETS [0 ] 0
+M_I Fwd_GET_INSTR [0 ] 0
+M_I WB_Ack [436 ] 436
+
+E_I Load [0 ] 0
+E_I Ifetch [0 ] 0
+E_I Store [0 ] 0
+E_I L1_Replacement [0 ] 0
+
+Cache Stats: system.l2_cntrl0.L2cacheMemory
+ system.l2_cntrl0.L2cacheMemory_total_misses: 0
+ system.l2_cntrl0.L2cacheMemory_total_demand_misses: 0
+ system.l2_cntrl0.L2cacheMemory_total_prefetches: 0
+ system.l2_cntrl0.L2cacheMemory_total_sw_prefetches: 0
+ system.l2_cntrl0.L2cacheMemory_total_hw_prefetches: 0
+
+
+ --- L2Cache ---
- Event Counts -
-L1_GET_INSTR 691
-L1_GETS 592
-L1_GETX 220
-L1_UPGRADE 0
-L1_PUTX 436
-L1_PUTX_old 0
-Fwd_L1_GETX 0
-Fwd_L1_GETS 0
-Fwd_L1_GET_INSTR 0
-L2_Replacement 142
-L2_Replacement_clean 1310
-Mem_Data 1460
-Mem_Ack 1452
-WB_Data 141
-WB_Data_clean 0
-Ack 0
-Ack_all 900
-Unblock 0
-Unblock_Cancel 0
-Exclusive_Unblock 799
-MEM_Inv 0
+L1_GET_INSTR [691 ] 691
+L1_GETS [592 ] 592
+L1_GETX [220 ] 220
+L1_UPGRADE [0 ] 0
+L1_PUTX [436 ] 436
+L1_PUTX_old [0 ] 0
+Fwd_L1_GETX [0 ] 0
+Fwd_L1_GETS [0 ] 0
+Fwd_L1_GET_INSTR [0 ] 0
+L2_Replacement [142 ] 142
+L2_Replacement_clean [1310 ] 1310
+Mem_Data [1460 ] 1460
+Mem_Ack [1452 ] 1452
+WB_Data [141 ] 141
+WB_Data_clean [0 ] 0
+Ack [0 ] 0
+Ack_all [900 ] 900
+Unblock [0 ] 0
+Unblock_Cancel [0 ] 0
+Exclusive_Unblock [799 ] 799
+MEM_Inv [0 ] 0
- Transitions -
-NP L1_GET_INSTR 686
-NP L1_GETS 570
-NP L1_GETX 204
-NP L1_PUTX 0 <--
-NP L1_PUTX_old 0 <--
-
-SS L1_GET_INSTR 5
-SS L1_GETS 0 <--
-SS L1_GETX 0 <--
-SS L1_UPGRADE 0 <--
-SS L1_PUTX 0 <--
-SS L1_PUTX_old 0 <--
-SS L2_Replacement 0 <--
-SS L2_Replacement_clean 681
-SS MEM_Inv 0 <--
-
-M L1_GET_INSTR 0 <--
-M L1_GETS 13
-M L1_GETX 12
-M L1_PUTX 0 <--
-M L1_PUTX_old 0 <--
-M L2_Replacement 134
-M L2_Replacement_clean 277
-M MEM_Inv 0 <--
-
-MT L1_GET_INSTR 0 <--
-MT L1_GETS 0 <--
-MT L1_GETX 0 <--
-MT L1_PUTX 436
-MT L1_PUTX_old 0 <--
-MT L2_Replacement 8
-MT L2_Replacement_clean 352
-MT MEM_Inv 0 <--
-
-M_I L1_GET_INSTR 0 <--
-M_I L1_GETS 9
-M_I L1_GETX 4
-M_I L1_UPGRADE 0 <--
-M_I L1_PUTX 0 <--
-M_I L1_PUTX_old 0 <--
-M_I Mem_Ack 1452
-M_I MEM_Inv 0 <--
-
-MT_I L1_GET_INSTR 0 <--
-MT_I L1_GETS 0 <--
-MT_I L1_GETX 0 <--
-MT_I L1_UPGRADE 0 <--
-MT_I L1_PUTX 0 <--
-MT_I L1_PUTX_old 0 <--
-MT_I WB_Data 6
-MT_I WB_Data_clean 0 <--
-MT_I Ack_all 2
-MT_I MEM_Inv 0 <--
-
-MCT_I L1_GET_INSTR 0 <--
-MCT_I L1_GETS 0 <--
-MCT_I L1_GETX 0 <--
-MCT_I L1_UPGRADE 0 <--
-MCT_I L1_PUTX 0 <--
-MCT_I L1_PUTX_old 0 <--
-MCT_I WB_Data 135
-MCT_I WB_Data_clean 0 <--
-MCT_I Ack_all 217
-
-I_I L1_GET_INSTR 0 <--
-I_I L1_GETS 0 <--
-I_I L1_GETX 0 <--
-I_I L1_UPGRADE 0 <--
-I_I L1_PUTX 0 <--
-I_I L1_PUTX_old 0 <--
-I_I Ack 0 <--
-I_I Ack_all 681
-
-S_I L1_GET_INSTR 0 <--
-S_I L1_GETS 0 <--
-S_I L1_GETX 0 <--
-S_I L1_UPGRADE 0 <--
-S_I L1_PUTX 0 <--
-S_I L1_PUTX_old 0 <--
-S_I Ack 0 <--
-S_I Ack_all 0 <--
-S_I MEM_Inv 0 <--
-
-ISS L1_GET_INSTR 0 <--
-ISS L1_GETS 0 <--
-ISS L1_GETX 0 <--
-ISS L1_PUTX 0 <--
-ISS L1_PUTX_old 0 <--
-ISS L2_Replacement 0 <--
-ISS L2_Replacement_clean 0 <--
-ISS Mem_Data 570
-ISS MEM_Inv 0 <--
-
-IS L1_GET_INSTR 0 <--
-IS L1_GETS 0 <--
-IS L1_GETX 0 <--
-IS L1_PUTX 0 <--
-IS L1_PUTX_old 0 <--
-IS L2_Replacement 0 <--
-IS L2_Replacement_clean 0 <--
-IS Mem_Data 686
-IS MEM_Inv 0 <--
-
-IM L1_GET_INSTR 0 <--
-IM L1_GETS 0 <--
-IM L1_GETX 0 <--
-IM L1_PUTX 0 <--
-IM L1_PUTX_old 0 <--
-IM L2_Replacement 0 <--
-IM L2_Replacement_clean 0 <--
-IM Mem_Data 204
-IM MEM_Inv 0 <--
-
-SS_MB L1_GET_INSTR 0 <--
-SS_MB L1_GETS 0 <--
-SS_MB L1_GETX 0 <--
-SS_MB L1_UPGRADE 0 <--
-SS_MB L1_PUTX 0 <--
-SS_MB L1_PUTX_old 0 <--
-SS_MB L2_Replacement 0 <--
-SS_MB L2_Replacement_clean 0 <--
-SS_MB Unblock_Cancel 0 <--
-SS_MB Exclusive_Unblock 0 <--
-SS_MB MEM_Inv 0 <--
-
-MT_MB L1_GET_INSTR 0 <--
-MT_MB L1_GETS 0 <--
-MT_MB L1_GETX 0 <--
-MT_MB L1_UPGRADE 0 <--
-MT_MB L1_PUTX 0 <--
-MT_MB L1_PUTX_old 0 <--
-MT_MB L2_Replacement 0 <--
-MT_MB L2_Replacement_clean 0 <--
-MT_MB Unblock_Cancel 0 <--
-MT_MB Exclusive_Unblock 799
-MT_MB MEM_Inv 0 <--
-
-M_MB L1_GET_INSTR 0 <--
-M_MB L1_GETS 0 <--
-M_MB L1_GETX 0 <--
-M_MB L1_UPGRADE 0 <--
-M_MB L1_PUTX 0 <--
-M_MB L1_PUTX_old 0 <--
-M_MB L2_Replacement 0 <--
-M_MB L2_Replacement_clean 0 <--
-M_MB Exclusive_Unblock 0 <--
-M_MB MEM_Inv 0 <--
-
-MT_IIB L1_GET_INSTR 0 <--
-MT_IIB L1_GETS 0 <--
-MT_IIB L1_GETX 0 <--
-MT_IIB L1_UPGRADE 0 <--
-MT_IIB L1_PUTX 0 <--
-MT_IIB L1_PUTX_old 0 <--
-MT_IIB L2_Replacement 0 <--
-MT_IIB L2_Replacement_clean 0 <--
-MT_IIB WB_Data 0 <--
-MT_IIB WB_Data_clean 0 <--
-MT_IIB Unblock 0 <--
-MT_IIB MEM_Inv 0 <--
-
-MT_IB L1_GET_INSTR 0 <--
-MT_IB L1_GETS 0 <--
-MT_IB L1_GETX 0 <--
-MT_IB L1_UPGRADE 0 <--
-MT_IB L1_PUTX 0 <--
-MT_IB L1_PUTX_old 0 <--
-MT_IB L2_Replacement 0 <--
-MT_IB L2_Replacement_clean 0 <--
-MT_IB WB_Data 0 <--
-MT_IB WB_Data_clean 0 <--
-MT_IB Unblock_Cancel 0 <--
-MT_IB MEM_Inv 0 <--
-
-MT_SB L1_GET_INSTR 0 <--
-MT_SB L1_GETS 0 <--
-MT_SB L1_GETX 0 <--
-MT_SB L1_UPGRADE 0 <--
-MT_SB L1_PUTX 0 <--
-MT_SB L1_PUTX_old 0 <--
-MT_SB L2_Replacement 0 <--
-MT_SB L2_Replacement_clean 0 <--
-MT_SB Unblock 0 <--
-MT_SB MEM_Inv 0 <--
-
-Memory controller: system.ruby.network.topology.ext_links2.ext_node.memBuffer:
+NP L1_GET_INSTR [686 ] 686
+NP L1_GETS [570 ] 570
+NP L1_GETX [204 ] 204
+NP L1_PUTX [0 ] 0
+NP L1_PUTX_old [0 ] 0
+
+SS L1_GET_INSTR [5 ] 5
+SS L1_GETS [0 ] 0
+SS L1_GETX [0 ] 0
+SS L1_UPGRADE [0 ] 0
+SS L1_PUTX [0 ] 0
+SS L1_PUTX_old [0 ] 0
+SS L2_Replacement [0 ] 0
+SS L2_Replacement_clean [681 ] 681
+SS MEM_Inv [0 ] 0
+
+M L1_GET_INSTR [0 ] 0
+M L1_GETS [13 ] 13
+M L1_GETX [12 ] 12
+M L1_PUTX [0 ] 0
+M L1_PUTX_old [0 ] 0
+M L2_Replacement [134 ] 134
+M L2_Replacement_clean [277 ] 277
+M MEM_Inv [0 ] 0
+
+MT L1_GET_INSTR [0 ] 0
+MT L1_GETS [0 ] 0
+MT L1_GETX [0 ] 0
+MT L1_PUTX [436 ] 436
+MT L1_PUTX_old [0 ] 0
+MT L2_Replacement [8 ] 8
+MT L2_Replacement_clean [352 ] 352
+MT MEM_Inv [0 ] 0
+
+M_I L1_GET_INSTR [0 ] 0
+M_I L1_GETS [9 ] 9
+M_I L1_GETX [4 ] 4
+M_I L1_UPGRADE [0 ] 0
+M_I L1_PUTX [0 ] 0
+M_I L1_PUTX_old [0 ] 0
+M_I Mem_Ack [1452 ] 1452
+M_I MEM_Inv [0 ] 0
+
+MT_I L1_GET_INSTR [0 ] 0
+MT_I L1_GETS [0 ] 0
+MT_I L1_GETX [0 ] 0
+MT_I L1_UPGRADE [0 ] 0
+MT_I L1_PUTX [0 ] 0
+MT_I L1_PUTX_old [0 ] 0
+MT_I WB_Data [6 ] 6
+MT_I WB_Data_clean [0 ] 0
+MT_I Ack_all [2 ] 2
+MT_I MEM_Inv [0 ] 0
+
+MCT_I L1_GET_INSTR [0 ] 0
+MCT_I L1_GETS [0 ] 0
+MCT_I L1_GETX [0 ] 0
+MCT_I L1_UPGRADE [0 ] 0
+MCT_I L1_PUTX [0 ] 0
+MCT_I L1_PUTX_old [0 ] 0
+MCT_I WB_Data [135 ] 135
+MCT_I WB_Data_clean [0 ] 0
+MCT_I Ack_all [217 ] 217
+
+I_I L1_GET_INSTR [0 ] 0
+I_I L1_GETS [0 ] 0
+I_I L1_GETX [0 ] 0
+I_I L1_UPGRADE [0 ] 0
+I_I L1_PUTX [0 ] 0
+I_I L1_PUTX_old [0 ] 0
+I_I Ack [0 ] 0
+I_I Ack_all [681 ] 681
+
+S_I L1_GET_INSTR [0 ] 0
+S_I L1_GETS [0 ] 0
+S_I L1_GETX [0 ] 0
+S_I L1_UPGRADE [0 ] 0
+S_I L1_PUTX [0 ] 0
+S_I L1_PUTX_old [0 ] 0
+S_I Ack [0 ] 0
+S_I Ack_all [0 ] 0
+S_I MEM_Inv [0 ] 0
+
+ISS L1_GET_INSTR [0 ] 0
+ISS L1_GETS [0 ] 0
+ISS L1_GETX [0 ] 0
+ISS L1_PUTX [0 ] 0
+ISS L1_PUTX_old [0 ] 0
+ISS L2_Replacement [0 ] 0
+ISS L2_Replacement_clean [0 ] 0
+ISS Mem_Data [570 ] 570
+ISS MEM_Inv [0 ] 0
+
+IS L1_GET_INSTR [0 ] 0
+IS L1_GETS [0 ] 0
+IS L1_GETX [0 ] 0
+IS L1_PUTX [0 ] 0
+IS L1_PUTX_old [0 ] 0
+IS L2_Replacement [0 ] 0
+IS L2_Replacement_clean [0 ] 0
+IS Mem_Data [686 ] 686
+IS MEM_Inv [0 ] 0
+
+IM L1_GET_INSTR [0 ] 0
+IM L1_GETS [0 ] 0
+IM L1_GETX [0 ] 0
+IM L1_PUTX [0 ] 0
+IM L1_PUTX_old [0 ] 0
+IM L2_Replacement [0 ] 0
+IM L2_Replacement_clean [0 ] 0
+IM Mem_Data [204 ] 204
+IM MEM_Inv [0 ] 0
+
+SS_MB L1_GET_INSTR [0 ] 0
+SS_MB L1_GETS [0 ] 0
+SS_MB L1_GETX [0 ] 0
+SS_MB L1_UPGRADE [0 ] 0
+SS_MB L1_PUTX [0 ] 0
+SS_MB L1_PUTX_old [0 ] 0
+SS_MB L2_Replacement [0 ] 0
+SS_MB L2_Replacement_clean [0 ] 0
+SS_MB Unblock_Cancel [0 ] 0
+SS_MB Exclusive_Unblock [0 ] 0
+SS_MB MEM_Inv [0 ] 0
+
+MT_MB L1_GET_INSTR [0 ] 0
+MT_MB L1_GETS [0 ] 0
+MT_MB L1_GETX [0 ] 0
+MT_MB L1_UPGRADE [0 ] 0
+MT_MB L1_PUTX [0 ] 0
+MT_MB L1_PUTX_old [0 ] 0
+MT_MB L2_Replacement [0 ] 0
+MT_MB L2_Replacement_clean [0 ] 0
+MT_MB Unblock_Cancel [0 ] 0
+MT_MB Exclusive_Unblock [799 ] 799
+MT_MB MEM_Inv [0 ] 0
+
+M_MB L1_GET_INSTR [0 ] 0
+M_MB L1_GETS [0 ] 0
+M_MB L1_GETX [0 ] 0
+M_MB L1_UPGRADE [0 ] 0
+M_MB L1_PUTX [0 ] 0
+M_MB L1_PUTX_old [0 ] 0
+M_MB L2_Replacement [0 ] 0
+M_MB L2_Replacement_clean [0 ] 0
+M_MB Exclusive_Unblock [0 ] 0
+M_MB MEM_Inv [0 ] 0
+
+MT_IIB L1_GET_INSTR [0 ] 0
+MT_IIB L1_GETS [0 ] 0
+MT_IIB L1_GETX [0 ] 0
+MT_IIB L1_UPGRADE [0 ] 0
+MT_IIB L1_PUTX [0 ] 0
+MT_IIB L1_PUTX_old [0 ] 0
+MT_IIB L2_Replacement [0 ] 0
+MT_IIB L2_Replacement_clean [0 ] 0
+MT_IIB WB_Data [0 ] 0
+MT_IIB WB_Data_clean [0 ] 0
+MT_IIB Unblock [0 ] 0
+MT_IIB MEM_Inv [0 ] 0
+
+MT_IB L1_GET_INSTR [0 ] 0
+MT_IB L1_GETS [0 ] 0
+MT_IB L1_GETX [0 ] 0
+MT_IB L1_UPGRADE [0 ] 0
+MT_IB L1_PUTX [0 ] 0
+MT_IB L1_PUTX_old [0 ] 0
+MT_IB L2_Replacement [0 ] 0
+MT_IB L2_Replacement_clean [0 ] 0
+MT_IB WB_Data [0 ] 0
+MT_IB WB_Data_clean [0 ] 0
+MT_IB Unblock_Cancel [0 ] 0
+MT_IB MEM_Inv [0 ] 0
+
+MT_SB L1_GET_INSTR [0 ] 0
+MT_SB L1_GETS [0 ] 0
+MT_SB L1_GETX [0 ] 0
+MT_SB L1_UPGRADE [0 ] 0
+MT_SB L1_PUTX [0 ] 0
+MT_SB L1_PUTX_old [0 ] 0
+MT_SB L2_Replacement [0 ] 0
+MT_SB L2_Replacement_clean [0 ] 0
+MT_SB Unblock [0 ] 0
+MT_SB MEM_Inv [0 ] 0
+
+Memory controller: system.dir_cntrl0.memBuffer:
memory_total_requests: 1737
memory_reads: 1460
memory_writes: 277
@@ -551,67 +556,66 @@ Memory controller: system.ruby.network.topology.ext_links2.ext_node.memBuffer:
memory_stalls_for_read_read_turnaround: 0
accesses_per_bank: 92 21 45 54 57 174 48 18 19 22 35 37 56 59 44 36 41 24 22 28 32 48 122 36 32 25 35 96 114 185 19 61
- --- Directory 0 ---
+ --- Directory ---
- Event Counts -
-Fetch 1460
-Data 277
-Memory_Data 1460
-Memory_Ack 277
-DMA_READ 0
-DMA_WRITE 0
-CleanReplacement 1175
+Fetch [1460 ] 1460
+Data [277 ] 277
+Memory_Data [1460 ] 1460
+Memory_Ack [277 ] 277
+DMA_READ [0 ] 0
+DMA_WRITE [0 ] 0
+CleanReplacement [1175 ] 1175
- Transitions -
-I Fetch 1460
-I DMA_READ 0 <--
-I DMA_WRITE 0 <--
-
-ID Fetch 0 <--
-ID Data 0 <--
-ID Memory_Data 0 <--
-ID DMA_READ 0 <--
-ID DMA_WRITE 0 <--
-
-ID_W Fetch 0 <--
-ID_W Data 0 <--
-ID_W Memory_Ack 0 <--
-ID_W DMA_READ 0 <--
-ID_W DMA_WRITE 0 <--
-
-M Data 277
-M DMA_READ 0 <--
-M DMA_WRITE 0 <--
-M CleanReplacement 1175
-
-IM Fetch 0 <--
-IM Data 0 <--
-IM Memory_Data 1460
-IM DMA_READ 0 <--
-IM DMA_WRITE 0 <--
-
-MI Fetch 0 <--
-MI Data 0 <--
-MI Memory_Ack 277
-MI DMA_READ 0 <--
-MI DMA_WRITE 0 <--
-
-M_DRD Data 0 <--
-M_DRD DMA_READ 0 <--
-M_DRD DMA_WRITE 0 <--
-
-M_DRDI Fetch 0 <--
-M_DRDI Data 0 <--
-M_DRDI Memory_Ack 0 <--
-M_DRDI DMA_READ 0 <--
-M_DRDI DMA_WRITE 0 <--
-
-M_DWR Data 0 <--
-M_DWR DMA_READ 0 <--
-M_DWR DMA_WRITE 0 <--
-
-M_DWRI Fetch 0 <--
-M_DWRI Data 0 <--
-M_DWRI Memory_Ack 0 <--
-M_DWRI DMA_READ 0 <--
-M_DWRI DMA_WRITE 0 <--
-
+I Fetch [1460 ] 1460
+I DMA_READ [0 ] 0
+I DMA_WRITE [0 ] 0
+
+ID Fetch [0 ] 0
+ID Data [0 ] 0
+ID Memory_Data [0 ] 0
+ID DMA_READ [0 ] 0
+ID DMA_WRITE [0 ] 0
+
+ID_W Fetch [0 ] 0
+ID_W Data [0 ] 0
+ID_W Memory_Ack [0 ] 0
+ID_W DMA_READ [0 ] 0
+ID_W DMA_WRITE [0 ] 0
+
+M Data [277 ] 277
+M DMA_READ [0 ] 0
+M DMA_WRITE [0 ] 0
+M CleanReplacement [1175 ] 1175
+
+IM Fetch [0 ] 0
+IM Data [0 ] 0
+IM Memory_Data [1460 ] 1460
+IM DMA_READ [0 ] 0
+IM DMA_WRITE [0 ] 0
+
+MI Fetch [0 ] 0
+MI Data [0 ] 0
+MI Memory_Ack [277 ] 277
+MI DMA_READ [0 ] 0
+MI DMA_WRITE [0 ] 0
+
+M_DRD Data [0 ] 0
+M_DRD DMA_READ [0 ] 0
+M_DRD DMA_WRITE [0 ] 0
+
+M_DRDI Fetch [0 ] 0
+M_DRDI Data [0 ] 0
+M_DRDI Memory_Ack [0 ] 0
+M_DRDI DMA_READ [0 ] 0
+M_DRDI DMA_WRITE [0 ] 0
+
+M_DWR Data [0 ] 0
+M_DWR DMA_READ [0 ] 0
+M_DWR DMA_WRITE [0 ] 0
+
+M_DWRI Fetch [0 ] 0
+M_DWRI Data [0 ] 0
+M_DWRI Memory_Ack [0 ] 0
+M_DWRI DMA_READ [0 ] 0
+M_DWRI DMA_WRITE \ No newline at end of file
diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/simout b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/simout
index 37377ab3d..513747fae 100755
--- a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/simout
+++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/simout
@@ -5,10 +5,10 @@ The Regents of The University of Michigan
All Rights Reserved
-M5 compiled Jan 28 2010 13:54:58
-M5 revision 6068d4fc30d3+ 6931+ default qtip tip brad/rubycfg_regress_udpate
-M5 started Jan 28 2010 13:57:42
-M5 executing on svvint03
+M5 compiled Aug 5 2010 10:22:52
+M5 revision 1cd2a169499f+ 7535+ default brad/hammer_merge_gets qtip tip
+M5 started Aug 5 2010 10:23:42
+M5 executing on svvint09
command line: build/ALPHA_SE_MESI_CMP_directory/m5.fast -d build/ALPHA_SE_MESI_CMP_directory/tests/fast/quick/00.hello/alpha/linux/simple-timing-ruby-MESI_CMP_directory -re tests/run.py build/ALPHA_SE_MESI_CMP_directory/tests/fast/quick/00.hello/alpha/linux/simple-timing-ruby-MESI_CMP_directory
Global frequency set at 1000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/stats.txt b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/stats.txt
index edabafa0b..d792ca5ac 100644
--- a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/stats.txt
+++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/stats.txt
@@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
-host_inst_rate 8106 # Simulator instruction rate (inst/s)
-host_mem_usage 215916 # Number of bytes of host memory used
-host_seconds 0.79 # Real time elapsed on the host
-host_tick_rate 348501 # Simulator tick rate (ticks/s)
+host_inst_rate 24630 # Simulator instruction rate (inst/s)
+host_mem_usage 212388 # Number of bytes of host memory used
+host_seconds 0.26 # Real time elapsed on the host
+host_tick_rate 1058851 # Simulator tick rate (ticks/s)
sim_freq 1000000000 # Frequency of simulated ticks
sim_insts 6404 # Number of instructions simulated
sim_seconds 0.000275 # Number of seconds simulated
diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/config.ini b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/config.ini
index aceab6a24..756bebd28 100644
--- a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/config.ini
+++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/config.ini
@@ -5,7 +5,7 @@ dummy=0
[system]
type=System
-children=cpu physmem ruby
+children=cpu dir_cntrl0 l1_cntrl0 l2_cntrl0 physmem ruby
mem_mode=timing
physmem=system.physmem
@@ -32,8 +32,8 @@ progress_interval=0
system=system
tracer=system.cpu.tracer
workload=system.cpu.workload
-dcache_port=system.ruby.network.topology.ext_links0.ext_node.sequencer.port[1]
-icache_port=system.ruby.network.topology.ext_links0.ext_node.sequencer.port[0]
+dcache_port=system.l1_cntrl0.sequencer.port[1]
+icache_port=system.l1_cntrl0.sequencer.port[0]
[system.cpu.dtb]
type=AlphaTLB
@@ -54,7 +54,7 @@ egid=100
env=
errout=cerr
euid=100
-executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/hello/bin/alpha/linux/hello
+executable=tests/test-progs/hello/bin/alpha/linux/hello
gid=100
input=cin
max_stack_size=67108864
@@ -65,6 +65,110 @@ simpoint=0
system=system
uid=100
+[system.dir_cntrl0]
+type=Directory_Controller
+children=directory memBuffer
+buffer_size=0
+directory=system.dir_cntrl0.directory
+directory_latency=6
+memBuffer=system.dir_cntrl0.memBuffer
+number_of_TBEs=256
+recycle_latency=10
+transitions_per_cycle=32
+version=0
+
+[system.dir_cntrl0.directory]
+type=RubyDirectoryMemory
+map_levels=4
+numa_high_bit=6
+size=134217728
+use_map=false
+version=0
+
+[system.dir_cntrl0.memBuffer]
+type=RubyMemoryControl
+bank_bit_0=8
+bank_busy_time=11
+bank_queue_size=12
+banks_per_rank=8
+basic_bus_busy_time=2
+dimm_bit_0=12
+dimms_per_channel=2
+mem_bus_cycle_multiplier=10
+mem_ctl_latency=12
+mem_fixed_delay=0
+mem_random_arbitrate=0
+rank_bit_0=11
+rank_rank_delay=1
+ranks_per_dimm=2
+read_write_delay=2
+refresh_period=1560
+tFaw=0
+version=0
+
+[system.l1_cntrl0]
+type=L1Cache_Controller
+children=sequencer
+L1DcacheMemory=system.l1_cntrl0.sequencer.dcache
+L1IcacheMemory=system.l1_cntrl0.sequencer.icache
+buffer_size=0
+l2_select_num_bits=0
+number_of_TBEs=256
+recycle_latency=10
+request_latency=2
+sequencer=system.l1_cntrl0.sequencer
+transitions_per_cycle=32
+version=0
+
+[system.l1_cntrl0.sequencer]
+type=RubySequencer
+children=dcache icache
+dcache=system.l1_cntrl0.sequencer.dcache
+deadlock_threshold=500000
+icache=system.l1_cntrl0.sequencer.icache
+max_outstanding_requests=16
+physmem=system.physmem
+using_ruby_tester=false
+version=0
+physMemPort=system.physmem.port[0]
+port=system.cpu.icache_port system.cpu.dcache_port
+
+[system.l1_cntrl0.sequencer.dcache]
+type=RubyCache
+assoc=2
+latency=3
+replacement_policy=PSEUDO_LRU
+size=256
+start_index_bit=6
+
+[system.l1_cntrl0.sequencer.icache]
+type=RubyCache
+assoc=2
+latency=3
+replacement_policy=PSEUDO_LRU
+size=256
+start_index_bit=6
+
+[system.l2_cntrl0]
+type=L2Cache_Controller
+children=L2cacheMemory
+L2cacheMemory=system.l2_cntrl0.L2cacheMemory
+buffer_size=0
+number_of_TBEs=256
+recycle_latency=10
+request_latency=2
+response_latency=2
+transitions_per_cycle=32
+version=0
+
+[system.l2_cntrl0.L2cacheMemory]
+type=RubyCache
+assoc=2
+latency=15
+replacement_policy=PSEUDO_LRU
+size=512
+start_index_bit=6
+
[system.physmem]
type=PhysicalMemory
file=
@@ -73,7 +177,7 @@ latency_var=0
null=false
range=0:134217727
zero=false
-port=system.ruby.network.topology.ext_links0.ext_node.sequencer.physMemPort
+port=system.l1_cntrl0.sequencer.physMemPort
[system.ruby]
type=RubySystem
@@ -83,6 +187,7 @@ clock=1
debug=system.ruby.debug
mem_size=134217728
network=system.ruby.network
+no_mem_vec=false
profiler=system.ruby.profiler
random_seed=1234
randomization=false
@@ -100,7 +205,7 @@ verbosity_string=none
[system.ruby.network]
type=SimpleNetwork
children=topology
-adaptive_routing=true
+adaptive_routing=false
buffer_size=0
control_msg_size=8
endpoint_bandwidth=10000
@@ -113,134 +218,34 @@ type=Topology
children=ext_links0 ext_links1 ext_links2 int_links0 int_links1 int_links2
ext_links=system.ruby.network.topology.ext_links0 system.ruby.network.topology.ext_links1 system.ruby.network.topology.ext_links2
int_links=system.ruby.network.topology.int_links0 system.ruby.network.topology.int_links1 system.ruby.network.topology.int_links2
+name=Crossbar
num_int_nodes=4
print_config=false
[system.ruby.network.topology.ext_links0]
type=ExtLink
-children=ext_node
bw_multiplier=64
-ext_node=system.ruby.network.topology.ext_links0.ext_node
+ext_node=system.l1_cntrl0
int_node=0
latency=1
weight=1
-[system.ruby.network.topology.ext_links0.ext_node]
-type=L1Cache_Controller
-children=sequencer
-L1DcacheMemory=system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache
-L1IcacheMemory=system.ruby.network.topology.ext_links0.ext_node.sequencer.icache
-buffer_size=0
-l2_select_num_bits=0
-number_of_TBEs=256
-recycle_latency=10
-request_latency=2
-sequencer=system.ruby.network.topology.ext_links0.ext_node.sequencer
-transitions_per_cycle=32
-version=0
-
-[system.ruby.network.topology.ext_links0.ext_node.sequencer]
-type=RubySequencer
-children=dcache icache
-dcache=system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache
-deadlock_threshold=500000
-icache=system.ruby.network.topology.ext_links0.ext_node.sequencer.icache
-max_outstanding_requests=16
-physmem=system.physmem
-using_ruby_tester=false
-version=0
-physMemPort=system.physmem.port[0]
-port=system.cpu.icache_port system.cpu.dcache_port
-
-[system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache]
-type=RubyCache
-assoc=2
-latency=3
-replacement_policy=PSEUDO_LRU
-size=256
-
-[system.ruby.network.topology.ext_links0.ext_node.sequencer.icache]
-type=RubyCache
-assoc=2
-latency=3
-replacement_policy=PSEUDO_LRU
-size=256
-
[system.ruby.network.topology.ext_links1]
type=ExtLink
-children=ext_node
bw_multiplier=64
-ext_node=system.ruby.network.topology.ext_links1.ext_node
+ext_node=system.l2_cntrl0
int_node=1
latency=1
weight=1
-[system.ruby.network.topology.ext_links1.ext_node]
-type=L2Cache_Controller
-children=L2cacheMemory
-L2cacheMemory=system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory
-buffer_size=0
-number_of_TBEs=256
-recycle_latency=10
-request_latency=2
-response_latency=2
-transitions_per_cycle=32
-version=0
-
-[system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory]
-type=RubyCache
-assoc=2
-latency=15
-replacement_policy=PSEUDO_LRU
-size=512
-
[system.ruby.network.topology.ext_links2]
type=ExtLink
-children=ext_node
bw_multiplier=64
-ext_node=system.ruby.network.topology.ext_links2.ext_node
+ext_node=system.dir_cntrl0
int_node=2
latency=1
weight=1
-[system.ruby.network.topology.ext_links2.ext_node]
-type=Directory_Controller
-children=directory memBuffer
-buffer_size=0
-directory=system.ruby.network.topology.ext_links2.ext_node.directory
-directory_latency=6
-memBuffer=system.ruby.network.topology.ext_links2.ext_node.memBuffer
-number_of_TBEs=256
-recycle_latency=10
-transitions_per_cycle=32
-version=0
-
-[system.ruby.network.topology.ext_links2.ext_node.directory]
-type=RubyDirectoryMemory
-size=134217728
-version=0
-
-[system.ruby.network.topology.ext_links2.ext_node.memBuffer]
-type=RubyMemoryControl
-bank_bit_0=8
-bank_busy_time=11
-bank_queue_size=12
-banks_per_rank=8
-basic_bus_busy_time=2
-dimm_bit_0=12
-dimms_per_channel=2
-mem_bus_cycle_multiplier=10
-mem_ctl_latency=12
-mem_fixed_delay=0
-mem_random_arbitrate=0
-rank_bit_0=11
-rank_rank_delay=1
-ranks_per_dimm=2
-read_write_delay=2
-refresh_period=1560
-tFaw=0
-version=0
-
[system.ruby.network.topology.int_links0]
type=IntLink
bw_multiplier=16
diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/ruby.stats b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/ruby.stats
index 89d0c3194..c3c1c36bf 100644
--- a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/ruby.stats
+++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/ruby.stats
@@ -13,7 +13,7 @@ RubySystem config:
Network Configuration
---------------------
network: SIMPLE_NETWORK
-topology:
+topology: Crossbar
virtual_net_0: active, unordered
virtual_net_1: active, unordered
@@ -34,40 +34,29 @@ periodic_stats_period: 1000000
================ End RubySystem Configuration Print ================
-Real time: Jan/28/2010 15:08:14
+Real time: Aug/05/2010 10:35:39
Profiler Stats
--------------
-Elapsed_time_in_seconds: 1
-Elapsed_time_in_minutes: 0.0166667
-Elapsed_time_in_hours: 0.000277778
-Elapsed_time_in_days: 1.15741e-05
+Elapsed_time_in_seconds: 0
+Elapsed_time_in_minutes: 0
+Elapsed_time_in_hours: 0
+Elapsed_time_in_days: 0
-Virtual_time_in_seconds: 0.8
-Virtual_time_in_minutes: 0.0133333
-Virtual_time_in_hours: 0.000222222
-Virtual_time_in_days: 9.25926e-06
+Virtual_time_in_seconds: 0.44
+Virtual_time_in_minutes: 0.00733333
+Virtual_time_in_hours: 0.000122222
+Virtual_time_in_days: 5.09259e-06
Ruby_current_time: 223854
Ruby_start_time: 0
Ruby_cycles: 223854
-mbytes_resident: 34.6055
-mbytes_total: 34.6133
+mbytes_resident: 34.9609
+mbytes_total: 34.9688
resident_ratio: 1
-Total_misses: 0
-total_misses: 0 [ 0 ]
-user_misses: 0 [ 0 ]
-supervisor_misses: 0 [ 0 ]
-
-ruby_cycles_executed: 223855 [ 223855 ]
-
-transactions_started: 0 [ 0 ]
-transactions_ended: 0 [ 0 ]
-cycles_per_transaction: 0 [ 0 ]
-misses_per_transaction: 0 [ 0 ]
-
+ruby_cycles_executed: [ 223855 ]
Busy Controller Counts:
L2Cache-0:0
@@ -82,9 +71,23 @@ sequencer_requests_outstanding: [binsize: 1 max: 1 count: 8465 average: 1 |
All Non-Zero Cycle Demand Cache Accesses
----------------------------------------
miss_latency: [binsize: 2 max: 276 count: 8464 average: 25.4478 | standard deviation: 56.39 | 0 7102 0 0 0 0 0 0 0 188 60 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 251 197 238 187 165 13 4 20 3 7 5 4 3 3 1 0 1 1 1 0 0 1 0 1 0 0 0 3 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
-miss_latency_1: [binsize: 2 max: 276 count: 6414 average: 17.9724 | standard deviation: 47.359 | 0 5768 0 0 0 0 0 0 0 76 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 153 110 113 93 66 5 3 16 1 3 0 1 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 2 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
-miss_latency_2: [binsize: 2 max: 259 count: 1185 average: 62.838 | standard deviation: 78.9565 | 0 660 0 0 0 0 0 0 0 112 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 98 55 84 84 63 2 1 3 2 3 5 3 2 2 0 0 1 0 1 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
-miss_latency_3: [binsize: 2 max: 227 count: 865 average: 29.6555 | standard deviation: 60.051 | 0 674 0 0 0 0 0 0 0 0 60 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 32 41 10 36 6 0 1 0 1 0 0 1 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency_IFETCH: [binsize: 2 max: 276 count: 6414 average: 17.9724 | standard deviation: 47.359 | 0 5768 0 0 0 0 0 0 0 76 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 153 110 113 93 66 5 3 16 1 3 0 1 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 2 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency_LD: [binsize: 2 max: 259 count: 1185 average: 62.838 | standard deviation: 78.9565 | 0 660 0 0 0 0 0 0 0 112 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 98 55 84 84 63 2 1 3 2 3 5 3 2 2 0 0 1 0 1 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency_ST: [binsize: 2 max: 227 count: 865 average: 29.6555 | standard deviation: 60.051 | 0 674 0 0 0 0 0 0 0 0 60 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 32 41 10 36 6 0 1 0 1 0 0 1 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency_NULL: [binsize: 2 max: 276 count: 8464 average: 25.4478 | standard deviation: 56.39 | 0 7102 0 0 0 0 0 0 0 188 60 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 251 197 238 187 165 13 4 20 3 7 5 4 3 3 1 0 1 1 1 0 0 1 0 1 0 0 0 3 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency_wCC_issue_to_initial_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+miss_latency_wCC_initial_forward_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+miss_latency_wCC_forward_to_first_response: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+miss_latency_wCC_first_response_to_completion: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+imcomplete_wCC_Times: 0
+miss_latency_dir_issue_to_initial_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+miss_latency_dir_initial_forward_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+miss_latency_dir_forward_to_first_response: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+miss_latency_dir_first_response_to_completion: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+imcomplete_dir_Times: 0
+miss_latency_IFETCH_NULL: [binsize: 2 max: 276 count: 6414 average: 17.9724 | standard deviation: 47.359 | 0 5768 0 0 0 0 0 0 0 76 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 153 110 113 93 66 5 3 16 1 3 0 1 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 2 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency_LD_NULL: [binsize: 2 max: 259 count: 1185 average: 62.838 | standard deviation: 78.9565 | 0 660 0 0 0 0 0 0 0 112 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 98 55 84 84 63 2 1 3 2 3 5 3 2 2 0 0 1 0 1 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency_ST_NULL: [binsize: 2 max: 227 count: 865 average: 29.6555 | standard deviation: 60.051 | 0 674 0 0 0 0 0 0 0 0 60 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 32 41 10 36 6 0 1 0 1 0 0 1 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
All Non-Zero Cycle SW Prefetch Requests
------------------------------------
@@ -116,8 +119,8 @@ Resource Usage
page_size: 4096
user_time: 0
system_time: 0
-page_reclaims: 7397
-page_faults: 2249
+page_reclaims: 7630
+page_faults: 2184
swaps: 0
block_inputs: 0
block_outputs: 0
@@ -125,6 +128,14 @@ block_outputs: 0
Network Stats
-------------
+total_msg_count_Request_Control: 7428 59424
+total_msg_count_Response_Data: 6684 481248
+total_msg_count_ResponseL2hit_Data: 744 53568
+total_msg_count_Writeback_Data: 4644 334368
+total_msg_count_Writeback_Control: 17424 139392
+total_msg_count_Unblock_Control: 7428 59424
+total_msgs: 44352 total_bytes: 1127424
+
switch_0_inlinks: 2
switch_0_outlinks: 2
links_utilized_percent_switch_0: 0.219641
@@ -190,972 +201,966 @@ links_utilized_percent_switch_3: 0.349752
outgoing_messages_switch_3_link_2_Writeback_Control: 2002 16016 [ 0 1098 904 0 0 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_3_link_2_Unblock_Control: 1114 8912 [ 0 0 1114 0 0 0 0 0 0 0 ] base_latency: 1
-Cache Stats: system.ruby.network.topology.ext_links0.ext_node.sequencer.icache
- system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_misses: 0
- system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_demand_misses: 0
- system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_prefetches: 0
- system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_sw_prefetches: 0
- system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_hw_prefetches: 0
- system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_misses_per_transaction: nan
+Cache Stats: system.l1_cntrl0.sequencer.icache
+ system.l1_cntrl0.sequencer.icache_total_misses: 0
+ system.l1_cntrl0.sequencer.icache_total_demand_misses: 0
+ system.l1_cntrl0.sequencer.icache_total_prefetches: 0
+ system.l1_cntrl0.sequencer.icache_total_sw_prefetches: 0
+ system.l1_cntrl0.sequencer.icache_total_hw_prefetches: 0
- system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
-Cache Stats: system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache
- system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_misses: 0
- system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_demand_misses: 0
- system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_prefetches: 0
- system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_sw_prefetches: 0
- system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_hw_prefetches: 0
- system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_misses_per_transaction: nan
+Cache Stats: system.l1_cntrl0.sequencer.dcache
+ system.l1_cntrl0.sequencer.dcache_total_misses: 0
+ system.l1_cntrl0.sequencer.dcache_total_demand_misses: 0
+ system.l1_cntrl0.sequencer.dcache_total_prefetches: 0
+ system.l1_cntrl0.sequencer.dcache_total_sw_prefetches: 0
+ system.l1_cntrl0.sequencer.dcache_total_hw_prefetches: 0
- system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
- --- L1Cache 0 ---
+ --- L1Cache ---
- Event Counts -
-Load 1185
-Ifetch 6414
-Store 865
-L1_Replacement 1379
-Own_GETX 0
-Fwd_GETX 0
-Fwd_GETS 0
-Fwd_DMA 0
-Inv 0
-Ack 0
-Data 0
-Exclusive_Data 1362
-Writeback_Ack 0
-Writeback_Ack_Data 1354
-Writeback_Nack 0
-All_acks 191
-Use_Timeout 1361
+Load [1185 ] 1185
+Ifetch [6414 ] 6414
+Store [865 ] 865
+L1_Replacement [1379 ] 1379
+Own_GETX [0 ] 0
+Fwd_GETX [0 ] 0
+Fwd_GETS [0 ] 0
+Fwd_DMA [0 ] 0
+Inv [0 ] 0
+Ack [0 ] 0
+Data [0 ] 0
+Exclusive_Data [1362 ] 1362
+Writeback_Ack [0 ] 0
+Writeback_Ack_Data [1354 ] 1354
+Writeback_Nack [0 ] 0
+All_acks [191 ] 191
+Use_Timeout [1361 ] 1361
- Transitions -
-I Load 525
-I Ifetch 646
-I Store 191
-I L1_Replacement 0 <--
-I Inv 0 <--
-
-S Load 0 <--
-S Ifetch 0 <--
-S Store 0 <--
-S L1_Replacement 0 <--
-S Fwd_GETS 0 <--
-S Fwd_DMA 0 <--
-S Inv 0 <--
-
-O Load 0 <--
-O Ifetch 0 <--
-O Store 0 <--
-O L1_Replacement 0 <--
-O Fwd_GETX 0 <--
-O Fwd_GETS 0 <--
-O Fwd_DMA 0 <--
-
-M Load 308
-M Ifetch 3484
-M Store 51
-M L1_Replacement 1086
-M Fwd_GETX 0 <--
-M Fwd_GETS 0 <--
-M Fwd_DMA 0 <--
-
-M_W Load 111
-M_W Ifetch 2284
-M_W Store 27
-M_W L1_Replacement 17
-M_W Own_GETX 0 <--
-M_W Fwd_GETX 0 <--
-M_W Fwd_GETS 0 <--
-M_W Fwd_DMA 0 <--
-M_W Inv 0 <--
-M_W Use_Timeout 1143
-
-MM Load 234
-MM Ifetch 0 <--
-MM Store 339
-MM L1_Replacement 268
-MM Fwd_GETX 0 <--
-MM Fwd_GETS 0 <--
-MM Fwd_DMA 0 <--
-
-MM_W Load 7
-MM_W Ifetch 0 <--
-MM_W Store 257
-MM_W L1_Replacement 8
-MM_W Own_GETX 0 <--
-MM_W Fwd_GETX 0 <--
-MM_W Fwd_GETS 0 <--
-MM_W Fwd_DMA 0 <--
-MM_W Inv 0 <--
-MM_W Use_Timeout 218
-
-IM Load 0 <--
-IM Ifetch 0 <--
-IM Store 0 <--
-IM L1_Replacement 0 <--
-IM Inv 0 <--
-IM Ack 0 <--
-IM Data 0 <--
-IM Exclusive_Data 191
-
-SM Load 0 <--
-SM Ifetch 0 <--
-SM Store 0 <--
-SM L1_Replacement 0 <--
-SM Fwd_GETS 0 <--
-SM Fwd_DMA 0 <--
-SM Inv 0 <--
-SM Ack 0 <--
-SM Data 0 <--
-SM Exclusive_Data 0 <--
-
-OM Load 0 <--
-OM Ifetch 0 <--
-OM Store 0 <--
-OM L1_Replacement 0 <--
-OM Own_GETX 0 <--
-OM Fwd_GETX 0 <--
-OM Fwd_GETS 0 <--
-OM Fwd_DMA 0 <--
-OM Ack 0 <--
-OM All_acks 191
-
-IS Load 0 <--
-IS Ifetch 0 <--
-IS Store 0 <--
-IS L1_Replacement 0 <--
-IS Inv 0 <--
-IS Data 0 <--
-IS Exclusive_Data 1171
-
-SI Load 0 <--
-SI Ifetch 0 <--
-SI Store 0 <--
-SI L1_Replacement 0 <--
-SI Fwd_GETS 0 <--
-SI Fwd_DMA 0 <--
-SI Inv 0 <--
-SI Writeback_Ack 0 <--
-SI Writeback_Ack_Data 0 <--
-SI Writeback_Nack 0 <--
-
-OI Load 0 <--
-OI Ifetch 0 <--
-OI Store 0 <--
-OI L1_Replacement 0 <--
-OI Fwd_GETX 0 <--
-OI Fwd_GETS 0 <--
-OI Fwd_DMA 0 <--
-OI Writeback_Ack 0 <--
-OI Writeback_Ack_Data 0 <--
-OI Writeback_Nack 0 <--
-
-MI Load 0 <--
-MI Ifetch 0 <--
-MI Store 0 <--
-MI L1_Replacement 0 <--
-MI Fwd_GETX 0 <--
-MI Fwd_GETS 0 <--
-MI Fwd_DMA 0 <--
-MI Writeback_Ack 0 <--
-MI Writeback_Ack_Data 1354
-MI Writeback_Nack 0 <--
-
-II Load 0 <--
-II Ifetch 0 <--
-II Store 0 <--
-II L1_Replacement 0 <--
-II Inv 0 <--
-II Writeback_Ack 0 <--
-II Writeback_Ack_Data 0 <--
-II Writeback_Nack 0 <--
-
-Cache Stats: system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory
- system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_total_misses: 0
- system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_total_demand_misses: 0
- system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_total_prefetches: 0
- system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_total_sw_prefetches: 0
- system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_total_hw_prefetches: 0
- system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_misses_per_transaction: nan
-
- system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
-
- --- L2Cache 0 ---
+I Load [525 ] 525
+I Ifetch [646 ] 646
+I Store [191 ] 191
+I L1_Replacement [0 ] 0
+I Inv [0 ] 0
+
+S Load [0 ] 0
+S Ifetch [0 ] 0
+S Store [0 ] 0
+S L1_Replacement [0 ] 0
+S Fwd_GETS [0 ] 0
+S Fwd_DMA [0 ] 0
+S Inv [0 ] 0
+
+O Load [0 ] 0
+O Ifetch [0 ] 0
+O Store [0 ] 0
+O L1_Replacement [0 ] 0
+O Fwd_GETX [0 ] 0
+O Fwd_GETS [0 ] 0
+O Fwd_DMA [0 ] 0
+
+M Load [308 ] 308
+M Ifetch [3484 ] 3484
+M Store [51 ] 51
+M L1_Replacement [1086 ] 1086
+M Fwd_GETX [0 ] 0
+M Fwd_GETS [0 ] 0
+M Fwd_DMA [0 ] 0
+
+M_W Load [111 ] 111
+M_W Ifetch [2284 ] 2284
+M_W Store [27 ] 27
+M_W L1_Replacement [17 ] 17
+M_W Own_GETX [0 ] 0
+M_W Fwd_GETX [0 ] 0
+M_W Fwd_GETS [0 ] 0
+M_W Fwd_DMA [0 ] 0
+M_W Inv [0 ] 0
+M_W Use_Timeout [1143 ] 1143
+
+MM Load [234 ] 234
+MM Ifetch [0 ] 0
+MM Store [339 ] 339
+MM L1_Replacement [268 ] 268
+MM Fwd_GETX [0 ] 0
+MM Fwd_GETS [0 ] 0
+MM Fwd_DMA [0 ] 0
+
+MM_W Load [7 ] 7
+MM_W Ifetch [0 ] 0
+MM_W Store [257 ] 257
+MM_W L1_Replacement [8 ] 8
+MM_W Own_GETX [0 ] 0
+MM_W Fwd_GETX [0 ] 0
+MM_W Fwd_GETS [0 ] 0
+MM_W Fwd_DMA [0 ] 0
+MM_W Inv [0 ] 0
+MM_W Use_Timeout [218 ] 218
+
+IM Load [0 ] 0
+IM Ifetch [0 ] 0
+IM Store [0 ] 0
+IM L1_Replacement [0 ] 0
+IM Inv [0 ] 0
+IM Ack [0 ] 0
+IM Data [0 ] 0
+IM Exclusive_Data [191 ] 191
+
+SM Load [0 ] 0
+SM Ifetch [0 ] 0
+SM Store [0 ] 0
+SM L1_Replacement [0 ] 0
+SM Fwd_GETS [0 ] 0
+SM Fwd_DMA [0 ] 0
+SM Inv [0 ] 0
+SM Ack [0 ] 0
+SM Data [0 ] 0
+SM Exclusive_Data [0 ] 0
+
+OM Load [0 ] 0
+OM Ifetch [0 ] 0
+OM Store [0 ] 0
+OM L1_Replacement [0 ] 0
+OM Own_GETX [0 ] 0
+OM Fwd_GETX [0 ] 0
+OM Fwd_GETS [0 ] 0
+OM Fwd_DMA [0 ] 0
+OM Ack [0 ] 0
+OM All_acks [191 ] 191
+
+IS Load [0 ] 0
+IS Ifetch [0 ] 0
+IS Store [0 ] 0
+IS L1_Replacement [0 ] 0
+IS Inv [0 ] 0
+IS Data [0 ] 0
+IS Exclusive_Data [1171 ] 1171
+
+SI Load [0 ] 0
+SI Ifetch [0 ] 0
+SI Store [0 ] 0
+SI L1_Replacement [0 ] 0
+SI Fwd_GETS [0 ] 0
+SI Fwd_DMA [0 ] 0
+SI Inv [0 ] 0
+SI Writeback_Ack [0 ] 0
+SI Writeback_Ack_Data [0 ] 0
+SI Writeback_Nack [0 ] 0
+
+OI Load [0 ] 0
+OI Ifetch [0 ] 0
+OI Store [0 ] 0
+OI L1_Replacement [0 ] 0
+OI Fwd_GETX [0 ] 0
+OI Fwd_GETS [0 ] 0
+OI Fwd_DMA [0 ] 0
+OI Writeback_Ack [0 ] 0
+OI Writeback_Ack_Data [0 ] 0
+OI Writeback_Nack [0 ] 0
+
+MI Load [0 ] 0
+MI Ifetch [0 ] 0
+MI Store [0 ] 0
+MI L1_Replacement [0 ] 0
+MI Fwd_GETX [0 ] 0
+MI Fwd_GETS [0 ] 0
+MI Fwd_DMA [0 ] 0
+MI Writeback_Ack [0 ] 0
+MI Writeback_Ack_Data [1354 ] 1354
+MI Writeback_Nack [0 ] 0
+
+II Load [0 ] 0
+II Ifetch [0 ] 0
+II Store [0 ] 0
+II L1_Replacement [0 ] 0
+II Inv [0 ] 0
+II Writeback_Ack [0 ] 0
+II Writeback_Ack_Data [0 ] 0
+II Writeback_Nack [0 ] 0
+
+Cache Stats: system.l2_cntrl0.L2cacheMemory
+ system.l2_cntrl0.L2cacheMemory_total_misses: 0
+ system.l2_cntrl0.L2cacheMemory_total_demand_misses: 0
+ system.l2_cntrl0.L2cacheMemory_total_prefetches: 0
+ system.l2_cntrl0.L2cacheMemory_total_sw_prefetches: 0
+ system.l2_cntrl0.L2cacheMemory_total_hw_prefetches: 0
+
+
+ --- L2Cache ---
- Event Counts -
-L1_GETS 1171
-L1_GETX 191
-L1_PUTO 0
-L1_PUTX 1354
-L1_PUTS_only 0
-L1_PUTS 0
-Fwd_GETX 0
-Fwd_GETS 0
-Fwd_DMA 0
-Own_GETX 0
-Inv 0
-IntAck 0
-ExtAck 0
-All_Acks 131
-Data 131
-Data_Exclusive 983
-L1_WBCLEANDATA 1059
-L1_WBDIRTYDATA 295
-Writeback_Ack 1098
-Writeback_Nack 0
-Unblock 0
-Exclusive_Unblock 1362
-L2_Replacement 1098
+L1_GETS [1171 ] 1171
+L1_GETX [191 ] 191
+L1_PUTO [0 ] 0
+L1_PUTX [1354 ] 1354
+L1_PUTS_only [0 ] 0
+L1_PUTS [0 ] 0
+Fwd_GETX [0 ] 0
+Fwd_GETS [0 ] 0
+Fwd_DMA [0 ] 0
+Own_GETX [0 ] 0
+Inv [0 ] 0
+IntAck [0 ] 0
+ExtAck [0 ] 0
+All_Acks [131 ] 131
+Data [131 ] 131
+Data_Exclusive [983 ] 983
+L1_WBCLEANDATA [1059 ] 1059
+L1_WBDIRTYDATA [295 ] 295
+Writeback_Ack [1098 ] 1098
+Writeback_Nack [0 ] 0
+Unblock [0 ] 0
+Exclusive_Unblock [1362 ] 1362
+L2_Replacement [1098 ] 1098
- Transitions -
-NP L1_GETS 983
-NP L1_GETX 131
-NP L1_PUTO 0 <--
-NP L1_PUTX 0 <--
-NP L1_PUTS 0 <--
-NP Inv 0 <--
-
-I L1_GETS 0 <--
-I L1_GETX 0 <--
-I L1_PUTO 0 <--
-I L1_PUTX 0 <--
-I L1_PUTS 0 <--
-I Inv 0 <--
-I L2_Replacement 0 <--
-
-ILS L1_GETS 0 <--
-ILS L1_GETX 0 <--
-ILS L1_PUTO 0 <--
-ILS L1_PUTX 0 <--
-ILS L1_PUTS_only 0 <--
-ILS L1_PUTS 0 <--
-ILS Inv 0 <--
-ILS L2_Replacement 0 <--
-
-ILX L1_GETS 0 <--
-ILX L1_GETX 0 <--
-ILX L1_PUTO 0 <--
-ILX L1_PUTX 1354
-ILX L1_PUTS_only 0 <--
-ILX L1_PUTS 0 <--
-ILX Fwd_GETX 0 <--
-ILX Fwd_GETS 0 <--
-ILX Fwd_DMA 0 <--
-ILX Inv 0 <--
-ILX Data 0 <--
-ILX L2_Replacement 0 <--
-
-ILO L1_GETS 0 <--
-ILO L1_GETX 0 <--
-ILO L1_PUTO 0 <--
-ILO L1_PUTX 0 <--
-ILO L1_PUTS 0 <--
-ILO Fwd_GETX 0 <--
-ILO Fwd_GETS 0 <--
-ILO Fwd_DMA 0 <--
-ILO Inv 0 <--
-ILO Data 0 <--
-ILO L2_Replacement 0 <--
-
-ILOX L1_GETS 0 <--
-ILOX L1_GETX 0 <--
-ILOX L1_PUTO 0 <--
-ILOX L1_PUTX 0 <--
-ILOX L1_PUTS 0 <--
-ILOX Fwd_GETX 0 <--
-ILOX Fwd_GETS 0 <--
-ILOX Fwd_DMA 0 <--
-ILOX Data 0 <--
-
-ILOS L1_GETS 0 <--
-ILOS L1_GETX 0 <--
-ILOS L1_PUTO 0 <--
-ILOS L1_PUTX 0 <--
-ILOS L1_PUTS_only 0 <--
-ILOS L1_PUTS 0 <--
-ILOS Fwd_GETX 0 <--
-ILOS Fwd_GETS 0 <--
-ILOS Fwd_DMA 0 <--
-ILOS Data 0 <--
-ILOS L2_Replacement 0 <--
-
-ILOSX L1_GETS 0 <--
-ILOSX L1_GETX 0 <--
-ILOSX L1_PUTO 0 <--
-ILOSX L1_PUTX 0 <--
-ILOSX L1_PUTS_only 0 <--
-ILOSX L1_PUTS 0 <--
-ILOSX Fwd_GETX 0 <--
-ILOSX Fwd_GETS 0 <--
-ILOSX Fwd_DMA 0 <--
-ILOSX Data 0 <--
-
-S L1_GETS 0 <--
-S L1_GETX 0 <--
-S L1_PUTX 0 <--
-S L1_PUTS 0 <--
-S Inv 0 <--
-S L2_Replacement 0 <--
-
-O L1_GETS 0 <--
-O L1_GETX 0 <--
-O L1_PUTX 0 <--
-O Fwd_GETX 0 <--
-O Fwd_GETS 0 <--
-O Fwd_DMA 0 <--
-O L2_Replacement 0 <--
-
-OLS L1_GETS 0 <--
-OLS L1_GETX 0 <--
-OLS L1_PUTX 0 <--
-OLS L1_PUTS_only 0 <--
-OLS L1_PUTS 0 <--
-OLS Fwd_GETX 0 <--
-OLS Fwd_GETS 0 <--
-OLS Fwd_DMA 0 <--
-OLS L2_Replacement 0 <--
-
-OLSX L1_GETS 0 <--
-OLSX L1_GETX 0 <--
-OLSX L1_PUTO 0 <--
-OLSX L1_PUTX 0 <--
-OLSX L1_PUTS_only 0 <--
-OLSX L1_PUTS 0 <--
-OLSX Fwd_GETX 0 <--
-OLSX Fwd_GETS 0 <--
-OLSX Fwd_DMA 0 <--
-OLSX L2_Replacement 0 <--
-
-SLS L1_GETS 0 <--
-SLS L1_GETX 0 <--
-SLS L1_PUTX 0 <--
-SLS L1_PUTS_only 0 <--
-SLS L1_PUTS 0 <--
-SLS Inv 0 <--
-SLS L2_Replacement 0 <--
-
-M L1_GETS 188
-M L1_GETX 60
-M L1_PUTO 0 <--
-M L1_PUTX 0 <--
-M L1_PUTS 0 <--
-M Fwd_GETX 0 <--
-M Fwd_GETS 0 <--
-M Fwd_DMA 0 <--
-M L2_Replacement 1098
-
-IFGX L1_GETS 0 <--
-IFGX L1_GETX 0 <--
-IFGX L1_PUTO 0 <--
-IFGX L1_PUTX 0 <--
-IFGX L1_PUTS_only 0 <--
-IFGX L1_PUTS 0 <--
-IFGX Fwd_GETX 0 <--
-IFGX Fwd_GETS 0 <--
-IFGX Fwd_DMA 0 <--
-IFGX Inv 0 <--
-IFGX Data 0 <--
-IFGX Data_Exclusive 0 <--
-IFGX L2_Replacement 0 <--
-
-IFGS L1_GETS 0 <--
-IFGS L1_GETX 0 <--
-IFGS L1_PUTO 0 <--
-IFGS L1_PUTX 0 <--
-IFGS L1_PUTS_only 0 <--
-IFGS L1_PUTS 0 <--
-IFGS Fwd_GETX 0 <--
-IFGS Fwd_GETS 0 <--
-IFGS Fwd_DMA 0 <--
-IFGS Inv 0 <--
-IFGS Data 0 <--
-IFGS Data_Exclusive 0 <--
-IFGS L2_Replacement 0 <--
-
-ISFGS L1_GETS 0 <--
-ISFGS L1_GETX 0 <--
-ISFGS L1_PUTO 0 <--
-ISFGS L1_PUTX 0 <--
-ISFGS L1_PUTS_only 0 <--
-ISFGS L1_PUTS 0 <--
-ISFGS Fwd_GETX 0 <--
-ISFGS Fwd_GETS 0 <--
-ISFGS Fwd_DMA 0 <--
-ISFGS Inv 0 <--
-ISFGS Data 0 <--
-ISFGS L2_Replacement 0 <--
-
-IFGXX L1_GETS 0 <--
-IFGXX L1_GETX 0 <--
-IFGXX L1_PUTO 0 <--
-IFGXX L1_PUTX 0 <--
-IFGXX L1_PUTS_only 0 <--
-IFGXX L1_PUTS 0 <--
-IFGXX Fwd_GETX 0 <--
-IFGXX Fwd_GETS 0 <--
-IFGXX Fwd_DMA 0 <--
-IFGXX Inv 0 <--
-IFGXX IntAck 0 <--
-IFGXX All_Acks 0 <--
-IFGXX Data_Exclusive 0 <--
-IFGXX L2_Replacement 0 <--
-
-OFGX L1_GETS 0 <--
-OFGX L1_GETX 0 <--
-OFGX L1_PUTO 0 <--
-OFGX L1_PUTX 0 <--
-OFGX L1_PUTS_only 0 <--
-OFGX L1_PUTS 0 <--
-OFGX Fwd_GETX 0 <--
-OFGX Fwd_GETS 0 <--
-OFGX Fwd_DMA 0 <--
-OFGX Inv 0 <--
-OFGX L2_Replacement 0 <--
-
-OLSF L1_GETS 0 <--
-OLSF L1_GETX 0 <--
-OLSF L1_PUTO 0 <--
-OLSF L1_PUTX 0 <--
-OLSF L1_PUTS_only 0 <--
-OLSF L1_PUTS 0 <--
-OLSF Fwd_GETX 0 <--
-OLSF Fwd_GETS 0 <--
-OLSF Fwd_DMA 0 <--
-OLSF Inv 0 <--
-OLSF IntAck 0 <--
-OLSF All_Acks 0 <--
-OLSF L2_Replacement 0 <--
-
-ILOW L1_GETS 0 <--
-ILOW L1_GETX 0 <--
-ILOW L1_PUTO 0 <--
-ILOW L1_PUTX 0 <--
-ILOW L1_PUTS_only 0 <--
-ILOW L1_PUTS 0 <--
-ILOW Fwd_GETX 0 <--
-ILOW Fwd_GETS 0 <--
-ILOW Fwd_DMA 0 <--
-ILOW Inv 0 <--
-ILOW L1_WBCLEANDATA 0 <--
-ILOW L1_WBDIRTYDATA 0 <--
-ILOW Unblock 0 <--
-ILOW L2_Replacement 0 <--
-
-ILOXW L1_GETS 0 <--
-ILOXW L1_GETX 0 <--
-ILOXW L1_PUTO 0 <--
-ILOXW L1_PUTX 0 <--
-ILOXW L1_PUTS_only 0 <--
-ILOXW L1_PUTS 0 <--
-ILOXW Fwd_GETX 0 <--
-ILOXW Fwd_GETS 0 <--
-ILOXW Fwd_DMA 0 <--
-ILOXW Inv 0 <--
-ILOXW L1_WBCLEANDATA 0 <--
-ILOXW L1_WBDIRTYDATA 0 <--
-ILOXW Unblock 0 <--
-ILOXW L2_Replacement 0 <--
-
-ILOSW L1_GETS 0 <--
-ILOSW L1_GETX 0 <--
-ILOSW L1_PUTO 0 <--
-ILOSW L1_PUTX 0 <--
-ILOSW L1_PUTS_only 0 <--
-ILOSW L1_PUTS 0 <--
-ILOSW Fwd_GETX 0 <--
-ILOSW Fwd_GETS 0 <--
-ILOSW Fwd_DMA 0 <--
-ILOSW Inv 0 <--
-ILOSW L1_WBCLEANDATA 0 <--
-ILOSW L1_WBDIRTYDATA 0 <--
-ILOSW Unblock 0 <--
-ILOSW L2_Replacement 0 <--
-
-ILOSXW L1_GETS 0 <--
-ILOSXW L1_GETX 0 <--
-ILOSXW L1_PUTO 0 <--
-ILOSXW L1_PUTX 0 <--
-ILOSXW L1_PUTS_only 0 <--
-ILOSXW L1_PUTS 0 <--
-ILOSXW Fwd_GETX 0 <--
-ILOSXW Fwd_GETS 0 <--
-ILOSXW Fwd_DMA 0 <--
-ILOSXW Inv 0 <--
-ILOSXW L1_WBCLEANDATA 0 <--
-ILOSXW L1_WBDIRTYDATA 0 <--
-ILOSXW Unblock 0 <--
-ILOSXW L2_Replacement 0 <--
-
-SLSW L1_GETS 0 <--
-SLSW L1_GETX 0 <--
-SLSW L1_PUTO 0 <--
-SLSW L1_PUTX 0 <--
-SLSW L1_PUTS_only 0 <--
-SLSW L1_PUTS 0 <--
-SLSW Fwd_GETX 0 <--
-SLSW Fwd_GETS 0 <--
-SLSW Fwd_DMA 0 <--
-SLSW Inv 0 <--
-SLSW Unblock 0 <--
-SLSW L2_Replacement 0 <--
-
-OLSW L1_GETS 0 <--
-OLSW L1_GETX 0 <--
-OLSW L1_PUTO 0 <--
-OLSW L1_PUTX 0 <--
-OLSW L1_PUTS_only 0 <--
-OLSW L1_PUTS 0 <--
-OLSW Fwd_GETX 0 <--
-OLSW Fwd_GETS 0 <--
-OLSW Fwd_DMA 0 <--
-OLSW Inv 0 <--
-OLSW Unblock 0 <--
-OLSW L2_Replacement 0 <--
-
-ILSW L1_GETS 0 <--
-ILSW L1_GETX 0 <--
-ILSW L1_PUTO 0 <--
-ILSW L1_PUTX 0 <--
-ILSW L1_PUTS_only 0 <--
-ILSW L1_PUTS 0 <--
-ILSW Fwd_GETX 0 <--
-ILSW Fwd_GETS 0 <--
-ILSW Fwd_DMA 0 <--
-ILSW Inv 0 <--
-ILSW L1_WBCLEANDATA 0 <--
-ILSW Unblock 0 <--
-ILSW L2_Replacement 0 <--
-
-IW L1_GETS 0 <--
-IW L1_GETX 0 <--
-IW L1_PUTO 0 <--
-IW L1_PUTX 0 <--
-IW L1_PUTS_only 0 <--
-IW L1_PUTS 0 <--
-IW Fwd_GETX 0 <--
-IW Fwd_GETS 0 <--
-IW Fwd_DMA 0 <--
-IW Inv 0 <--
-IW L1_WBCLEANDATA 0 <--
-IW L2_Replacement 0 <--
-
-OW L1_GETS 0 <--
-OW L1_GETX 0 <--
-OW L1_PUTO 0 <--
-OW L1_PUTX 0 <--
-OW L1_PUTS_only 0 <--
-OW L1_PUTS 0 <--
-OW Fwd_GETX 0 <--
-OW Fwd_GETS 0 <--
-OW Fwd_DMA 0 <--
-OW Inv 0 <--
-OW Unblock 0 <--
-OW L2_Replacement 0 <--
-
-SW L1_GETS 0 <--
-SW L1_GETX 0 <--
-SW L1_PUTO 0 <--
-SW L1_PUTX 0 <--
-SW L1_PUTS_only 0 <--
-SW L1_PUTS 0 <--
-SW Fwd_GETX 0 <--
-SW Fwd_GETS 0 <--
-SW Fwd_DMA 0 <--
-SW Inv 0 <--
-SW Unblock 0 <--
-SW L2_Replacement 0 <--
-
-OXW L1_GETS 0 <--
-OXW L1_GETX 0 <--
-OXW L1_PUTO 0 <--
-OXW L1_PUTX 0 <--
-OXW L1_PUTS_only 0 <--
-OXW L1_PUTS 0 <--
-OXW Fwd_GETX 0 <--
-OXW Fwd_GETS 0 <--
-OXW Fwd_DMA 0 <--
-OXW Inv 0 <--
-OXW Unblock 0 <--
-OXW L2_Replacement 0 <--
-
-OLSXW L1_GETS 0 <--
-OLSXW L1_GETX 0 <--
-OLSXW L1_PUTO 0 <--
-OLSXW L1_PUTX 0 <--
-OLSXW L1_PUTS_only 0 <--
-OLSXW L1_PUTS 0 <--
-OLSXW Fwd_GETX 0 <--
-OLSXW Fwd_GETS 0 <--
-OLSXW Fwd_DMA 0 <--
-OLSXW Inv 0 <--
-OLSXW Unblock 0 <--
-OLSXW L2_Replacement 0 <--
-
-ILXW L1_GETS 0 <--
-ILXW L1_GETX 0 <--
-ILXW L1_PUTO 0 <--
-ILXW L1_PUTX 0 <--
-ILXW L1_PUTS_only 0 <--
-ILXW L1_PUTS 0 <--
-ILXW Fwd_GETX 0 <--
-ILXW Fwd_GETS 0 <--
-ILXW Fwd_DMA 0 <--
-ILXW Inv 0 <--
-ILXW Data 0 <--
-ILXW L1_WBCLEANDATA 1059
-ILXW L1_WBDIRTYDATA 295
-ILXW Unblock 0 <--
-ILXW L2_Replacement 0 <--
-
-IFLS L1_GETS 0 <--
-IFLS L1_GETX 0 <--
-IFLS L1_PUTO 0 <--
-IFLS L1_PUTX 0 <--
-IFLS L1_PUTS_only 0 <--
-IFLS L1_PUTS 0 <--
-IFLS Fwd_GETX 0 <--
-IFLS Fwd_GETS 0 <--
-IFLS Fwd_DMA 0 <--
-IFLS Inv 0 <--
-IFLS Unblock 0 <--
-IFLS L2_Replacement 0 <--
-
-IFLO L1_GETS 0 <--
-IFLO L1_GETX 0 <--
-IFLO L1_PUTO 0 <--
-IFLO L1_PUTX 0 <--
-IFLO L1_PUTS_only 0 <--
-IFLO L1_PUTS 0 <--
-IFLO Fwd_GETX 0 <--
-IFLO Fwd_GETS 0 <--
-IFLO Fwd_DMA 0 <--
-IFLO Inv 0 <--
-IFLO Unblock 0 <--
-IFLO L2_Replacement 0 <--
-
-IFLOX L1_GETS 0 <--
-IFLOX L1_GETX 0 <--
-IFLOX L1_PUTO 0 <--
-IFLOX L1_PUTX 0 <--
-IFLOX L1_PUTS_only 0 <--
-IFLOX L1_PUTS 0 <--
-IFLOX Fwd_GETX 0 <--
-IFLOX Fwd_GETS 0 <--
-IFLOX Fwd_DMA 0 <--
-IFLOX Inv 0 <--
-IFLOX Unblock 0 <--
-IFLOX Exclusive_Unblock 0 <--
-IFLOX L2_Replacement 0 <--
-
-IFLOXX L1_GETS 0 <--
-IFLOXX L1_GETX 0 <--
-IFLOXX L1_PUTO 0 <--
-IFLOXX L1_PUTX 0 <--
-IFLOXX L1_PUTS_only 0 <--
-IFLOXX L1_PUTS 0 <--
-IFLOXX Fwd_GETX 0 <--
-IFLOXX Fwd_GETS 0 <--
-IFLOXX Fwd_DMA 0 <--
-IFLOXX Inv 0 <--
-IFLOXX Unblock 0 <--
-IFLOXX Exclusive_Unblock 0 <--
-IFLOXX L2_Replacement 0 <--
-
-IFLOSX L1_GETS 0 <--
-IFLOSX L1_GETX 0 <--
-IFLOSX L1_PUTO 0 <--
-IFLOSX L1_PUTX 0 <--
-IFLOSX L1_PUTS_only 0 <--
-IFLOSX L1_PUTS 0 <--
-IFLOSX Fwd_GETX 0 <--
-IFLOSX Fwd_GETS 0 <--
-IFLOSX Fwd_DMA 0 <--
-IFLOSX Inv 0 <--
-IFLOSX Unblock 0 <--
-IFLOSX Exclusive_Unblock 0 <--
-IFLOSX L2_Replacement 0 <--
-
-IFLXO L1_GETS 0 <--
-IFLXO L1_GETX 0 <--
-IFLXO L1_PUTO 0 <--
-IFLXO L1_PUTX 0 <--
-IFLXO L1_PUTS_only 0 <--
-IFLXO L1_PUTS 0 <--
-IFLXO Fwd_GETX 0 <--
-IFLXO Fwd_GETS 0 <--
-IFLXO Fwd_DMA 0 <--
-IFLXO Inv 0 <--
-IFLXO Exclusive_Unblock 0 <--
-IFLXO L2_Replacement 0 <--
-
-IGS L1_GETS 0 <--
-IGS L1_GETX 0 <--
-IGS L1_PUTO 0 <--
-IGS L1_PUTX 0 <--
-IGS L1_PUTS_only 0 <--
-IGS L1_PUTS 0 <--
-IGS Fwd_GETX 0 <--
-IGS Fwd_GETS 0 <--
-IGS Fwd_DMA 0 <--
-IGS Own_GETX 0 <--
-IGS Inv 0 <--
-IGS Data 0 <--
-IGS Data_Exclusive 983
-IGS Unblock 0 <--
-IGS Exclusive_Unblock 983
-IGS L2_Replacement 0 <--
-
-IGM L1_GETS 0 <--
-IGM L1_GETX 0 <--
-IGM L1_PUTO 0 <--
-IGM L1_PUTX 0 <--
-IGM L1_PUTS_only 0 <--
-IGM L1_PUTS 0 <--
-IGM Fwd_GETX 0 <--
-IGM Fwd_GETS 0 <--
-IGM Fwd_DMA 0 <--
-IGM Own_GETX 0 <--
-IGM Inv 0 <--
-IGM ExtAck 0 <--
-IGM Data 131
-IGM Data_Exclusive 0 <--
-IGM L2_Replacement 0 <--
-
-IGMLS L1_GETS 0 <--
-IGMLS L1_GETX 0 <--
-IGMLS L1_PUTO 0 <--
-IGMLS L1_PUTX 0 <--
-IGMLS L1_PUTS_only 0 <--
-IGMLS L1_PUTS 0 <--
-IGMLS Inv 0 <--
-IGMLS IntAck 0 <--
-IGMLS ExtAck 0 <--
-IGMLS All_Acks 0 <--
-IGMLS Data 0 <--
-IGMLS Data_Exclusive 0 <--
-IGMLS L2_Replacement 0 <--
-
-IGMO L1_GETS 0 <--
-IGMO L1_GETX 0 <--
-IGMO L1_PUTO 0 <--
-IGMO L1_PUTX 0 <--
-IGMO L1_PUTS_only 0 <--
-IGMO L1_PUTS 0 <--
-IGMO Fwd_GETX 0 <--
-IGMO Fwd_GETS 0 <--
-IGMO Fwd_DMA 0 <--
-IGMO Own_GETX 0 <--
-IGMO ExtAck 0 <--
-IGMO All_Acks 131
-IGMO Exclusive_Unblock 131
-IGMO L2_Replacement 0 <--
-
-IGMIO L1_GETS 0 <--
-IGMIO L1_GETX 0 <--
-IGMIO L1_PUTO 0 <--
-IGMIO L1_PUTX 0 <--
-IGMIO L1_PUTS_only 0 <--
-IGMIO L1_PUTS 0 <--
-IGMIO Fwd_GETX 0 <--
-IGMIO Fwd_GETS 0 <--
-IGMIO Fwd_DMA 0 <--
-IGMIO Own_GETX 0 <--
-IGMIO ExtAck 0 <--
-IGMIO All_Acks 0 <--
-
-OGMIO L1_GETS 0 <--
-OGMIO L1_GETX 0 <--
-OGMIO L1_PUTO 0 <--
-OGMIO L1_PUTX 0 <--
-OGMIO L1_PUTS_only 0 <--
-OGMIO L1_PUTS 0 <--
-OGMIO Fwd_GETX 0 <--
-OGMIO Fwd_GETS 0 <--
-OGMIO Fwd_DMA 0 <--
-OGMIO Own_GETX 0 <--
-OGMIO ExtAck 0 <--
-OGMIO All_Acks 0 <--
-
-IGMIOF L1_GETS 0 <--
-IGMIOF L1_GETX 0 <--
-IGMIOF L1_PUTO 0 <--
-IGMIOF L1_PUTX 0 <--
-IGMIOF L1_PUTS_only 0 <--
-IGMIOF L1_PUTS 0 <--
-IGMIOF IntAck 0 <--
-IGMIOF All_Acks 0 <--
-IGMIOF Data_Exclusive 0 <--
-
-IGMIOFS L1_GETS 0 <--
-IGMIOFS L1_GETX 0 <--
-IGMIOFS L1_PUTO 0 <--
-IGMIOFS L1_PUTX 0 <--
-IGMIOFS L1_PUTS_only 0 <--
-IGMIOFS L1_PUTS 0 <--
-IGMIOFS Fwd_GETX 0 <--
-IGMIOFS Fwd_GETS 0 <--
-IGMIOFS Fwd_DMA 0 <--
-IGMIOFS Inv 0 <--
-IGMIOFS Data 0 <--
-IGMIOFS L2_Replacement 0 <--
-
-OGMIOF L1_GETS 0 <--
-OGMIOF L1_GETX 0 <--
-OGMIOF L1_PUTO 0 <--
-OGMIOF L1_PUTX 0 <--
-OGMIOF L1_PUTS_only 0 <--
-OGMIOF L1_PUTS 0 <--
-OGMIOF IntAck 0 <--
-OGMIOF All_Acks 0 <--
-
-II L1_GETS 0 <--
-II L1_GETX 0 <--
-II L1_PUTO 0 <--
-II L1_PUTX 0 <--
-II L1_PUTS_only 0 <--
-II L1_PUTS 0 <--
-II IntAck 0 <--
-II All_Acks 0 <--
-
-MM L1_GETS 0 <--
-MM L1_GETX 0 <--
-MM L1_PUTO 0 <--
-MM L1_PUTX 0 <--
-MM L1_PUTS_only 0 <--
-MM L1_PUTS 0 <--
-MM Fwd_GETX 0 <--
-MM Fwd_GETS 0 <--
-MM Fwd_DMA 0 <--
-MM Inv 0 <--
-MM Exclusive_Unblock 60
-MM L2_Replacement 0 <--
-
-SS L1_GETS 0 <--
-SS L1_GETX 0 <--
-SS L1_PUTO 0 <--
-SS L1_PUTX 0 <--
-SS L1_PUTS_only 0 <--
-SS L1_PUTS 0 <--
-SS Fwd_GETX 0 <--
-SS Fwd_GETS 0 <--
-SS Fwd_DMA 0 <--
-SS Inv 0 <--
-SS Unblock 0 <--
-SS L2_Replacement 0 <--
-
-OO L1_GETS 0 <--
-OO L1_GETX 0 <--
-OO L1_PUTO 0 <--
-OO L1_PUTX 0 <--
-OO L1_PUTS_only 0 <--
-OO L1_PUTS 0 <--
-OO Fwd_GETX 0 <--
-OO Fwd_GETS 0 <--
-OO Fwd_DMA 0 <--
-OO Inv 0 <--
-OO Unblock 0 <--
-OO Exclusive_Unblock 188
-OO L2_Replacement 0 <--
-
-OLSS L1_GETS 0 <--
-OLSS L1_GETX 0 <--
-OLSS L1_PUTO 0 <--
-OLSS L1_PUTX 0 <--
-OLSS L1_PUTS_only 0 <--
-OLSS L1_PUTS 0 <--
-OLSS Fwd_GETX 0 <--
-OLSS Fwd_GETS 0 <--
-OLSS Fwd_DMA 0 <--
-OLSS Inv 0 <--
-OLSS Unblock 0 <--
-OLSS L2_Replacement 0 <--
-
-OLSXS L1_GETS 0 <--
-OLSXS L1_GETX 0 <--
-OLSXS L1_PUTO 0 <--
-OLSXS L1_PUTX 0 <--
-OLSXS L1_PUTS_only 0 <--
-OLSXS L1_PUTS 0 <--
-OLSXS Fwd_GETX 0 <--
-OLSXS Fwd_GETS 0 <--
-OLSXS Fwd_DMA 0 <--
-OLSXS Inv 0 <--
-OLSXS Unblock 0 <--
-OLSXS L2_Replacement 0 <--
-
-SLSS L1_GETS 0 <--
-SLSS L1_GETX 0 <--
-SLSS L1_PUTO 0 <--
-SLSS L1_PUTX 0 <--
-SLSS L1_PUTS_only 0 <--
-SLSS L1_PUTS 0 <--
-SLSS Fwd_GETX 0 <--
-SLSS Fwd_GETS 0 <--
-SLSS Fwd_DMA 0 <--
-SLSS Inv 0 <--
-SLSS Unblock 0 <--
-SLSS L2_Replacement 0 <--
-
-OI L1_GETS 0 <--
-OI L1_GETX 0 <--
-OI L1_PUTO 0 <--
-OI L1_PUTX 0 <--
-OI L1_PUTS_only 0 <--
-OI L1_PUTS 0 <--
-OI Fwd_GETX 0 <--
-OI Fwd_GETS 0 <--
-OI Fwd_DMA 0 <--
-OI Writeback_Ack 0 <--
-OI Writeback_Nack 0 <--
-OI L2_Replacement 0 <--
-
-MI L1_GETS 0 <--
-MI L1_GETX 0 <--
-MI L1_PUTO 0 <--
-MI L1_PUTX 0 <--
-MI L1_PUTS_only 0 <--
-MI L1_PUTS 0 <--
-MI Fwd_GETX 0 <--
-MI Fwd_GETS 0 <--
-MI Fwd_DMA 0 <--
-MI Writeback_Ack 1098
-MI L2_Replacement 0 <--
-
-MII L1_GETS 0 <--
-MII L1_GETX 0 <--
-MII L1_PUTO 0 <--
-MII L1_PUTX 0 <--
-MII L1_PUTS_only 0 <--
-MII L1_PUTS 0 <--
-MII Writeback_Ack 0 <--
-MII Writeback_Nack 0 <--
-MII L2_Replacement 0 <--
-
-OLSI L1_GETS 0 <--
-OLSI L1_GETX 0 <--
-OLSI L1_PUTO 0 <--
-OLSI L1_PUTX 0 <--
-OLSI L1_PUTS_only 0 <--
-OLSI L1_PUTS 0 <--
-OLSI Fwd_GETX 0 <--
-OLSI Fwd_GETS 0 <--
-OLSI Fwd_DMA 0 <--
-OLSI Writeback_Ack 0 <--
-OLSI L2_Replacement 0 <--
-
-ILSI L1_GETS 0 <--
-ILSI L1_GETX 0 <--
-ILSI L1_PUTO 0 <--
-ILSI L1_PUTX 0 <--
-ILSI L1_PUTS_only 0 <--
-ILSI L1_PUTS 0 <--
-ILSI IntAck 0 <--
-ILSI All_Acks 0 <--
-ILSI Writeback_Ack 0 <--
-ILSI L2_Replacement 0 <--
-
-Memory controller: system.ruby.network.topology.ext_links2.ext_node.memBuffer:
+NP L1_GETS [983 ] 983
+NP L1_GETX [131 ] 131
+NP L1_PUTO [0 ] 0
+NP L1_PUTX [0 ] 0
+NP L1_PUTS [0 ] 0
+NP Inv [0 ] 0
+
+I L1_GETS [0 ] 0
+I L1_GETX [0 ] 0
+I L1_PUTO [0 ] 0
+I L1_PUTX [0 ] 0
+I L1_PUTS [0 ] 0
+I Inv [0 ] 0
+I L2_Replacement [0 ] 0
+
+ILS L1_GETS [0 ] 0
+ILS L1_GETX [0 ] 0
+ILS L1_PUTO [0 ] 0
+ILS L1_PUTX [0 ] 0
+ILS L1_PUTS_only [0 ] 0
+ILS L1_PUTS [0 ] 0
+ILS Inv [0 ] 0
+ILS L2_Replacement [0 ] 0
+
+ILX L1_GETS [0 ] 0
+ILX L1_GETX [0 ] 0
+ILX L1_PUTO [0 ] 0
+ILX L1_PUTX [1354 ] 1354
+ILX L1_PUTS_only [0 ] 0
+ILX L1_PUTS [0 ] 0
+ILX Fwd_GETX [0 ] 0
+ILX Fwd_GETS [0 ] 0
+ILX Fwd_DMA [0 ] 0
+ILX Inv [0 ] 0
+ILX Data [0 ] 0
+ILX L2_Replacement [0 ] 0
+
+ILO L1_GETS [0 ] 0
+ILO L1_GETX [0 ] 0
+ILO L1_PUTO [0 ] 0
+ILO L1_PUTX [0 ] 0
+ILO L1_PUTS [0 ] 0
+ILO Fwd_GETX [0 ] 0
+ILO Fwd_GETS [0 ] 0
+ILO Fwd_DMA [0 ] 0
+ILO Inv [0 ] 0
+ILO Data [0 ] 0
+ILO L2_Replacement [0 ] 0
+
+ILOX L1_GETS [0 ] 0
+ILOX L1_GETX [0 ] 0
+ILOX L1_PUTO [0 ] 0
+ILOX L1_PUTX [0 ] 0
+ILOX L1_PUTS [0 ] 0
+ILOX Fwd_GETX [0 ] 0
+ILOX Fwd_GETS [0 ] 0
+ILOX Fwd_DMA [0 ] 0
+ILOX Data [0 ] 0
+
+ILOS L1_GETS [0 ] 0
+ILOS L1_GETX [0 ] 0
+ILOS L1_PUTO [0 ] 0
+ILOS L1_PUTX [0 ] 0
+ILOS L1_PUTS_only [0 ] 0
+ILOS L1_PUTS [0 ] 0
+ILOS Fwd_GETX [0 ] 0
+ILOS Fwd_GETS [0 ] 0
+ILOS Fwd_DMA [0 ] 0
+ILOS Data [0 ] 0
+ILOS L2_Replacement [0 ] 0
+
+ILOSX L1_GETS [0 ] 0
+ILOSX L1_GETX [0 ] 0
+ILOSX L1_PUTO [0 ] 0
+ILOSX L1_PUTX [0 ] 0
+ILOSX L1_PUTS_only [0 ] 0
+ILOSX L1_PUTS [0 ] 0
+ILOSX Fwd_GETX [0 ] 0
+ILOSX Fwd_GETS [0 ] 0
+ILOSX Fwd_DMA [0 ] 0
+ILOSX Data [0 ] 0
+
+S L1_GETS [0 ] 0
+S L1_GETX [0 ] 0
+S L1_PUTX [0 ] 0
+S L1_PUTS [0 ] 0
+S Inv [0 ] 0
+S L2_Replacement [0 ] 0
+
+O L1_GETS [0 ] 0
+O L1_GETX [0 ] 0
+O L1_PUTX [0 ] 0
+O Fwd_GETX [0 ] 0
+O Fwd_GETS [0 ] 0
+O Fwd_DMA [0 ] 0
+O L2_Replacement [0 ] 0
+
+OLS L1_GETS [0 ] 0
+OLS L1_GETX [0 ] 0
+OLS L1_PUTX [0 ] 0
+OLS L1_PUTS_only [0 ] 0
+OLS L1_PUTS [0 ] 0
+OLS Fwd_GETX [0 ] 0
+OLS Fwd_GETS [0 ] 0
+OLS Fwd_DMA [0 ] 0
+OLS L2_Replacement [0 ] 0
+
+OLSX L1_GETS [0 ] 0
+OLSX L1_GETX [0 ] 0
+OLSX L1_PUTO [0 ] 0
+OLSX L1_PUTX [0 ] 0
+OLSX L1_PUTS_only [0 ] 0
+OLSX L1_PUTS [0 ] 0
+OLSX Fwd_GETX [0 ] 0
+OLSX Fwd_GETS [0 ] 0
+OLSX Fwd_DMA [0 ] 0
+OLSX L2_Replacement [0 ] 0
+
+SLS L1_GETS [0 ] 0
+SLS L1_GETX [0 ] 0
+SLS L1_PUTX [0 ] 0
+SLS L1_PUTS_only [0 ] 0
+SLS L1_PUTS [0 ] 0
+SLS Inv [0 ] 0
+SLS L2_Replacement [0 ] 0
+
+M L1_GETS [188 ] 188
+M L1_GETX [60 ] 60
+M L1_PUTO [0 ] 0
+M L1_PUTX [0 ] 0
+M L1_PUTS [0 ] 0
+M Fwd_GETX [0 ] 0
+M Fwd_GETS [0 ] 0
+M Fwd_DMA [0 ] 0
+M L2_Replacement [1098 ] 1098
+
+IFGX L1_GETS [0 ] 0
+IFGX L1_GETX [0 ] 0
+IFGX L1_PUTO [0 ] 0
+IFGX L1_PUTX [0 ] 0
+IFGX L1_PUTS_only [0 ] 0
+IFGX L1_PUTS [0 ] 0
+IFGX Fwd_GETX [0 ] 0
+IFGX Fwd_GETS [0 ] 0
+IFGX Fwd_DMA [0 ] 0
+IFGX Inv [0 ] 0
+IFGX Data [0 ] 0
+IFGX Data_Exclusive [0 ] 0
+IFGX L2_Replacement [0 ] 0
+
+IFGS L1_GETS [0 ] 0
+IFGS L1_GETX [0 ] 0
+IFGS L1_PUTO [0 ] 0
+IFGS L1_PUTX [0 ] 0
+IFGS L1_PUTS_only [0 ] 0
+IFGS L1_PUTS [0 ] 0
+IFGS Fwd_GETX [0 ] 0
+IFGS Fwd_GETS [0 ] 0
+IFGS Fwd_DMA [0 ] 0
+IFGS Inv [0 ] 0
+IFGS Data [0 ] 0
+IFGS Data_Exclusive [0 ] 0
+IFGS L2_Replacement [0 ] 0
+
+ISFGS L1_GETS [0 ] 0
+ISFGS L1_GETX [0 ] 0
+ISFGS L1_PUTO [0 ] 0
+ISFGS L1_PUTX [0 ] 0
+ISFGS L1_PUTS_only [0 ] 0
+ISFGS L1_PUTS [0 ] 0
+ISFGS Fwd_GETX [0 ] 0
+ISFGS Fwd_GETS [0 ] 0
+ISFGS Fwd_DMA [0 ] 0
+ISFGS Inv [0 ] 0
+ISFGS Data [0 ] 0
+ISFGS L2_Replacement [0 ] 0
+
+IFGXX L1_GETS [0 ] 0
+IFGXX L1_GETX [0 ] 0
+IFGXX L1_PUTO [0 ] 0
+IFGXX L1_PUTX [0 ] 0
+IFGXX L1_PUTS_only [0 ] 0
+IFGXX L1_PUTS [0 ] 0
+IFGXX Fwd_GETX [0 ] 0
+IFGXX Fwd_GETS [0 ] 0
+IFGXX Fwd_DMA [0 ] 0
+IFGXX Inv [0 ] 0
+IFGXX IntAck [0 ] 0
+IFGXX All_Acks [0 ] 0
+IFGXX Data_Exclusive [0 ] 0
+IFGXX L2_Replacement [0 ] 0
+
+OFGX L1_GETS [0 ] 0
+OFGX L1_GETX [0 ] 0
+OFGX L1_PUTO [0 ] 0
+OFGX L1_PUTX [0 ] 0
+OFGX L1_PUTS_only [0 ] 0
+OFGX L1_PUTS [0 ] 0
+OFGX Fwd_GETX [0 ] 0
+OFGX Fwd_GETS [0 ] 0
+OFGX Fwd_DMA [0 ] 0
+OFGX Inv [0 ] 0
+OFGX L2_Replacement [0 ] 0
+
+OLSF L1_GETS [0 ] 0
+OLSF L1_GETX [0 ] 0
+OLSF L1_PUTO [0 ] 0
+OLSF L1_PUTX [0 ] 0
+OLSF L1_PUTS_only [0 ] 0
+OLSF L1_PUTS [0 ] 0
+OLSF Fwd_GETX [0 ] 0
+OLSF Fwd_GETS [0 ] 0
+OLSF Fwd_DMA [0 ] 0
+OLSF Inv [0 ] 0
+OLSF IntAck [0 ] 0
+OLSF All_Acks [0 ] 0
+OLSF L2_Replacement [0 ] 0
+
+ILOW L1_GETS [0 ] 0
+ILOW L1_GETX [0 ] 0
+ILOW L1_PUTO [0 ] 0
+ILOW L1_PUTX [0 ] 0
+ILOW L1_PUTS_only [0 ] 0
+ILOW L1_PUTS [0 ] 0
+ILOW Fwd_GETX [0 ] 0
+ILOW Fwd_GETS [0 ] 0
+ILOW Fwd_DMA [0 ] 0
+ILOW Inv [0 ] 0
+ILOW L1_WBCLEANDATA [0 ] 0
+ILOW L1_WBDIRTYDATA [0 ] 0
+ILOW Unblock [0 ] 0
+ILOW L2_Replacement [0 ] 0
+
+ILOXW L1_GETS [0 ] 0
+ILOXW L1_GETX [0 ] 0
+ILOXW L1_PUTO [0 ] 0
+ILOXW L1_PUTX [0 ] 0
+ILOXW L1_PUTS_only [0 ] 0
+ILOXW L1_PUTS [0 ] 0
+ILOXW Fwd_GETX [0 ] 0
+ILOXW Fwd_GETS [0 ] 0
+ILOXW Fwd_DMA [0 ] 0
+ILOXW Inv [0 ] 0
+ILOXW L1_WBCLEANDATA [0 ] 0
+ILOXW L1_WBDIRTYDATA [0 ] 0
+ILOXW Unblock [0 ] 0
+ILOXW L2_Replacement [0 ] 0
+
+ILOSW L1_GETS [0 ] 0
+ILOSW L1_GETX [0 ] 0
+ILOSW L1_PUTO [0 ] 0
+ILOSW L1_PUTX [0 ] 0
+ILOSW L1_PUTS_only [0 ] 0
+ILOSW L1_PUTS [0 ] 0
+ILOSW Fwd_GETX [0 ] 0
+ILOSW Fwd_GETS [0 ] 0
+ILOSW Fwd_DMA [0 ] 0
+ILOSW Inv [0 ] 0
+ILOSW L1_WBCLEANDATA [0 ] 0
+ILOSW L1_WBDIRTYDATA [0 ] 0
+ILOSW Unblock [0 ] 0
+ILOSW L2_Replacement [0 ] 0
+
+ILOSXW L1_GETS [0 ] 0
+ILOSXW L1_GETX [0 ] 0
+ILOSXW L1_PUTO [0 ] 0
+ILOSXW L1_PUTX [0 ] 0
+ILOSXW L1_PUTS_only [0 ] 0
+ILOSXW L1_PUTS [0 ] 0
+ILOSXW Fwd_GETX [0 ] 0
+ILOSXW Fwd_GETS [0 ] 0
+ILOSXW Fwd_DMA [0 ] 0
+ILOSXW Inv [0 ] 0
+ILOSXW L1_WBCLEANDATA [0 ] 0
+ILOSXW L1_WBDIRTYDATA [0 ] 0
+ILOSXW Unblock [0 ] 0
+ILOSXW L2_Replacement [0 ] 0
+
+SLSW L1_GETS [0 ] 0
+SLSW L1_GETX [0 ] 0
+SLSW L1_PUTO [0 ] 0
+SLSW L1_PUTX [0 ] 0
+SLSW L1_PUTS_only [0 ] 0
+SLSW L1_PUTS [0 ] 0
+SLSW Fwd_GETX [0 ] 0
+SLSW Fwd_GETS [0 ] 0
+SLSW Fwd_DMA [0 ] 0
+SLSW Inv [0 ] 0
+SLSW Unblock [0 ] 0
+SLSW L2_Replacement [0 ] 0
+
+OLSW L1_GETS [0 ] 0
+OLSW L1_GETX [0 ] 0
+OLSW L1_PUTO [0 ] 0
+OLSW L1_PUTX [0 ] 0
+OLSW L1_PUTS_only [0 ] 0
+OLSW L1_PUTS [0 ] 0
+OLSW Fwd_GETX [0 ] 0
+OLSW Fwd_GETS [0 ] 0
+OLSW Fwd_DMA [0 ] 0
+OLSW Inv [0 ] 0
+OLSW Unblock [0 ] 0
+OLSW L2_Replacement [0 ] 0
+
+ILSW L1_GETS [0 ] 0
+ILSW L1_GETX [0 ] 0
+ILSW L1_PUTO [0 ] 0
+ILSW L1_PUTX [0 ] 0
+ILSW L1_PUTS_only [0 ] 0
+ILSW L1_PUTS [0 ] 0
+ILSW Fwd_GETX [0 ] 0
+ILSW Fwd_GETS [0 ] 0
+ILSW Fwd_DMA [0 ] 0
+ILSW Inv [0 ] 0
+ILSW L1_WBCLEANDATA [0 ] 0
+ILSW Unblock [0 ] 0
+ILSW L2_Replacement [0 ] 0
+
+IW L1_GETS [0 ] 0
+IW L1_GETX [0 ] 0
+IW L1_PUTO [0 ] 0
+IW L1_PUTX [0 ] 0
+IW L1_PUTS_only [0 ] 0
+IW L1_PUTS [0 ] 0
+IW Fwd_GETX [0 ] 0
+IW Fwd_GETS [0 ] 0
+IW Fwd_DMA [0 ] 0
+IW Inv [0 ] 0
+IW L1_WBCLEANDATA [0 ] 0
+IW L2_Replacement [0 ] 0
+
+OW L1_GETS [0 ] 0
+OW L1_GETX [0 ] 0
+OW L1_PUTO [0 ] 0
+OW L1_PUTX [0 ] 0
+OW L1_PUTS_only [0 ] 0
+OW L1_PUTS [0 ] 0
+OW Fwd_GETX [0 ] 0
+OW Fwd_GETS [0 ] 0
+OW Fwd_DMA [0 ] 0
+OW Inv [0 ] 0
+OW Unblock [0 ] 0
+OW L2_Replacement [0 ] 0
+
+SW L1_GETS [0 ] 0
+SW L1_GETX [0 ] 0
+SW L1_PUTO [0 ] 0
+SW L1_PUTX [0 ] 0
+SW L1_PUTS_only [0 ] 0
+SW L1_PUTS [0 ] 0
+SW Fwd_GETX [0 ] 0
+SW Fwd_GETS [0 ] 0
+SW Fwd_DMA [0 ] 0
+SW Inv [0 ] 0
+SW Unblock [0 ] 0
+SW L2_Replacement [0 ] 0
+
+OXW L1_GETS [0 ] 0
+OXW L1_GETX [0 ] 0
+OXW L1_PUTO [0 ] 0
+OXW L1_PUTX [0 ] 0
+OXW L1_PUTS_only [0 ] 0
+OXW L1_PUTS [0 ] 0
+OXW Fwd_GETX [0 ] 0
+OXW Fwd_GETS [0 ] 0
+OXW Fwd_DMA [0 ] 0
+OXW Inv [0 ] 0
+OXW Unblock [0 ] 0
+OXW L2_Replacement [0 ] 0
+
+OLSXW L1_GETS [0 ] 0
+OLSXW L1_GETX [0 ] 0
+OLSXW L1_PUTO [0 ] 0
+OLSXW L1_PUTX [0 ] 0
+OLSXW L1_PUTS_only [0 ] 0
+OLSXW L1_PUTS [0 ] 0
+OLSXW Fwd_GETX [0 ] 0
+OLSXW Fwd_GETS [0 ] 0
+OLSXW Fwd_DMA [0 ] 0
+OLSXW Inv [0 ] 0
+OLSXW Unblock [0 ] 0
+OLSXW L2_Replacement [0 ] 0
+
+ILXW L1_GETS [0 ] 0
+ILXW L1_GETX [0 ] 0
+ILXW L1_PUTO [0 ] 0
+ILXW L1_PUTX [0 ] 0
+ILXW L1_PUTS_only [0 ] 0
+ILXW L1_PUTS [0 ] 0
+ILXW Fwd_GETX [0 ] 0
+ILXW Fwd_GETS [0 ] 0
+ILXW Fwd_DMA [0 ] 0
+ILXW Inv [0 ] 0
+ILXW Data [0 ] 0
+ILXW L1_WBCLEANDATA [1059 ] 1059
+ILXW L1_WBDIRTYDATA [295 ] 295
+ILXW Unblock [0 ] 0
+ILXW L2_Replacement [0 ] 0
+
+IFLS L1_GETS [0 ] 0
+IFLS L1_GETX [0 ] 0
+IFLS L1_PUTO [0 ] 0
+IFLS L1_PUTX [0 ] 0
+IFLS L1_PUTS_only [0 ] 0
+IFLS L1_PUTS [0 ] 0
+IFLS Fwd_GETX [0 ] 0
+IFLS Fwd_GETS [0 ] 0
+IFLS Fwd_DMA [0 ] 0
+IFLS Inv [0 ] 0
+IFLS Unblock [0 ] 0
+IFLS L2_Replacement [0 ] 0
+
+IFLO L1_GETS [0 ] 0
+IFLO L1_GETX [0 ] 0
+IFLO L1_PUTO [0 ] 0
+IFLO L1_PUTX [0 ] 0
+IFLO L1_PUTS_only [0 ] 0
+IFLO L1_PUTS [0 ] 0
+IFLO Fwd_GETX [0 ] 0
+IFLO Fwd_GETS [0 ] 0
+IFLO Fwd_DMA [0 ] 0
+IFLO Inv [0 ] 0
+IFLO Unblock [0 ] 0
+IFLO L2_Replacement [0 ] 0
+
+IFLOX L1_GETS [0 ] 0
+IFLOX L1_GETX [0 ] 0
+IFLOX L1_PUTO [0 ] 0
+IFLOX L1_PUTX [0 ] 0
+IFLOX L1_PUTS_only [0 ] 0
+IFLOX L1_PUTS [0 ] 0
+IFLOX Fwd_GETX [0 ] 0
+IFLOX Fwd_GETS [0 ] 0
+IFLOX Fwd_DMA [0 ] 0
+IFLOX Inv [0 ] 0
+IFLOX Unblock [0 ] 0
+IFLOX Exclusive_Unblock [0 ] 0
+IFLOX L2_Replacement [0 ] 0
+
+IFLOXX L1_GETS [0 ] 0
+IFLOXX L1_GETX [0 ] 0
+IFLOXX L1_PUTO [0 ] 0
+IFLOXX L1_PUTX [0 ] 0
+IFLOXX L1_PUTS_only [0 ] 0
+IFLOXX L1_PUTS [0 ] 0
+IFLOXX Fwd_GETX [0 ] 0
+IFLOXX Fwd_GETS [0 ] 0
+IFLOXX Fwd_DMA [0 ] 0
+IFLOXX Inv [0 ] 0
+IFLOXX Unblock [0 ] 0
+IFLOXX Exclusive_Unblock [0 ] 0
+IFLOXX L2_Replacement [0 ] 0
+
+IFLOSX L1_GETS [0 ] 0
+IFLOSX L1_GETX [0 ] 0
+IFLOSX L1_PUTO [0 ] 0
+IFLOSX L1_PUTX [0 ] 0
+IFLOSX L1_PUTS_only [0 ] 0
+IFLOSX L1_PUTS [0 ] 0
+IFLOSX Fwd_GETX [0 ] 0
+IFLOSX Fwd_GETS [0 ] 0
+IFLOSX Fwd_DMA [0 ] 0
+IFLOSX Inv [0 ] 0
+IFLOSX Unblock [0 ] 0
+IFLOSX Exclusive_Unblock [0 ] 0
+IFLOSX L2_Replacement [0 ] 0
+
+IFLXO L1_GETS [0 ] 0
+IFLXO L1_GETX [0 ] 0
+IFLXO L1_PUTO [0 ] 0
+IFLXO L1_PUTX [0 ] 0
+IFLXO L1_PUTS_only [0 ] 0
+IFLXO L1_PUTS [0 ] 0
+IFLXO Fwd_GETX [0 ] 0
+IFLXO Fwd_GETS [0 ] 0
+IFLXO Fwd_DMA [0 ] 0
+IFLXO Inv [0 ] 0
+IFLXO Exclusive_Unblock [0 ] 0
+IFLXO L2_Replacement [0 ] 0
+
+IGS L1_GETS [0 ] 0
+IGS L1_GETX [0 ] 0
+IGS L1_PUTO [0 ] 0
+IGS L1_PUTX [0 ] 0
+IGS L1_PUTS_only [0 ] 0
+IGS L1_PUTS [0 ] 0
+IGS Fwd_GETX [0 ] 0
+IGS Fwd_GETS [0 ] 0
+IGS Fwd_DMA [0 ] 0
+IGS Own_GETX [0 ] 0
+IGS Inv [0 ] 0
+IGS Data [0 ] 0
+IGS Data_Exclusive [983 ] 983
+IGS Unblock [0 ] 0
+IGS Exclusive_Unblock [983 ] 983
+IGS L2_Replacement [0 ] 0
+
+IGM L1_GETS [0 ] 0
+IGM L1_GETX [0 ] 0
+IGM L1_PUTO [0 ] 0
+IGM L1_PUTX [0 ] 0
+IGM L1_PUTS_only [0 ] 0
+IGM L1_PUTS [0 ] 0
+IGM Fwd_GETX [0 ] 0
+IGM Fwd_GETS [0 ] 0
+IGM Fwd_DMA [0 ] 0
+IGM Own_GETX [0 ] 0
+IGM Inv [0 ] 0
+IGM ExtAck [0 ] 0
+IGM Data [131 ] 131
+IGM Data_Exclusive [0 ] 0
+IGM L2_Replacement [0 ] 0
+
+IGMLS L1_GETS [0 ] 0
+IGMLS L1_GETX [0 ] 0
+IGMLS L1_PUTO [0 ] 0
+IGMLS L1_PUTX [0 ] 0
+IGMLS L1_PUTS_only [0 ] 0
+IGMLS L1_PUTS [0 ] 0
+IGMLS Inv [0 ] 0
+IGMLS IntAck [0 ] 0
+IGMLS ExtAck [0 ] 0
+IGMLS All_Acks [0 ] 0
+IGMLS Data [0 ] 0
+IGMLS Data_Exclusive [0 ] 0
+IGMLS L2_Replacement [0 ] 0
+
+IGMO L1_GETS [0 ] 0
+IGMO L1_GETX [0 ] 0
+IGMO L1_PUTO [0 ] 0
+IGMO L1_PUTX [0 ] 0
+IGMO L1_PUTS_only [0 ] 0
+IGMO L1_PUTS [0 ] 0
+IGMO Fwd_GETX [0 ] 0
+IGMO Fwd_GETS [0 ] 0
+IGMO Fwd_DMA [0 ] 0
+IGMO Own_GETX [0 ] 0
+IGMO ExtAck [0 ] 0
+IGMO All_Acks [131 ] 131
+IGMO Exclusive_Unblock [131 ] 131
+IGMO L2_Replacement [0 ] 0
+
+IGMIO L1_GETS [0 ] 0
+IGMIO L1_GETX [0 ] 0
+IGMIO L1_PUTO [0 ] 0
+IGMIO L1_PUTX [0 ] 0
+IGMIO L1_PUTS_only [0 ] 0
+IGMIO L1_PUTS [0 ] 0
+IGMIO Fwd_GETX [0 ] 0
+IGMIO Fwd_GETS [0 ] 0
+IGMIO Fwd_DMA [0 ] 0
+IGMIO Own_GETX [0 ] 0
+IGMIO ExtAck [0 ] 0
+IGMIO All_Acks [0 ] 0
+
+OGMIO L1_GETS [0 ] 0
+OGMIO L1_GETX [0 ] 0
+OGMIO L1_PUTO [0 ] 0
+OGMIO L1_PUTX [0 ] 0
+OGMIO L1_PUTS_only [0 ] 0
+OGMIO L1_PUTS [0 ] 0
+OGMIO Fwd_GETX [0 ] 0
+OGMIO Fwd_GETS [0 ] 0
+OGMIO Fwd_DMA [0 ] 0
+OGMIO Own_GETX [0 ] 0
+OGMIO ExtAck [0 ] 0
+OGMIO All_Acks [0 ] 0
+
+IGMIOF L1_GETS [0 ] 0
+IGMIOF L1_GETX [0 ] 0
+IGMIOF L1_PUTO [0 ] 0
+IGMIOF L1_PUTX [0 ] 0
+IGMIOF L1_PUTS_only [0 ] 0
+IGMIOF L1_PUTS [0 ] 0
+IGMIOF IntAck [0 ] 0
+IGMIOF All_Acks [0 ] 0
+IGMIOF Data_Exclusive [0 ] 0
+
+IGMIOFS L1_GETS [0 ] 0
+IGMIOFS L1_GETX [0 ] 0
+IGMIOFS L1_PUTO [0 ] 0
+IGMIOFS L1_PUTX [0 ] 0
+IGMIOFS L1_PUTS_only [0 ] 0
+IGMIOFS L1_PUTS [0 ] 0
+IGMIOFS Fwd_GETX [0 ] 0
+IGMIOFS Fwd_GETS [0 ] 0
+IGMIOFS Fwd_DMA [0 ] 0
+IGMIOFS Inv [0 ] 0
+IGMIOFS Data [0 ] 0
+IGMIOFS L2_Replacement [0 ] 0
+
+OGMIOF L1_GETS [0 ] 0
+OGMIOF L1_GETX [0 ] 0
+OGMIOF L1_PUTO [0 ] 0
+OGMIOF L1_PUTX [0 ] 0
+OGMIOF L1_PUTS_only [0 ] 0
+OGMIOF L1_PUTS [0 ] 0
+OGMIOF IntAck [0 ] 0
+OGMIOF All_Acks [0 ] 0
+
+II L1_GETS [0 ] 0
+II L1_GETX [0 ] 0
+II L1_PUTO [0 ] 0
+II L1_PUTX [0 ] 0
+II L1_PUTS_only [0 ] 0
+II L1_PUTS [0 ] 0
+II IntAck [0 ] 0
+II All_Acks [0 ] 0
+
+MM L1_GETS [0 ] 0
+MM L1_GETX [0 ] 0
+MM L1_PUTO [0 ] 0
+MM L1_PUTX [0 ] 0
+MM L1_PUTS_only [0 ] 0
+MM L1_PUTS [0 ] 0
+MM Fwd_GETX [0 ] 0
+MM Fwd_GETS [0 ] 0
+MM Fwd_DMA [0 ] 0
+MM Inv [0 ] 0
+MM Exclusive_Unblock [60 ] 60
+MM L2_Replacement [0 ] 0
+
+SS L1_GETS [0 ] 0
+SS L1_GETX [0 ] 0
+SS L1_PUTO [0 ] 0
+SS L1_PUTX [0 ] 0
+SS L1_PUTS_only [0 ] 0
+SS L1_PUTS [0 ] 0
+SS Fwd_GETX [0 ] 0
+SS Fwd_GETS [0 ] 0
+SS Fwd_DMA [0 ] 0
+SS Inv [0 ] 0
+SS Unblock [0 ] 0
+SS L2_Replacement [0 ] 0
+
+OO L1_GETS [0 ] 0
+OO L1_GETX [0 ] 0
+OO L1_PUTO [0 ] 0
+OO L1_PUTX [0 ] 0
+OO L1_PUTS_only [0 ] 0
+OO L1_PUTS [0 ] 0
+OO Fwd_GETX [0 ] 0
+OO Fwd_GETS [0 ] 0
+OO Fwd_DMA [0 ] 0
+OO Inv [0 ] 0
+OO Unblock [0 ] 0
+OO Exclusive_Unblock [188 ] 188
+OO L2_Replacement [0 ] 0
+
+OLSS L1_GETS [0 ] 0
+OLSS L1_GETX [0 ] 0
+OLSS L1_PUTO [0 ] 0
+OLSS L1_PUTX [0 ] 0
+OLSS L1_PUTS_only [0 ] 0
+OLSS L1_PUTS [0 ] 0
+OLSS Fwd_GETX [0 ] 0
+OLSS Fwd_GETS [0 ] 0
+OLSS Fwd_DMA [0 ] 0
+OLSS Inv [0 ] 0
+OLSS Unblock [0 ] 0
+OLSS L2_Replacement [0 ] 0
+
+OLSXS L1_GETS [0 ] 0
+OLSXS L1_GETX [0 ] 0
+OLSXS L1_PUTO [0 ] 0
+OLSXS L1_PUTX [0 ] 0
+OLSXS L1_PUTS_only [0 ] 0
+OLSXS L1_PUTS [0 ] 0
+OLSXS Fwd_GETX [0 ] 0
+OLSXS Fwd_GETS [0 ] 0
+OLSXS Fwd_DMA [0 ] 0
+OLSXS Inv [0 ] 0
+OLSXS Unblock [0 ] 0
+OLSXS L2_Replacement [0 ] 0
+
+SLSS L1_GETS [0 ] 0
+SLSS L1_GETX [0 ] 0
+SLSS L1_PUTO [0 ] 0
+SLSS L1_PUTX [0 ] 0
+SLSS L1_PUTS_only [0 ] 0
+SLSS L1_PUTS [0 ] 0
+SLSS Fwd_GETX [0 ] 0
+SLSS Fwd_GETS [0 ] 0
+SLSS Fwd_DMA [0 ] 0
+SLSS Inv [0 ] 0
+SLSS Unblock [0 ] 0
+SLSS L2_Replacement [0 ] 0
+
+OI L1_GETS [0 ] 0
+OI L1_GETX [0 ] 0
+OI L1_PUTO [0 ] 0
+OI L1_PUTX [0 ] 0
+OI L1_PUTS_only [0 ] 0
+OI L1_PUTS [0 ] 0
+OI Fwd_GETX [0 ] 0
+OI Fwd_GETS [0 ] 0
+OI Fwd_DMA [0 ] 0
+OI Writeback_Ack [0 ] 0
+OI Writeback_Nack [0 ] 0
+OI L2_Replacement [0 ] 0
+
+MI L1_GETS [0 ] 0
+MI L1_GETX [0 ] 0
+MI L1_PUTO [0 ] 0
+MI L1_PUTX [0 ] 0
+MI L1_PUTS_only [0 ] 0
+MI L1_PUTS [0 ] 0
+MI Fwd_GETX [0 ] 0
+MI Fwd_GETS [0 ] 0
+MI Fwd_DMA [0 ] 0
+MI Writeback_Ack [1098 ] 1098
+MI L2_Replacement [0 ] 0
+
+MII L1_GETS [0 ] 0
+MII L1_GETX [0 ] 0
+MII L1_PUTO [0 ] 0
+MII L1_PUTX [0 ] 0
+MII L1_PUTS_only [0 ] 0
+MII L1_PUTS [0 ] 0
+MII Writeback_Ack [0 ] 0
+MII Writeback_Nack [0 ] 0
+MII L2_Replacement [0 ] 0
+
+OLSI L1_GETS [0 ] 0
+OLSI L1_GETX [0 ] 0
+OLSI L1_PUTO [0 ] 0
+OLSI L1_PUTX [0 ] 0
+OLSI L1_PUTS_only [0 ] 0
+OLSI L1_PUTS [0 ] 0
+OLSI Fwd_GETX [0 ] 0
+OLSI Fwd_GETS [0 ] 0
+OLSI Fwd_DMA [0 ] 0
+OLSI Writeback_Ack [0 ] 0
+OLSI L2_Replacement [0 ] 0
+
+ILSI L1_GETS [0 ] 0
+ILSI L1_GETX [0 ] 0
+ILSI L1_PUTO [0 ] 0
+ILSI L1_PUTX [0 ] 0
+ILSI L1_PUTS_only [0 ] 0
+ILSI L1_PUTS [0 ] 0
+ILSI IntAck [0 ] 0
+ILSI All_Acks [0 ] 0
+ILSI Writeback_Ack [0 ] 0
+ILSI L2_Replacement [0 ] 0
+
+Memory controller: system.dir_cntrl0.memBuffer:
memory_total_requests: 1308
memory_reads: 1114
memory_writes: 194
@@ -1175,201 +1180,200 @@ Memory controller: system.ruby.network.topology.ext_links2.ext_node.memBuffer:
memory_stalls_for_read_read_turnaround: 0
accesses_per_bank: 75 17 45 40 54 99 29 16 19 22 32 34 52 48 38 30 39 21 21 27 28 37 55 22 31 22 32 70 84 104 13 52
- --- Directory 0 ---
+ --- Directory ---
- Event Counts -
-GETX 131
-GETS 983
-PUTX 1098
-PUTO 0
-PUTO_SHARERS 0
-Unblock 0
-Last_Unblock 0
-Exclusive_Unblock 1114
-Clean_Writeback 904
-Dirty_Writeback 194
-Memory_Data 1114
-Memory_Ack 194
-DMA_READ 0
-DMA_WRITE 0
-Data 0
+GETX [131 ] 131
+GETS [983 ] 983
+PUTX [1098 ] 1098
+PUTO [0 ] 0
+PUTO_SHARERS [0 ] 0
+Unblock [0 ] 0
+Last_Unblock [0 ] 0
+Exclusive_Unblock [1114 ] 1114
+Clean_Writeback [904 ] 904
+Dirty_Writeback [194 ] 194
+Memory_Data [1114 ] 1114
+Memory_Ack [194 ] 194
+DMA_READ [0 ] 0
+DMA_WRITE [0 ] 0
+Data [0 ] 0
- Transitions -
-I GETX 131
-I GETS 983
-I PUTX 0 <--
-I PUTO 0 <--
-I Memory_Data 0 <--
-I Memory_Ack 191
-I DMA_READ 0 <--
-I DMA_WRITE 0 <--
-
-S GETX 0 <--
-S GETS 0 <--
-S PUTX 0 <--
-S PUTO 0 <--
-S Memory_Data 0 <--
-S Memory_Ack 0 <--
-S DMA_READ 0 <--
-S DMA_WRITE 0 <--
-
-O GETX 0 <--
-O GETS 0 <--
-O PUTX 0 <--
-O PUTO 0 <--
-O PUTO_SHARERS 0 <--
-O Memory_Data 0 <--
-O Memory_Ack 0 <--
-O DMA_READ 0 <--
-O DMA_WRITE 0 <--
-
-M GETX 0 <--
-M GETS 0 <--
-M PUTX 1098
-M PUTO 0 <--
-M PUTO_SHARERS 0 <--
-M Memory_Data 0 <--
-M Memory_Ack 0 <--
-M DMA_READ 0 <--
-M DMA_WRITE 0 <--
-
-IS GETX 0 <--
-IS GETS 0 <--
-IS PUTX 0 <--
-IS PUTO 0 <--
-IS PUTO_SHARERS 0 <--
-IS Unblock 0 <--
-IS Exclusive_Unblock 983
-IS Memory_Data 983
-IS Memory_Ack 2
-IS DMA_READ 0 <--
-IS DMA_WRITE 0 <--
-
-SS GETX 0 <--
-SS GETS 0 <--
-SS PUTX 0 <--
-SS PUTO 0 <--
-SS PUTO_SHARERS 0 <--
-SS Unblock 0 <--
-SS Last_Unblock 0 <--
-SS Memory_Data 0 <--
-SS Memory_Ack 0 <--
-SS DMA_READ 0 <--
-SS DMA_WRITE 0 <--
-
-OO GETX 0 <--
-OO GETS 0 <--
-OO PUTX 0 <--
-OO PUTO 0 <--
-OO PUTO_SHARERS 0 <--
-OO Unblock 0 <--
-OO Last_Unblock 0 <--
-OO Memory_Data 0 <--
-OO Memory_Ack 0 <--
-OO DMA_READ 0 <--
-OO DMA_WRITE 0 <--
-
-MO GETX 0 <--
-MO GETS 0 <--
-MO PUTX 0 <--
-MO PUTO 0 <--
-MO PUTO_SHARERS 0 <--
-MO Unblock 0 <--
-MO Exclusive_Unblock 0 <--
-MO Memory_Data 0 <--
-MO Memory_Ack 0 <--
-MO DMA_READ 0 <--
-MO DMA_WRITE 0 <--
-
-MM GETX 0 <--
-MM GETS 0 <--
-MM PUTX 0 <--
-MM PUTO 0 <--
-MM PUTO_SHARERS 0 <--
-MM Exclusive_Unblock 131
-MM Memory_Data 131
-MM Memory_Ack 1
-MM DMA_READ 0 <--
-MM DMA_WRITE 0 <--
-
-
-MI GETX 0 <--
-MI GETS 0 <--
-MI PUTX 0 <--
-MI PUTO 0 <--
-MI PUTO_SHARERS 0 <--
-MI Unblock 0 <--
-MI Clean_Writeback 904
-MI Dirty_Writeback 194
-MI Memory_Data 0 <--
-MI Memory_Ack 0 <--
-MI DMA_READ 0 <--
-MI DMA_WRITE 0 <--
-
-MIS GETX 0 <--
-MIS GETS 0 <--
-MIS PUTX 0 <--
-MIS PUTO 0 <--
-MIS PUTO_SHARERS 0 <--
-MIS Unblock 0 <--
-MIS Clean_Writeback 0 <--
-MIS Dirty_Writeback 0 <--
-MIS Memory_Data 0 <--
-MIS Memory_Ack 0 <--
-MIS DMA_READ 0 <--
-MIS DMA_WRITE 0 <--
-
-OS GETX 0 <--
-OS GETS 0 <--
-OS PUTX 0 <--
-OS PUTO 0 <--
-OS PUTO_SHARERS 0 <--
-OS Unblock 0 <--
-OS Clean_Writeback 0 <--
-OS Dirty_Writeback 0 <--
-OS Memory_Data 0 <--
-OS Memory_Ack 0 <--
-OS DMA_READ 0 <--
-OS DMA_WRITE 0 <--
-
-OSS GETX 0 <--
-OSS GETS 0 <--
-OSS PUTX 0 <--
-OSS PUTO 0 <--
-OSS PUTO_SHARERS 0 <--
-OSS Unblock 0 <--
-OSS Clean_Writeback 0 <--
-OSS Dirty_Writeback 0 <--
-OSS Memory_Data 0 <--
-OSS Memory_Ack 0 <--
-OSS DMA_READ 0 <--
-OSS DMA_WRITE 0 <--
-
-XI_M GETX 0 <--
-XI_M GETS 0 <--
-XI_M PUTX 0 <--
-XI_M PUTO 0 <--
-XI_M PUTO_SHARERS 0 <--
-XI_M Memory_Data 0 <--
-XI_M Memory_Ack 0 <--
-XI_M DMA_READ 0 <--
-XI_M DMA_WRITE 0 <--
-
-XI_U GETX 0 <--
-XI_U GETS 0 <--
-XI_U PUTX 0 <--
-XI_U PUTO 0 <--
-XI_U PUTO_SHARERS 0 <--
-XI_U Exclusive_Unblock 0 <--
-XI_U Memory_Ack 0 <--
-XI_U DMA_READ 0 <--
-XI_U DMA_WRITE 0 <--
-
-OI_D GETX 0 <--
-OI_D GETS 0 <--
-OI_D PUTX 0 <--
-OI_D PUTO 0 <--
-OI_D PUTO_SHARERS 0 <--
-OI_D DMA_READ 0 <--
-OI_D DMA_WRITE 0 <--
-OI_D Data 0 <--
-
+I GETX [131 ] 131
+I GETS [983 ] 983
+I PUTX [0 ] 0
+I PUTO [0 ] 0
+I Memory_Data [0 ] 0
+I Memory_Ack [191 ] 191
+I DMA_READ [0 ] 0
+I DMA_WRITE [0 ] 0
+
+S GETX [0 ] 0
+S GETS [0 ] 0
+S PUTX [0 ] 0
+S PUTO [0 ] 0
+S Memory_Data [0 ] 0
+S Memory_Ack [0 ] 0
+S DMA_READ [0 ] 0
+S DMA_WRITE [0 ] 0
+
+O GETX [0 ] 0
+O GETS [0 ] 0
+O PUTX [0 ] 0
+O PUTO [0 ] 0
+O PUTO_SHARERS [0 ] 0
+O Memory_Data [0 ] 0
+O Memory_Ack [0 ] 0
+O DMA_READ [0 ] 0
+O DMA_WRITE [0 ] 0
+
+M GETX [0 ] 0
+M GETS [0 ] 0
+M PUTX [1098 ] 1098
+M PUTO [0 ] 0
+M PUTO_SHARERS [0 ] 0
+M Memory_Data [0 ] 0
+M Memory_Ack [0 ] 0
+M DMA_READ [0 ] 0
+M DMA_WRITE [0 ] 0
+
+IS GETX [0 ] 0
+IS GETS [0 ] 0
+IS PUTX [0 ] 0
+IS PUTO [0 ] 0
+IS PUTO_SHARERS [0 ] 0
+IS Unblock [0 ] 0
+IS Exclusive_Unblock [983 ] 983
+IS Memory_Data [983 ] 983
+IS Memory_Ack [2 ] 2
+IS DMA_READ [0 ] 0
+IS DMA_WRITE [0 ] 0
+
+SS GETX [0 ] 0
+SS GETS [0 ] 0
+SS PUTX [0 ] 0
+SS PUTO [0 ] 0
+SS PUTO_SHARERS [0 ] 0
+SS Unblock [0 ] 0
+SS Last_Unblock [0 ] 0
+SS Memory_Data [0 ] 0
+SS Memory_Ack [0 ] 0
+SS DMA_READ [0 ] 0
+SS DMA_WRITE [0 ] 0
+
+OO GETX [0 ] 0
+OO GETS [0 ] 0
+OO PUTX [0 ] 0
+OO PUTO [0 ] 0
+OO PUTO_SHARERS [0 ] 0
+OO Unblock [0 ] 0
+OO Last_Unblock [0 ] 0
+OO Memory_Data [0 ] 0
+OO Memory_Ack [0 ] 0
+OO DMA_READ [0 ] 0
+OO DMA_WRITE [0 ] 0
+
+MO GETX [0 ] 0
+MO GETS [0 ] 0
+MO PUTX [0 ] 0
+MO PUTO [0 ] 0
+MO PUTO_SHARERS [0 ] 0
+MO Unblock [0 ] 0
+MO Exclusive_Unblock [0 ] 0
+MO Memory_Data [0 ] 0
+MO Memory_Ack [0 ] 0
+MO DMA_READ [0 ] 0
+MO DMA_WRITE [0 ] 0
+
+MM GETX [0 ] 0
+MM GETS [0 ] 0
+MM PUTX [0 ] 0
+MM PUTO [0 ] 0
+MM PUTO_SHARERS [0 ] 0
+MM Exclusive_Unblock [131 ] 131
+MM Memory_Data [131 ] 131
+MM Memory_Ack [1 ] 1
+MM DMA_READ [0 ] 0
+MM DMA_WRITE [0 ] 0
+
+
+MI GETX [0 ] 0
+MI GETS [0 ] 0
+MI PUTX [0 ] 0
+MI PUTO [0 ] 0
+MI PUTO_SHARERS [0 ] 0
+MI Unblock [0 ] 0
+MI Clean_Writeback [904 ] 904
+MI Dirty_Writeback [194 ] 194
+MI Memory_Data [0 ] 0
+MI Memory_Ack [0 ] 0
+MI DMA_READ [0 ] 0
+MI DMA_WRITE [0 ] 0
+
+MIS GETX [0 ] 0
+MIS GETS [0 ] 0
+MIS PUTX [0 ] 0
+MIS PUTO [0 ] 0
+MIS PUTO_SHARERS [0 ] 0
+MIS Unblock [0 ] 0
+MIS Clean_Writeback [0 ] 0
+MIS Dirty_Writeback [0 ] 0
+MIS Memory_Data [0 ] 0
+MIS Memory_Ack [0 ] 0
+MIS DMA_READ [0 ] 0
+MIS DMA_WRITE [0 ] 0
+
+OS GETX [0 ] 0
+OS GETS [0 ] 0
+OS PUTX [0 ] 0
+OS PUTO [0 ] 0
+OS PUTO_SHARERS [0 ] 0
+OS Unblock [0 ] 0
+OS Clean_Writeback [0 ] 0
+OS Dirty_Writeback [0 ] 0
+OS Memory_Data [0 ] 0
+OS Memory_Ack [0 ] 0
+OS DMA_READ [0 ] 0
+OS DMA_WRITE [0 ] 0
+
+OSS GETX [0 ] 0
+OSS GETS [0 ] 0
+OSS PUTX [0 ] 0
+OSS PUTO [0 ] 0
+OSS PUTO_SHARERS [0 ] 0
+OSS Unblock [0 ] 0
+OSS Clean_Writeback [0 ] 0
+OSS Dirty_Writeback [0 ] 0
+OSS Memory_Data [0 ] 0
+OSS Memory_Ack [0 ] 0
+OSS DMA_READ [0 ] 0
+OSS DMA_WRITE [0 ] 0
+
+XI_M GETX [0 ] 0
+XI_M GETS [0 ] 0
+XI_M PUTX [0 ] 0
+XI_M PUTO [0 ] 0
+XI_M PUTO_SHARERS [0 ] 0
+XI_M Memory_Data [0 ] 0
+XI_M Memory_Ack [0 ] 0
+XI_M DMA_READ [0 ] 0
+XI_M DMA_WRITE [0 ] 0
+
+XI_U GETX [0 ] 0
+XI_U GETS [0 ] 0
+XI_U PUTX [0 ] 0
+XI_U PUTO [0 ] 0
+XI_U PUTO_SHARERS [0 ] 0
+XI_U Exclusive_Unblock [0 ] 0
+XI_U Memory_Ack [0 ] 0
+XI_U DMA_READ [0 ] 0
+XI_U DMA_WRITE [0 ] 0
+
+OI_D GETX [0 ] 0
+OI_D GETS [0 ] 0
+OI_D PUTX [0 ] 0
+OI_D PUTO [0 ] 0
+OI_D PUTO_SHARERS [0 ] 0
+OI_D DMA_READ [0 ] 0
+OI_D DMA_WRITE [0 ] 0
+OI_D Data \ No newline at end of file
diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/simout b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/simout
index a5c547a14..7e21d792f 100755
--- a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/simout
+++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/simout
@@ -5,10 +5,10 @@ The Regents of The University of Michigan
All Rights Reserved
-M5 compiled Jan 28 2010 14:49:51
-M5 revision 6068d4fc30d3+ 6931+ default qtip tip brad/rubycfg_regress_udpate
-M5 started Jan 28 2010 15:08:13
-M5 executing on svvint05
+M5 compiled Aug 5 2010 10:34:54
+M5 revision 1cd2a169499f+ 7535+ default brad/hammer_merge_gets qtip tip
+M5 started Aug 5 2010 10:35:39
+M5 executing on svvint09
command line: build/ALPHA_SE_MOESI_CMP_directory/m5.fast -d build/ALPHA_SE_MOESI_CMP_directory/tests/fast/quick/00.hello/alpha/linux/simple-timing-ruby-MOESI_CMP_directory -re tests/run.py build/ALPHA_SE_MOESI_CMP_directory/tests/fast/quick/00.hello/alpha/linux/simple-timing-ruby-MOESI_CMP_directory
Global frequency set at 1000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/stats.txt b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/stats.txt
index f1675ef82..add084384 100644
--- a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/stats.txt
+++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/stats.txt
@@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
-host_inst_rate 11859 # Simulator instruction rate (inst/s)
-host_mem_usage 216064 # Number of bytes of host memory used
-host_seconds 0.55 # Real time elapsed on the host
-host_tick_rate 407003 # Simulator tick rate (ticks/s)
+host_inst_rate 23717 # Simulator instruction rate (inst/s)
+host_mem_usage 212528 # Number of bytes of host memory used
+host_seconds 0.27 # Real time elapsed on the host
+host_tick_rate 829037 # Simulator tick rate (ticks/s)
sim_freq 1000000000 # Frequency of simulated ticks
sim_insts 6404 # Number of instructions simulated
sim_seconds 0.000224 # Number of seconds simulated
diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/config.ini b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/config.ini
index 1658b1622..d5555ef31 100644
--- a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/config.ini
+++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/config.ini
@@ -5,7 +5,7 @@ dummy=0
[system]
type=System
-children=cpu physmem ruby
+children=cpu dir_cntrl0 l1_cntrl0 l2_cntrl0 physmem ruby
mem_mode=timing
physmem=system.physmem
@@ -32,8 +32,8 @@ progress_interval=0
system=system
tracer=system.cpu.tracer
workload=system.cpu.workload
-dcache_port=system.ruby.network.topology.ext_links0.ext_node.sequencer.port[1]
-icache_port=system.ruby.network.topology.ext_links0.ext_node.sequencer.port[0]
+dcache_port=system.l1_cntrl0.sequencer.port[1]
+icache_port=system.l1_cntrl0.sequencer.port[0]
[system.cpu.dtb]
type=AlphaTLB
@@ -54,7 +54,7 @@ egid=100
env=
errout=cerr
euid=100
-executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/hello/bin/alpha/linux/hello
+executable=tests/test-progs/hello/bin/alpha/linux/hello
gid=100
input=cin
max_stack_size=67108864
@@ -65,6 +65,121 @@ simpoint=0
system=system
uid=100
+[system.dir_cntrl0]
+type=Directory_Controller
+children=directory memBuffer
+buffer_size=0
+directory=system.dir_cntrl0.directory
+directory_latency=5
+distributed_persistent=true
+fixed_timeout_latency=100
+l2_select_num_bits=0
+memBuffer=system.dir_cntrl0.memBuffer
+number_of_TBEs=256
+recycle_latency=10
+transitions_per_cycle=32
+version=0
+
+[system.dir_cntrl0.directory]
+type=RubyDirectoryMemory
+map_levels=4
+numa_high_bit=6
+size=134217728
+use_map=false
+version=0
+
+[system.dir_cntrl0.memBuffer]
+type=RubyMemoryControl
+bank_bit_0=8
+bank_busy_time=11
+bank_queue_size=12
+banks_per_rank=8
+basic_bus_busy_time=2
+dimm_bit_0=12
+dimms_per_channel=2
+mem_bus_cycle_multiplier=10
+mem_ctl_latency=12
+mem_fixed_delay=0
+mem_random_arbitrate=0
+rank_bit_0=11
+rank_rank_delay=1
+ranks_per_dimm=2
+read_write_delay=2
+refresh_period=1560
+tFaw=0
+version=0
+
+[system.l1_cntrl0]
+type=L1Cache_Controller
+children=sequencer
+L1DcacheMemory=system.l1_cntrl0.sequencer.dcache
+L1IcacheMemory=system.l1_cntrl0.sequencer.icache
+N_tokens=2
+buffer_size=0
+dynamic_timeout_enabled=true
+fixed_timeout_latency=300
+l1_request_latency=2
+l1_response_latency=2
+l2_select_num_bits=0
+no_mig_atomic=true
+number_of_TBEs=256
+recycle_latency=10
+retry_threshold=1
+sequencer=system.l1_cntrl0.sequencer
+transitions_per_cycle=32
+version=0
+
+[system.l1_cntrl0.sequencer]
+type=RubySequencer
+children=dcache icache
+dcache=system.l1_cntrl0.sequencer.dcache
+deadlock_threshold=500000
+icache=system.l1_cntrl0.sequencer.icache
+max_outstanding_requests=16
+physmem=system.physmem
+using_ruby_tester=false
+version=0
+physMemPort=system.physmem.port[0]
+port=system.cpu.icache_port system.cpu.dcache_port
+
+[system.l1_cntrl0.sequencer.dcache]
+type=RubyCache
+assoc=2
+latency=2
+replacement_policy=PSEUDO_LRU
+size=256
+start_index_bit=6
+
+[system.l1_cntrl0.sequencer.icache]
+type=RubyCache
+assoc=2
+latency=2
+replacement_policy=PSEUDO_LRU
+size=256
+start_index_bit=6
+
+[system.l2_cntrl0]
+type=L2Cache_Controller
+children=L2cacheMemory
+L2cacheMemory=system.l2_cntrl0.L2cacheMemory
+N_tokens=2
+buffer_size=0
+filtering_enabled=true
+l2_request_latency=5
+l2_response_latency=5
+number_of_TBEs=256
+recycle_latency=10
+transitions_per_cycle=32
+version=0
+
+[system.l2_cntrl0.L2cacheMemory]
+type=RubyCache
+assoc=2
+latency=10
+replacement_policy=PSEUDO_LRU
+size=512
+start_index_bit=0
+
[system.physmem]
type=PhysicalMemory
file=
@@ -73,7 +188,7 @@ latency_var=0
null=false
range=0:134217727
zero=false
-port=system.ruby.network.topology.ext_links0.ext_node.sequencer.physMemPort
+port=system.l1_cntrl0.sequencer.physMemPort
[system.ruby]
type=RubySystem
@@ -83,6 +198,7 @@ clock=1
debug=system.ruby.debug
mem_size=134217728
network=system.ruby.network
+no_mem_vec=false
profiler=system.ruby.profiler
random_seed=1234
randomization=false
@@ -100,7 +216,7 @@ verbosity_string=none
[system.ruby.network]
type=SimpleNetwork
children=topology
-adaptive_routing=true
+adaptive_routing=false
buffer_size=0
control_msg_size=8
endpoint_bandwidth=10000
@@ -113,144 +229,34 @@ type=Topology
children=ext_links0 ext_links1 ext_links2 int_links0 int_links1 int_links2
ext_links=system.ruby.network.topology.ext_links0 system.ruby.network.topology.ext_links1 system.ruby.network.topology.ext_links2
int_links=system.ruby.network.topology.int_links0 system.ruby.network.topology.int_links1 system.ruby.network.topology.int_links2
+name=Crossbar
num_int_nodes=4
print_config=false
[system.ruby.network.topology.ext_links0]
type=ExtLink
-children=ext_node
bw_multiplier=64
-ext_node=system.ruby.network.topology.ext_links0.ext_node
+ext_node=system.l1_cntrl0
int_node=0
latency=1
weight=1
-[system.ruby.network.topology.ext_links0.ext_node]
-type=L1Cache_Controller
-children=sequencer
-L1DcacheMemory=system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache
-L1IcacheMemory=system.ruby.network.topology.ext_links0.ext_node.sequencer.icache
-N_tokens=2
-buffer_size=0
-dynamic_timeout_enabled=true
-fixed_timeout_latency=300
-l1_request_latency=2
-l1_response_latency=2
-l2_select_num_bits=0
-number_of_TBEs=256
-recycle_latency=10
-retry_threshold=1
-sequencer=system.ruby.network.topology.ext_links0.ext_node.sequencer
-transitions_per_cycle=32
-version=0
-
-[system.ruby.network.topology.ext_links0.ext_node.sequencer]
-type=RubySequencer
-children=dcache icache
-dcache=system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache
-deadlock_threshold=500000
-icache=system.ruby.network.topology.ext_links0.ext_node.sequencer.icache
-max_outstanding_requests=16
-physmem=system.physmem
-using_ruby_tester=false
-version=0
-physMemPort=system.physmem.port[0]
-port=system.cpu.icache_port system.cpu.dcache_port
-
-[system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache]
-type=RubyCache
-assoc=2
-latency=3
-replacement_policy=PSEUDO_LRU
-size=256
-
-[system.ruby.network.topology.ext_links0.ext_node.sequencer.icache]
-type=RubyCache
-assoc=2
-latency=3
-replacement_policy=PSEUDO_LRU
-size=256
-
[system.ruby.network.topology.ext_links1]
type=ExtLink
-children=ext_node
bw_multiplier=64
-ext_node=system.ruby.network.topology.ext_links1.ext_node
+ext_node=system.l2_cntrl0
int_node=1
latency=1
weight=1
-[system.ruby.network.topology.ext_links1.ext_node]
-type=L2Cache_Controller
-children=L2cacheMemory
-L2cacheMemory=system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory
-N_tokens=2
-buffer_size=0
-filtering_enabled=true
-l2_request_latency=10
-l2_response_latency=10
-number_of_TBEs=256
-recycle_latency=10
-transitions_per_cycle=32
-version=0
-
-[system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory]
-type=RubyCache
-assoc=2
-latency=15
-replacement_policy=PSEUDO_LRU
-size=512
-
[system.ruby.network.topology.ext_links2]
type=ExtLink
-children=ext_node
bw_multiplier=64
-ext_node=system.ruby.network.topology.ext_links2.ext_node
+ext_node=system.dir_cntrl0
int_node=2
latency=1
weight=1
-[system.ruby.network.topology.ext_links2.ext_node]
-type=Directory_Controller
-children=directory memBuffer
-buffer_size=0
-directory=system.ruby.network.topology.ext_links2.ext_node.directory
-directory_latency=6
-distributed_persistent=true
-fixed_timeout_latency=300
-l2_select_num_bits=0
-memBuffer=system.ruby.network.topology.ext_links2.ext_node.memBuffer
-number_of_TBEs=256
-recycle_latency=10
-transitions_per_cycle=32
-version=0
-
-[system.ruby.network.topology.ext_links2.ext_node.directory]
-type=RubyDirectoryMemory
-size=134217728
-version=0
-
-[system.ruby.network.topology.ext_links2.ext_node.memBuffer]
-type=RubyMemoryControl
-bank_bit_0=8
-bank_busy_time=11
-bank_queue_size=12
-banks_per_rank=8
-basic_bus_busy_time=2
-dimm_bit_0=12
-dimms_per_channel=2
-mem_bus_cycle_multiplier=10
-mem_ctl_latency=12
-mem_fixed_delay=0
-mem_random_arbitrate=0
-rank_bit_0=11
-rank_rank_delay=1
-ranks_per_dimm=2
-read_write_delay=2
-refresh_period=1560
-tFaw=0
-version=0
-
[system.ruby.network.topology.int_links0]
type=IntLink
bw_multiplier=16
diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/ruby.stats b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/ruby.stats
index ae58be613..39236835d 100644
--- a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/ruby.stats
+++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/ruby.stats
@@ -13,12 +13,12 @@ RubySystem config:
Network Configuration
---------------------
network: SIMPLE_NETWORK
-topology:
+topology: Crossbar
virtual_net_0: active, ordered
virtual_net_1: active, unordered
-virtual_net_2: active, ordered
-virtual_net_3: active, unordered
+virtual_net_2: active, unordered
+virtual_net_3: active, ordered
virtual_net_4: active, unordered
virtual_net_5: active, ordered
virtual_net_6: inactive
@@ -34,7 +34,7 @@ periodic_stats_period: 1000000
================ End RubySystem Configuration Print ================
-Real time: Jan/28/2010 15:55:45
+Real time: Aug/05/2010 10:42:35
Profiler Stats
--------------
@@ -43,31 +43,20 @@ Elapsed_time_in_minutes: 0
Elapsed_time_in_hours: 0
Elapsed_time_in_days: 0
-Virtual_time_in_seconds: 0.43
-Virtual_time_in_minutes: 0.00716667
-Virtual_time_in_hours: 0.000119444
-Virtual_time_in_days: 4.97685e-06
+Virtual_time_in_seconds: 0.27
+Virtual_time_in_minutes: 0.0045
+Virtual_time_in_hours: 7.5e-05
+Virtual_time_in_days: 3.125e-06
-Ruby_current_time: 236654
+Ruby_current_time: 243131
Ruby_start_time: 0
-Ruby_cycles: 236654
+Ruby_cycles: 243131
-mbytes_resident: 34.4141
-mbytes_total: 34.4219
+mbytes_resident: 34.8711
+mbytes_total: 34.8789
resident_ratio: 1
-Total_misses: 0
-total_misses: 0 [ 0 ]
-user_misses: 0 [ 0 ]
-supervisor_misses: 0 [ 0 ]
-
-ruby_cycles_executed: 236655 [ 236655 ]
-
-transactions_started: 0 [ 0 ]
-transactions_ended: 0 [ 0 ]
-cycles_per_transaction: 0 [ 0 ]
-misses_per_transaction: 0 [ 0 ]
-
+ruby_cycles_executed: [ 243132 ]
Busy Controller Counts:
L1Cache-0:0
@@ -81,10 +70,32 @@ sequencer_requests_outstanding: [binsize: 1 max: 1 count: 8465 average: 1 |
All Non-Zero Cycle Demand Cache Accesses
----------------------------------------
-miss_latency: [binsize: 2 max: 279 count: 8464 average: 26.9601 | standard deviation: 58.5578 | 0 7082 0 0 0 0 0 0 0 0 0 0 0 220 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 268 180 200 165 117 12 3 8 3 4 46 30 32 33 37 0 1 1 1 2 1 4 1 3 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 4 1 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
-miss_latency_1: [binsize: 2 max: 279 count: 6414 average: 18.8457 | standard deviation: 49.2277 | 0 5768 0 0 0 0 0 0 0 0 0 0 0 55 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 125 84 121 94 59 8 2 4 1 3 20 12 18 22 8 0 1 0 0 0 0 2 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
-miss_latency_2: [binsize: 2 max: 279 count: 1185 average: 66.1527 | standard deviation: 80.7635 | 0 660 0 0 0 0 0 0 0 0 0 0 0 99 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 112 56 67 56 46 4 0 3 2 0 24 12 14 10 10 0 0 0 1 1 1 2 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
-miss_latency_3: [binsize: 2 max: 213 count: 865 average: 33.437 | standard deviation: 63.4371 | 0 654 0 0 0 0 0 0 0 0 0 0 0 66 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 40 12 15 12 0 1 1 0 1 2 6 0 1 19 0 0 1 0 1 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency: [binsize: 2 max: 286 count: 8464 average: 27.7253 | standard deviation: 60.155 | 0 7084 0 0 0 0 0 0 0 0 79 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 203 180 133 156 350 5 6 5 2 10 39 29 65 31 60 0 0 0 1 0 1 1 3 0 2 1 0 0 3 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 2 0 4 4 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency_IFETCH: [binsize: 2 max: 215 count: 6414 average: 18.3631 | standard deviation: 49.3028 | 0 5768 0 0 0 0 0 0 0 0 10 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 112 61 67 108 171 2 3 3 1 2 18 10 29 22 23 0 0 0 0 0 1 0 2 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency_LD: [binsize: 2 max: 286 count: 1185 average: 71.4084 | standard deviation: 82.7283 | 0 660 0 0 0 0 0 0 0 0 38 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 67 68 54 42 153 3 1 0 1 7 19 12 7 6 29 0 0 0 1 0 0 1 0 0 2 1 0 0 2 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 4 3 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency_ST: [binsize: 2 max: 276 count: 865 average: 37.3029 | standard deviation: 68.2954 | 0 656 0 0 0 0 0 0 0 0 31 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 24 51 12 6 26 0 2 2 0 1 2 7 29 3 8 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 2 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency_L1Cache: [binsize: 1 max: 2 count: 7084 average: 2 | standard deviation: 0 | 0 0 7084 ]
+miss_latency_L2Cache: [binsize: 1 max: 21 count: 79 average: 21 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 79 ]
+miss_latency_Directory: [binsize: 2 max: 286 count: 1301 average: 168.209 | standard deviation: 14.0495 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 203 180 133 156 350 5 6 5 2 10 39 29 65 31 60 0 0 0 1 0 1 1 3 0 2 1 0 0 3 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 2 0 4 4 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency_wCC_issue_to_initial_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+miss_latency_wCC_initial_forward_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+miss_latency_wCC_forward_to_first_response: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+miss_latency_wCC_first_response_to_completion: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+imcomplete_wCC_Times: 0
+miss_latency_dir_issue_to_initial_request: [binsize: 1 max: 0 count: 1 average: 0 | standard deviation: 0 | 1 ]
+miss_latency_dir_initial_forward_request: [binsize: 1 max: 0 count: 1 average: 0 | standard deviation: 0 | 1 ]
+miss_latency_dir_forward_to_first_response: [binsize: 1 max: 0 count: 1 average: 0 | standard deviation: 0 | 1 ]
+miss_latency_dir_first_response_to_completion: [binsize: 1 max: 169 count: 1 average: 169 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ]
+imcomplete_dir_Times: 1300
+miss_latency_IFETCH_L1Cache: [binsize: 1 max: 2 count: 5768 average: 2 | standard deviation: 0 | 0 0 5768 ]
+miss_latency_IFETCH_L2Cache: [binsize: 1 max: 21 count: 10 average: 21 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 10 ]
+miss_latency_IFETCH_Directory: [binsize: 2 max: 215 count: 636 average: 166.722 | standard deviation: 8.46373 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 112 61 67 108 171 2 3 3 1 2 18 10 29 22 23 0 0 0 0 0 1 0 2 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency_LD_L1Cache: [binsize: 1 max: 2 count: 660 average: 2 | standard deviation: 0 | 0 0 660 ]
+miss_latency_LD_L2Cache: [binsize: 1 max: 21 count: 38 average: 21 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 38 ]
+miss_latency_LD_Directory: [binsize: 2 max: 286 count: 487 average: 169.407 | standard deviation: 17.5782 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 67 68 54 42 153 3 1 0 1 7 19 12 7 6 29 0 0 0 1 0 0 1 0 0 2 1 0 0 2 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 4 3 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency_ST_L1Cache: [binsize: 1 max: 2 count: 656 average: 2 | standard deviation: 0 | 0 0 656 ]
+miss_latency_ST_L2Cache: [binsize: 1 max: 21 count: 31 average: 21 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 ]
+miss_latency_ST_Directory: [binsize: 2 max: 276 count: 178 average: 170.247 | standard deviation: 18.1183 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 24 51 12 6 26 0 2 2 0 1 2 7 29 3 8 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 2 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
All Non-Zero Cycle SW Prefetch Requests
------------------------------------
@@ -116,8 +127,8 @@ Resource Usage
page_size: 4096
user_time: 0
system_time: 0
-page_reclaims: 7348
-page_faults: 2239
+page_reclaims: 7568
+page_faults: 2181
swaps: 0
block_inputs: 0
block_outputs: 0
@@ -125,788 +136,900 @@ block_outputs: 0
Network Stats
-------------
+total_msg_count_Request_Control: 8046 64368
+total_msg_count_Response_Data: 3903 281016
+total_msg_count_ResponseL2hit_Data: 237 17064
+total_msg_count_Response_Control: 3 24
+total_msg_count_Writeback_Data: 4785 344520
+total_msg_count_Writeback_Control: 3222 25776
+total_msgs: 20196 total_bytes: 732768
+
switch_0_inlinks: 2
switch_0_outlinks: 2
-links_utilized_percent_switch_0: 0.164956
- links_utilized_percent_switch_0_link_0: 0.0658979 bw: 640000 base_latency: 1
- links_utilized_percent_switch_0_link_1: 0.264014 bw: 160000 base_latency: 1
+links_utilized_percent_switch_0: 0.171423
+ links_utilized_percent_switch_0_link_0: 0.0638596 bw: 640000 base_latency: 1
+ links_utilized_percent_switch_0_link_1: 0.278985 bw: 160000 base_latency: 1
- outgoing_messages_switch_0_link_0_Response_Data: 1162 83664 [ 0 1162 0 0 0 0 0 0 0 0 ] base_latency: 1
- outgoing_messages_switch_0_link_0_ResponseL2hit_Data: 220 15840 [ 0 220 0 0 0 0 0 0 0 0 ] base_latency: 1
- outgoing_messages_switch_0_link_0_Response_Control: 38 304 [ 0 38 0 0 0 0 0 0 0 0 ] base_latency: 1
- outgoing_messages_switch_0_link_1_Request_Control: 1382 11056 [ 0 0 0 0 1382 0 0 0 0 0 ] base_latency: 1
- outgoing_messages_switch_0_link_1_Writeback_Data: 1220 87840 [ 0 1220 0 0 0 0 0 0 0 0 ] base_latency: 1
- outgoing_messages_switch_0_link_1_Writeback_Control: 134 1072 [ 0 134 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_0_link_0_Response_Data: 1301 93672 [ 0 0 0 0 1301 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_0_link_0_ResponseL2hit_Data: 79 5688 [ 0 0 0 0 79 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_0_link_0_Response_Control: 1 8 [ 0 0 0 0 1 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_0_link_1_Request_Control: 1380 11040 [ 0 1380 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_0_link_1_Writeback_Data: 1354 97488 [ 0 0 0 0 1354 0 0 0 0 0 ] base_latency: 1
switch_1_inlinks: 2
switch_1_outlinks: 2
-links_utilized_percent_switch_1: 0.0968503
- links_utilized_percent_switch_1_link_0: 0.0660035 bw: 640000 base_latency: 1
- links_utilized_percent_switch_1_link_1: 0.127697 bw: 160000 base_latency: 1
-
- outgoing_messages_switch_1_link_0_Request_Control: 1382 11056 [ 0 0 0 0 1382 0 0 0 0 0 ] base_latency: 1
- outgoing_messages_switch_1_link_0_Writeback_Data: 1220 87840 [ 0 1220 0 0 0 0 0 0 0 0 ] base_latency: 1
- outgoing_messages_switch_1_link_0_Writeback_Control: 134 1072 [ 0 134 0 0 0 0 0 0 0 0 ] base_latency: 1
- outgoing_messages_switch_1_link_1_Request_Control: 1180 9440 [ 0 0 0 1180 0 0 0 0 0 0 ] base_latency: 1
- outgoing_messages_switch_1_link_1_ResponseL2hit_Data: 220 15840 [ 0 220 0 0 0 0 0 0 0 0 ] base_latency: 1
- outgoing_messages_switch_1_link_1_Response_Control: 38 304 [ 0 38 0 0 0 0 0 0 0 0 ] base_latency: 1
- outgoing_messages_switch_1_link_1_Writeback_Data: 207 14904 [ 0 207 0 0 0 0 0 0 0 0 ] base_latency: 1
- outgoing_messages_switch_1_link_1_Writeback_Control: 983 7864 [ 0 983 0 0 0 0 0 0 0 0 ] base_latency: 1
+links_utilized_percent_switch_1: 0.0889284
+ links_utilized_percent_switch_1_link_0: 0.0697464 bw: 640000 base_latency: 1
+ links_utilized_percent_switch_1_link_1: 0.10811 bw: 160000 base_latency: 1
+
+ outgoing_messages_switch_1_link_0_Request_Control: 1380 11040 [ 0 1380 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_1_link_0_Writeback_Data: 1354 97488 [ 0 0 0 0 1354 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_1_link_1_Request_Control: 1302 10416 [ 0 0 1302 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_1_link_1_ResponseL2hit_Data: 79 5688 [ 0 0 0 0 79 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_1_link_1_Response_Control: 1 8 [ 0 0 0 0 1 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_1_link_1_Writeback_Data: 241 17352 [ 0 0 0 0 241 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_1_link_1_Writeback_Control: 1074 8592 [ 0 0 0 0 1074 0 0 0 0 0 ] base_latency: 1
switch_2_inlinks: 2
switch_2_outlinks: 2
-links_utilized_percent_switch_2: 0.12111
- links_utilized_percent_switch_2_link_0: 0.0212652 bw: 640000 base_latency: 1
- links_utilized_percent_switch_2_link_1: 0.220955 bw: 160000 base_latency: 1
+links_utilized_percent_switch_2: 0.132082
+ links_utilized_percent_switch_2_link_0: 0.023367 bw: 640000 base_latency: 1
+ links_utilized_percent_switch_2_link_1: 0.240796 bw: 160000 base_latency: 1
- outgoing_messages_switch_2_link_0_Request_Control: 1180 9440 [ 0 0 0 1180 0 0 0 0 0 0 ] base_latency: 1
- outgoing_messages_switch_2_link_0_Writeback_Data: 207 14904 [ 0 207 0 0 0 0 0 0 0 0 ] base_latency: 1
- outgoing_messages_switch_2_link_0_Writeback_Control: 983 7864 [ 0 983 0 0 0 0 0 0 0 0 ] base_latency: 1
- outgoing_messages_switch_2_link_1_Response_Data: 1162 83664 [ 0 1162 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_2_link_0_Request_Control: 1302 10416 [ 0 0 1302 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_2_link_0_Writeback_Data: 241 17352 [ 0 0 0 0 241 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_2_link_0_Writeback_Control: 1074 8592 [ 0 0 0 0 1074 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_2_link_1_Response_Data: 1301 93672 [ 0 0 0 0 1301 0 0 0 0 0 ] base_latency: 1
switch_3_inlinks: 3
switch_3_outlinks: 3
-links_utilized_percent_switch_3: 0.204222
- links_utilized_percent_switch_3_link_0: 0.263592 bw: 160000 base_latency: 1
- links_utilized_percent_switch_3_link_1: 0.264014 bw: 160000 base_latency: 1
- links_utilized_percent_switch_3_link_2: 0.0850609 bw: 160000 base_latency: 1
-
- outgoing_messages_switch_3_link_0_Response_Data: 1162 83664 [ 0 1162 0 0 0 0 0 0 0 0 ] base_latency: 1
- outgoing_messages_switch_3_link_0_ResponseL2hit_Data: 220 15840 [ 0 220 0 0 0 0 0 0 0 0 ] base_latency: 1
- outgoing_messages_switch_3_link_0_Response_Control: 38 304 [ 0 38 0 0 0 0 0 0 0 0 ] base_latency: 1
- outgoing_messages_switch_3_link_1_Request_Control: 1382 11056 [ 0 0 0 0 1382 0 0 0 0 0 ] base_latency: 1
- outgoing_messages_switch_3_link_1_Writeback_Data: 1220 87840 [ 0 1220 0 0 0 0 0 0 0 0 ] base_latency: 1
- outgoing_messages_switch_3_link_1_Writeback_Control: 134 1072 [ 0 134 0 0 0 0 0 0 0 0 ] base_latency: 1
- outgoing_messages_switch_3_link_2_Request_Control: 1180 9440 [ 0 0 0 1180 0 0 0 0 0 0 ] base_latency: 1
- outgoing_messages_switch_3_link_2_Writeback_Data: 207 14904 [ 0 207 0 0 0 0 0 0 0 0 ] base_latency: 1
- outgoing_messages_switch_3_link_2_Writeback_Control: 983 7864 [ 0 983 0 0 0 0 0 0 0 0 ] base_latency: 1
-
-Cache Stats: system.ruby.network.topology.ext_links0.ext_node.sequencer.icache
- system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_misses: 0
- system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_demand_misses: 0
- system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_prefetches: 0
- system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_sw_prefetches: 0
- system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_hw_prefetches: 0
- system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_misses_per_transaction: nan
-
- system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
-
-Cache Stats: system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache
- system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_misses: 0
- system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_demand_misses: 0
- system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_prefetches: 0
- system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_sw_prefetches: 0
- system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_hw_prefetches: 0
- system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_misses_per_transaction: nan
-
- system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
-
- --- L1Cache 0 ---
+links_utilized_percent_switch_3: 0.209297
+ links_utilized_percent_switch_3_link_0: 0.255438 bw: 160000 base_latency: 1
+ links_utilized_percent_switch_3_link_1: 0.278985 bw: 160000 base_latency: 1
+ links_utilized_percent_switch_3_link_2: 0.0934681 bw: 160000 base_latency: 1
+
+ outgoing_messages_switch_3_link_0_Response_Data: 1301 93672 [ 0 0 0 0 1301 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_3_link_0_ResponseL2hit_Data: 79 5688 [ 0 0 0 0 79 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_3_link_0_Response_Control: 1 8 [ 0 0 0 0 1 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_3_link_1_Request_Control: 1380 11040 [ 0 1380 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_3_link_1_Writeback_Data: 1354 97488 [ 0 0 0 0 1354 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_3_link_2_Request_Control: 1302 10416 [ 0 0 1302 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_3_link_2_Writeback_Data: 241 17352 [ 0 0 0 0 241 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_3_link_2_Writeback_Control: 1074 8592 [ 0 0 0 0 1074 0 0 0 0 0 ] base_latency: 1
+
+Cache Stats: system.l1_cntrl0.sequencer.icache
+ system.l1_cntrl0.sequencer.icache_total_misses: 646
+ system.l1_cntrl0.sequencer.icache_total_demand_misses: 646
+ system.l1_cntrl0.sequencer.icache_total_prefetches: 0
+ system.l1_cntrl0.sequencer.icache_total_sw_prefetches: 0
+ system.l1_cntrl0.sequencer.icache_total_hw_prefetches: 0
+
+ system.l1_cntrl0.sequencer.icache_request_type_IFETCH: 100%
+
+ system.l1_cntrl0.sequencer.icache_access_mode_type_SupervisorMode: 646 100%
+
+Cache Stats: system.l1_cntrl0.sequencer.dcache
+ system.l1_cntrl0.sequencer.dcache_total_misses: 734
+ system.l1_cntrl0.sequencer.dcache_total_demand_misses: 734
+ system.l1_cntrl0.sequencer.dcache_total_prefetches: 0
+ system.l1_cntrl0.sequencer.dcache_total_sw_prefetches: 0
+ system.l1_cntrl0.sequencer.dcache_total_hw_prefetches: 0
+
+ system.l1_cntrl0.sequencer.dcache_request_type_LD: 71.5259%
+ system.l1_cntrl0.sequencer.dcache_request_type_ST: 28.4741%
+
+ system.l1_cntrl0.sequencer.dcache_access_mode_type_SupervisorMode: 734 100%
+
+ --- L1Cache ---
- Event Counts -
-Load 1185
-Ifetch 6414
-Store 865
-L1_Replacement 1375
-Data_Shared 154
-Data_Owner 0
-Data_All_Tokens 1228
-Ack 38
-Ack_All_Tokens 0
-Transient_GETX 0
-Transient_Local_GETX 0
-Transient_GETS 0
-Transient_Local_GETS 0
-Transient_GETS_Last_Token 0
-Transient_Local_GETS_Last_Token 0
-Persistent_GETX 0
-Persistent_GETS 0
-Own_Lock_or_Unlock 0
-Request_Timeout 0
-Use_TimeoutStarverX 0
-Use_TimeoutStarverS 0
-Use_TimeoutNoStarvers 1227
+Load [1185 ] 1185
+Ifetch [6414 ] 6414
+Store [865 ] 865
+Atomic [0 ] 0
+L1_Replacement [1384 ] 1384
+Data_Shared [48 ] 48
+Data_Owner [0 ] 0
+Data_All_Tokens [1332 ] 1332
+Ack [1 ] 1
+Ack_All_Tokens [0 ] 0
+Transient_GETX [0 ] 0
+Transient_Local_GETX [0 ] 0
+Transient_GETS [0 ] 0
+Transient_Local_GETS [0 ] 0
+Transient_GETS_Last_Token [0 ] 0
+Transient_Local_GETS_Last_Token [0 ] 0
+Persistent_GETX [0 ] 0
+Persistent_GETS [0 ] 0
+Persistent_GETS_Last_Token [0 ] 0
+Own_Lock_or_Unlock [0 ] 0
+Request_Timeout [0 ] 0
+Use_TimeoutStarverX [0 ] 0
+Use_TimeoutStarverS [0 ] 0
+Use_TimeoutNoStarvers [1331 ] 1331
+Use_TimeoutNoStarvers_NoMig [0 ] 0
- Transitions -
-NP Load 525
-NP Ifetch 646
-NP Store 191
-NP Data_Shared 0 <--
-NP Data_Owner 0 <--
-NP Data_All_Tokens 0 <--
-NP Ack 0 <--
-NP Transient_GETX 0 <--
-NP Transient_Local_GETX 0 <--
-NP Transient_GETS 0 <--
-NP Transient_Local_GETS 0 <--
-NP Persistent_GETX 0 <--
-NP Persistent_GETS 0 <--
-NP Own_Lock_or_Unlock 0 <--
-
-I Load 0 <--
-I Ifetch 0 <--
-I Store 0 <--
-I L1_Replacement 0 <--
-I Data_Shared 0 <--
-I Data_Owner 0 <--
-I Data_All_Tokens 0 <--
-I Ack 0 <--
-I Transient_GETX 0 <--
-I Transient_Local_GETX 0 <--
-I Transient_GETS 0 <--
-I Transient_Local_GETS 0 <--
-I Transient_GETS_Last_Token 0 <--
-I Transient_Local_GETS_Last_Token 0 <--
-I Persistent_GETX 0 <--
-I Persistent_GETS 0 <--
-I Own_Lock_or_Unlock 0 <--
-
-S Load 166
-S Ifetch 314
-S Store 20
-S L1_Replacement 134
-S Data_Shared 0 <--
-S Data_Owner 0 <--
-S Data_All_Tokens 0 <--
-S Ack 0 <--
-S Transient_GETX 0 <--
-S Transient_Local_GETX 0 <--
-S Transient_GETS 0 <--
-S Transient_Local_GETS 0 <--
-S Transient_GETS_Last_Token 0 <--
-S Transient_Local_GETS_Last_Token 0 <--
-S Persistent_GETX 0 <--
-S Persistent_GETS 0 <--
-S Own_Lock_or_Unlock 0 <--
-
-O Load 0 <--
-O Ifetch 0 <--
-O Store 0 <--
-O L1_Replacement 0 <--
-O Data_Shared 0 <--
-O Data_All_Tokens 0 <--
-O Ack 0 <--
-O Ack_All_Tokens 0 <--
-O Transient_GETX 0 <--
-O Transient_Local_GETX 0 <--
-O Transient_GETS 0 <--
-O Transient_Local_GETS 0 <--
-O Transient_GETS_Last_Token 0 <--
-O Transient_Local_GETS_Last_Token 0 <--
-O Persistent_GETX 0 <--
-O Persistent_GETS 0 <--
-O Own_Lock_or_Unlock 0 <--
-
-M Load 184
-M Ifetch 3447
-M Store 33
-M L1_Replacement 952
-M Transient_GETX 0 <--
-M Transient_Local_GETX 0 <--
-M Transient_GETS 0 <--
-M Transient_Local_GETS 0 <--
-M Persistent_GETX 0 <--
-M Persistent_GETS 0 <--
-M Own_Lock_or_Unlock 0 <--
-
-MM Load 221
-MM Ifetch 0 <--
-MM Store 333
-MM L1_Replacement 268
-MM Transient_GETX 0 <--
-MM Transient_Local_GETX 0 <--
-MM Transient_GETS 0 <--
-MM Transient_Local_GETS 0 <--
-MM Persistent_GETX 0 <--
-MM Persistent_GETS 0 <--
-MM Own_Lock_or_Unlock 0 <--
-
-M_W Load 69
-M_W Ifetch 2007
-M_W Store 25
-M_W L1_Replacement 14
-M_W Transient_GETX 0 <--
-M_W Transient_Local_GETX 0 <--
-M_W Transient_GETS 0 <--
-M_W Transient_Local_GETS 0 <--
-M_W Persistent_GETX 0 <--
-M_W Persistent_GETS 0 <--
-M_W Own_Lock_or_Unlock 0 <--
-M_W Use_TimeoutStarverX 0 <--
-M_W Use_TimeoutStarverS 0 <--
-M_W Use_TimeoutNoStarvers 991
-
-MM_W Load 20
-MM_W Ifetch 0 <--
-MM_W Store 263
-MM_W L1_Replacement 7
-MM_W Transient_GETX 0 <--
-MM_W Transient_Local_GETX 0 <--
-MM_W Transient_GETS 0 <--
-MM_W Transient_Local_GETS 0 <--
-MM_W Persistent_GETX 0 <--
-MM_W Persistent_GETS 0 <--
-MM_W Own_Lock_or_Unlock 0 <--
-MM_W Use_TimeoutStarverX 0 <--
-MM_W Use_TimeoutStarverS 0 <--
-MM_W Use_TimeoutNoStarvers 236
-
-IM Load 0 <--
-IM Ifetch 0 <--
-IM Store 0 <--
-IM L1_Replacement 0 <--
-IM Data_Shared 0 <--
-IM Data_Owner 0 <--
-IM Data_All_Tokens 191
-IM Ack 7
-IM Transient_GETX 0 <--
-IM Transient_Local_GETX 0 <--
-IM Transient_GETS 0 <--
-IM Transient_Local_GETS 0 <--
-IM Transient_GETS_Last_Token 0 <--
-IM Transient_Local_GETS_Last_Token 0 <--
-IM Persistent_GETX 0 <--
-IM Persistent_GETS 0 <--
-IM Own_Lock_or_Unlock 0 <--
-IM Request_Timeout 0 <--
-
-SM Load 0 <--
-SM Ifetch 0 <--
-SM Store 0 <--
-SM L1_Replacement 0 <--
-SM Data_Shared 0 <--
-SM Data_Owner 0 <--
-SM Data_All_Tokens 20
-SM Ack 0 <--
-SM Transient_GETX 0 <--
-SM Transient_Local_GETX 0 <--
-SM Transient_GETS 0 <--
-SM Transient_Local_GETS 0 <--
-SM Transient_GETS_Last_Token 0 <--
-SM Transient_Local_GETS_Last_Token 0 <--
-SM Persistent_GETX 0 <--
-SM Persistent_GETS 0 <--
-SM Own_Lock_or_Unlock 0 <--
-SM Request_Timeout 0 <--
-
-OM Load 0 <--
-OM Ifetch 0 <--
-OM Store 0 <--
-OM L1_Replacement 0 <--
-OM Data_Shared 0 <--
-OM Data_All_Tokens 0 <--
-OM Ack 0 <--
-OM Ack_All_Tokens 0 <--
-OM Transient_GETX 0 <--
-OM Transient_Local_GETX 0 <--
-OM Transient_GETS 0 <--
-OM Transient_Local_GETS 0 <--
-OM Transient_GETS_Last_Token 0 <--
-OM Transient_Local_GETS_Last_Token 0 <--
-OM Persistent_GETX 0 <--
-OM Persistent_GETS 0 <--
-OM Own_Lock_or_Unlock 0 <--
-OM Request_Timeout 0 <--
-
-IS Load 0 <--
-IS Ifetch 0 <--
-IS Store 0 <--
-IS L1_Replacement 0 <--
-IS Data_Shared 154
-IS Data_Owner 0 <--
-IS Data_All_Tokens 1017
-IS Ack 31
-IS Transient_GETX 0 <--
-IS Transient_Local_GETX 0 <--
-IS Transient_GETS 0 <--
-IS Transient_Local_GETS 0 <--
-IS Transient_GETS_Last_Token 0 <--
-IS Transient_Local_GETS_Last_Token 0 <--
-IS Persistent_GETX 0 <--
-IS Persistent_GETS 0 <--
-IS Own_Lock_or_Unlock 0 <--
-IS Request_Timeout 0 <--
-
-I_L Load 0 <--
-I_L Ifetch 0 <--
-I_L Store 0 <--
-I_L L1_Replacement 0 <--
-I_L Data_Shared 0 <--
-I_L Data_Owner 0 <--
-I_L Data_All_Tokens 0 <--
-I_L Ack 0 <--
-I_L Transient_GETX 0 <--
-I_L Transient_Local_GETX 0 <--
-I_L Transient_GETS 0 <--
-I_L Transient_Local_GETS 0 <--
-I_L Transient_GETS_Last_Token 0 <--
-I_L Transient_Local_GETS_Last_Token 0 <--
-I_L Persistent_GETX 0 <--
-I_L Persistent_GETS 0 <--
-I_L Own_Lock_or_Unlock 0 <--
-
-S_L Load 0 <--
-S_L Ifetch 0 <--
-S_L Store 0 <--
-S_L L1_Replacement 0 <--
-S_L Data_Shared 0 <--
-S_L Data_Owner 0 <--
-S_L Data_All_Tokens 0 <--
-S_L Ack 0 <--
-S_L Transient_GETX 0 <--
-S_L Transient_Local_GETX 0 <--
-S_L Transient_GETS 0 <--
-S_L Transient_Local_GETS 0 <--
-S_L Transient_GETS_Last_Token 0 <--
-S_L Transient_Local_GETS_Last_Token 0 <--
-S_L Persistent_GETX 0 <--
-S_L Persistent_GETS 0 <--
-S_L Own_Lock_or_Unlock 0 <--
-
-IM_L Load 0 <--
-IM_L Ifetch 0 <--
-IM_L Store 0 <--
-IM_L L1_Replacement 0 <--
-IM_L Data_Shared 0 <--
-IM_L Data_Owner 0 <--
-IM_L Data_All_Tokens 0 <--
-IM_L Ack 0 <--
-IM_L Transient_GETX 0 <--
-IM_L Transient_Local_GETX 0 <--
-IM_L Transient_GETS 0 <--
-IM_L Transient_Local_GETS 0 <--
-IM_L Transient_GETS_Last_Token 0 <--
-IM_L Transient_Local_GETS_Last_Token 0 <--
-IM_L Persistent_GETX 0 <--
-IM_L Persistent_GETS 0 <--
-IM_L Own_Lock_or_Unlock 0 <--
-IM_L Request_Timeout 0 <--
-
-SM_L Load 0 <--
-SM_L Ifetch 0 <--
-SM_L Store 0 <--
-SM_L L1_Replacement 0 <--
-SM_L Data_Shared 0 <--
-SM_L Data_Owner 0 <--
-SM_L Data_All_Tokens 0 <--
-SM_L Ack 0 <--
-SM_L Transient_GETX 0 <--
-SM_L Transient_Local_GETX 0 <--
-SM_L Transient_GETS 0 <--
-SM_L Transient_Local_GETS 0 <--
-SM_L Transient_GETS_Last_Token 0 <--
-SM_L Transient_Local_GETS_Last_Token 0 <--
-SM_L Persistent_GETX 0 <--
-SM_L Persistent_GETS 0 <--
-SM_L Own_Lock_or_Unlock 0 <--
-SM_L Request_Timeout 0 <--
-
-IS_L Load 0 <--
-IS_L Ifetch 0 <--
-IS_L Store 0 <--
-IS_L L1_Replacement 0 <--
-IS_L Data_Shared 0 <--
-IS_L Data_Owner 0 <--
-IS_L Data_All_Tokens 0 <--
-IS_L Ack 0 <--
-IS_L Transient_GETX 0 <--
-IS_L Transient_Local_GETX 0 <--
-IS_L Transient_GETS 0 <--
-IS_L Transient_Local_GETS 0 <--
-IS_L Transient_GETS_Last_Token 0 <--
-IS_L Transient_Local_GETS_Last_Token 0 <--
-IS_L Persistent_GETX 0 <--
-IS_L Persistent_GETS 0 <--
-IS_L Own_Lock_or_Unlock 0 <--
-IS_L Request_Timeout 0 <--
-
-Cache Stats: system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory
- system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_total_misses: 0
- system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_total_demand_misses: 0
- system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_total_prefetches: 0
- system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_total_sw_prefetches: 0
- system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_total_hw_prefetches: 0
- system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_misses_per_transaction: nan
-
- system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
-
- --- L2Cache 0 ---
+NP Load [525 ] 525
+NP Ifetch [646 ] 646
+NP Store [191 ] 191
+NP Atomic [0 ] 0
+NP Data_Shared [0 ] 0
+NP Data_Owner [0 ] 0
+NP Data_All_Tokens [0 ] 0
+NP Ack [0 ] 0
+NP Transient_GETX [0 ] 0
+NP Transient_Local_GETX [0 ] 0
+NP Transient_GETS [0 ] 0
+NP Transient_Local_GETS [0 ] 0
+NP Persistent_GETX [0 ] 0
+NP Persistent_GETS [0 ] 0
+NP Persistent_GETS_Last_Token [0 ] 0
+NP Own_Lock_or_Unlock [0 ] 0
+
+I Load [0 ] 0
+I Ifetch [0 ] 0
+I Store [0 ] 0
+I Atomic [0 ] 0
+I L1_Replacement [0 ] 0
+I Data_Shared [0 ] 0
+I Data_Owner [0 ] 0
+I Data_All_Tokens [0 ] 0
+I Ack [0 ] 0
+I Transient_GETX [0 ] 0
+I Transient_Local_GETX [0 ] 0
+I Transient_GETS [0 ] 0
+I Transient_Local_GETS [0 ] 0
+I Transient_GETS_Last_Token [0 ] 0
+I Transient_Local_GETS_Last_Token [0 ] 0
+I Persistent_GETX [0 ] 0
+I Persistent_GETS [0 ] 0
+I Persistent_GETS_Last_Token [0 ] 0
+I Own_Lock_or_Unlock [0 ] 0
+
+S Load [95 ] 95
+S Ifetch [64 ] 64
+S Store [18 ] 18
+S Atomic [0 ] 0
+S L1_Replacement [30 ] 30
+S Data_Shared [0 ] 0
+S Data_Owner [0 ] 0
+S Data_All_Tokens [0 ] 0
+S Ack [0 ] 0
+S Transient_GETX [0 ] 0
+S Transient_Local_GETX [0 ] 0
+S Transient_GETS [0 ] 0
+S Transient_Local_GETS [0 ] 0
+S Transient_GETS_Last_Token [0 ] 0
+S Transient_Local_GETS_Last_Token [0 ] 0
+S Persistent_GETX [0 ] 0
+S Persistent_GETS [0 ] 0
+S Persistent_GETS_Last_Token [0 ] 0
+S Own_Lock_or_Unlock [0 ] 0
+
+O Load [0 ] 0
+O Ifetch [0 ] 0
+O Store [0 ] 0
+O Atomic [0 ] 0
+O L1_Replacement [0 ] 0
+O Data_Shared [0 ] 0
+O Data_All_Tokens [0 ] 0
+O Ack [0 ] 0
+O Ack_All_Tokens [0 ] 0
+O Transient_GETX [0 ] 0
+O Transient_Local_GETX [0 ] 0
+O Transient_GETS [0 ] 0
+O Transient_Local_GETS [0 ] 0
+O Transient_GETS_Last_Token [0 ] 0
+O Transient_Local_GETS_Last_Token [0 ] 0
+O Persistent_GETX [0 ] 0
+O Persistent_GETS [0 ] 0
+O Persistent_GETS_Last_Token [0 ] 0
+O Own_Lock_or_Unlock [0 ] 0
+
+M Load [222 ] 222
+M Ifetch [3433 ] 3433
+M Store [35 ] 35
+M Atomic [0 ] 0
+M L1_Replacement [1056 ] 1056
+M Transient_GETX [0 ] 0
+M Transient_Local_GETX [0 ] 0
+M Transient_GETS [0 ] 0
+M Transient_Local_GETS [0 ] 0
+M Persistent_GETX [0 ] 0
+M Persistent_GETS [0 ] 0
+M Own_Lock_or_Unlock [0 ] 0
+
+MM Load [220 ] 220
+MM Ifetch [0 ] 0
+MM Store [331 ] 331
+MM Atomic [0 ] 0
+MM L1_Replacement [268 ] 268
+MM Transient_GETX [0 ] 0
+MM Transient_Local_GETX [0 ] 0
+MM Transient_GETS [0 ] 0
+MM Transient_Local_GETS [0 ] 0
+MM Persistent_GETX [0 ] 0
+MM Persistent_GETS [0 ] 0
+MM Own_Lock_or_Unlock [0 ] 0
+
+M_W Load [102 ] 102
+M_W Ifetch [2271 ] 2271
+M_W Store [25 ] 25
+M_W Atomic [0 ] 0
+M_W L1_Replacement [21 ] 21
+M_W Transient_GETX [0 ] 0
+M_W Transient_Local_GETX [0 ] 0
+M_W Transient_GETS [0 ] 0
+M_W Transient_Local_GETS [0 ] 0
+M_W Persistent_GETX [0 ] 0
+M_W Persistent_GETS [0 ] 0
+M_W Own_Lock_or_Unlock [0 ] 0
+M_W Use_TimeoutStarverX [0 ] 0
+M_W Use_TimeoutStarverS [0 ] 0
+M_W Use_TimeoutNoStarvers [1097 ] 1097
+M_W Use_TimeoutNoStarvers_NoMig [0 ] 0
+
+MM_W Load [21 ] 21
+MM_W Ifetch [0 ] 0
+MM_W Store [265 ] 265
+MM_W Atomic [0 ] 0
+MM_W L1_Replacement [9 ] 9
+MM_W Transient_GETX [0 ] 0
+MM_W Transient_Local_GETX [0 ] 0
+MM_W Transient_GETS [0 ] 0
+MM_W Transient_Local_GETS [0 ] 0
+MM_W Persistent_GETX [0 ] 0
+MM_W Persistent_GETS [0 ] 0
+MM_W Own_Lock_or_Unlock [0 ] 0
+MM_W Use_TimeoutStarverX [0 ] 0
+MM_W Use_TimeoutStarverS [0 ] 0
+MM_W Use_TimeoutNoStarvers [234 ] 234
+MM_W Use_TimeoutNoStarvers_NoMig [0 ] 0
+
+IM Load [0 ] 0
+IM Ifetch [0 ] 0
+IM Store [0 ] 0
+IM Atomic [0 ] 0
+IM L1_Replacement [0 ] 0
+IM Data_Shared [0 ] 0
+IM Data_Owner [0 ] 0
+IM Data_All_Tokens [191 ] 191
+IM Ack [1 ] 1
+IM Transient_GETX [0 ] 0
+IM Transient_Local_GETX [0 ] 0
+IM Transient_GETS [0 ] 0
+IM Transient_Local_GETS [0 ] 0
+IM Transient_GETS_Last_Token [0 ] 0
+IM Transient_Local_GETS_Last_Token [0 ] 0
+IM Persistent_GETX [0 ] 0
+IM Persistent_GETS [0 ] 0
+IM Persistent_GETS_Last_Token [0 ] 0
+IM Own_Lock_or_Unlock [0 ] 0
+IM Request_Timeout [0 ] 0
+
+SM Load [0 ] 0
+SM Ifetch [0 ] 0
+SM Store [0 ] 0
+SM Atomic [0 ] 0
+SM L1_Replacement [0 ] 0
+SM Data_Shared [0 ] 0
+SM Data_Owner [0 ] 0
+SM Data_All_Tokens [18 ] 18
+SM Ack [0 ] 0
+SM Transient_GETX [0 ] 0
+SM Transient_Local_GETX [0 ] 0
+SM Transient_GETS [0 ] 0
+SM Transient_Local_GETS [0 ] 0
+SM Transient_GETS_Last_Token [0 ] 0
+SM Transient_Local_GETS_Last_Token [0 ] 0
+SM Persistent_GETX [0 ] 0
+SM Persistent_GETS [0 ] 0
+SM Persistent_GETS_Last_Token [0 ] 0
+SM Own_Lock_or_Unlock [0 ] 0
+SM Request_Timeout [0 ] 0
+
+OM Load [0 ] 0
+OM Ifetch [0 ] 0
+OM Store [0 ] 0
+OM Atomic [0 ] 0
+OM L1_Replacement [0 ] 0
+OM Data_Shared [0 ] 0
+OM Data_All_Tokens [0 ] 0
+OM Ack [0 ] 0
+OM Ack_All_Tokens [0 ] 0
+OM Transient_GETX [0 ] 0
+OM Transient_Local_GETX [0 ] 0
+OM Transient_GETS [0 ] 0
+OM Transient_Local_GETS [0 ] 0
+OM Transient_GETS_Last_Token [0 ] 0
+OM Transient_Local_GETS_Last_Token [0 ] 0
+OM Persistent_GETX [0 ] 0
+OM Persistent_GETS [0 ] 0
+OM Persistent_GETS_Last_Token [0 ] 0
+OM Own_Lock_or_Unlock [0 ] 0
+OM Request_Timeout [0 ] 0
+
+IS Load [0 ] 0
+IS Ifetch [0 ] 0
+IS Store [0 ] 0
+IS Atomic [0 ] 0
+IS L1_Replacement [0 ] 0
+IS Data_Shared [48 ] 48
+IS Data_Owner [0 ] 0
+IS Data_All_Tokens [1123 ] 1123
+IS Ack [0 ] 0
+IS Transient_GETX [0 ] 0
+IS Transient_Local_GETX [0 ] 0
+IS Transient_GETS [0 ] 0
+IS Transient_Local_GETS [0 ] 0
+IS Transient_GETS_Last_Token [0 ] 0
+IS Transient_Local_GETS_Last_Token [0 ] 0
+IS Persistent_GETX [0 ] 0
+IS Persistent_GETS [0 ] 0
+IS Persistent_GETS_Last_Token [0 ] 0
+IS Own_Lock_or_Unlock [0 ] 0
+IS Request_Timeout [0 ] 0
+
+I_L Load [0 ] 0
+I_L Ifetch [0 ] 0
+I_L Store [0 ] 0
+I_L Atomic [0 ] 0
+I_L L1_Replacement [0 ] 0
+I_L Data_Shared [0 ] 0
+I_L Data_Owner [0 ] 0
+I_L Data_All_Tokens [0 ] 0
+I_L Ack [0 ] 0
+I_L Transient_GETX [0 ] 0
+I_L Transient_Local_GETX [0 ] 0
+I_L Transient_GETS [0 ] 0
+I_L Transient_Local_GETS [0 ] 0
+I_L Transient_GETS_Last_Token [0 ] 0
+I_L Transient_Local_GETS_Last_Token [0 ] 0
+I_L Persistent_GETX [0 ] 0
+I_L Persistent_GETS [0 ] 0
+I_L Persistent_GETS_Last_Token [0 ] 0
+I_L Own_Lock_or_Unlock [0 ] 0
+
+S_L Load [0 ] 0
+S_L Ifetch [0 ] 0
+S_L Store [0 ] 0
+S_L Atomic [0 ] 0
+S_L L1_Replacement [0 ] 0
+S_L Data_Shared [0 ] 0
+S_L Data_Owner [0 ] 0
+S_L Data_All_Tokens [0 ] 0
+S_L Ack [0 ] 0
+S_L Transient_GETX [0 ] 0
+S_L Transient_Local_GETX [0 ] 0
+S_L Transient_GETS [0 ] 0
+S_L Transient_Local_GETS [0 ] 0
+S_L Transient_GETS_Last_Token [0 ] 0
+S_L Transient_Local_GETS_Last_Token [0 ] 0
+S_L Persistent_GETX [0 ] 0
+S_L Persistent_GETS [0 ] 0
+S_L Persistent_GETS_Last_Token [0 ] 0
+S_L Own_Lock_or_Unlock [0 ] 0
+
+IM_L Load [0 ] 0
+IM_L Ifetch [0 ] 0
+IM_L Store [0 ] 0
+IM_L Atomic [0 ] 0
+IM_L L1_Replacement [0 ] 0
+IM_L Data_Shared [0 ] 0
+IM_L Data_Owner [0 ] 0
+IM_L Data_All_Tokens [0 ] 0
+IM_L Ack [0 ] 0
+IM_L Transient_GETX [0 ] 0
+IM_L Transient_Local_GETX [0 ] 0
+IM_L Transient_GETS [0 ] 0
+IM_L Transient_Local_GETS [0 ] 0
+IM_L Transient_GETS_Last_Token [0 ] 0
+IM_L Transient_Local_GETS_Last_Token [0 ] 0
+IM_L Persistent_GETX [0 ] 0
+IM_L Persistent_GETS [0 ] 0
+IM_L Own_Lock_or_Unlock [0 ] 0
+IM_L Request_Timeout [0 ] 0
+
+SM_L Load [0 ] 0
+SM_L Ifetch [0 ] 0
+SM_L Store [0 ] 0
+SM_L Atomic [0 ] 0
+SM_L L1_Replacement [0 ] 0
+SM_L Data_Shared [0 ] 0
+SM_L Data_Owner [0 ] 0
+SM_L Data_All_Tokens [0 ] 0
+SM_L Ack [0 ] 0
+SM_L Transient_GETX [0 ] 0
+SM_L Transient_Local_GETX [0 ] 0
+SM_L Transient_GETS [0 ] 0
+SM_L Transient_Local_GETS [0 ] 0
+SM_L Transient_GETS_Last_Token [0 ] 0
+SM_L Transient_Local_GETS_Last_Token [0 ] 0
+SM_L Persistent_GETX [0 ] 0
+SM_L Persistent_GETS [0 ] 0
+SM_L Persistent_GETS_Last_Token [0 ] 0
+SM_L Own_Lock_or_Unlock [0 ] 0
+SM_L Request_Timeout [0 ] 0
+
+IS_L Load [0 ] 0
+IS_L Ifetch [0 ] 0
+IS_L Store [0 ] 0
+IS_L Atomic [0 ] 0
+IS_L L1_Replacement [0 ] 0
+IS_L Data_Shared [0 ] 0
+IS_L Data_Owner [0 ] 0
+IS_L Data_All_Tokens [0 ] 0
+IS_L Ack [0 ] 0
+IS_L Transient_GETX [0 ] 0
+IS_L Transient_Local_GETX [0 ] 0
+IS_L Transient_GETS [0 ] 0
+IS_L Transient_Local_GETS [0 ] 0
+IS_L Transient_GETS_Last_Token [0 ] 0
+IS_L Transient_Local_GETS_Last_Token [0 ] 0
+IS_L Persistent_GETX [0 ] 0
+IS_L Persistent_GETS [0 ] 0
+IS_L Own_Lock_or_Unlock [0 ] 0
+IS_L Request_Timeout [0 ] 0
+
+Cache Stats: system.l2_cntrl0.L2cacheMemory
+ system.l2_cntrl0.L2cacheMemory_total_misses: 1302
+ system.l2_cntrl0.L2cacheMemory_total_demand_misses: 1302
+ system.l2_cntrl0.L2cacheMemory_total_prefetches: 0
+ system.l2_cntrl0.L2cacheMemory_total_sw_prefetches: 0
+ system.l2_cntrl0.L2cacheMemory_total_hw_prefetches: 0
+
+ system.l2_cntrl0.L2cacheMemory_request_type_GETS: 86.2519%
+ system.l2_cntrl0.L2cacheMemory_request_type_GETX: 13.7481%
+
+ system.l2_cntrl0.L2cacheMemory_access_mode_type_SupervisorMode: 1302 100%
+
+ --- L2Cache ---
- Event Counts -
-L1_GETS 1140
-L1_GETS_Last_Token 31
-L1_GETX 211
-L1_INV 0
-Transient_GETX 0
-Transient_GETS 0
-Transient_GETS_Last_Token 0
-L2_Replacement 1276
-Writeback_Tokens 82
-Writeback_Shared_Data 0
-Writeback_All_Tokens 1272
-Writeback_Owned 0
-Data_Shared 0
-Data_Owner 0
-Data_All_Tokens 0
-Ack 0
-Ack_All_Tokens 0
-Persistent_GETX 0
-Persistent_GETS 0
-Own_Lock_or_Unlock 0
+L1_GETS [1168 ] 1168
+L1_GETS_Last_Token [3 ] 3
+L1_GETX [209 ] 209
+L1_INV [0 ] 0
+Transient_GETX [0 ] 0
+Transient_GETS [0 ] 0
+Transient_GETS_Last_Token [0 ] 0
+L2_Replacement [1349 ] 1349
+Writeback_Tokens [0 ] 0
+Writeback_Shared_Data [28 ] 28
+Writeback_All_Tokens [1326 ] 1326
+Writeback_Owned [0 ] 0
+Data_Shared [0 ] 0
+Data_Owner [0 ] 0
+Data_All_Tokens [0 ] 0
+Ack [0 ] 0
+Ack_All_Tokens [0 ] 0
+Persistent_GETX [0 ] 0
+Persistent_GETS [0 ] 0
+Persistent_GETS_Last_Token [0 ] 0
+Own_Lock_or_Unlock [0 ] 0
- Transitions -
-NP L1_GETS 986
-NP L1_GETX 138
-NP L1_INV 0 <--
-NP Transient_GETX 0 <--
-NP Transient_GETS 0 <--
-NP Writeback_Tokens 82
-NP Writeback_Shared_Data 0 <--
-NP Writeback_All_Tokens 1202
-NP Writeback_Owned 0 <--
-NP Data_Shared 0 <--
-NP Data_Owner 0 <--
-NP Data_All_Tokens 0 <--
-NP Ack 0 <--
-NP Persistent_GETX 0 <--
-NP Persistent_GETS 0 <--
-NP Own_Lock_or_Unlock 0 <--
-
-I L1_GETS 0 <--
-I L1_GETS_Last_Token 31
-I L1_GETX 7
-I L1_INV 0 <--
-I Transient_GETX 0 <--
-I Transient_GETS 0 <--
-I Transient_GETS_Last_Token 0 <--
-I L2_Replacement 130
-I Writeback_Tokens 0 <--
-I Writeback_Shared_Data 0 <--
-I Writeback_All_Tokens 18
-I Writeback_Owned 0 <--
-I Data_Shared 0 <--
-I Data_Owner 0 <--
-I Data_All_Tokens 0 <--
-I Ack 0 <--
-I Persistent_GETX 0 <--
-I Persistent_GETS 0 <--
-I Own_Lock_or_Unlock 0 <--
-
-S L1_GETS 0 <--
-S L1_GETS_Last_Token 0 <--
-S L1_GETX 0 <--
-S L1_INV 0 <--
-S Transient_GETX 0 <--
-S Transient_GETS 0 <--
-S Transient_GETS_Last_Token 0 <--
-S L2_Replacement 0 <--
-S Writeback_Tokens 0 <--
-S Writeback_Shared_Data 0 <--
-S Writeback_All_Tokens 0 <--
-S Writeback_Owned 0 <--
-S Data_Shared 0 <--
-S Data_Owner 0 <--
-S Data_All_Tokens 0 <--
-S Ack 0 <--
-S Persistent_GETX 0 <--
-S Persistent_GETS 0 <--
-S Own_Lock_or_Unlock 0 <--
-
-O L1_GETS 0 <--
-O L1_GETS_Last_Token 0 <--
-O L1_GETX 18
-O L1_INV 0 <--
-O Transient_GETX 0 <--
-O Transient_GETS 0 <--
-O Transient_GETS_Last_Token 0 <--
-O L2_Replacement 84
-O Writeback_Tokens 0 <--
-O Writeback_Shared_Data 0 <--
-O Writeback_All_Tokens 52
-O Data_Shared 0 <--
-O Data_All_Tokens 0 <--
-O Ack 0 <--
-O Ack_All_Tokens 0 <--
-O Persistent_GETX 0 <--
-O Persistent_GETS 0 <--
-O Own_Lock_or_Unlock 0 <--
-
-M L1_GETS 154
-M L1_GETX 48
-M L1_INV 0 <--
-M Transient_GETX 0 <--
-M Transient_GETS 0 <--
-M L2_Replacement 1062
-M Persistent_GETX 0 <--
-M Persistent_GETS 0 <--
-M Own_Lock_or_Unlock 0 <--
-
-I_L L1_GETS 0 <--
-I_L L1_GETX 0 <--
-I_L L1_INV 0 <--
-I_L Transient_GETX 0 <--
-I_L Transient_GETS 0 <--
-I_L Transient_GETS_Last_Token 0 <--
-I_L L2_Replacement 0 <--
-I_L Writeback_Tokens 0 <--
-I_L Writeback_Shared_Data 0 <--
-I_L Writeback_All_Tokens 0 <--
-I_L Writeback_Owned 0 <--
-I_L Data_Shared 0 <--
-I_L Data_Owner 0 <--
-I_L Data_All_Tokens 0 <--
-I_L Ack 0 <--
-I_L Persistent_GETX 0 <--
-I_L Persistent_GETS 0 <--
-I_L Own_Lock_or_Unlock 0 <--
-
-S_L L1_GETS 0 <--
-S_L L1_GETS_Last_Token 0 <--
-S_L L1_GETX 0 <--
-S_L L1_INV 0 <--
-S_L Transient_GETX 0 <--
-S_L Transient_GETS 0 <--
-S_L Transient_GETS_Last_Token 0 <--
-S_L L2_Replacement 0 <--
-S_L Writeback_Tokens 0 <--
-S_L Writeback_Shared_Data 0 <--
-S_L Writeback_All_Tokens 0 <--
-S_L Writeback_Owned 0 <--
-S_L Data_Shared 0 <--
-S_L Data_Owner 0 <--
-S_L Data_All_Tokens 0 <--
-S_L Ack 0 <--
-S_L Persistent_GETX 0 <--
-S_L Persistent_GETS 0 <--
-S_L Own_Lock_or_Unlock 0 <--
-
-Memory controller: system.ruby.network.topology.ext_links2.ext_node.memBuffer:
- memory_total_requests: 1369
- memory_reads: 1162
- memory_writes: 207
- memory_refreshes: 493
- memory_total_request_delays: 529
- memory_delays_per_request: 0.386413
- memory_delays_in_input_queue: 185
+NP L1_GETS [1123 ] 1123
+NP L1_GETX [177 ] 177
+NP L1_INV [0 ] 0
+NP Transient_GETX [0 ] 0
+NP Transient_GETS [0 ] 0
+NP Writeback_Tokens [0 ] 0
+NP Writeback_Shared_Data [28 ] 28
+NP Writeback_All_Tokens [1323 ] 1323
+NP Writeback_Owned [0 ] 0
+NP Data_Shared [0 ] 0
+NP Data_Owner [0 ] 0
+NP Data_All_Tokens [0 ] 0
+NP Ack [0 ] 0
+NP Persistent_GETX [0 ] 0
+NP Persistent_GETS [0 ] 0
+NP Persistent_GETS_Last_Token [0 ] 0
+NP Own_Lock_or_Unlock [0 ] 0
+
+I L1_GETS [0 ] 0
+I L1_GETS_Last_Token [0 ] 0
+I L1_GETX [0 ] 0
+I L1_INV [0 ] 0
+I Transient_GETX [0 ] 0
+I Transient_GETS [0 ] 0
+I Transient_GETS_Last_Token [0 ] 0
+I L2_Replacement [34 ] 34
+I Writeback_Tokens [0 ] 0
+I Writeback_Shared_Data [0 ] 0
+I Writeback_All_Tokens [1 ] 1
+I Writeback_Owned [0 ] 0
+I Data_Shared [0 ] 0
+I Data_Owner [0 ] 0
+I Data_All_Tokens [0 ] 0
+I Ack [0 ] 0
+I Persistent_GETX [0 ] 0
+I Persistent_GETS [0 ] 0
+I Persistent_GETS_Last_Token [0 ] 0
+I Own_Lock_or_Unlock [0 ] 0
+
+S L1_GETS [0 ] 0
+S L1_GETS_Last_Token [3 ] 3
+S L1_GETX [1 ] 1
+S L1_INV [0 ] 0
+S Transient_GETX [0 ] 0
+S Transient_GETS [0 ] 0
+S Transient_GETS_Last_Token [0 ] 0
+S L2_Replacement [24 ] 24
+S Writeback_Tokens [0 ] 0
+S Writeback_Shared_Data [0 ] 0
+S Writeback_All_Tokens [0 ] 0
+S Writeback_Owned [0 ] 0
+S Data_Shared [0 ] 0
+S Data_Owner [0 ] 0
+S Data_All_Tokens [0 ] 0
+S Ack [0 ] 0
+S Persistent_GETX [0 ] 0
+S Persistent_GETS [0 ] 0
+S Persistent_GETS_Last_Token [0 ] 0
+S Own_Lock_or_Unlock [0 ] 0
+
+O L1_GETS [0 ] 0
+O L1_GETS_Last_Token [0 ] 0
+O L1_GETX [1 ] 1
+O L1_INV [0 ] 0
+O Transient_GETX [0 ] 0
+O Transient_GETS [0 ] 0
+O Transient_GETS_Last_Token [0 ] 0
+O L2_Replacement [42 ] 42
+O Writeback_Tokens [0 ] 0
+O Writeback_Shared_Data [0 ] 0
+O Writeback_All_Tokens [2 ] 2
+O Data_Shared [0 ] 0
+O Data_All_Tokens [0 ] 0
+O Ack [0 ] 0
+O Ack_All_Tokens [0 ] 0
+O Persistent_GETX [0 ] 0
+O Persistent_GETS [0 ] 0
+O Persistent_GETS_Last_Token [0 ] 0
+O Own_Lock_or_Unlock [0 ] 0
+
+M L1_GETS [45 ] 45
+M L1_GETX [30 ] 30
+M L1_INV [0 ] 0
+M Transient_GETX [0 ] 0
+M Transient_GETS [0 ] 0
+M L2_Replacement [1249 ] 1249
+M Persistent_GETX [0 ] 0
+M Persistent_GETS [0 ] 0
+M Own_Lock_or_Unlock [0 ] 0
+
+I_L L1_GETS [0 ] 0
+I_L L1_GETX [0 ] 0
+I_L L1_INV [0 ] 0
+I_L Transient_GETX [0 ] 0
+I_L Transient_GETS [0 ] 0
+I_L Transient_GETS_Last_Token [0 ] 0
+I_L L2_Replacement [0 ] 0
+I_L Writeback_Tokens [0 ] 0
+I_L Writeback_Shared_Data [0 ] 0
+I_L Writeback_All_Tokens [0 ] 0
+I_L Writeback_Owned [0 ] 0
+I_L Data_Shared [0 ] 0
+I_L Data_Owner [0 ] 0
+I_L Data_All_Tokens [0 ] 0
+I_L Ack [0 ] 0
+I_L Persistent_GETX [0 ] 0
+I_L Persistent_GETS [0 ] 0
+I_L Own_Lock_or_Unlock [0 ] 0
+
+S_L L1_GETS [0 ] 0
+S_L L1_GETS_Last_Token [0 ] 0
+S_L L1_GETX [0 ] 0
+S_L L1_INV [0 ] 0
+S_L Transient_GETX [0 ] 0
+S_L Transient_GETS [0 ] 0
+S_L Transient_GETS_Last_Token [0 ] 0
+S_L L2_Replacement [0 ] 0
+S_L Writeback_Tokens [0 ] 0
+S_L Writeback_Shared_Data [0 ] 0
+S_L Writeback_All_Tokens [0 ] 0
+S_L Writeback_Owned [0 ] 0
+S_L Data_Shared [0 ] 0
+S_L Data_Owner [0 ] 0
+S_L Data_All_Tokens [0 ] 0
+S_L Ack [0 ] 0
+S_L Persistent_GETX [0 ] 0
+S_L Persistent_GETS [0 ] 0
+S_L Persistent_GETS_Last_Token [0 ] 0
+S_L Own_Lock_or_Unlock [0 ] 0
+
+Memory controller: system.dir_cntrl0.memBuffer:
+ memory_total_requests: 1542
+ memory_reads: 1301
+ memory_writes: 241
+ memory_refreshes: 507
+ memory_total_request_delays: 714
+ memory_delays_per_request: 0.463035
+ memory_delays_in_input_queue: 240
memory_delays_behind_head_of_bank_queue: 0
- memory_delays_stalled_at_head_of_bank_queue: 344
- memory_stalls_for_bank_busy: 101
+ memory_delays_stalled_at_head_of_bank_queue: 474
+ memory_stalls_for_bank_busy: 148
memory_stalls_for_random_busy: 0
memory_stalls_for_anti_starvation: 0
- memory_stalls_for_arbitration: 19
- memory_stalls_for_bus: 222
+ memory_stalls_for_arbitration: 30
+ memory_stalls_for_bus: 278
memory_stalls_for_tfaw: 0
- memory_stalls_for_read_write_turnaround: 2
+ memory_stalls_for_read_write_turnaround: 18
memory_stalls_for_read_read_turnaround: 0
- accesses_per_bank: 75 17 45 46 54 108 37 16 19 22 32 34 52 49 39 31 39 21 21 21 28 38 61 27 30 22 32 72 90 124 14 53
+ accesses_per_bank: 80 17 45 54 54 148 45 17 20 22 33 34 54 53 44 33 40 22 21 28 28 42 73 34 32 25 34 75 101 159 19 56
- --- Directory 0 ---
+ --- Directory ---
- Event Counts -
-GETX 163
-GETS 1017
-Lockdown 0
-Unlockdown 0
-Own_Lock_or_Unlock 0
-Data_Owner 19
-Data_All_Tokens 188
-Ack_Owner 65
-Ack_Owner_All_Tokens 874
-Tokens 0
-Ack_All_Tokens 44
-Request_Timeout 0
-Memory_Data 1162
-Memory_Ack 207
-DMA_READ 0
-DMA_WRITE 0
-DMA_WRITE_All_Tokens 0
+GETX [179 ] 179
+GETS [1123 ] 1123
+Lockdown [0 ] 0
+Unlockdown [0 ] 0
+Own_Lock_or_Unlock [0 ] 0
+Own_Lock_or_Unlock_Tokens [0 ] 0
+Data_Owner [21 ] 21
+Data_All_Tokens [220 ] 220
+Ack_Owner [21 ] 21
+Ack_Owner_All_Tokens [1029 ] 1029
+Tokens [0 ] 0
+Ack_All_Tokens [24 ] 24
+Request_Timeout [0 ] 0
+Memory_Data [1301 ] 1301
+Memory_Ack [241 ] 241
+DMA_READ [0 ] 0
+DMA_WRITE [0 ] 0
+DMA_WRITE_All_Tokens [0 ] 0
- Transitions -
-O GETX 145
-O GETS 1017
-O Lockdown 0 <--
-O Own_Lock_or_Unlock 0 <--
-O Data_Owner 0 <--
-O Data_All_Tokens 0 <--
-O Tokens 0 <--
-O Ack_All_Tokens 44
-O DMA_READ 0 <--
-O DMA_WRITE 0 <--
-O DMA_WRITE_All_Tokens 0 <--
-
-NO GETX 18
-NO GETS 0 <--
-NO Lockdown 0 <--
-NO Own_Lock_or_Unlock 0 <--
-NO Data_Owner 19
-NO Data_All_Tokens 188
-NO Ack_Owner 65
-NO Ack_Owner_All_Tokens 874
-NO Tokens 0 <--
-NO DMA_READ 0 <--
-NO DMA_WRITE 0 <--
-
-L GETX 0 <--
-L GETS 0 <--
-L Lockdown 0 <--
-L Unlockdown 0 <--
-L Own_Lock_or_Unlock 0 <--
-L Data_Owner 0 <--
-L Data_All_Tokens 0 <--
-L Ack_Owner 0 <--
-L Ack_Owner_All_Tokens 0 <--
-L Tokens 0 <--
-L DMA_READ 0 <--
-L DMA_WRITE 0 <--
-
-O_W GETX 0 <--
-O_W GETS 0 <--
-O_W Lockdown 0 <--
-O_W Unlockdown 0 <--
-O_W Own_Lock_or_Unlock 0 <--
-O_W Data_Owner 0 <--
-O_W Ack_Owner 0 <--
-O_W Tokens 0 <--
-O_W Ack_All_Tokens 0 <--
-O_W Memory_Data 0 <--
-O_W Memory_Ack 207
-O_W DMA_READ 0 <--
-O_W DMA_WRITE 0 <--
-
-L_O_W GETX 0 <--
-L_O_W GETS 0 <--
-L_O_W Lockdown 0 <--
-L_O_W Unlockdown 0 <--
-L_O_W Own_Lock_or_Unlock 0 <--
-L_O_W Data_Owner 0 <--
-L_O_W Ack_Owner 0 <--
-L_O_W Tokens 0 <--
-L_O_W Ack_All_Tokens 0 <--
-L_O_W Memory_Data 0 <--
-L_O_W Memory_Ack 0 <--
-L_O_W DMA_READ 0 <--
-L_O_W DMA_WRITE 0 <--
-
-L_NO_W GETX 0 <--
-L_NO_W GETS 0 <--
-L_NO_W Lockdown 0 <--
-L_NO_W Unlockdown 0 <--
-L_NO_W Own_Lock_or_Unlock 0 <--
-L_NO_W Data_Owner 0 <--
-L_NO_W Ack_Owner 0 <--
-L_NO_W Tokens 0 <--
-L_NO_W Ack_All_Tokens 0 <--
-L_NO_W Memory_Data 0 <--
-L_NO_W DMA_READ 0 <--
-L_NO_W DMA_WRITE 0 <--
-
-DR_L_W GETX 0 <--
-DR_L_W GETS 0 <--
-DR_L_W Lockdown 0 <--
-DR_L_W Unlockdown 0 <--
-DR_L_W Own_Lock_or_Unlock 0 <--
-DR_L_W Data_Owner 0 <--
-DR_L_W Ack_Owner 0 <--
-DR_L_W Tokens 0 <--
-DR_L_W Ack_All_Tokens 0 <--
-DR_L_W Request_Timeout 0 <--
-DR_L_W Memory_Data 0 <--
-DR_L_W DMA_READ 0 <--
-DR_L_W DMA_WRITE 0 <--
-
-NO_W GETX 0 <--
-NO_W GETS 0 <--
-NO_W Lockdown 0 <--
-NO_W Unlockdown 0 <--
-NO_W Own_Lock_or_Unlock 0 <--
-NO_W Data_Owner 0 <--
-NO_W Ack_Owner 0 <--
-NO_W Tokens 0 <--
-NO_W Ack_All_Tokens 0 <--
-NO_W Memory_Data 1162
-NO_W DMA_READ 0 <--
-NO_W DMA_WRITE 0 <--
-
-O_DW_W GETX 0 <--
-O_DW_W GETS 0 <--
-O_DW_W Data_Owner 0 <--
-O_DW_W Ack_Owner 0 <--
-O_DW_W Tokens 0 <--
-O_DW_W Ack_All_Tokens 0 <--
-O_DW_W Memory_Ack 0 <--
-O_DW_W DMA_READ 0 <--
-O_DW_W DMA_WRITE 0 <--
-
-O_DR_W GETX 0 <--
-O_DR_W GETS 0 <--
-O_DR_W Lockdown 0 <--
-O_DR_W Unlockdown 0 <--
-O_DR_W Own_Lock_or_Unlock 0 <--
-O_DR_W Data_Owner 0 <--
-O_DR_W Ack_Owner 0 <--
-O_DR_W Tokens 0 <--
-O_DR_W Ack_All_Tokens 0 <--
-O_DR_W Memory_Data 0 <--
-O_DR_W DMA_READ 0 <--
-O_DR_W DMA_WRITE 0 <--
-
-O_DW GETX 0 <--
-O_DW GETS 0 <--
-O_DW Lockdown 0 <--
-O_DW Own_Lock_or_Unlock 0 <--
-O_DW Data_Owner 0 <--
-O_DW Data_All_Tokens 0 <--
-O_DW Ack_Owner 0 <--
-O_DW Ack_Owner_All_Tokens 0 <--
-O_DW Tokens 0 <--
-O_DW Ack_All_Tokens 0 <--
-O_DW DMA_READ 0 <--
-O_DW DMA_WRITE 0 <--
-
-NO_DW GETX 0 <--
-NO_DW GETS 0 <--
-NO_DW Lockdown 0 <--
-NO_DW Own_Lock_or_Unlock 0 <--
-NO_DW Data_Owner 0 <--
-NO_DW Data_All_Tokens 0 <--
-NO_DW Tokens 0 <--
-NO_DW Request_Timeout 0 <--
-NO_DW DMA_READ 0 <--
-NO_DW DMA_WRITE 0 <--
-
-NO_DR GETX 0 <--
-NO_DR GETS 0 <--
-NO_DR Lockdown 0 <--
-NO_DR Own_Lock_or_Unlock 0 <--
-NO_DR Data_Owner 0 <--
-NO_DR Data_All_Tokens 0 <--
-NO_DR Tokens 0 <--
-NO_DR Request_Timeout 0 <--
-NO_DR DMA_READ 0 <--
-NO_DR DMA_WRITE 0 <--
-
-DW_L GETX 0 <--
-DW_L GETS 0 <--
-DW_L Lockdown 0 <--
-DW_L Unlockdown 0 <--
-DW_L Own_Lock_or_Unlock 0 <--
-DW_L Data_Owner 0 <--
-DW_L Data_All_Tokens 0 <--
-DW_L Ack_Owner 0 <--
-DW_L Ack_Owner_All_Tokens 0 <--
-DW_L Tokens 0 <--
-DW_L Request_Timeout 0 <--
-DW_L DMA_READ 0 <--
-DW_L DMA_WRITE 0 <--
-
-DR_L GETX 0 <--
-DR_L GETS 0 <--
-DR_L Lockdown 0 <--
-DR_L Unlockdown 0 <--
-DR_L Own_Lock_or_Unlock 0 <--
-DR_L Data_Owner 0 <--
-DR_L Data_All_Tokens 0 <--
-DR_L Ack_Owner 0 <--
-DR_L Ack_Owner_All_Tokens 0 <--
-DR_L Tokens 0 <--
-DR_L Request_Timeout 0 <--
-DR_L DMA_READ 0 <--
-DR_L DMA_WRITE 0 <--
-
+O GETX [178 ] 178
+O GETS [1123 ] 1123
+O Lockdown [0 ] 0
+O Unlockdown [0 ] 0
+O Own_Lock_or_Unlock [0 ] 0
+O Own_Lock_or_Unlock_Tokens [0 ] 0
+O Data_Owner [0 ] 0
+O Data_All_Tokens [0 ] 0
+O Tokens [0 ] 0
+O Ack_All_Tokens [24 ] 24
+O DMA_READ [0 ] 0
+O DMA_WRITE [0 ] 0
+O DMA_WRITE_All_Tokens [0 ] 0
+
+NO GETX [1 ] 1
+NO GETS [0 ] 0
+NO Lockdown [0 ] 0
+NO Unlockdown [0 ] 0
+NO Own_Lock_or_Unlock [0 ] 0
+NO Own_Lock_or_Unlock_Tokens [0 ] 0
+NO Data_Owner [21 ] 21
+NO Data_All_Tokens [220 ] 220
+NO Ack_Owner [21 ] 21
+NO Ack_Owner_All_Tokens [1029 ] 1029
+NO Tokens [0 ] 0
+NO DMA_READ [0 ] 0
+NO DMA_WRITE [0 ] 0
+
+L GETX [0 ] 0
+L GETS [0 ] 0
+L Lockdown [0 ] 0
+L Unlockdown [0 ] 0
+L Own_Lock_or_Unlock [0 ] 0
+L Own_Lock_or_Unlock_Tokens [0 ] 0
+L Data_Owner [0 ] 0
+L Data_All_Tokens [0 ] 0
+L Ack_Owner [0 ] 0
+L Ack_Owner_All_Tokens [0 ] 0
+L Tokens [0 ] 0
+L DMA_READ [0 ] 0
+L DMA_WRITE [0 ] 0
+L DMA_WRITE_All_Tokens [0 ] 0
+
+O_W GETX [0 ] 0
+O_W GETS [0 ] 0
+O_W Lockdown [0 ] 0
+O_W Unlockdown [0 ] 0
+O_W Own_Lock_or_Unlock [0 ] 0
+O_W Own_Lock_or_Unlock_Tokens [0 ] 0
+O_W Data_Owner [0 ] 0
+O_W Data_All_Tokens [0 ] 0
+O_W Ack_Owner [0 ] 0
+O_W Tokens [0 ] 0
+O_W Ack_All_Tokens [0 ] 0
+O_W Memory_Data [0 ] 0
+O_W Memory_Ack [241 ] 241
+O_W DMA_READ [0 ] 0
+O_W DMA_WRITE [0 ] 0
+O_W DMA_WRITE_All_Tokens [0 ] 0
+
+L_O_W GETX [0 ] 0
+L_O_W GETS [0 ] 0
+L_O_W Lockdown [0 ] 0
+L_O_W Unlockdown [0 ] 0
+L_O_W Own_Lock_or_Unlock [0 ] 0
+L_O_W Own_Lock_or_Unlock_Tokens [0 ] 0
+L_O_W Data_Owner [0 ] 0
+L_O_W Data_All_Tokens [0 ] 0
+L_O_W Ack_Owner [0 ] 0
+L_O_W Tokens [0 ] 0
+L_O_W Ack_All_Tokens [0 ] 0
+L_O_W Memory_Data [0 ] 0
+L_O_W Memory_Ack [0 ] 0
+L_O_W DMA_READ [0 ] 0
+L_O_W DMA_WRITE [0 ] 0
+L_O_W DMA_WRITE_All_Tokens [0 ] 0
+
+L_NO_W GETX [0 ] 0
+L_NO_W GETS [0 ] 0
+L_NO_W Lockdown [0 ] 0
+L_NO_W Unlockdown [0 ] 0
+L_NO_W Own_Lock_or_Unlock [0 ] 0
+L_NO_W Own_Lock_or_Unlock_Tokens [0 ] 0
+L_NO_W Data_Owner [0 ] 0
+L_NO_W Data_All_Tokens [0 ] 0
+L_NO_W Ack_Owner [0 ] 0
+L_NO_W Tokens [0 ] 0
+L_NO_W Ack_All_Tokens [0 ] 0
+L_NO_W Memory_Data [0 ] 0
+L_NO_W DMA_READ [0 ] 0
+L_NO_W DMA_WRITE [0 ] 0
+L_NO_W DMA_WRITE_All_Tokens [0 ] 0
+
+DR_L_W GETX [0 ] 0
+DR_L_W GETS [0 ] 0
+DR_L_W Lockdown [0 ] 0
+DR_L_W Unlockdown [0 ] 0
+DR_L_W Own_Lock_or_Unlock [0 ] 0
+DR_L_W Own_Lock_or_Unlock_Tokens [0 ] 0
+DR_L_W Data_Owner [0 ] 0
+DR_L_W Data_All_Tokens [0 ] 0
+DR_L_W Ack_Owner [0 ] 0
+DR_L_W Tokens [0 ] 0
+DR_L_W Ack_All_Tokens [0 ] 0
+DR_L_W Request_Timeout [0 ] 0
+DR_L_W Memory_Data [0 ] 0
+DR_L_W DMA_READ [0 ] 0
+DR_L_W DMA_WRITE [0 ] 0
+DR_L_W DMA_WRITE_All_Tokens [0 ] 0
+
+DW_L_W GETX [0 ] 0
+DW_L_W GETS [0 ] 0
+DW_L_W Lockdown [0 ] 0
+DW_L_W Unlockdown [0 ] 0
+DW_L_W Own_Lock_or_Unlock [0 ] 0
+DW_L_W Own_Lock_or_Unlock_Tokens [0 ] 0
+DW_L_W Data_Owner [0 ] 0
+DW_L_W Data_All_Tokens [0 ] 0
+DW_L_W Ack_Owner [0 ] 0
+DW_L_W Tokens [0 ] 0
+DW_L_W Ack_All_Tokens [0 ] 0
+DW_L_W Request_Timeout [0 ] 0
+DW_L_W Memory_Ack [0 ] 0
+DW_L_W DMA_READ [0 ] 0
+DW_L_W DMA_WRITE [0 ] 0
+DW_L_W DMA_WRITE_All_Tokens [0 ] 0
+
+NO_W GETX [0 ] 0
+NO_W GETS [0 ] 0
+NO_W Lockdown [0 ] 0
+NO_W Unlockdown [0 ] 0
+NO_W Own_Lock_or_Unlock [0 ] 0
+NO_W Own_Lock_or_Unlock_Tokens [0 ] 0
+NO_W Data_Owner [0 ] 0
+NO_W Data_All_Tokens [0 ] 0
+NO_W Ack_Owner [0 ] 0
+NO_W Tokens [0 ] 0
+NO_W Ack_All_Tokens [0 ] 0
+NO_W Memory_Data [1301 ] 1301
+NO_W DMA_READ [0 ] 0
+NO_W DMA_WRITE [0 ] 0
+NO_W DMA_WRITE_All_Tokens [0 ] 0
+
+O_DW_W GETX [0 ] 0
+O_DW_W GETS [0 ] 0
+O_DW_W Lockdown [0 ] 0
+O_DW_W Unlockdown [0 ] 0
+O_DW_W Own_Lock_or_Unlock [0 ] 0
+O_DW_W Own_Lock_or_Unlock_Tokens [0 ] 0
+O_DW_W Data_Owner [0 ] 0
+O_DW_W Data_All_Tokens [0 ] 0
+O_DW_W Ack_Owner [0 ] 0
+O_DW_W Tokens [0 ] 0
+O_DW_W Ack_All_Tokens [0 ] 0
+O_DW_W Request_Timeout [0 ] 0
+O_DW_W Memory_Ack [0 ] 0
+O_DW_W DMA_READ [0 ] 0
+O_DW_W DMA_WRITE [0 ] 0
+O_DW_W DMA_WRITE_All_Tokens [0 ] 0
+
+O_DR_W GETX [0 ] 0
+O_DR_W GETS [0 ] 0
+O_DR_W Lockdown [0 ] 0
+O_DR_W Unlockdown [0 ] 0
+O_DR_W Own_Lock_or_Unlock [0 ] 0
+O_DR_W Own_Lock_or_Unlock_Tokens [0 ] 0
+O_DR_W Data_Owner [0 ] 0
+O_DR_W Data_All_Tokens [0 ] 0
+O_DR_W Ack_Owner [0 ] 0
+O_DR_W Tokens [0 ] 0
+O_DR_W Ack_All_Tokens [0 ] 0
+O_DR_W Request_Timeout [0 ] 0
+O_DR_W Memory_Data [0 ] 0
+O_DR_W DMA_READ [0 ] 0
+O_DR_W DMA_WRITE [0 ] 0
+O_DR_W DMA_WRITE_All_Tokens [0 ] 0
+
+O_DW GETX [0 ] 0
+O_DW GETS [0 ] 0
+O_DW Lockdown [0 ] 0
+O_DW Unlockdown [0 ] 0
+O_DW Own_Lock_or_Unlock [0 ] 0
+O_DW Own_Lock_or_Unlock_Tokens [0 ] 0
+O_DW Data_Owner [0 ] 0
+O_DW Data_All_Tokens [0 ] 0
+O_DW Ack_Owner [0 ] 0
+O_DW Ack_Owner_All_Tokens [0 ] 0
+O_DW Tokens [0 ] 0
+O_DW Ack_All_Tokens [0 ] 0
+O_DW Request_Timeout [0 ] 0
+O_DW DMA_READ [0 ] 0
+O_DW DMA_WRITE [0 ] 0
+O_DW DMA_WRITE_All_Tokens [0 ] 0
+
+NO_DW GETX [0 ] 0
+NO_DW GETS [0 ] 0
+NO_DW Lockdown [0 ] 0
+NO_DW Unlockdown [0 ] 0
+NO_DW Own_Lock_or_Unlock [0 ] 0
+NO_DW Own_Lock_or_Unlock_Tokens [0 ] 0
+NO_DW Data_Owner [0 ] 0
+NO_DW Data_All_Tokens [0 ] 0
+NO_DW Tokens [0 ] 0
+NO_DW Request_Timeout [0 ] 0
+NO_DW DMA_READ [0 ] 0
+NO_DW DMA_WRITE [0 ] 0
+NO_DW DMA_WRITE_All_Tokens [0 ] 0
+
+NO_DR GETX [0 ] 0
+NO_DR GETS [0 ] 0
+NO_DR Lockdown [0 ] 0
+NO_DR Unlockdown [0 ] 0
+NO_DR Own_Lock_or_Unlock [0 ] 0
+NO_DR Own_Lock_or_Unlock_Tokens [0 ] 0
+NO_DR Data_Owner [0 ] 0
+NO_DR Data_All_Tokens [0 ] 0
+NO_DR Tokens [0 ] 0
+NO_DR Request_Timeout [0 ] 0
+NO_DR DMA_READ [0 ] 0
+NO_DR DMA_WRITE [0 ] 0
+NO_DR DMA_WRITE_All_Tokens [0 ] 0
+
+DW_L GETX [0 ] 0
+DW_L GETS [0 ] 0
+DW_L Lockdown [0 ] 0
+DW_L Unlockdown [0 ] 0
+DW_L Own_Lock_or_Unlock [0 ] 0
+DW_L Own_Lock_or_Unlock_Tokens [0 ] 0
+DW_L Data_Owner [0 ] 0
+DW_L Data_All_Tokens [0 ] 0
+DW_L Ack_Owner [0 ] 0
+DW_L Ack_Owner_All_Tokens [0 ] 0
+DW_L Tokens [0 ] 0
+DW_L Request_Timeout [0 ] 0
+DW_L DMA_READ [0 ] 0
+DW_L DMA_WRITE [0 ] 0
+DW_L DMA_WRITE_All_Tokens [0 ] 0
+
+DR_L GETX [0 ] 0
+DR_L GETS [0 ] 0
+DR_L Lockdown [0 ] 0
+DR_L Unlockdown [0 ] 0
+DR_L Own_Lock_or_Unlock [0 ] 0
+DR_L Own_Lock_or_Unlock_Tokens [0 ] 0
+DR_L Data_Owner [0 ] 0
+DR_L Data_All_Tokens [0 ] 0
+DR_L Ack_Owner [0 ] 0
+DR_L Ack_Owner_All_Tokens [0 ] 0
+DR_L Tokens [0 ] 0
+DR_L Request_Timeout [0 ] 0
+DR_L DMA_READ [0 ] 0
+DR_L DMA_WRITE [0 ] 0
+DR_L DMA_WRITE_All_Tokens \ No newline at end of file
diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/simout b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/simout
index 9f63d9c39..bfe534678 100755
--- a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/simout
+++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/simout
@@ -5,13 +5,13 @@ The Regents of The University of Michigan
All Rights Reserved
-M5 compiled Jan 28 2010 15:54:34
-M5 revision 6068d4fc30d3+ 6931+ default qtip tip brad/rubycfg_regress_udpate
-M5 started Jan 28 2010 15:55:45
-M5 executing on svvint04
+M5 compiled Aug 5 2010 10:41:36
+M5 revision 1cd2a169499f+ 7535+ default brad/hammer_merge_gets qtip tip
+M5 started Aug 5 2010 10:42:35
+M5 executing on svvint09
command line: build/ALPHA_SE_MOESI_CMP_token/m5.fast -d build/ALPHA_SE_MOESI_CMP_token/tests/fast/quick/00.hello/alpha/linux/simple-timing-ruby-MOESI_CMP_token -re tests/run.py build/ALPHA_SE_MOESI_CMP_token/tests/fast/quick/00.hello/alpha/linux/simple-timing-ruby-MOESI_CMP_token
Global frequency set at 1000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
Hello world!
-Exiting @ tick 236654 because target called exit()
+Exiting @ tick 243131 because target called exit()
diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/stats.txt b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/stats.txt
index 717c91c49..4330907be 100644
--- a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/stats.txt
+++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/stats.txt
@@ -1,13 +1,13 @@
---------- Begin Simulation Statistics ----------
-host_inst_rate 35577 # Simulator instruction rate (inst/s)
-host_mem_usage 215884 # Number of bytes of host memory used
-host_seconds 0.18 # Real time elapsed on the host
-host_tick_rate 1314701 # Simulator tick rate (ticks/s)
+host_inst_rate 45740 # Simulator instruction rate (inst/s)
+host_mem_usage 212336 # Number of bytes of host memory used
+host_seconds 0.14 # Real time elapsed on the host
+host_tick_rate 1736538 # Simulator tick rate (ticks/s)
sim_freq 1000000000 # Frequency of simulated ticks
sim_insts 6404 # Number of instructions simulated
-sim_seconds 0.000237 # Number of seconds simulated
-sim_ticks 236654 # Number of ticks simulated
+sim_seconds 0.000243 # Number of seconds simulated
+sim_ticks 243131 # Number of ticks simulated
system.cpu.dtb.data_accesses 2060 # DTB accesses
system.cpu.dtb.data_acv 0 # DTB access violations
system.cpu.dtb.data_hits 2050 # DTB hits
@@ -42,7 +42,7 @@ system.cpu.itb.write_acv 0 # DT
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
-system.cpu.numCycles 236654 # number of cpu cycles simulated
+system.cpu.numCycles 243131 # number of cpu cycles simulated
system.cpu.num_insts 6404 # Number of instructions executed
system.cpu.num_refs 2060 # Number of memory references
system.cpu.workload.PROG:num_syscalls 17 # Number of system calls
diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/config.ini b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/config.ini
index 2f4078396..a5602ce6c 100644
--- a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/config.ini
+++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/config.ini
@@ -5,7 +5,7 @@ dummy=0
[system]
type=System
-children=cpu physmem ruby
+children=cpu dir_cntrl0 l1_cntrl0 physmem ruby
mem_mode=timing
physmem=system.physmem
@@ -32,8 +32,8 @@ progress_interval=0
system=system
tracer=system.cpu.tracer
workload=system.cpu.workload
-dcache_port=system.ruby.network.topology.ext_links0.ext_node.sequencer.port[1]
-icache_port=system.ruby.network.topology.ext_links0.ext_node.sequencer.port[0]
+dcache_port=system.l1_cntrl0.sequencer.port[1]
+icache_port=system.l1_cntrl0.sequencer.port[0]
[system.cpu.dtb]
type=AlphaTLB
@@ -65,6 +65,110 @@ simpoint=0
system=system
uid=100
+[system.dir_cntrl0]
+type=Directory_Controller
+children=directory memBuffer probeFilter
+buffer_size=0
+directory=system.dir_cntrl0.directory
+memBuffer=system.dir_cntrl0.memBuffer
+memory_controller_latency=2
+number_of_TBEs=256
+probeFilter=system.dir_cntrl0.probeFilter
+probe_filter_enabled=false
+recycle_latency=10
+transitions_per_cycle=32
+version=0
+
+[system.dir_cntrl0.directory]
+type=RubyDirectoryMemory
+map_levels=4
+numa_high_bit=6
+size=134217728
+use_map=false
+version=0
+
+[system.dir_cntrl0.memBuffer]
+type=RubyMemoryControl
+bank_bit_0=8
+bank_busy_time=11
+bank_queue_size=12
+banks_per_rank=8
+basic_bus_busy_time=2
+dimm_bit_0=12
+dimms_per_channel=2
+mem_bus_cycle_multiplier=10
+mem_ctl_latency=12
+mem_fixed_delay=0
+mem_random_arbitrate=0
+rank_bit_0=11
+rank_rank_delay=1
+ranks_per_dimm=2
+read_write_delay=2
+refresh_period=1560
+tFaw=0
+version=0
+
+[system.dir_cntrl0.probeFilter]
+type=RubyCache
+assoc=4
+latency=1
+replacement_policy=PSEUDO_LRU
+size=1024
+start_index_bit=6
+
+[system.l1_cntrl0]
+type=L1Cache_Controller
+children=L2cacheMemory sequencer
+L1DcacheMemory=system.l1_cntrl0.sequencer.dcache
+L1IcacheMemory=system.l1_cntrl0.sequencer.icache
+L2cacheMemory=system.l1_cntrl0.L2cacheMemory
+buffer_size=0
+cache_response_latency=10
+issue_latency=2
+no_mig_atomic=true
+number_of_TBEs=256
+recycle_latency=10
+sequencer=system.l1_cntrl0.sequencer
+transitions_per_cycle=32
+version=0
+
+[system.l1_cntrl0.L2cacheMemory]
+type=RubyCache
+assoc=2
+latency=10
+replacement_policy=PSEUDO_LRU
+size=512
+start_index_bit=6
+
+[system.l1_cntrl0.sequencer]
+type=RubySequencer
+children=dcache icache
+dcache=system.l1_cntrl0.sequencer.dcache
+deadlock_threshold=500000
+icache=system.l1_cntrl0.sequencer.icache
+max_outstanding_requests=16
+physmem=system.physmem
+using_ruby_tester=false
+version=0
+physMemPort=system.physmem.port[0]
+port=system.cpu.icache_port system.cpu.dcache_port
+
+[system.l1_cntrl0.sequencer.dcache]
+type=RubyCache
+assoc=2
+latency=2
+replacement_policy=PSEUDO_LRU
+size=256
+start_index_bit=6
+
+[system.l1_cntrl0.sequencer.icache]
+type=RubyCache
+assoc=2
+latency=2
+replacement_policy=PSEUDO_LRU
+size=256
+start_index_bit=6
+
[system.physmem]
type=PhysicalMemory
file=
@@ -73,7 +177,7 @@ latency_var=0
null=false
range=0:134217727
zero=false
-port=system.ruby.network.topology.ext_links0.ext_node.sequencer.physMemPort
+port=system.l1_cntrl0.sequencer.physMemPort
[system.ruby]
type=RubySystem
@@ -83,6 +187,7 @@ clock=1
debug=system.ruby.debug
mem_size=134217728
network=system.ruby.network
+no_mem_vec=false
profiler=system.ruby.profiler
random_seed=1234
randomization=false
@@ -100,7 +205,7 @@ verbosity_string=none
[system.ruby.network]
type=SimpleNetwork
children=topology
-adaptive_routing=true
+adaptive_routing=false
buffer_size=0
control_msg_size=8
endpoint_bandwidth=10000
@@ -113,114 +218,26 @@ type=Topology
children=ext_links0 ext_links1 int_links0 int_links1
ext_links=system.ruby.network.topology.ext_links0 system.ruby.network.topology.ext_links1
int_links=system.ruby.network.topology.int_links0 system.ruby.network.topology.int_links1
+name=Crossbar
num_int_nodes=3
print_config=false
[system.ruby.network.topology.ext_links0]
type=ExtLink
-children=ext_node
bw_multiplier=64
-ext_node=system.ruby.network.topology.ext_links0.ext_node
+ext_node=system.l1_cntrl0
int_node=0
latency=1
weight=1
-[system.ruby.network.topology.ext_links0.ext_node]
-type=L1Cache_Controller
-children=L2cacheMemory sequencer
-L1DcacheMemory=system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache
-L1IcacheMemory=system.ruby.network.topology.ext_links0.ext_node.sequencer.icache
-L2cacheMemory=system.ruby.network.topology.ext_links0.ext_node.L2cacheMemory
-buffer_size=0
-cache_response_latency=12
-issue_latency=2
-number_of_TBEs=256
-recycle_latency=10
-sequencer=system.ruby.network.topology.ext_links0.ext_node.sequencer
-transitions_per_cycle=32
-version=0
-
-[system.ruby.network.topology.ext_links0.ext_node.L2cacheMemory]
-type=RubyCache
-assoc=2
-latency=15
-replacement_policy=PSEUDO_LRU
-size=512
-
-[system.ruby.network.topology.ext_links0.ext_node.sequencer]
-type=RubySequencer
-children=dcache icache
-dcache=system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache
-deadlock_threshold=500000
-icache=system.ruby.network.topology.ext_links0.ext_node.sequencer.icache
-max_outstanding_requests=16
-physmem=system.physmem
-using_ruby_tester=false
-version=0
-physMemPort=system.physmem.port[0]
-port=system.cpu.icache_port system.cpu.dcache_port
-
-[system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache]
-type=RubyCache
-assoc=2
-latency=3
-replacement_policy=PSEUDO_LRU
-size=256
-
-[system.ruby.network.topology.ext_links0.ext_node.sequencer.icache]
-type=RubyCache
-assoc=2
-latency=3
-replacement_policy=PSEUDO_LRU
-size=256
-
[system.ruby.network.topology.ext_links1]
type=ExtLink
-children=ext_node
bw_multiplier=64
-ext_node=system.ruby.network.topology.ext_links1.ext_node
+ext_node=system.dir_cntrl0
int_node=1
latency=1
weight=1
-[system.ruby.network.topology.ext_links1.ext_node]
-type=Directory_Controller
-children=directory memBuffer
-buffer_size=0
-directory=system.ruby.network.topology.ext_links1.ext_node.directory
-memBuffer=system.ruby.network.topology.ext_links1.ext_node.memBuffer
-memory_controller_latency=12
-number_of_TBEs=256
-recycle_latency=10
-transitions_per_cycle=32
-version=0
-
-[system.ruby.network.topology.ext_links1.ext_node.directory]
-type=RubyDirectoryMemory
-size=134217728
-version=0
-
-[system.ruby.network.topology.ext_links1.ext_node.memBuffer]
-type=RubyMemoryControl
-bank_bit_0=8
-bank_busy_time=11
-bank_queue_size=12
-banks_per_rank=8
-basic_bus_busy_time=2
-dimm_bit_0=12
-dimms_per_channel=2
-mem_bus_cycle_multiplier=10
-mem_ctl_latency=12
-mem_fixed_delay=0
-mem_random_arbitrate=0
-rank_bit_0=11
-rank_rank_delay=1
-ranks_per_dimm=2
-read_write_delay=2
-refresh_period=1560
-tFaw=0
-version=0
-
[system.ruby.network.topology.int_links0]
type=IntLink
bw_multiplier=16
diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/ruby.stats b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/ruby.stats
index b64bafefe..422144bd2 100644
--- a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/ruby.stats
+++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/ruby.stats
@@ -13,14 +13,14 @@ RubySystem config:
Network Configuration
---------------------
network: SIMPLE_NETWORK
-topology:
+topology: Crossbar
-virtual_net_0: active, unordered
-virtual_net_1: active, unordered
+virtual_net_0: active, ordered
+virtual_net_1: active, ordered
virtual_net_2: active, unordered
virtual_net_3: active, unordered
-virtual_net_4: active, ordered
-virtual_net_5: active, ordered
+virtual_net_4: active, unordered
+virtual_net_5: active, unordered
virtual_net_6: inactive
virtual_net_7: inactive
virtual_net_8: inactive
@@ -34,7 +34,7 @@ periodic_stats_period: 1000000
================ End RubySystem Configuration Print ================
-Real time: Jan/28/2010 11:55:11
+Real time: Aug/05/2010 11:09:30
Profiler Stats
--------------
@@ -43,31 +43,20 @@ Elapsed_time_in_minutes: 0
Elapsed_time_in_hours: 0
Elapsed_time_in_days: 0
-Virtual_time_in_seconds: 0.39
-Virtual_time_in_minutes: 0.0065
-Virtual_time_in_hours: 0.000108333
-Virtual_time_in_days: 4.51389e-06
+Virtual_time_in_seconds: 0.61
+Virtual_time_in_minutes: 0.0101667
+Virtual_time_in_hours: 0.000169444
+Virtual_time_in_days: 7.06019e-06
-Ruby_current_time: 215528
+Ruby_current_time: 207970
Ruby_start_time: 0
-Ruby_cycles: 215528
+Ruby_cycles: 207970
-mbytes_resident: 33.1406
-mbytes_total: 33.1484
-resident_ratio: 1
-
-Total_misses: 0
-total_misses: 0 [ 0 ]
-user_misses: 0 [ 0 ]
-supervisor_misses: 0 [ 0 ]
-
-ruby_cycles_executed: 215529 [ 215529 ]
-
-transactions_started: 0 [ 0 ]
-transactions_ended: 0 [ 0 ]
-cycles_per_transaction: 0 [ 0 ]
-misses_per_transaction: 0 [ 0 ]
+mbytes_resident: 34.3633
+mbytes_total: 206.125
+resident_ratio: 0.166768
+ruby_cycles_executed: [ 207971 ]
Busy Controller Counts:
L1Cache-0:0
@@ -80,10 +69,32 @@ sequencer_requests_outstanding: [binsize: 1 max: 1 count: 8465 average: 1 |
All Non-Zero Cycle Demand Cache Accesses
----------------------------------------
-miss_latency: [binsize: 2 max: 377 count: 8464 average: 24.4641 | standard deviation: 54.9689 | 0 7305 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 199 174 167 309 200 14 3 4 1 4 0 15 1 5 2 1 0 0 0 1 3 4 4 7 1 1 0 0 0 0 0 0 0 0 2 0 0 0 0 0 0 0 0 0 1 0 2 0 0 0 0 1 0 1 0 2 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 15 4 1 1 0 2 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 ]
-miss_latency_1: [binsize: 2 max: 261 count: 6414 average: 16.7424 | standard deviation: 43.645 | 0 5833 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 111 113 72 159 92 10 2 2 1 2 0 0 0 1 0 0 0 0 0 1 3 1 4 3 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
-miss_latency_2: [binsize: 2 max: 333 count: 1185 average: 57.908 | standard deviation: 75.2483 | 0 765 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 80 52 60 116 72 4 1 0 0 1 0 12 1 2 2 1 0 0 0 0 0 2 0 3 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 2 0 0 0 0 0 0 1 0 2 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
-miss_latency_3: [binsize: 2 max: 377 count: 865 average: 35.904 | standard deviation: 74.7708 | 0 707 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 8 9 35 34 36 0 0 2 0 1 0 3 0 2 0 0 0 0 0 0 0 1 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 14 3 1 0 0 2 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 ]
+miss_latency: [binsize: 2 max: 340 count: 8464 average: 23.5711 | standard deviation: 54.4023 | 0 7102 0 0 0 0 203 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 105 186 155 195 147 260 3 10 2 4 5 17 3 8 6 12 5 1 0 0 0 0 0 0 0 1 0 0 0 0 2 0 1 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 2 2 3 15 0 0 0 0 1 0 0 0 1 3 0 0 0 0 0 0 ]
+miss_latency_IFETCH: [binsize: 2 max: 206 count: 6414 average: 15.8318 | standard deviation: 43.5273 | 0 5768 0 0 0 0 65 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 58 104 55 89 94 142 2 1 1 2 2 14 2 2 3 6 2 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency_LD: [binsize: 2 max: 320 count: 1185 average: 57.1789 | standard deviation: 73.4856 | 0 660 0 0 0 0 105 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 41 75 63 68 46 92 1 7 1 2 2 3 0 4 2 4 2 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 2 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency_ST: [binsize: 2 max: 340 count: 865 average: 34.9179 | standard deviation: 73.5132 | 0 674 0 0 0 0 33 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 6 7 37 38 7 26 0 2 0 0 1 0 1 2 1 2 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 3 14 0 0 0 0 1 0 0 0 1 3 ]
+miss_latency_L1Cache: [binsize: 1 max: 2 count: 7102 average: 2 | standard deviation: 0 | 0 0 7102 ]
+miss_latency_L2Cache: [binsize: 1 max: 12 count: 203 average: 12 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 203 ]
+miss_latency_Directory: [binsize: 2 max: 340 count: 1159 average: 157.779 | standard deviation: 26.9285 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 105 186 155 195 147 260 3 10 2 4 5 17 3 8 6 12 5 1 0 0 0 0 0 0 0 1 0 0 0 0 2 0 1 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 2 2 3 15 0 0 0 0 1 0 0 0 1 3 0 0 0 0 0 0 ]
+miss_latency_wCC_issue_to_initial_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+miss_latency_wCC_initial_forward_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+miss_latency_wCC_forward_to_first_response: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+miss_latency_wCC_first_response_to_completion: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+imcomplete_wCC_Times: 0
+miss_latency_dir_issue_to_initial_request: [binsize: 1 max: 0 count: 1 average: 0 | standard deviation: 0 | 1 ]
+miss_latency_dir_initial_forward_request: [binsize: 1 max: 0 count: 1 average: 0 | standard deviation: 0 | 1 ]
+miss_latency_dir_forward_to_first_response: [binsize: 1 max: 158 count: 1 average: 158 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ]
+miss_latency_dir_first_response_to_completion: [binsize: 1 max: 0 count: 1 average: 0 | standard deviation: 0 | 1 ]
+imcomplete_dir_Times: 1158
+miss_latency_IFETCH_L1Cache: [binsize: 1 max: 2 count: 5768 average: 2 | standard deviation: 0 | 0 0 5768 ]
+miss_latency_IFETCH_L2Cache: [binsize: 1 max: 12 count: 65 average: 12 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 65 ]
+miss_latency_IFETCH_Directory: [binsize: 2 max: 206 count: 581 average: 153.578 | standard deviation: 6.13441 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 58 104 55 89 94 142 2 1 1 2 2 14 2 2 3 6 2 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency_LD_L1Cache: [binsize: 1 max: 2 count: 660 average: 2 | standard deviation: 0 | 0 0 660 ]
+miss_latency_LD_L2Cache: [binsize: 1 max: 12 count: 105 average: 12 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 105 ]
+miss_latency_LD_Directory: [binsize: 2 max: 320 count: 420 average: 155.183 | standard deviation: 18.008 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 41 75 63 68 46 92 1 7 1 2 2 3 0 4 2 4 2 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 2 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency_ST_L1Cache: [binsize: 1 max: 2 count: 674 average: 2 | standard deviation: 0 | 0 0 674 ]
+miss_latency_ST_L2Cache: [binsize: 1 max: 12 count: 33 average: 12 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 33 ]
+miss_latency_ST_Directory: [binsize: 2 max: 340 count: 158 average: 180.127 | standard deviation: 61.3036 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 6 7 37 38 7 26 0 2 0 0 1 0 1 2 1 2 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 3 14 0 0 0 0 1 0 0 0 1 3 ]
All Non-Zero Cycle SW Prefetch Requests
------------------------------------
@@ -115,8 +126,8 @@ Resource Usage
page_size: 4096
user_time: 0
system_time: 0
-page_reclaims: 7120
-page_faults: 2128
+page_reclaims: 9927
+page_faults: 0
swaps: 0
block_inputs: 0
block_outputs: 0
@@ -124,453 +135,665 @@ block_outputs: 0
Network Stats
-------------
+total_msg_count_Request_Control: 3477 27816
+total_msg_count_Response_Data: 3477 250344
+total_msg_count_Writeback_Data: 660 47520
+total_msg_count_Writeback_Control: 9627 77016
+total_msg_count_Unblock_Control: 3477 27816
+total_msgs: 20718 total_bytes: 430512
+
switch_0_inlinks: 2
switch_0_outlinks: 2
-links_utilized_percent_switch_0: 0.107382
- links_utilized_percent_switch_0_link_0: 0.0671258 bw: 640000 base_latency: 1
- links_utilized_percent_switch_0_link_1: 0.147637 bw: 160000 base_latency: 1
+links_utilized_percent_switch_0: 0.111284
+ links_utilized_percent_switch_0_link_0: 0.0695653 bw: 640000 base_latency: 1
+ links_utilized_percent_switch_0_link_1: 0.153003 bw: 160000 base_latency: 1
- outgoing_messages_switch_0_link_0_Response_Data: 1159 83448 [ 0 1159 0 0 0 0 0 0 0 0 ] base_latency: 1
- outgoing_messages_switch_0_link_0_Writeback_Control: 1143 9144 [ 0 0 1143 0 0 0 0 0 0 0 ] base_latency: 1
- outgoing_messages_switch_0_link_1_Request_Control: 1159 9272 [ 0 0 0 1159 0 0 0 0 0 0 ] base_latency: 1
- outgoing_messages_switch_0_link_1_Writeback_Data: 220 15840 [ 220 0 0 0 0 0 0 0 0 0 ] base_latency: 1
- outgoing_messages_switch_0_link_1_Writeback_Control: 2066 16528 [ 923 0 0 1143 0 0 0 0 0 0 ] base_latency: 1
- outgoing_messages_switch_0_link_1_Unblock_Control: 1159 9272 [ 1159 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_0_link_0_Response_Data: 1159 83448 [ 0 0 0 0 1159 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_0_link_0_Writeback_Control: 1143 9144 [ 0 0 0 1143 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_0_link_1_Request_Control: 1159 9272 [ 0 0 1159 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_0_link_1_Writeback_Data: 220 15840 [ 0 0 0 0 0 220 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_0_link_1_Writeback_Control: 2066 16528 [ 0 0 1143 0 0 923 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_0_link_1_Unblock_Control: 1159 9272 [ 0 0 0 0 0 1159 0 0 0 0 ] base_latency: 1
switch_1_inlinks: 2
switch_1_outlinks: 2
-links_utilized_percent_switch_1: 0.152706
- links_utilized_percent_switch_1_link_0: 0.0369094 bw: 640000 base_latency: 1
- links_utilized_percent_switch_1_link_1: 0.268503 bw: 160000 base_latency: 1
+links_utilized_percent_switch_1: 0.158256
+ links_utilized_percent_switch_1_link_0: 0.0382507 bw: 640000 base_latency: 1
+ links_utilized_percent_switch_1_link_1: 0.278261 bw: 160000 base_latency: 1
- outgoing_messages_switch_1_link_0_Request_Control: 1159 9272 [ 0 0 0 1159 0 0 0 0 0 0 ] base_latency: 1
- outgoing_messages_switch_1_link_0_Writeback_Data: 220 15840 [ 220 0 0 0 0 0 0 0 0 0 ] base_latency: 1
- outgoing_messages_switch_1_link_0_Writeback_Control: 2066 16528 [ 923 0 0 1143 0 0 0 0 0 0 ] base_latency: 1
- outgoing_messages_switch_1_link_0_Unblock_Control: 1159 9272 [ 1159 0 0 0 0 0 0 0 0 0 ] base_latency: 1
- outgoing_messages_switch_1_link_1_Response_Data: 1159 83448 [ 0 1159 0 0 0 0 0 0 0 0 ] base_latency: 1
- outgoing_messages_switch_1_link_1_Writeback_Control: 1143 9144 [ 0 0 1143 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_1_link_0_Request_Control: 1159 9272 [ 0 0 1159 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_1_link_0_Writeback_Data: 220 15840 [ 0 0 0 0 0 220 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_1_link_0_Writeback_Control: 2066 16528 [ 0 0 1143 0 0 923 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_1_link_0_Unblock_Control: 1159 9272 [ 0 0 0 0 0 1159 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_1_link_1_Response_Data: 1159 83448 [ 0 0 0 0 1159 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_1_link_1_Writeback_Control: 1143 9144 [ 0 0 0 1143 0 0 0 0 0 0 ] base_latency: 1
switch_2_inlinks: 2
switch_2_outlinks: 2
-links_utilized_percent_switch_2: 0.20807
- links_utilized_percent_switch_2_link_0: 0.268503 bw: 160000 base_latency: 1
- links_utilized_percent_switch_2_link_1: 0.147637 bw: 160000 base_latency: 1
-
- outgoing_messages_switch_2_link_0_Response_Data: 1159 83448 [ 0 1159 0 0 0 0 0 0 0 0 ] base_latency: 1
- outgoing_messages_switch_2_link_0_Writeback_Control: 1143 9144 [ 0 0 1143 0 0 0 0 0 0 0 ] base_latency: 1
- outgoing_messages_switch_2_link_1_Request_Control: 1159 9272 [ 0 0 0 1159 0 0 0 0 0 0 ] base_latency: 1
- outgoing_messages_switch_2_link_1_Writeback_Data: 220 15840 [ 220 0 0 0 0 0 0 0 0 0 ] base_latency: 1
- outgoing_messages_switch_2_link_1_Writeback_Control: 2066 16528 [ 923 0 0 1143 0 0 0 0 0 0 ] base_latency: 1
- outgoing_messages_switch_2_link_1_Unblock_Control: 1159 9272 [ 1159 0 0 0 0 0 0 0 0 0 ] base_latency: 1
-
-Cache Stats: system.ruby.network.topology.ext_links0.ext_node.sequencer.icache
- system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_misses: 581
- system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_demand_misses: 581
- system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_prefetches: 0
- system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_sw_prefetches: 0
- system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_hw_prefetches: 0
- system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_misses_per_transaction: inf
-
- system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_request_type_IFETCH: 100%
-
- system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_access_mode_type_SupervisorMode: 581 100%
- system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_request_size: [binsize: 1 max: 4 count: 581 average: 4 | standard deviation: 0 | 0 0 0 0 581 ]
-
-Cache Stats: system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache
- system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_misses: 578
- system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_demand_misses: 578
- system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_prefetches: 0
- system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_sw_prefetches: 0
- system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_hw_prefetches: 0
- system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_misses_per_transaction: inf
-
- system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_request_type_LD: 72.6644%
- system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_request_type_ST: 27.3356%
-
- system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_access_mode_type_SupervisorMode: 578 100%
- system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_request_size: [binsize: 1 max: 8 count: 578 average: 7.5917 | standard deviation: 1.2123 | 0 0 0 0 59 0 0 0 519 ]
-
-Cache Stats: system.ruby.network.topology.ext_links0.ext_node.L2cacheMemory
- system.ruby.network.topology.ext_links0.ext_node.L2cacheMemory_total_misses: 0
- system.ruby.network.topology.ext_links0.ext_node.L2cacheMemory_total_demand_misses: 0
- system.ruby.network.topology.ext_links0.ext_node.L2cacheMemory_total_prefetches: 0
- system.ruby.network.topology.ext_links0.ext_node.L2cacheMemory_total_sw_prefetches: 0
- system.ruby.network.topology.ext_links0.ext_node.L2cacheMemory_total_hw_prefetches: 0
- system.ruby.network.topology.ext_links0.ext_node.L2cacheMemory_misses_per_transaction: nan
-
- system.ruby.network.topology.ext_links0.ext_node.L2cacheMemory_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
-
- --- L1Cache 0 ---
+links_utilized_percent_switch_2: 0.215632
+ links_utilized_percent_switch_2_link_0: 0.278261 bw: 160000 base_latency: 1
+ links_utilized_percent_switch_2_link_1: 0.153003 bw: 160000 base_latency: 1
+
+ outgoing_messages_switch_2_link_0_Response_Data: 1159 83448 [ 0 0 0 0 1159 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_2_link_0_Writeback_Control: 1143 9144 [ 0 0 0 1143 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_2_link_1_Request_Control: 1159 9272 [ 0 0 1159 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_2_link_1_Writeback_Data: 220 15840 [ 0 0 0 0 0 220 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_2_link_1_Writeback_Control: 2066 16528 [ 0 0 1143 0 0 923 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_2_link_1_Unblock_Control: 1159 9272 [ 0 0 0 0 0 1159 0 0 0 0 ] base_latency: 1
+
+Cache Stats: system.l1_cntrl0.sequencer.icache
+ system.l1_cntrl0.sequencer.icache_total_misses: 646
+ system.l1_cntrl0.sequencer.icache_total_demand_misses: 646
+ system.l1_cntrl0.sequencer.icache_total_prefetches: 0
+ system.l1_cntrl0.sequencer.icache_total_sw_prefetches: 0
+ system.l1_cntrl0.sequencer.icache_total_hw_prefetches: 0
+
+ system.l1_cntrl0.sequencer.icache_request_type_IFETCH: 100%
+
+ system.l1_cntrl0.sequencer.icache_access_mode_type_SupervisorMode: 646 100%
+
+Cache Stats: system.l1_cntrl0.sequencer.dcache
+ system.l1_cntrl0.sequencer.dcache_total_misses: 716
+ system.l1_cntrl0.sequencer.dcache_total_demand_misses: 716
+ system.l1_cntrl0.sequencer.dcache_total_prefetches: 0
+ system.l1_cntrl0.sequencer.dcache_total_sw_prefetches: 0
+ system.l1_cntrl0.sequencer.dcache_total_hw_prefetches: 0
+
+ system.l1_cntrl0.sequencer.dcache_request_type_LD: 73.324%
+ system.l1_cntrl0.sequencer.dcache_request_type_ST: 26.676%
+
+ system.l1_cntrl0.sequencer.dcache_access_mode_type_SupervisorMode: 716 100%
+
+Cache Stats: system.l1_cntrl0.L2cacheMemory
+ system.l1_cntrl0.L2cacheMemory_total_misses: 1159
+ system.l1_cntrl0.L2cacheMemory_total_demand_misses: 1159
+ system.l1_cntrl0.L2cacheMemory_total_prefetches: 0
+ system.l1_cntrl0.L2cacheMemory_total_sw_prefetches: 0
+ system.l1_cntrl0.L2cacheMemory_total_hw_prefetches: 0
+
+ system.l1_cntrl0.L2cacheMemory_request_type_LD: 36.2381%
+ system.l1_cntrl0.L2cacheMemory_request_type_ST: 13.6324%
+ system.l1_cntrl0.L2cacheMemory_request_type_IFETCH: 50.1294%
+
+ system.l1_cntrl0.L2cacheMemory_access_mode_type_SupervisorMode: 1159 100%
+
+ --- L1Cache ---
- Event Counts -
-Load 1209
-Ifetch 6447
-Store 946
-L2_Replacement 1143
-L1_to_L2 1354
-L2_to_L1D 138
-L2_to_L1I 65
-Other_GETX 0
-Other_GETS 0
-Ack 0
-Shared_Ack 0
-Data 0
-Shared_Data 0
-Exclusive_Data 1159
-Writeback_Ack 1143
-Writeback_Nack 0
-All_acks 0
-All_acks_no_sharers 1159
+Load [1201 ] 1201
+Ifetch [6436 ] 6436
+Store [919 ] 919
+L2_Replacement [1143 ] 1143
+L1_to_L2 [1354 ] 1354
+Trigger_L2_to_L1D [138 ] 138
+Trigger_L2_to_L1I [65 ] 65
+Complete_L2_to_L1 [203 ] 203
+Other_GETX [0 ] 0
+Other_GETS [0 ] 0
+Merged_GETS [0 ] 0
+Other_GETS_No_Mig [0 ] 0
+Invalidate [0 ] 0
+Ack [0 ] 0
+Shared_Ack [0 ] 0
+Data [0 ] 0
+Shared_Data [0 ] 0
+Exclusive_Data [1159 ] 1159
+Writeback_Ack [1143 ] 1143
+Writeback_Nack [0 ] 0
+All_acks [0 ] 0
+All_acks_no_sharers [1159 ] 1159
- Transitions -
-I Load 420
-I Ifetch 581
-I Store 158
-I L2_Replacement 0 <--
-I L1_to_L2 0 <--
-I L2_to_L1D 0 <--
-I L2_to_L1I 0 <--
-I Other_GETX 0 <--
-I Other_GETS 0 <--
-
-S Load 0 <--
-S Ifetch 0 <--
-S Store 0 <--
-S L2_Replacement 0 <--
-S L1_to_L2 0 <--
-S L2_to_L1D 0 <--
-S L2_to_L1I 0 <--
-S Other_GETX 0 <--
-S Other_GETS 0 <--
-
-O Load 0 <--
-O Ifetch 0 <--
-O Store 0 <--
-O L2_Replacement 0 <--
-O L1_to_L2 0 <--
-O L2_to_L1D 0 <--
-O L2_to_L1I 0 <--
-O Other_GETX 0 <--
-O Other_GETS 0 <--
-
-M Load 368
-M Ifetch 5833
-M Store 66
-M L2_Replacement 923
-M L1_to_L2 1061
-M L2_to_L1D 68
-M L2_to_L1I 65
-M Other_GETX 0 <--
-M Other_GETS 0 <--
-
-MM Load 397
-MM Ifetch 0 <--
-MM Store 641
-MM L2_Replacement 220
-MM L1_to_L2 293
-MM L2_to_L1D 70
-MM L2_to_L1I 0 <--
-MM Other_GETX 0 <--
-MM Other_GETS 0 <--
-
-IM Load 0 <--
-IM Ifetch 0 <--
-IM Store 0 <--
-IM L2_Replacement 0 <--
-IM L1_to_L2 0 <--
-IM Other_GETX 0 <--
-IM Other_GETS 0 <--
-IM Ack 0 <--
-IM Data 0 <--
-IM Exclusive_Data 158
-
-SM Load 0 <--
-SM Ifetch 0 <--
-SM Store 0 <--
-SM L2_Replacement 0 <--
-SM L1_to_L2 0 <--
-SM Other_GETX 0 <--
-SM Other_GETS 0 <--
-SM Ack 0 <--
-SM Data 0 <--
-
-OM Load 0 <--
-OM Ifetch 0 <--
-OM Store 0 <--
-OM L2_Replacement 0 <--
-OM L1_to_L2 0 <--
-OM Other_GETX 0 <--
-OM Other_GETS 0 <--
-OM Ack 0 <--
-OM All_acks 0 <--
-OM All_acks_no_sharers 0 <--
-
-ISM Load 0 <--
-ISM Ifetch 0 <--
-ISM Store 0 <--
-ISM L2_Replacement 0 <--
-ISM L1_to_L2 0 <--
-ISM Ack 0 <--
-ISM All_acks_no_sharers 0 <--
-
-M_W Load 0 <--
-M_W Ifetch 0 <--
-M_W Store 0 <--
-M_W L2_Replacement 0 <--
-M_W L1_to_L2 0 <--
-M_W Ack 0 <--
-M_W All_acks_no_sharers 1001
-
-MM_W Load 0 <--
-MM_W Ifetch 0 <--
-MM_W Store 0 <--
-MM_W L2_Replacement 0 <--
-MM_W L1_to_L2 0 <--
-MM_W Ack 0 <--
-MM_W All_acks_no_sharers 158
-
-IS Load 0 <--
-IS Ifetch 0 <--
-IS Store 0 <--
-IS L2_Replacement 0 <--
-IS L1_to_L2 0 <--
-IS Other_GETX 0 <--
-IS Other_GETS 0 <--
-IS Ack 0 <--
-IS Shared_Ack 0 <--
-IS Data 0 <--
-IS Shared_Data 0 <--
-IS Exclusive_Data 1001
-
-SS Load 0 <--
-SS Ifetch 0 <--
-SS Store 0 <--
-SS L2_Replacement 0 <--
-SS L1_to_L2 0 <--
-SS Ack 0 <--
-SS Shared_Ack 0 <--
-SS All_acks 0 <--
-SS All_acks_no_sharers 0 <--
-
-OI Load 0 <--
-OI Ifetch 0 <--
-OI Store 0 <--
-OI L2_Replacement 0 <--
-OI L1_to_L2 0 <--
-OI Other_GETX 0 <--
-OI Other_GETS 0 <--
-OI Writeback_Ack 0 <--
-
-MI Load 24
-MI Ifetch 33
-MI Store 81
-MI L2_Replacement 0 <--
-MI L1_to_L2 0 <--
-MI Other_GETX 0 <--
-MI Other_GETS 0 <--
-MI Writeback_Ack 1143
-
-II Load 0 <--
-II Ifetch 0 <--
-II Store 0 <--
-II L2_Replacement 0 <--
-II L1_to_L2 0 <--
-II Other_GETX 0 <--
-II Other_GETS 0 <--
-II Writeback_Ack 0 <--
-II Writeback_Nack 0 <--
-
-Memory controller: system.ruby.network.topology.ext_links1.ext_node.memBuffer:
+I Load [420 ] 420
+I Ifetch [581 ] 581
+I Store [158 ] 158
+I L2_Replacement [0 ] 0
+I L1_to_L2 [0 ] 0
+I Trigger_L2_to_L1D [0 ] 0
+I Trigger_L2_to_L1I [0 ] 0
+I Other_GETX [0 ] 0
+I Other_GETS [0 ] 0
+I Other_GETS_No_Mig [0 ] 0
+I Invalidate [0 ] 0
+
+S Load [0 ] 0
+S Ifetch [0 ] 0
+S Store [0 ] 0
+S L2_Replacement [0 ] 0
+S L1_to_L2 [0 ] 0
+S Trigger_L2_to_L1D [0 ] 0
+S Trigger_L2_to_L1I [0 ] 0
+S Other_GETX [0 ] 0
+S Other_GETS [0 ] 0
+S Other_GETS_No_Mig [0 ] 0
+S Invalidate [0 ] 0
+
+O Load [0 ] 0
+O Ifetch [0 ] 0
+O Store [0 ] 0
+O L2_Replacement [0 ] 0
+O L1_to_L2 [0 ] 0
+O Trigger_L2_to_L1D [0 ] 0
+O Trigger_L2_to_L1I [0 ] 0
+O Other_GETX [0 ] 0
+O Other_GETS [0 ] 0
+O Merged_GETS [0 ] 0
+O Other_GETS_No_Mig [0 ] 0
+O Invalidate [0 ] 0
+
+M Load [368 ] 368
+M Ifetch [5833 ] 5833
+M Store [66 ] 66
+M L2_Replacement [923 ] 923
+M L1_to_L2 [1061 ] 1061
+M Trigger_L2_to_L1D [68 ] 68
+M Trigger_L2_to_L1I [65 ] 65
+M Other_GETX [0 ] 0
+M Other_GETS [0 ] 0
+M Merged_GETS [0 ] 0
+M Other_GETS_No_Mig [0 ] 0
+M Invalidate [0 ] 0
+
+MM Load [397 ] 397
+MM Ifetch [0 ] 0
+MM Store [641 ] 641
+MM L2_Replacement [220 ] 220
+MM L1_to_L2 [293 ] 293
+MM Trigger_L2_to_L1D [70 ] 70
+MM Trigger_L2_to_L1I [0 ] 0
+MM Other_GETX [0 ] 0
+MM Other_GETS [0 ] 0
+MM Merged_GETS [0 ] 0
+MM Other_GETS_No_Mig [0 ] 0
+MM Invalidate [0 ] 0
+
+IM Load [0 ] 0
+IM Ifetch [0 ] 0
+IM Store [0 ] 0
+IM L2_Replacement [0 ] 0
+IM L1_to_L2 [0 ] 0
+IM Other_GETX [0 ] 0
+IM Other_GETS [0 ] 0
+IM Other_GETS_No_Mig [0 ] 0
+IM Invalidate [0 ] 0
+IM Ack [0 ] 0
+IM Data [0 ] 0
+IM Exclusive_Data [158 ] 158
+
+SM Load [0 ] 0
+SM Ifetch [0 ] 0
+SM Store [0 ] 0
+SM L2_Replacement [0 ] 0
+SM L1_to_L2 [0 ] 0
+SM Other_GETX [0 ] 0
+SM Other_GETS [0 ] 0
+SM Other_GETS_No_Mig [0 ] 0
+SM Invalidate [0 ] 0
+SM Ack [0 ] 0
+SM Data [0 ] 0
+
+OM Load [0 ] 0
+OM Ifetch [0 ] 0
+OM Store [0 ] 0
+OM L2_Replacement [0 ] 0
+OM L1_to_L2 [0 ] 0
+OM Other_GETX [0 ] 0
+OM Other_GETS [0 ] 0
+OM Merged_GETS [0 ] 0
+OM Other_GETS_No_Mig [0 ] 0
+OM Invalidate [0 ] 0
+OM Ack [0 ] 0
+OM All_acks [0 ] 0
+OM All_acks_no_sharers [0 ] 0
+
+ISM Load [0 ] 0
+ISM Ifetch [0 ] 0
+ISM Store [0 ] 0
+ISM L2_Replacement [0 ] 0
+ISM L1_to_L2 [0 ] 0
+ISM Ack [0 ] 0
+ISM All_acks_no_sharers [0 ] 0
+
+M_W Load [0 ] 0
+M_W Ifetch [0 ] 0
+M_W Store [0 ] 0
+M_W L2_Replacement [0 ] 0
+M_W L1_to_L2 [0 ] 0
+M_W Ack [0 ] 0
+M_W All_acks_no_sharers [1001 ] 1001
+
+MM_W Load [0 ] 0
+MM_W Ifetch [0 ] 0
+MM_W Store [0 ] 0
+MM_W L2_Replacement [0 ] 0
+MM_W L1_to_L2 [0 ] 0
+MM_W Ack [0 ] 0
+MM_W All_acks_no_sharers [158 ] 158
+
+IS Load [0 ] 0
+IS Ifetch [0 ] 0
+IS Store [0 ] 0
+IS L2_Replacement [0 ] 0
+IS L1_to_L2 [0 ] 0
+IS Other_GETX [0 ] 0
+IS Other_GETS [0 ] 0
+IS Other_GETS_No_Mig [0 ] 0
+IS Invalidate [0 ] 0
+IS Ack [0 ] 0
+IS Shared_Ack [0 ] 0
+IS Data [0 ] 0
+IS Shared_Data [0 ] 0
+IS Exclusive_Data [1001 ] 1001
+
+SS Load [0 ] 0
+SS Ifetch [0 ] 0
+SS Store [0 ] 0
+SS L2_Replacement [0 ] 0
+SS L1_to_L2 [0 ] 0
+SS Ack [0 ] 0
+SS Shared_Ack [0 ] 0
+SS All_acks [0 ] 0
+SS All_acks_no_sharers [0 ] 0
+
+OI Load [0 ] 0
+OI Ifetch [0 ] 0
+OI Store [0 ] 0
+OI L2_Replacement [0 ] 0
+OI L1_to_L2 [0 ] 0
+OI Other_GETX [0 ] 0
+OI Other_GETS [0 ] 0
+OI Merged_GETS [0 ] 0
+OI Other_GETS_No_Mig [0 ] 0
+OI Invalidate [0 ] 0
+OI Writeback_Ack [0 ] 0
+
+MI Load [16 ] 16
+MI Ifetch [22 ] 22
+MI Store [54 ] 54
+MI L2_Replacement [0 ] 0
+MI L1_to_L2 [0 ] 0
+MI Other_GETX [0 ] 0
+MI Other_GETS [0 ] 0
+MI Merged_GETS [0 ] 0
+MI Other_GETS_No_Mig [0 ] 0
+MI Invalidate [0 ] 0
+MI Writeback_Ack [1143 ] 1143
+
+II Load [0 ] 0
+II Ifetch [0 ] 0
+II Store [0 ] 0
+II L2_Replacement [0 ] 0
+II L1_to_L2 [0 ] 0
+II Other_GETX [0 ] 0
+II Other_GETS [0 ] 0
+II Other_GETS_No_Mig [0 ] 0
+II Invalidate [0 ] 0
+II Writeback_Ack [0 ] 0
+II Writeback_Nack [0 ] 0
+
+IT Load [0 ] 0
+IT Ifetch [0 ] 0
+IT Store [0 ] 0
+IT L2_Replacement [0 ] 0
+IT L1_to_L2 [0 ] 0
+IT Complete_L2_to_L1 [0 ] 0
+IT Other_GETX [0 ] 0
+IT Other_GETS [0 ] 0
+IT Merged_GETS [0 ] 0
+IT Other_GETS_No_Mig [0 ] 0
+IT Invalidate [0 ] 0
+
+ST Load [0 ] 0
+ST Ifetch [0 ] 0
+ST Store [0 ] 0
+ST L2_Replacement [0 ] 0
+ST L1_to_L2 [0 ] 0
+ST Complete_L2_to_L1 [0 ] 0
+ST Other_GETX [0 ] 0
+ST Other_GETS [0 ] 0
+ST Merged_GETS [0 ] 0
+ST Other_GETS_No_Mig [0 ] 0
+ST Invalidate [0 ] 0
+
+OT Load [0 ] 0
+OT Ifetch [0 ] 0
+OT Store [0 ] 0
+OT L2_Replacement [0 ] 0
+OT L1_to_L2 [0 ] 0
+OT Complete_L2_to_L1 [0 ] 0
+OT Other_GETX [0 ] 0
+OT Other_GETS [0 ] 0
+OT Merged_GETS [0 ] 0
+OT Other_GETS_No_Mig [0 ] 0
+OT Invalidate [0 ] 0
+
+MT Load [0 ] 0
+MT Ifetch [0 ] 0
+MT Store [0 ] 0
+MT L2_Replacement [0 ] 0
+MT L1_to_L2 [0 ] 0
+MT Complete_L2_to_L1 [133 ] 133
+MT Other_GETX [0 ] 0
+MT Other_GETS [0 ] 0
+MT Merged_GETS [0 ] 0
+MT Other_GETS_No_Mig [0 ] 0
+MT Invalidate [0 ] 0
+
+MMT Load [0 ] 0
+MMT Ifetch [0 ] 0
+MMT Store [0 ] 0
+MMT L2_Replacement [0 ] 0
+MMT L1_to_L2 [0 ] 0
+MMT Complete_L2_to_L1 [70 ] 70
+MMT Other_GETX [0 ] 0
+MMT Other_GETS [0 ] 0
+MMT Merged_GETS [0 ] 0
+MMT Other_GETS_No_Mig [0 ] 0
+MMT Invalidate [0 ] 0
+
+Cache Stats: system.dir_cntrl0.probeFilter
+ system.dir_cntrl0.probeFilter_total_misses: 0
+ system.dir_cntrl0.probeFilter_total_demand_misses: 0
+ system.dir_cntrl0.probeFilter_total_prefetches: 0
+ system.dir_cntrl0.probeFilter_total_sw_prefetches: 0
+ system.dir_cntrl0.probeFilter_total_hw_prefetches: 0
+
+
+Memory controller: system.dir_cntrl0.memBuffer:
memory_total_requests: 1379
memory_reads: 1159
memory_writes: 220
- memory_refreshes: 449
- memory_total_request_delays: 342
- memory_delays_per_request: 0.248006
- memory_delays_in_input_queue: 1
+ memory_refreshes: 434
+ memory_total_request_delays: 471
+ memory_delays_per_request: 0.341552
+ memory_delays_in_input_queue: 15
memory_delays_behind_head_of_bank_queue: 0
- memory_delays_stalled_at_head_of_bank_queue: 341
- memory_stalls_for_bank_busy: 167
+ memory_delays_stalled_at_head_of_bank_queue: 456
+ memory_stalls_for_bank_busy: 86
memory_stalls_for_random_busy: 0
memory_stalls_for_anti_starvation: 0
- memory_stalls_for_arbitration: 19
- memory_stalls_for_bus: 57
+ memory_stalls_for_arbitration: 30
+ memory_stalls_for_bus: 78
memory_stalls_for_tfaw: 0
- memory_stalls_for_read_write_turnaround: 98
+ memory_stalls_for_read_write_turnaround: 262
memory_stalls_for_read_read_turnaround: 0
accesses_per_bank: 75 17 45 40 54 101 33 16 20 22 32 34 53 50 39 31 39 22 21 27 28 38 81 22 31 23 32 72 89 126 14 52
- --- Directory 0 ---
+ --- Directory ---
- Event Counts -
-GETX 519
-GETS 1114
-PUT 1143
-Unblock 1159
-Writeback_Clean 0
-Writeback_Dirty 0
-Writeback_Exclusive_Clean 923
-Writeback_Exclusive_Dirty 220
-DMA_READ 0
-DMA_WRITE 0
-Memory_Data 1159
-Memory_Ack 220
-Ack 0
-Shared_Ack 0
-Shared_Data 0
-Exclusive_Data 0
-All_acks_and_data 0
-All_acks_and_data_no_sharers 0
+GETX [189 ] 189
+GETS [1027 ] 1027
+PUT [1143 ] 1143
+Unblock [0 ] 0
+UnblockS [0 ] 0
+UnblockM [1159 ] 1159
+Writeback_Clean [0 ] 0
+Writeback_Dirty [0 ] 0
+Writeback_Exclusive_Clean [923 ] 923
+Writeback_Exclusive_Dirty [220 ] 220
+Pf_Replacement [0 ] 0
+DMA_READ [0 ] 0
+DMA_WRITE [0 ] 0
+Memory_Data [1159 ] 1159
+Memory_Ack [220 ] 220
+Ack [0 ] 0
+Shared_Ack [0 ] 0
+Shared_Data [0 ] 0
+Data [0 ] 0
+Exclusive_Data [0 ] 0
+All_acks_and_shared_data [0 ] 0
+All_acks_and_owner_data [0 ] 0
+All_acks_and_data_no_sharers [0 ] 0
+All_Unblocks [0 ] 0
- Transitions -
-NO GETX 0 <--
-NO GETS 0 <--
-NO PUT 1143
-NO DMA_READ 0 <--
-NO DMA_WRITE 0 <--
-
-O GETX 0 <--
-O GETS 0 <--
-O PUT 0 <--
-O DMA_READ 0 <--
-O DMA_WRITE 0 <--
-
-E GETX 158
-E GETS 1001
-E PUT 0 <--
-E DMA_READ 0 <--
-E DMA_WRITE 0 <--
-
-NO_B GETX 0 <--
-NO_B GETS 0 <--
-NO_B PUT 0 <--
-NO_B Unblock 1159
-NO_B DMA_READ 0 <--
-NO_B DMA_WRITE 0 <--
-
-O_B GETX 0 <--
-O_B GETS 0 <--
-O_B PUT 0 <--
-O_B Unblock 0 <--
-O_B DMA_READ 0 <--
-O_B DMA_WRITE 0 <--
-
-NO_B_W GETX 0 <--
-NO_B_W GETS 0 <--
-NO_B_W PUT 0 <--
-NO_B_W Unblock 0 <--
-NO_B_W DMA_READ 0 <--
-NO_B_W DMA_WRITE 0 <--
-NO_B_W Memory_Data 1159
-
-O_B_W GETX 0 <--
-O_B_W GETS 0 <--
-O_B_W PUT 0 <--
-O_B_W Unblock 0 <--
-O_B_W DMA_READ 0 <--
-O_B_W DMA_WRITE 0 <--
-O_B_W Memory_Data 0 <--
-
-NO_W GETX 0 <--
-NO_W GETS 0 <--
-NO_W PUT 0 <--
-NO_W DMA_READ 0 <--
-NO_W DMA_WRITE 0 <--
-NO_W Memory_Data 0 <--
-
-O_W GETX 0 <--
-O_W GETS 0 <--
-O_W PUT 0 <--
-O_W DMA_READ 0 <--
-O_W DMA_WRITE 0 <--
-O_W Memory_Data 0 <--
-
-NO_DW_B_W GETX 0 <--
-NO_DW_B_W GETS 0 <--
-NO_DW_B_W PUT 0 <--
-NO_DW_B_W DMA_READ 0 <--
-NO_DW_B_W DMA_WRITE 0 <--
-NO_DW_B_W Ack 0 <--
-NO_DW_B_W Exclusive_Data 0 <--
-NO_DW_B_W All_acks_and_data_no_sharers 0 <--
-
-NO_DR_B_W GETX 0 <--
-NO_DR_B_W GETS 0 <--
-NO_DR_B_W PUT 0 <--
-NO_DR_B_W DMA_READ 0 <--
-NO_DR_B_W DMA_WRITE 0 <--
-NO_DR_B_W Memory_Data 0 <--
-NO_DR_B_W Ack 0 <--
-NO_DR_B_W Shared_Ack 0 <--
-NO_DR_B_W Shared_Data 0 <--
-NO_DR_B_W Exclusive_Data 0 <--
-
-NO_DR_B_D GETX 0 <--
-NO_DR_B_D GETS 0 <--
-NO_DR_B_D PUT 0 <--
-NO_DR_B_D DMA_READ 0 <--
-NO_DR_B_D DMA_WRITE 0 <--
-NO_DR_B_D Ack 0 <--
-NO_DR_B_D Shared_Ack 0 <--
-NO_DR_B_D Shared_Data 0 <--
-NO_DR_B_D Exclusive_Data 0 <--
-NO_DR_B_D All_acks_and_data 0 <--
-NO_DR_B_D All_acks_and_data_no_sharers 0 <--
-
-NO_DR_B GETX 0 <--
-NO_DR_B GETS 0 <--
-NO_DR_B PUT 0 <--
-NO_DR_B DMA_READ 0 <--
-NO_DR_B DMA_WRITE 0 <--
-NO_DR_B Ack 0 <--
-NO_DR_B Shared_Ack 0 <--
-NO_DR_B Shared_Data 0 <--
-NO_DR_B Exclusive_Data 0 <--
-NO_DR_B All_acks_and_data 0 <--
-NO_DR_B All_acks_and_data_no_sharers 0 <--
-
-NO_DW_W GETX 0 <--
-NO_DW_W GETS 0 <--
-NO_DW_W PUT 0 <--
-NO_DW_W DMA_READ 0 <--
-NO_DW_W DMA_WRITE 0 <--
-NO_DW_W Memory_Ack 0 <--
-
-O_DR_B_W GETX 0 <--
-O_DR_B_W GETS 0 <--
-O_DR_B_W PUT 0 <--
-O_DR_B_W DMA_READ 0 <--
-O_DR_B_W DMA_WRITE 0 <--
-O_DR_B_W Memory_Data 0 <--
-
-O_DR_B GETX 0 <--
-O_DR_B GETS 0 <--
-O_DR_B PUT 0 <--
-O_DR_B DMA_READ 0 <--
-O_DR_B DMA_WRITE 0 <--
-O_DR_B Ack 0 <--
-O_DR_B All_acks_and_data_no_sharers 0 <--
-
-WB GETX 27
-WB GETS 20
-WB PUT 0 <--
-WB Unblock 0 <--
-WB Writeback_Clean 0 <--
-WB Writeback_Dirty 0 <--
-WB Writeback_Exclusive_Clean 923
-WB Writeback_Exclusive_Dirty 220
-WB DMA_READ 0 <--
-WB DMA_WRITE 0 <--
-
-WB_O_W GETX 0 <--
-WB_O_W GETS 0 <--
-WB_O_W PUT 0 <--
-WB_O_W DMA_READ 0 <--
-WB_O_W DMA_WRITE 0 <--
-WB_O_W Memory_Ack 0 <--
-
-WB_E_W GETX 334
-WB_E_W GETS 93
-WB_E_W PUT 0 <--
-WB_E_W DMA_READ 0 <--
-WB_E_W DMA_WRITE 0 <--
-WB_E_W Memory_Ack 220
-
+NX GETX [0 ] 0
+NX GETS [0 ] 0
+NX PUT [0 ] 0
+NX Pf_Replacement [0 ] 0
+NX DMA_READ [0 ] 0
+NX DMA_WRITE [0 ] 0
+
+NO GETX [0 ] 0
+NO GETS [0 ] 0
+NO PUT [1143 ] 1143
+NO Pf_Replacement [0 ] 0
+NO DMA_READ [0 ] 0
+NO DMA_WRITE [0 ] 0
+
+S GETX [0 ] 0
+S GETS [0 ] 0
+S PUT [0 ] 0
+S Pf_Replacement [0 ] 0
+S DMA_READ [0 ] 0
+S DMA_WRITE [0 ] 0
+
+O GETX [0 ] 0
+O GETS [0 ] 0
+O PUT [0 ] 0
+O Pf_Replacement [0 ] 0
+O DMA_READ [0 ] 0
+O DMA_WRITE [0 ] 0
+
+E GETX [158 ] 158
+E GETS [1001 ] 1001
+E PUT [0 ] 0
+E DMA_READ [0 ] 0
+E DMA_WRITE [0 ] 0
+
+O_R GETX [0 ] 0
+O_R GETS [0 ] 0
+O_R PUT [0 ] 0
+O_R Pf_Replacement [0 ] 0
+O_R DMA_READ [0 ] 0
+O_R DMA_WRITE [0 ] 0
+O_R Ack [0 ] 0
+O_R All_acks_and_data_no_sharers [0 ] 0
+
+S_R GETX [0 ] 0
+S_R GETS [0 ] 0
+S_R PUT [0 ] 0
+S_R Pf_Replacement [0 ] 0
+S_R DMA_READ [0 ] 0
+S_R DMA_WRITE [0 ] 0
+S_R Ack [0 ] 0
+S_R Data [0 ] 0
+S_R All_acks_and_data_no_sharers [0 ] 0
+
+NO_R GETX [0 ] 0
+NO_R GETS [0 ] 0
+NO_R PUT [0 ] 0
+NO_R Pf_Replacement [0 ] 0
+NO_R DMA_READ [0 ] 0
+NO_R DMA_WRITE [0 ] 0
+NO_R Ack [0 ] 0
+NO_R Data [0 ] 0
+NO_R Exclusive_Data [0 ] 0
+NO_R All_acks_and_data_no_sharers [0 ] 0
+
+NO_B GETX [0 ] 0
+NO_B GETS [0 ] 0
+NO_B PUT [0 ] 0
+NO_B UnblockS [0 ] 0
+NO_B UnblockM [1159 ] 1159
+NO_B Pf_Replacement [0 ] 0
+NO_B DMA_READ [0 ] 0
+NO_B DMA_WRITE [0 ] 0
+
+NO_B_X GETX [0 ] 0
+NO_B_X GETS [0 ] 0
+NO_B_X PUT [0 ] 0
+NO_B_X UnblockS [0 ] 0
+NO_B_X UnblockM [0 ] 0
+NO_B_X Pf_Replacement [0 ] 0
+
+NO_B_S GETX [0 ] 0
+NO_B_S GETS [0 ] 0
+NO_B_S PUT [0 ] 0
+NO_B_S UnblockS [0 ] 0
+NO_B_S UnblockM [0 ] 0
+NO_B_S Pf_Replacement [0 ] 0
+NO_B_S DMA_READ [0 ] 0
+NO_B_S DMA_WRITE [0 ] 0
+
+NO_B_S_W GETX [0 ] 0
+NO_B_S_W GETS [0 ] 0
+NO_B_S_W PUT [0 ] 0
+NO_B_S_W UnblockS [0 ] 0
+NO_B_S_W Pf_Replacement [0 ] 0
+NO_B_S_W DMA_READ [0 ] 0
+NO_B_S_W DMA_WRITE [0 ] 0
+NO_B_S_W All_Unblocks [0 ] 0
+
+O_B GETX [0 ] 0
+O_B GETS [0 ] 0
+O_B PUT [0 ] 0
+O_B UnblockS [0 ] 0
+O_B Pf_Replacement [0 ] 0
+O_B DMA_READ [0 ] 0
+O_B DMA_WRITE [0 ] 0
+
+NO_B_W GETX [0 ] 0
+NO_B_W GETS [0 ] 0
+NO_B_W PUT [0 ] 0
+NO_B_W UnblockS [0 ] 0
+NO_B_W UnblockM [0 ] 0
+NO_B_W Pf_Replacement [0 ] 0
+NO_B_W DMA_READ [0 ] 0
+NO_B_W DMA_WRITE [0 ] 0
+NO_B_W Memory_Data [1159 ] 1159
+
+O_B_W GETX [0 ] 0
+O_B_W GETS [0 ] 0
+O_B_W PUT [0 ] 0
+O_B_W UnblockS [0 ] 0
+O_B_W Pf_Replacement [0 ] 0
+O_B_W DMA_READ [0 ] 0
+O_B_W DMA_WRITE [0 ] 0
+O_B_W Memory_Data [0 ] 0
+
+NO_W GETX [0 ] 0
+NO_W GETS [0 ] 0
+NO_W PUT [0 ] 0
+NO_W Pf_Replacement [0 ] 0
+NO_W DMA_READ [0 ] 0
+NO_W DMA_WRITE [0 ] 0
+NO_W Memory_Data [0 ] 0
+
+O_W GETX [0 ] 0
+O_W GETS [0 ] 0
+O_W PUT [0 ] 0
+O_W Pf_Replacement [0 ] 0
+O_W DMA_READ [0 ] 0
+O_W DMA_WRITE [0 ] 0
+O_W Memory_Data [0 ] 0
+
+NO_DW_B_W GETX [0 ] 0
+NO_DW_B_W GETS [0 ] 0
+NO_DW_B_W PUT [0 ] 0
+NO_DW_B_W Pf_Replacement [0 ] 0
+NO_DW_B_W DMA_READ [0 ] 0
+NO_DW_B_W DMA_WRITE [0 ] 0
+NO_DW_B_W Ack [0 ] 0
+NO_DW_B_W Data [0 ] 0
+NO_DW_B_W Exclusive_Data [0 ] 0
+NO_DW_B_W All_acks_and_data_no_sharers [0 ] 0
+
+NO_DR_B_W GETX [0 ] 0
+NO_DR_B_W GETS [0 ] 0
+NO_DR_B_W PUT [0 ] 0
+NO_DR_B_W Pf_Replacement [0 ] 0
+NO_DR_B_W DMA_READ [0 ] 0
+NO_DR_B_W DMA_WRITE [0 ] 0
+NO_DR_B_W Memory_Data [0 ] 0
+NO_DR_B_W Ack [0 ] 0
+NO_DR_B_W Shared_Ack [0 ] 0
+NO_DR_B_W Shared_Data [0 ] 0
+NO_DR_B_W Data [0 ] 0
+NO_DR_B_W Exclusive_Data [0 ] 0
+
+NO_DR_B_D GETX [0 ] 0
+NO_DR_B_D GETS [0 ] 0
+NO_DR_B_D PUT [0 ] 0
+NO_DR_B_D Pf_Replacement [0 ] 0
+NO_DR_B_D DMA_READ [0 ] 0
+NO_DR_B_D DMA_WRITE [0 ] 0
+NO_DR_B_D Ack [0 ] 0
+NO_DR_B_D Shared_Ack [0 ] 0
+NO_DR_B_D Shared_Data [0 ] 0
+NO_DR_B_D Data [0 ] 0
+NO_DR_B_D Exclusive_Data [0 ] 0
+NO_DR_B_D All_acks_and_shared_data [0 ] 0
+NO_DR_B_D All_acks_and_owner_data [0 ] 0
+NO_DR_B_D All_acks_and_data_no_sharers [0 ] 0
+
+NO_DR_B GETX [0 ] 0
+NO_DR_B GETS [0 ] 0
+NO_DR_B PUT [0 ] 0
+NO_DR_B Pf_Replacement [0 ] 0
+NO_DR_B DMA_READ [0 ] 0
+NO_DR_B DMA_WRITE [0 ] 0
+NO_DR_B Ack [0 ] 0
+NO_DR_B Shared_Ack [0 ] 0
+NO_DR_B Shared_Data [0 ] 0
+NO_DR_B Data [0 ] 0
+NO_DR_B Exclusive_Data [0 ] 0
+NO_DR_B All_acks_and_shared_data [0 ] 0
+NO_DR_B All_acks_and_owner_data [0 ] 0
+NO_DR_B All_acks_and_data_no_sharers [0 ] 0
+
+NO_DW_W GETX [0 ] 0
+NO_DW_W GETS [0 ] 0
+NO_DW_W PUT [0 ] 0
+NO_DW_W Pf_Replacement [0 ] 0
+NO_DW_W DMA_READ [0 ] 0
+NO_DW_W DMA_WRITE [0 ] 0
+NO_DW_W Memory_Ack [0 ] 0
+
+O_DR_B_W GETX [0 ] 0
+O_DR_B_W GETS [0 ] 0
+O_DR_B_W PUT [0 ] 0
+O_DR_B_W Pf_Replacement [0 ] 0
+O_DR_B_W DMA_READ [0 ] 0
+O_DR_B_W DMA_WRITE [0 ] 0
+O_DR_B_W Memory_Data [0 ] 0
+O_DR_B_W Ack [0 ] 0
+O_DR_B_W Shared_Ack [0 ] 0
+
+O_DR_B GETX [0 ] 0
+O_DR_B GETS [0 ] 0
+O_DR_B PUT [0 ] 0
+O_DR_B Pf_Replacement [0 ] 0
+O_DR_B DMA_READ [0 ] 0
+O_DR_B DMA_WRITE [0 ] 0
+O_DR_B Ack [0 ] 0
+O_DR_B Shared_Ack [0 ] 0
+O_DR_B All_acks_and_owner_data [0 ] 0
+O_DR_B All_acks_and_data_no_sharers [0 ] 0
+
+WB GETX [27 ] 27
+WB GETS [19 ] 19
+WB PUT [0 ] 0
+WB Unblock [0 ] 0
+WB Writeback_Clean [0 ] 0
+WB Writeback_Dirty [0 ] 0
+WB Writeback_Exclusive_Clean [923 ] 923
+WB Writeback_Exclusive_Dirty [220 ] 220
+WB Pf_Replacement [0 ] 0
+WB DMA_READ [0 ] 0
+WB DMA_WRITE [0 ] 0
+
+WB_O_W GETX [0 ] 0
+WB_O_W GETS [0 ] 0
+WB_O_W PUT [0 ] 0
+WB_O_W Pf_Replacement [0 ] 0
+WB_O_W DMA_READ [0 ] 0
+WB_O_W DMA_WRITE [0 ] 0
+WB_O_W Memory_Ack [0 ] 0
+
+WB_E_W GETX [4 ] 4
+WB_E_W GETS [7 ] 7
+WB_E_W PUT [0 ] 0
+WB_E_W Pf_Replacement [0 ] 0
+WB_E_W DMA_READ [0 ] 0
+WB_E_W DMA_WRITE [0 ] 0
+WB_E_W Memory_Ack \ No newline at end of file
diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/simout b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/simout
index 8dfe8bf7b..01467c4b7 100755
--- a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/simout
+++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/simout
@@ -1,3 +1,5 @@
+Redirecting stdout to build/ALPHA_SE_MOESI_hammer/tests/fast/quick/00.hello/alpha/linux/simple-timing-ruby-MOESI_hammer/simout
+Redirecting stderr to build/ALPHA_SE_MOESI_hammer/tests/fast/quick/00.hello/alpha/linux/simple-timing-ruby-MOESI_hammer/simerr
M5 Simulator System
Copyright (c) 2001-2008
@@ -5,13 +7,13 @@ The Regents of The University of Michigan
All Rights Reserved
-M5 compiled Jan 28 2010 11:30:01
-M5 revision 6068d4fc30d3+ 6931+ default qtip tip brad/rubycfg_regress_udpate
-M5 started Jan 28 2010 11:55:11
-M5 executing on svvint06
+M5 compiled Aug 5 2010 11:09:13
+M5 revision c5f5b5533e96 7536 default qtip tip brad/regress_updates
+M5 started Aug 5 2010 11:09:30
+M5 executing on SC2B0617
command line: build/ALPHA_SE_MOESI_hammer/m5.fast -d build/ALPHA_SE_MOESI_hammer/tests/fast/quick/00.hello/alpha/linux/simple-timing-ruby-MOESI_hammer -re tests/run.py build/ALPHA_SE_MOESI_hammer/tests/fast/quick/00.hello/alpha/linux/simple-timing-ruby-MOESI_hammer
Global frequency set at 1000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
Hello world!
-Exiting @ tick 215528 because target called exit()
+Exiting @ tick 207970 because target called exit()
diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/stats.txt b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/stats.txt
index 67cd72f19..8112f9791 100644
--- a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/stats.txt
+++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/stats.txt
@@ -1,13 +1,13 @@
---------- Begin Simulation Statistics ----------
-host_inst_rate 45742 # Simulator instruction rate (inst/s)
-host_mem_usage 213100 # Number of bytes of host memory used
-host_seconds 0.14 # Real time elapsed on the host
-host_tick_rate 1539442 # Simulator tick rate (ticks/s)
+host_inst_rate 31390 # Simulator instruction rate (inst/s)
+host_mem_usage 211076 # Number of bytes of host memory used
+host_seconds 0.20 # Real time elapsed on the host
+host_tick_rate 1018487 # Simulator tick rate (ticks/s)
sim_freq 1000000000 # Frequency of simulated ticks
sim_insts 6404 # Number of instructions simulated
-sim_seconds 0.000216 # Number of seconds simulated
-sim_ticks 215528 # Number of ticks simulated
+sim_seconds 0.000208 # Number of seconds simulated
+sim_ticks 207970 # Number of ticks simulated
system.cpu.dtb.data_accesses 2060 # DTB accesses
system.cpu.dtb.data_acv 0 # DTB access violations
system.cpu.dtb.data_hits 2050 # DTB hits
@@ -42,7 +42,7 @@ system.cpu.itb.write_acv 0 # DT
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
-system.cpu.numCycles 215528 # number of cpu cycles simulated
+system.cpu.numCycles 207970 # number of cpu cycles simulated
system.cpu.num_insts 6404 # Number of instructions executed
system.cpu.num_refs 2060 # Number of memory references
system.cpu.workload.PROG:num_syscalls 17 # Number of system calls
diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/config.ini b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/config.ini
index 401021812..1a58721d4 100644
--- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/config.ini
+++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/config.ini
@@ -5,7 +5,7 @@ dummy=0
[system]
type=System
-children=cpu physmem ruby
+children=cpu dir_cntrl0 l1_cntrl0 l2_cntrl0 physmem ruby
mem_mode=timing
physmem=system.physmem
@@ -32,8 +32,8 @@ progress_interval=0
system=system
tracer=system.cpu.tracer
workload=system.cpu.workload
-dcache_port=system.ruby.network.topology.ext_links0.ext_node.sequencer.port[1]
-icache_port=system.ruby.network.topology.ext_links0.ext_node.sequencer.port[0]
+dcache_port=system.l1_cntrl0.sequencer.port[1]
+icache_port=system.l1_cntrl0.sequencer.port[0]
[system.cpu.dtb]
type=AlphaTLB
@@ -54,7 +54,7 @@ egid=100
env=
errout=cerr
euid=100
-executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/hello/bin/alpha/tru64/hello
+executable=tests/test-progs/hello/bin/alpha/tru64/hello
gid=100
input=cin
max_stack_size=67108864
@@ -65,6 +65,114 @@ simpoint=0
system=system
uid=100
+[system.dir_cntrl0]
+type=Directory_Controller
+children=directory memBuffer
+buffer_size=0
+directory=system.dir_cntrl0.directory
+directory_latency=6
+memBuffer=system.dir_cntrl0.memBuffer
+number_of_TBEs=256
+recycle_latency=10
+to_mem_ctrl_latency=1
+transitions_per_cycle=32
+version=0
+
+[system.dir_cntrl0.directory]
+type=RubyDirectoryMemory
+map_levels=4
+numa_high_bit=6
+size=134217728
+use_map=false
+version=0
+
+[system.dir_cntrl0.memBuffer]
+type=RubyMemoryControl
+bank_bit_0=8
+bank_busy_time=11
+bank_queue_size=12
+banks_per_rank=8
+basic_bus_busy_time=2
+dimm_bit_0=12
+dimms_per_channel=2
+mem_bus_cycle_multiplier=10
+mem_ctl_latency=12
+mem_fixed_delay=0
+mem_random_arbitrate=0
+rank_bit_0=11
+rank_rank_delay=1
+ranks_per_dimm=2
+read_write_delay=2
+refresh_period=1560
+tFaw=0
+version=0
+
+[system.l1_cntrl0]
+type=L1Cache_Controller
+children=sequencer
+L1DcacheMemory=system.l1_cntrl0.sequencer.dcache
+L1IcacheMemory=system.l1_cntrl0.sequencer.icache
+buffer_size=0
+l1_request_latency=2
+l1_response_latency=2
+l2_select_num_bits=0
+number_of_TBEs=256
+recycle_latency=10
+sequencer=system.l1_cntrl0.sequencer
+to_l2_latency=1
+transitions_per_cycle=32
+version=0
+
+[system.l1_cntrl0.sequencer]
+type=RubySequencer
+children=dcache icache
+dcache=system.l1_cntrl0.sequencer.dcache
+deadlock_threshold=500000
+icache=system.l1_cntrl0.sequencer.icache
+max_outstanding_requests=16
+physmem=system.physmem
+using_ruby_tester=false
+version=0
+physMemPort=system.physmem.port[0]
+port=system.cpu.icache_port system.cpu.dcache_port
+
+[system.l1_cntrl0.sequencer.dcache]
+type=RubyCache
+assoc=2
+latency=3
+replacement_policy=PSEUDO_LRU
+size=256
+start_index_bit=6
+
+[system.l1_cntrl0.sequencer.icache]
+type=RubyCache
+assoc=2
+latency=3
+replacement_policy=PSEUDO_LRU
+size=256
+start_index_bit=6
+
+[system.l2_cntrl0]
+type=L2Cache_Controller
+children=L2cacheMemory
+L2cacheMemory=system.l2_cntrl0.L2cacheMemory
+buffer_size=0
+l2_request_latency=2
+l2_response_latency=2
+number_of_TBEs=256
+recycle_latency=10
+to_l1_latency=1
+transitions_per_cycle=32
+version=0
+
+[system.l2_cntrl0.L2cacheMemory]
+type=RubyCache
+assoc=2
+latency=15
+replacement_policy=PSEUDO_LRU
+size=512
+start_index_bit=6
+
[system.physmem]
type=PhysicalMemory
file=
@@ -73,7 +181,7 @@ latency_var=0
null=false
range=0:134217727
zero=false
-port=system.ruby.network.topology.ext_links0.ext_node.sequencer.physMemPort
+port=system.l1_cntrl0.sequencer.physMemPort
[system.ruby]
type=RubySystem
@@ -83,6 +191,7 @@ clock=1
debug=system.ruby.debug
mem_size=134217728
network=system.ruby.network
+no_mem_vec=false
profiler=system.ruby.profiler
random_seed=1234
randomization=false
@@ -100,7 +209,7 @@ verbosity_string=none
[system.ruby.network]
type=SimpleNetwork
children=topology
-adaptive_routing=true
+adaptive_routing=false
buffer_size=0
control_msg_size=8
endpoint_bandwidth=10000
@@ -113,138 +222,34 @@ type=Topology
children=ext_links0 ext_links1 ext_links2 int_links0 int_links1 int_links2
ext_links=system.ruby.network.topology.ext_links0 system.ruby.network.topology.ext_links1 system.ruby.network.topology.ext_links2
int_links=system.ruby.network.topology.int_links0 system.ruby.network.topology.int_links1 system.ruby.network.topology.int_links2
+name=Crossbar
num_int_nodes=4
print_config=false
[system.ruby.network.topology.ext_links0]
type=ExtLink
-children=ext_node
bw_multiplier=64
-ext_node=system.ruby.network.topology.ext_links0.ext_node
+ext_node=system.l1_cntrl0
int_node=0
latency=1
weight=1
-[system.ruby.network.topology.ext_links0.ext_node]
-type=L1Cache_Controller
-children=sequencer
-L1DcacheMemory=system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache
-L1IcacheMemory=system.ruby.network.topology.ext_links0.ext_node.sequencer.icache
-buffer_size=0
-l1_request_latency=2
-l1_response_latency=2
-l2_select_num_bits=0
-number_of_TBEs=256
-recycle_latency=10
-sequencer=system.ruby.network.topology.ext_links0.ext_node.sequencer
-to_l2_latency=1
-transitions_per_cycle=32
-version=0
-
-[system.ruby.network.topology.ext_links0.ext_node.sequencer]
-type=RubySequencer
-children=dcache icache
-dcache=system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache
-deadlock_threshold=500000
-icache=system.ruby.network.topology.ext_links0.ext_node.sequencer.icache
-max_outstanding_requests=16
-physmem=system.physmem
-using_ruby_tester=false
-version=0
-physMemPort=system.physmem.port[0]
-port=system.cpu.icache_port system.cpu.dcache_port
-
-[system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache]
-type=RubyCache
-assoc=2
-latency=3
-replacement_policy=PSEUDO_LRU
-size=256
-
-[system.ruby.network.topology.ext_links0.ext_node.sequencer.icache]
-type=RubyCache
-assoc=2
-latency=3
-replacement_policy=PSEUDO_LRU
-size=256
-
[system.ruby.network.topology.ext_links1]
type=ExtLink
-children=ext_node
bw_multiplier=64
-ext_node=system.ruby.network.topology.ext_links1.ext_node
+ext_node=system.l2_cntrl0
int_node=1
latency=1
weight=1
-[system.ruby.network.topology.ext_links1.ext_node]
-type=L2Cache_Controller
-children=L2cacheMemory
-L2cacheMemory=system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory
-buffer_size=0
-l2_request_latency=2
-l2_response_latency=2
-number_of_TBEs=256
-recycle_latency=10
-to_l1_latency=1
-transitions_per_cycle=32
-version=0
-
-[system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory]
-type=RubyCache
-assoc=2
-latency=15
-replacement_policy=PSEUDO_LRU
-size=512
-
[system.ruby.network.topology.ext_links2]
type=ExtLink
-children=ext_node
bw_multiplier=64
-ext_node=system.ruby.network.topology.ext_links2.ext_node
+ext_node=system.dir_cntrl0
int_node=2
latency=1
weight=1
-[system.ruby.network.topology.ext_links2.ext_node]
-type=Directory_Controller
-children=directory memBuffer
-buffer_size=0
-directory=system.ruby.network.topology.ext_links2.ext_node.directory
-directory_latency=6
-memBuffer=system.ruby.network.topology.ext_links2.ext_node.memBuffer
-number_of_TBEs=256
-recycle_latency=10
-to_mem_ctrl_latency=1
-transitions_per_cycle=32
-version=0
-
-[system.ruby.network.topology.ext_links2.ext_node.directory]
-type=RubyDirectoryMemory
-size=134217728
-version=0
-
-[system.ruby.network.topology.ext_links2.ext_node.memBuffer]
-type=RubyMemoryControl
-bank_bit_0=8
-bank_busy_time=11
-bank_queue_size=12
-banks_per_rank=8
-basic_bus_busy_time=2
-dimm_bit_0=12
-dimms_per_channel=2
-mem_bus_cycle_multiplier=10
-mem_ctl_latency=12
-mem_fixed_delay=0
-mem_random_arbitrate=0
-rank_bit_0=11
-rank_rank_delay=1
-ranks_per_dimm=2
-read_write_delay=2
-refresh_period=1560
-tFaw=0
-version=0
-
[system.ruby.network.topology.int_links0]
type=IntLink
bw_multiplier=16
diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/ruby.stats b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/ruby.stats
index e13eebd85..f8968612d 100644
--- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/ruby.stats
+++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/ruby.stats
@@ -13,7 +13,7 @@ RubySystem config:
Network Configuration
---------------------
network: SIMPLE_NETWORK
-topology:
+topology: Crossbar
virtual_net_0: active, unordered
virtual_net_1: active, unordered
@@ -34,7 +34,7 @@ periodic_stats_period: 1000000
================ End RubySystem Configuration Print ================
-Real time: Jan/28/2010 13:57:45
+Real time: Aug/05/2010 10:31:34
Profiler Stats
--------------
@@ -43,31 +43,20 @@ Elapsed_time_in_minutes: 0
Elapsed_time_in_hours: 0
Elapsed_time_in_days: 0
-Virtual_time_in_seconds: 0.45
-Virtual_time_in_minutes: 0.0075
-Virtual_time_in_hours: 0.000125
-Virtual_time_in_days: 5.20833e-06
+Virtual_time_in_seconds: 0.26
+Virtual_time_in_minutes: 0.00433333
+Virtual_time_in_hours: 7.22222e-05
+Virtual_time_in_days: 3.00926e-06
Ruby_current_time: 103637
Ruby_start_time: 0
Ruby_cycles: 103637
-mbytes_resident: 33.0938
-mbytes_total: 33.1016
+mbytes_resident: 33.5703
+mbytes_total: 33.5781
resident_ratio: 1
-Total_misses: 0
-total_misses: 0 [ 0 ]
-user_misses: 0 [ 0 ]
-supervisor_misses: 0 [ 0 ]
-
-ruby_cycles_executed: 103638 [ 103638 ]
-
-transactions_started: 0 [ 0 ]
-transactions_ended: 0 [ 0 ]
-cycles_per_transaction: 0 [ 0 ]
-misses_per_transaction: 0 [ 0 ]
-
+ruby_cycles_executed: [ 103638 ]
Busy Controller Counts:
L1Cache-0:0
@@ -82,9 +71,23 @@ sequencer_requests_outstanding: [binsize: 1 max: 1 count: 3295 average: 1 |
All Non-Zero Cycle Demand Cache Accesses
----------------------------------------
miss_latency: [binsize: 2 max: 223 count: 3294 average: 30.4624 | standard deviation: 61.2716 | 0 2722 0 0 0 0 0 0 0 25 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 68 156 96 122 80 3 4 5 3 3 0 5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
-miss_latency_1: [binsize: 1 max: 181 count: 2585 average: 21.5791 | standard deviation: 52.0174 | 0 0 0 2285 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 9 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 32 0 70 0 67 0 59 0 54 0 1 1 1 0 3 0 0 0 3 ]
-miss_latency_2: [binsize: 2 max: 217 count: 415 average: 79.6169 | standard deviation: 81.8661 | 0 211 0 0 0 0 0 0 0 12 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 30 58 25 52 15 1 2 2 2 0 0 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
-miss_latency_3: [binsize: 2 max: 223 count: 294 average: 39.1837 | standard deviation: 68.3072 | 0 226 0 0 0 0 0 0 0 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 6 28 4 11 11 1 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency_IFETCH: [binsize: 1 max: 181 count: 2585 average: 21.5791 | standard deviation: 52.0174 | 0 0 0 2285 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 9 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 32 0 70 0 67 0 59 0 54 0 1 1 1 0 3 0 0 0 3 ]
+miss_latency_LD: [binsize: 2 max: 217 count: 415 average: 79.6169 | standard deviation: 81.8661 | 0 211 0 0 0 0 0 0 0 12 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 30 58 25 52 15 1 2 2 2 0 0 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency_ST: [binsize: 2 max: 223 count: 294 average: 39.1837 | standard deviation: 68.3072 | 0 226 0 0 0 0 0 0 0 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 6 28 4 11 11 1 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency_NULL: [binsize: 2 max: 223 count: 3294 average: 30.4624 | standard deviation: 61.2716 | 0 2722 0 0 0 0 0 0 0 25 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 68 156 96 122 80 3 4 5 3 3 0 5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency_wCC_issue_to_initial_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+miss_latency_wCC_initial_forward_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+miss_latency_wCC_forward_to_first_response: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+miss_latency_wCC_first_response_to_completion: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+imcomplete_wCC_Times: 0
+miss_latency_dir_issue_to_initial_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+miss_latency_dir_initial_forward_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+miss_latency_dir_forward_to_first_response: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+miss_latency_dir_first_response_to_completion: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+imcomplete_dir_Times: 0
+miss_latency_IFETCH_NULL: [binsize: 1 max: 181 count: 2585 average: 21.5791 | standard deviation: 52.0174 | 0 0 0 2285 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 9 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 32 0 70 0 67 0 59 0 54 0 1 1 1 0 3 0 0 0 3 ]
+miss_latency_LD_NULL: [binsize: 2 max: 217 count: 415 average: 79.6169 | standard deviation: 81.8661 | 0 211 0 0 0 0 0 0 0 12 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 30 58 25 52 15 1 2 2 2 0 0 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency_ST_NULL: [binsize: 2 max: 223 count: 294 average: 39.1837 | standard deviation: 68.3072 | 0 226 0 0 0 0 0 0 0 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 6 28 4 11 11 1 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
All Non-Zero Cycle SW Prefetch Requests
------------------------------------
@@ -116,8 +119,8 @@ Resource Usage
page_size: 4096
user_time: 0
system_time: 0
-page_reclaims: 7156
-page_faults: 2112
+page_reclaims: 7325
+page_faults: 2071
swaps: 0
block_inputs: 0
block_outputs: 0
@@ -125,6 +128,14 @@ block_outputs: 0
Network Stats
-------------
+total_msg_count_Control: 3357 26856
+total_msg_count_Request_Control: 1293 10344
+total_msg_count_Response_Data: 3666 263952
+total_msg_count_Response_Control: 5220 41760
+total_msg_count_Writeback_Data: 327 23544
+total_msg_count_Writeback_Control: 231 1848
+total_msgs: 14094 total_bytes: 368304
+
switch_0_inlinks: 2
switch_0_outlinks: 2
links_utilized_percent_switch_0: 0.0891754
@@ -186,352 +197,346 @@ links_utilized_percent_switch_3: 0.246791
outgoing_messages_switch_3_link_2_Response_Data: 103 7416 [ 0 103 0 0 0 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_3_link_2_Response_Control: 436 3488 [ 0 436 0 0 0 0 0 0 0 0 ] base_latency: 1
-Cache Stats: system.ruby.network.topology.ext_links0.ext_node.sequencer.icache
- system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_misses: 0
- system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_demand_misses: 0
- system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_prefetches: 0
- system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_sw_prefetches: 0
- system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_hw_prefetches: 0
- system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_misses_per_transaction: nan
+Cache Stats: system.l1_cntrl0.sequencer.icache
+ system.l1_cntrl0.sequencer.icache_total_misses: 0
+ system.l1_cntrl0.sequencer.icache_total_demand_misses: 0
+ system.l1_cntrl0.sequencer.icache_total_prefetches: 0
+ system.l1_cntrl0.sequencer.icache_total_sw_prefetches: 0
+ system.l1_cntrl0.sequencer.icache_total_hw_prefetches: 0
- system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
-Cache Stats: system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache
- system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_misses: 0
- system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_demand_misses: 0
- system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_prefetches: 0
- system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_sw_prefetches: 0
- system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_hw_prefetches: 0
- system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_misses_per_transaction: nan
+Cache Stats: system.l1_cntrl0.sequencer.dcache
+ system.l1_cntrl0.sequencer.dcache_total_misses: 0
+ system.l1_cntrl0.sequencer.dcache_total_demand_misses: 0
+ system.l1_cntrl0.sequencer.dcache_total_prefetches: 0
+ system.l1_cntrl0.sequencer.dcache_total_sw_prefetches: 0
+ system.l1_cntrl0.sequencer.dcache_total_hw_prefetches: 0
- system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
- --- L1Cache 0 ---
+ --- L1Cache ---
- Event Counts -
-Load 415
-Ifetch 2585
-Store 294
-Inv 431
-L1_Replacement 502
-Fwd_GETX 0
-Fwd_GETS 0
-Fwd_GET_INSTR 0
-Data 0
-Data_Exclusive 204
-DataS_fromL1 0
-Data_all_Acks 368
-Ack 0
-Ack_all 0
-WB_Ack 124
+Load [415 ] 415
+Ifetch [2585 ] 2585
+Store [294 ] 294
+Inv [431 ] 431
+L1_Replacement [502 ] 502
+Fwd_GETX [0 ] 0
+Fwd_GETS [0 ] 0
+Fwd_GET_INSTR [0 ] 0
+Data [0 ] 0
+Data_Exclusive [204 ] 204
+DataS_fromL1 [0 ] 0
+Data_all_Acks [368 ] 368
+Ack [0 ] 0
+Ack_all [0 ] 0
+WB_Ack [124 ] 124
- Transitions -
-NP Load 182
-NP Ifetch 270
-NP Store 58
-NP Inv 162
-NP L1_Replacement 0 <--
-
-I Load 22
-I Ifetch 30
-I Store 10
-I Inv 0 <--
-I L1_Replacement 206
-
-S Load 0 <--
-S Ifetch 2285
-S Store 0 <--
-S Inv 124
-S L1_Replacement 172
-
-E Load 140
-E Ifetch 0 <--
-E Store 41
-E Inv 83
-E L1_Replacement 79
-E Fwd_GETX 0 <--
-E Fwd_GETS 0 <--
-E Fwd_GET_INSTR 0 <--
-
-M Load 71
-M Ifetch 0 <--
-M Store 185
-M Inv 62
-M L1_Replacement 45
-M Fwd_GETX 0 <--
-M Fwd_GETS 0 <--
-M Fwd_GET_INSTR 0 <--
-
-IS Load 0 <--
-IS Ifetch 0 <--
-IS Store 0 <--
-IS Inv 0 <--
-IS L1_Replacement 0 <--
-IS Data_Exclusive 204
-IS DataS_fromL1 0 <--
-IS Data_all_Acks 300
-
-IM Load 0 <--
-IM Ifetch 0 <--
-IM Store 0 <--
-IM Inv 0 <--
-IM L1_Replacement 0 <--
-IM Data 0 <--
-IM Data_all_Acks 68
-IM Ack 0 <--
-
-SM Load 0 <--
-SM Ifetch 0 <--
-SM Store 0 <--
-SM Inv 0 <--
-SM L1_Replacement 0 <--
-SM Ack 0 <--
-SM Ack_all 0 <--
-
-IS_I Load 0 <--
-IS_I Ifetch 0 <--
-IS_I Store 0 <--
-IS_I Inv 0 <--
-IS_I L1_Replacement 0 <--
-IS_I Data_Exclusive 0 <--
-IS_I DataS_fromL1 0 <--
-IS_I Data_all_Acks 0 <--
-
-M_I Load 0 <--
-M_I Ifetch 0 <--
-M_I Store 0 <--
-M_I Inv 0 <--
-M_I L1_Replacement 0 <--
-M_I Fwd_GETX 0 <--
-M_I Fwd_GETS 0 <--
-M_I Fwd_GET_INSTR 0 <--
-M_I WB_Ack 124
-
-E_I Load 0 <--
-E_I Ifetch 0 <--
-E_I Store 0 <--
-E_I L1_Replacement 0 <--
-
-Cache Stats: system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory
- system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_total_misses: 0
- system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_total_demand_misses: 0
- system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_total_prefetches: 0
- system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_total_sw_prefetches: 0
- system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_total_hw_prefetches: 0
- system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_misses_per_transaction: nan
-
- system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
-
- --- L2Cache 0 ---
+NP Load [182 ] 182
+NP Ifetch [270 ] 270
+NP Store [58 ] 58
+NP Inv [162 ] 162
+NP L1_Replacement [0 ] 0
+
+I Load [22 ] 22
+I Ifetch [30 ] 30
+I Store [10 ] 10
+I Inv [0 ] 0
+I L1_Replacement [206 ] 206
+
+S Load [0 ] 0
+S Ifetch [2285 ] 2285
+S Store [0 ] 0
+S Inv [124 ] 124
+S L1_Replacement [172 ] 172
+
+E Load [140 ] 140
+E Ifetch [0 ] 0
+E Store [41 ] 41
+E Inv [83 ] 83
+E L1_Replacement [79 ] 79
+E Fwd_GETX [0 ] 0
+E Fwd_GETS [0 ] 0
+E Fwd_GET_INSTR [0 ] 0
+
+M Load [71 ] 71
+M Ifetch [0 ] 0
+M Store [185 ] 185
+M Inv [62 ] 62
+M L1_Replacement [45 ] 45
+M Fwd_GETX [0 ] 0
+M Fwd_GETS [0 ] 0
+M Fwd_GET_INSTR [0 ] 0
+
+IS Load [0 ] 0
+IS Ifetch [0 ] 0
+IS Store [0 ] 0
+IS Inv [0 ] 0
+IS L1_Replacement [0 ] 0
+IS Data_Exclusive [204 ] 204
+IS DataS_fromL1 [0 ] 0
+IS Data_all_Acks [300 ] 300
+
+IM Load [0 ] 0
+IM Ifetch [0 ] 0
+IM Store [0 ] 0
+IM Inv [0 ] 0
+IM L1_Replacement [0 ] 0
+IM Data [0 ] 0
+IM Data_all_Acks [68 ] 68
+IM Ack [0 ] 0
+
+SM Load [0 ] 0
+SM Ifetch [0 ] 0
+SM Store [0 ] 0
+SM Inv [0 ] 0
+SM L1_Replacement [0 ] 0
+SM Ack [0 ] 0
+SM Ack_all [0 ] 0
+
+IS_I Load [0 ] 0
+IS_I Ifetch [0 ] 0
+IS_I Store [0 ] 0
+IS_I Inv [0 ] 0
+IS_I L1_Replacement [0 ] 0
+IS_I Data_Exclusive [0 ] 0
+IS_I DataS_fromL1 [0 ] 0
+IS_I Data_all_Acks [0 ] 0
+
+M_I Load [0 ] 0
+M_I Ifetch [0 ] 0
+M_I Store [0 ] 0
+M_I Inv [0 ] 0
+M_I L1_Replacement [0 ] 0
+M_I Fwd_GETX [0 ] 0
+M_I Fwd_GETS [0 ] 0
+M_I Fwd_GET_INSTR [0 ] 0
+M_I WB_Ack [124 ] 124
+
+E_I Load [0 ] 0
+E_I Ifetch [0 ] 0
+E_I Store [0 ] 0
+E_I L1_Replacement [0 ] 0
+
+Cache Stats: system.l2_cntrl0.L2cacheMemory
+ system.l2_cntrl0.L2cacheMemory_total_misses: 0
+ system.l2_cntrl0.L2cacheMemory_total_demand_misses: 0
+ system.l2_cntrl0.L2cacheMemory_total_prefetches: 0
+ system.l2_cntrl0.L2cacheMemory_total_sw_prefetches: 0
+ system.l2_cntrl0.L2cacheMemory_total_hw_prefetches: 0
+
+
+ --- L2Cache ---
- Event Counts -
-L1_GET_INSTR 300
-L1_GETS 209
-L1_GETX 71
-L1_UPGRADE 0
-L1_PUTX 124
-L1_PUTX_old 0
-Fwd_L1_GETX 0
-Fwd_L1_GETS 0
-Fwd_L1_GET_INSTR 0
-L2_Replacement 43
-L2_Replacement_clean 496
-Mem_Data 547
-Mem_Ack 539
-WB_Data 62
-WB_Data_clean 0
-Ack 0
-Ack_all 369
-Unblock 0
-Unblock_Cancel 0
-Exclusive_Unblock 272
-MEM_Inv 0
+L1_GET_INSTR [300 ] 300
+L1_GETS [209 ] 209
+L1_GETX [71 ] 71
+L1_UPGRADE [0 ] 0
+L1_PUTX [124 ] 124
+L1_PUTX_old [0 ] 0
+Fwd_L1_GETX [0 ] 0
+Fwd_L1_GETS [0 ] 0
+Fwd_L1_GET_INSTR [0 ] 0
+L2_Replacement [43 ] 43
+L2_Replacement_clean [496 ] 496
+Mem_Data [547 ] 547
+Mem_Ack [539 ] 539
+WB_Data [62 ] 62
+WB_Data_clean [0 ] 0
+Ack [0 ] 0
+Ack_all [369 ] 369
+Unblock [0 ] 0
+Unblock_Cancel [0 ] 0
+Exclusive_Unblock [272 ] 272
+MEM_Inv [0 ] 0
- Transitions -
-NP L1_GET_INSTR 291
-NP L1_GETS 192
-NP L1_GETX 64
-NP L1_PUTX 0 <--
-NP L1_PUTX_old 0 <--
-
-SS L1_GET_INSTR 9
-SS L1_GETS 0 <--
-SS L1_GETX 0 <--
-SS L1_UPGRADE 0 <--
-SS L1_PUTX 0 <--
-SS L1_PUTX_old 0 <--
-SS L2_Replacement 0 <--
-SS L2_Replacement_clean 286
-SS MEM_Inv 0 <--
-
-M L1_GET_INSTR 0 <--
-M L1_GETS 12
-M L1_GETX 4
-M L1_PUTX 0 <--
-M L1_PUTX_old 0 <--
-M L2_Replacement 39
-M L2_Replacement_clean 69
-M MEM_Inv 0 <--
-
-MT L1_GET_INSTR 0 <--
-MT L1_GETS 0 <--
-MT L1_GETX 0 <--
-MT L1_PUTX 124
-MT L1_PUTX_old 0 <--
-MT L2_Replacement 4
-MT L2_Replacement_clean 141
-MT MEM_Inv 0 <--
-
-M_I L1_GET_INSTR 0 <--
-M_I L1_GETS 5
-M_I L1_GETX 3
-M_I L1_UPGRADE 0 <--
-M_I L1_PUTX 0 <--
-M_I L1_PUTX_old 0 <--
-M_I Mem_Ack 539
-M_I MEM_Inv 0 <--
-
-MT_I L1_GET_INSTR 0 <--
-MT_I L1_GETS 0 <--
-MT_I L1_GETX 0 <--
-MT_I L1_UPGRADE 0 <--
-MT_I L1_PUTX 0 <--
-MT_I L1_PUTX_old 0 <--
-MT_I WB_Data 2
-MT_I WB_Data_clean 0 <--
-MT_I Ack_all 2
-MT_I MEM_Inv 0 <--
-
-MCT_I L1_GET_INSTR 0 <--
-MCT_I L1_GETS 0 <--
-MCT_I L1_GETX 0 <--
-MCT_I L1_UPGRADE 0 <--
-MCT_I L1_PUTX 0 <--
-MCT_I L1_PUTX_old 0 <--
-MCT_I WB_Data 60
-MCT_I WB_Data_clean 0 <--
-MCT_I Ack_all 81
-
-I_I L1_GET_INSTR 0 <--
-I_I L1_GETS 0 <--
-I_I L1_GETX 0 <--
-I_I L1_UPGRADE 0 <--
-I_I L1_PUTX 0 <--
-I_I L1_PUTX_old 0 <--
-I_I Ack 0 <--
-I_I Ack_all 286
-
-S_I L1_GET_INSTR 0 <--
-S_I L1_GETS 0 <--
-S_I L1_GETX 0 <--
-S_I L1_UPGRADE 0 <--
-S_I L1_PUTX 0 <--
-S_I L1_PUTX_old 0 <--
-S_I Ack 0 <--
-S_I Ack_all 0 <--
-S_I MEM_Inv 0 <--
-
-ISS L1_GET_INSTR 0 <--
-ISS L1_GETS 0 <--
-ISS L1_GETX 0 <--
-ISS L1_PUTX 0 <--
-ISS L1_PUTX_old 0 <--
-ISS L2_Replacement 0 <--
-ISS L2_Replacement_clean 0 <--
-ISS Mem_Data 192
-ISS MEM_Inv 0 <--
-
-IS L1_GET_INSTR 0 <--
-IS L1_GETS 0 <--
-IS L1_GETX 0 <--
-IS L1_PUTX 0 <--
-IS L1_PUTX_old 0 <--
-IS L2_Replacement 0 <--
-IS L2_Replacement_clean 0 <--
-IS Mem_Data 291
-IS MEM_Inv 0 <--
-
-IM L1_GET_INSTR 0 <--
-IM L1_GETS 0 <--
-IM L1_GETX 0 <--
-IM L1_PUTX 0 <--
-IM L1_PUTX_old 0 <--
-IM L2_Replacement 0 <--
-IM L2_Replacement_clean 0 <--
-IM Mem_Data 64
-IM MEM_Inv 0 <--
-
-SS_MB L1_GET_INSTR 0 <--
-SS_MB L1_GETS 0 <--
-SS_MB L1_GETX 0 <--
-SS_MB L1_UPGRADE 0 <--
-SS_MB L1_PUTX 0 <--
-SS_MB L1_PUTX_old 0 <--
-SS_MB L2_Replacement 0 <--
-SS_MB L2_Replacement_clean 0 <--
-SS_MB Unblock_Cancel 0 <--
-SS_MB Exclusive_Unblock 0 <--
-SS_MB MEM_Inv 0 <--
-
-MT_MB L1_GET_INSTR 0 <--
-MT_MB L1_GETS 0 <--
-MT_MB L1_GETX 0 <--
-MT_MB L1_UPGRADE 0 <--
-MT_MB L1_PUTX 0 <--
-MT_MB L1_PUTX_old 0 <--
-MT_MB L2_Replacement 0 <--
-MT_MB L2_Replacement_clean 0 <--
-MT_MB Unblock_Cancel 0 <--
-MT_MB Exclusive_Unblock 272
-MT_MB MEM_Inv 0 <--
-
-M_MB L1_GET_INSTR 0 <--
-M_MB L1_GETS 0 <--
-M_MB L1_GETX 0 <--
-M_MB L1_UPGRADE 0 <--
-M_MB L1_PUTX 0 <--
-M_MB L1_PUTX_old 0 <--
-M_MB L2_Replacement 0 <--
-M_MB L2_Replacement_clean 0 <--
-M_MB Exclusive_Unblock 0 <--
-M_MB MEM_Inv 0 <--
-
-MT_IIB L1_GET_INSTR 0 <--
-MT_IIB L1_GETS 0 <--
-MT_IIB L1_GETX 0 <--
-MT_IIB L1_UPGRADE 0 <--
-MT_IIB L1_PUTX 0 <--
-MT_IIB L1_PUTX_old 0 <--
-MT_IIB L2_Replacement 0 <--
-MT_IIB L2_Replacement_clean 0 <--
-MT_IIB WB_Data 0 <--
-MT_IIB WB_Data_clean 0 <--
-MT_IIB Unblock 0 <--
-MT_IIB MEM_Inv 0 <--
-
-MT_IB L1_GET_INSTR 0 <--
-MT_IB L1_GETS 0 <--
-MT_IB L1_GETX 0 <--
-MT_IB L1_UPGRADE 0 <--
-MT_IB L1_PUTX 0 <--
-MT_IB L1_PUTX_old 0 <--
-MT_IB L2_Replacement 0 <--
-MT_IB L2_Replacement_clean 0 <--
-MT_IB WB_Data 0 <--
-MT_IB WB_Data_clean 0 <--
-MT_IB Unblock_Cancel 0 <--
-MT_IB MEM_Inv 0 <--
-
-MT_SB L1_GET_INSTR 0 <--
-MT_SB L1_GETS 0 <--
-MT_SB L1_GETX 0 <--
-MT_SB L1_UPGRADE 0 <--
-MT_SB L1_PUTX 0 <--
-MT_SB L1_PUTX_old 0 <--
-MT_SB L2_Replacement 0 <--
-MT_SB L2_Replacement_clean 0 <--
-MT_SB Unblock 0 <--
-MT_SB MEM_Inv 0 <--
-
-Memory controller: system.ruby.network.topology.ext_links2.ext_node.memBuffer:
+NP L1_GET_INSTR [291 ] 291
+NP L1_GETS [192 ] 192
+NP L1_GETX [64 ] 64
+NP L1_PUTX [0 ] 0
+NP L1_PUTX_old [0 ] 0
+
+SS L1_GET_INSTR [9 ] 9
+SS L1_GETS [0 ] 0
+SS L1_GETX [0 ] 0
+SS L1_UPGRADE [0 ] 0
+SS L1_PUTX [0 ] 0
+SS L1_PUTX_old [0 ] 0
+SS L2_Replacement [0 ] 0
+SS L2_Replacement_clean [286 ] 286
+SS MEM_Inv [0 ] 0
+
+M L1_GET_INSTR [0 ] 0
+M L1_GETS [12 ] 12
+M L1_GETX [4 ] 4
+M L1_PUTX [0 ] 0
+M L1_PUTX_old [0 ] 0
+M L2_Replacement [39 ] 39
+M L2_Replacement_clean [69 ] 69
+M MEM_Inv [0 ] 0
+
+MT L1_GET_INSTR [0 ] 0
+MT L1_GETS [0 ] 0
+MT L1_GETX [0 ] 0
+MT L1_PUTX [124 ] 124
+MT L1_PUTX_old [0 ] 0
+MT L2_Replacement [4 ] 4
+MT L2_Replacement_clean [141 ] 141
+MT MEM_Inv [0 ] 0
+
+M_I L1_GET_INSTR [0 ] 0
+M_I L1_GETS [5 ] 5
+M_I L1_GETX [3 ] 3
+M_I L1_UPGRADE [0 ] 0
+M_I L1_PUTX [0 ] 0
+M_I L1_PUTX_old [0 ] 0
+M_I Mem_Ack [539 ] 539
+M_I MEM_Inv [0 ] 0
+
+MT_I L1_GET_INSTR [0 ] 0
+MT_I L1_GETS [0 ] 0
+MT_I L1_GETX [0 ] 0
+MT_I L1_UPGRADE [0 ] 0
+MT_I L1_PUTX [0 ] 0
+MT_I L1_PUTX_old [0 ] 0
+MT_I WB_Data [2 ] 2
+MT_I WB_Data_clean [0 ] 0
+MT_I Ack_all [2 ] 2
+MT_I MEM_Inv [0 ] 0
+
+MCT_I L1_GET_INSTR [0 ] 0
+MCT_I L1_GETS [0 ] 0
+MCT_I L1_GETX [0 ] 0
+MCT_I L1_UPGRADE [0 ] 0
+MCT_I L1_PUTX [0 ] 0
+MCT_I L1_PUTX_old [0 ] 0
+MCT_I WB_Data [60 ] 60
+MCT_I WB_Data_clean [0 ] 0
+MCT_I Ack_all [81 ] 81
+
+I_I L1_GET_INSTR [0 ] 0
+I_I L1_GETS [0 ] 0
+I_I L1_GETX [0 ] 0
+I_I L1_UPGRADE [0 ] 0
+I_I L1_PUTX [0 ] 0
+I_I L1_PUTX_old [0 ] 0
+I_I Ack [0 ] 0
+I_I Ack_all [286 ] 286
+
+S_I L1_GET_INSTR [0 ] 0
+S_I L1_GETS [0 ] 0
+S_I L1_GETX [0 ] 0
+S_I L1_UPGRADE [0 ] 0
+S_I L1_PUTX [0 ] 0
+S_I L1_PUTX_old [0 ] 0
+S_I Ack [0 ] 0
+S_I Ack_all [0 ] 0
+S_I MEM_Inv [0 ] 0
+
+ISS L1_GET_INSTR [0 ] 0
+ISS L1_GETS [0 ] 0
+ISS L1_GETX [0 ] 0
+ISS L1_PUTX [0 ] 0
+ISS L1_PUTX_old [0 ] 0
+ISS L2_Replacement [0 ] 0
+ISS L2_Replacement_clean [0 ] 0
+ISS Mem_Data [192 ] 192
+ISS MEM_Inv [0 ] 0
+
+IS L1_GET_INSTR [0 ] 0
+IS L1_GETS [0 ] 0
+IS L1_GETX [0 ] 0
+IS L1_PUTX [0 ] 0
+IS L1_PUTX_old [0 ] 0
+IS L2_Replacement [0 ] 0
+IS L2_Replacement_clean [0 ] 0
+IS Mem_Data [291 ] 291
+IS MEM_Inv [0 ] 0
+
+IM L1_GET_INSTR [0 ] 0
+IM L1_GETS [0 ] 0
+IM L1_GETX [0 ] 0
+IM L1_PUTX [0 ] 0
+IM L1_PUTX_old [0 ] 0
+IM L2_Replacement [0 ] 0
+IM L2_Replacement_clean [0 ] 0
+IM Mem_Data [64 ] 64
+IM MEM_Inv [0 ] 0
+
+SS_MB L1_GET_INSTR [0 ] 0
+SS_MB L1_GETS [0 ] 0
+SS_MB L1_GETX [0 ] 0
+SS_MB L1_UPGRADE [0 ] 0
+SS_MB L1_PUTX [0 ] 0
+SS_MB L1_PUTX_old [0 ] 0
+SS_MB L2_Replacement [0 ] 0
+SS_MB L2_Replacement_clean [0 ] 0
+SS_MB Unblock_Cancel [0 ] 0
+SS_MB Exclusive_Unblock [0 ] 0
+SS_MB MEM_Inv [0 ] 0
+
+MT_MB L1_GET_INSTR [0 ] 0
+MT_MB L1_GETS [0 ] 0
+MT_MB L1_GETX [0 ] 0
+MT_MB L1_UPGRADE [0 ] 0
+MT_MB L1_PUTX [0 ] 0
+MT_MB L1_PUTX_old [0 ] 0
+MT_MB L2_Replacement [0 ] 0
+MT_MB L2_Replacement_clean [0 ] 0
+MT_MB Unblock_Cancel [0 ] 0
+MT_MB Exclusive_Unblock [272 ] 272
+MT_MB MEM_Inv [0 ] 0
+
+M_MB L1_GET_INSTR [0 ] 0
+M_MB L1_GETS [0 ] 0
+M_MB L1_GETX [0 ] 0
+M_MB L1_UPGRADE [0 ] 0
+M_MB L1_PUTX [0 ] 0
+M_MB L1_PUTX_old [0 ] 0
+M_MB L2_Replacement [0 ] 0
+M_MB L2_Replacement_clean [0 ] 0
+M_MB Exclusive_Unblock [0 ] 0
+M_MB MEM_Inv [0 ] 0
+
+MT_IIB L1_GET_INSTR [0 ] 0
+MT_IIB L1_GETS [0 ] 0
+MT_IIB L1_GETX [0 ] 0
+MT_IIB L1_UPGRADE [0 ] 0
+MT_IIB L1_PUTX [0 ] 0
+MT_IIB L1_PUTX_old [0 ] 0
+MT_IIB L2_Replacement [0 ] 0
+MT_IIB L2_Replacement_clean [0 ] 0
+MT_IIB WB_Data [0 ] 0
+MT_IIB WB_Data_clean [0 ] 0
+MT_IIB Unblock [0 ] 0
+MT_IIB MEM_Inv [0 ] 0
+
+MT_IB L1_GET_INSTR [0 ] 0
+MT_IB L1_GETS [0 ] 0
+MT_IB L1_GETX [0 ] 0
+MT_IB L1_UPGRADE [0 ] 0
+MT_IB L1_PUTX [0 ] 0
+MT_IB L1_PUTX_old [0 ] 0
+MT_IB L2_Replacement [0 ] 0
+MT_IB L2_Replacement_clean [0 ] 0
+MT_IB WB_Data [0 ] 0
+MT_IB WB_Data_clean [0 ] 0
+MT_IB Unblock_Cancel [0 ] 0
+MT_IB MEM_Inv [0 ] 0
+
+MT_SB L1_GET_INSTR [0 ] 0
+MT_SB L1_GETS [0 ] 0
+MT_SB L1_GETX [0 ] 0
+MT_SB L1_UPGRADE [0 ] 0
+MT_SB L1_PUTX [0 ] 0
+MT_SB L1_PUTX_old [0 ] 0
+MT_SB L2_Replacement [0 ] 0
+MT_SB L2_Replacement_clean [0 ] 0
+MT_SB Unblock [0 ] 0
+MT_SB MEM_Inv [0 ] 0
+
+Memory controller: system.dir_cntrl0.memBuffer:
memory_total_requests: 650
memory_reads: 547
memory_writes: 103
@@ -551,67 +556,66 @@ Memory controller: system.ruby.network.topology.ext_links2.ext_node.memBuffer:
memory_stalls_for_read_read_turnaround: 0
accesses_per_bank: 26 14 0 49 21 21 42 25 6 4 7 4 24 42 26 3 5 7 7 18 10 29 15 50 19 5 6 16 14 24 19 92
- --- Directory 0 ---
+ --- Directory ---
- Event Counts -
-Fetch 547
-Data 103
-Memory_Data 547
-Memory_Ack 103
-DMA_READ 0
-DMA_WRITE 0
-CleanReplacement 436
+Fetch [547 ] 547
+Data [103 ] 103
+Memory_Data [547 ] 547
+Memory_Ack [103 ] 103
+DMA_READ [0 ] 0
+DMA_WRITE [0 ] 0
+CleanReplacement [436 ] 436
- Transitions -
-I Fetch 547
-I DMA_READ 0 <--
-I DMA_WRITE 0 <--
-
-ID Fetch 0 <--
-ID Data 0 <--
-ID Memory_Data 0 <--
-ID DMA_READ 0 <--
-ID DMA_WRITE 0 <--
-
-ID_W Fetch 0 <--
-ID_W Data 0 <--
-ID_W Memory_Ack 0 <--
-ID_W DMA_READ 0 <--
-ID_W DMA_WRITE 0 <--
-
-M Data 103
-M DMA_READ 0 <--
-M DMA_WRITE 0 <--
-M CleanReplacement 436
-
-IM Fetch 0 <--
-IM Data 0 <--
-IM Memory_Data 547
-IM DMA_READ 0 <--
-IM DMA_WRITE 0 <--
-
-MI Fetch 0 <--
-MI Data 0 <--
-MI Memory_Ack 103
-MI DMA_READ 0 <--
-MI DMA_WRITE 0 <--
-
-M_DRD Data 0 <--
-M_DRD DMA_READ 0 <--
-M_DRD DMA_WRITE 0 <--
-
-M_DRDI Fetch 0 <--
-M_DRDI Data 0 <--
-M_DRDI Memory_Ack 0 <--
-M_DRDI DMA_READ 0 <--
-M_DRDI DMA_WRITE 0 <--
-
-M_DWR Data 0 <--
-M_DWR DMA_READ 0 <--
-M_DWR DMA_WRITE 0 <--
-
-M_DWRI Fetch 0 <--
-M_DWRI Data 0 <--
-M_DWRI Memory_Ack 0 <--
-M_DWRI DMA_READ 0 <--
-M_DWRI DMA_WRITE 0 <--
-
+I Fetch [547 ] 547
+I DMA_READ [0 ] 0
+I DMA_WRITE [0 ] 0
+
+ID Fetch [0 ] 0
+ID Data [0 ] 0
+ID Memory_Data [0 ] 0
+ID DMA_READ [0 ] 0
+ID DMA_WRITE [0 ] 0
+
+ID_W Fetch [0 ] 0
+ID_W Data [0 ] 0
+ID_W Memory_Ack [0 ] 0
+ID_W DMA_READ [0 ] 0
+ID_W DMA_WRITE [0 ] 0
+
+M Data [103 ] 103
+M DMA_READ [0 ] 0
+M DMA_WRITE [0 ] 0
+M CleanReplacement [436 ] 436
+
+IM Fetch [0 ] 0
+IM Data [0 ] 0
+IM Memory_Data [547 ] 547
+IM DMA_READ [0 ] 0
+IM DMA_WRITE [0 ] 0
+
+MI Fetch [0 ] 0
+MI Data [0 ] 0
+MI Memory_Ack [103 ] 103
+MI DMA_READ [0 ] 0
+MI DMA_WRITE [0 ] 0
+
+M_DRD Data [0 ] 0
+M_DRD DMA_READ [0 ] 0
+M_DRD DMA_WRITE [0 ] 0
+
+M_DRDI Fetch [0 ] 0
+M_DRDI Data [0 ] 0
+M_DRDI Memory_Ack [0 ] 0
+M_DRDI DMA_READ [0 ] 0
+M_DRDI DMA_WRITE [0 ] 0
+
+M_DWR Data [0 ] 0
+M_DWR DMA_READ [0 ] 0
+M_DWR DMA_WRITE [0 ] 0
+
+M_DWRI Fetch [0 ] 0
+M_DWRI Data [0 ] 0
+M_DWRI Memory_Ack [0 ] 0
+M_DWRI DMA_READ [0 ] 0
+M_DWRI DMA_WRITE \ No newline at end of file
diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/simout b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/simout
index b009b1ffa..243aba647 100755
--- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/simout
+++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/simout
@@ -5,10 +5,10 @@ The Regents of The University of Michigan
All Rights Reserved
-M5 compiled Jan 28 2010 13:54:58
-M5 revision 6068d4fc30d3+ 6931+ default qtip tip brad/rubycfg_regress_udpate
-M5 started Jan 28 2010 13:57:44
-M5 executing on svvint03
+M5 compiled Aug 5 2010 10:22:52
+M5 revision 1cd2a169499f+ 7535+ default brad/hammer_merge_gets qtip tip
+M5 started Aug 5 2010 10:31:34
+M5 executing on svvint09
command line: build/ALPHA_SE_MESI_CMP_directory/m5.fast -d build/ALPHA_SE_MESI_CMP_directory/tests/fast/quick/00.hello/alpha/tru64/simple-timing-ruby-MESI_CMP_directory -re tests/run.py build/ALPHA_SE_MESI_CMP_directory/tests/fast/quick/00.hello/alpha/tru64/simple-timing-ruby-MESI_CMP_directory
Global frequency set at 1000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/stats.txt b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/stats.txt
index f42778f42..dd48ee784 100644
--- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/stats.txt
+++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/stats.txt
@@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
-host_inst_rate 21475 # Simulator instruction rate (inst/s)
-host_mem_usage 214848 # Number of bytes of host memory used
-host_seconds 0.12 # Real time elapsed on the host
-host_tick_rate 863649 # Simulator tick rate (ticks/s)
+host_inst_rate 25769 # Simulator instruction rate (inst/s)
+host_mem_usage 211408 # Number of bytes of host memory used
+host_seconds 0.10 # Real time elapsed on the host
+host_tick_rate 1036329 # Simulator tick rate (ticks/s)
sim_freq 1000000000 # Frequency of simulated ticks
sim_insts 2577 # Number of instructions simulated
sim_seconds 0.000104 # Number of seconds simulated
diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/config.ini b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/config.ini
index 7f9336521..59f975e1e 100644
--- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/config.ini
+++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/config.ini
@@ -5,7 +5,7 @@ dummy=0
[system]
type=System
-children=cpu physmem ruby
+children=cpu dir_cntrl0 l1_cntrl0 l2_cntrl0 physmem ruby
mem_mode=timing
physmem=system.physmem
@@ -32,8 +32,8 @@ progress_interval=0
system=system
tracer=system.cpu.tracer
workload=system.cpu.workload
-dcache_port=system.ruby.network.topology.ext_links0.ext_node.sequencer.port[1]
-icache_port=system.ruby.network.topology.ext_links0.ext_node.sequencer.port[0]
+dcache_port=system.l1_cntrl0.sequencer.port[1]
+icache_port=system.l1_cntrl0.sequencer.port[0]
[system.cpu.dtb]
type=AlphaTLB
@@ -54,7 +54,7 @@ egid=100
env=
errout=cerr
euid=100
-executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/hello/bin/alpha/tru64/hello
+executable=tests/test-progs/hello/bin/alpha/tru64/hello
gid=100
input=cin
max_stack_size=67108864
@@ -65,6 +65,110 @@ simpoint=0
system=system
uid=100
+[system.dir_cntrl0]
+type=Directory_Controller
+children=directory memBuffer
+buffer_size=0
+directory=system.dir_cntrl0.directory
+directory_latency=6
+memBuffer=system.dir_cntrl0.memBuffer
+number_of_TBEs=256
+recycle_latency=10
+transitions_per_cycle=32
+version=0
+
+[system.dir_cntrl0.directory]
+type=RubyDirectoryMemory
+map_levels=4
+numa_high_bit=6
+size=134217728
+use_map=false
+version=0
+
+[system.dir_cntrl0.memBuffer]
+type=RubyMemoryControl
+bank_bit_0=8
+bank_busy_time=11
+bank_queue_size=12
+banks_per_rank=8
+basic_bus_busy_time=2
+dimm_bit_0=12
+dimms_per_channel=2
+mem_bus_cycle_multiplier=10
+mem_ctl_latency=12
+mem_fixed_delay=0
+mem_random_arbitrate=0
+rank_bit_0=11
+rank_rank_delay=1
+ranks_per_dimm=2
+read_write_delay=2
+refresh_period=1560
+tFaw=0
+version=0
+
+[system.l1_cntrl0]
+type=L1Cache_Controller
+children=sequencer
+L1DcacheMemory=system.l1_cntrl0.sequencer.dcache
+L1IcacheMemory=system.l1_cntrl0.sequencer.icache
+buffer_size=0
+l2_select_num_bits=0
+number_of_TBEs=256
+recycle_latency=10
+request_latency=2
+sequencer=system.l1_cntrl0.sequencer
+transitions_per_cycle=32
+version=0
+
+[system.l1_cntrl0.sequencer]
+type=RubySequencer
+children=dcache icache
+dcache=system.l1_cntrl0.sequencer.dcache
+deadlock_threshold=500000
+icache=system.l1_cntrl0.sequencer.icache
+max_outstanding_requests=16
+physmem=system.physmem
+using_ruby_tester=false
+version=0
+physMemPort=system.physmem.port[0]
+port=system.cpu.icache_port system.cpu.dcache_port
+
+[system.l1_cntrl0.sequencer.dcache]
+type=RubyCache
+assoc=2
+latency=3
+replacement_policy=PSEUDO_LRU
+size=256
+start_index_bit=6
+
+[system.l1_cntrl0.sequencer.icache]
+type=RubyCache
+assoc=2
+latency=3
+replacement_policy=PSEUDO_LRU
+size=256
+start_index_bit=6
+
+[system.l2_cntrl0]
+type=L2Cache_Controller
+children=L2cacheMemory
+L2cacheMemory=system.l2_cntrl0.L2cacheMemory
+buffer_size=0
+number_of_TBEs=256
+recycle_latency=10
+request_latency=2
+response_latency=2
+transitions_per_cycle=32
+version=0
+
+[system.l2_cntrl0.L2cacheMemory]
+type=RubyCache
+assoc=2
+latency=15
+replacement_policy=PSEUDO_LRU
+size=512
+start_index_bit=6
+
[system.physmem]
type=PhysicalMemory
file=
@@ -73,7 +177,7 @@ latency_var=0
null=false
range=0:134217727
zero=false
-port=system.ruby.network.topology.ext_links0.ext_node.sequencer.physMemPort
+port=system.l1_cntrl0.sequencer.physMemPort
[system.ruby]
type=RubySystem
@@ -83,6 +187,7 @@ clock=1
debug=system.ruby.debug
mem_size=134217728
network=system.ruby.network
+no_mem_vec=false
profiler=system.ruby.profiler
random_seed=1234
randomization=false
@@ -100,7 +205,7 @@ verbosity_string=none
[system.ruby.network]
type=SimpleNetwork
children=topology
-adaptive_routing=true
+adaptive_routing=false
buffer_size=0
control_msg_size=8
endpoint_bandwidth=10000
@@ -113,134 +218,34 @@ type=Topology
children=ext_links0 ext_links1 ext_links2 int_links0 int_links1 int_links2
ext_links=system.ruby.network.topology.ext_links0 system.ruby.network.topology.ext_links1 system.ruby.network.topology.ext_links2
int_links=system.ruby.network.topology.int_links0 system.ruby.network.topology.int_links1 system.ruby.network.topology.int_links2
+name=Crossbar
num_int_nodes=4
print_config=false
[system.ruby.network.topology.ext_links0]
type=ExtLink
-children=ext_node
bw_multiplier=64
-ext_node=system.ruby.network.topology.ext_links0.ext_node
+ext_node=system.l1_cntrl0
int_node=0
latency=1
weight=1
-[system.ruby.network.topology.ext_links0.ext_node]
-type=L1Cache_Controller
-children=sequencer
-L1DcacheMemory=system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache
-L1IcacheMemory=system.ruby.network.topology.ext_links0.ext_node.sequencer.icache
-buffer_size=0
-l2_select_num_bits=0
-number_of_TBEs=256
-recycle_latency=10
-request_latency=2
-sequencer=system.ruby.network.topology.ext_links0.ext_node.sequencer
-transitions_per_cycle=32
-version=0
-
-[system.ruby.network.topology.ext_links0.ext_node.sequencer]
-type=RubySequencer
-children=dcache icache
-dcache=system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache
-deadlock_threshold=500000
-icache=system.ruby.network.topology.ext_links0.ext_node.sequencer.icache
-max_outstanding_requests=16
-physmem=system.physmem
-using_ruby_tester=false
-version=0
-physMemPort=system.physmem.port[0]
-port=system.cpu.icache_port system.cpu.dcache_port
-
-[system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache]
-type=RubyCache
-assoc=2
-latency=3
-replacement_policy=PSEUDO_LRU
-size=256
-
-[system.ruby.network.topology.ext_links0.ext_node.sequencer.icache]
-type=RubyCache
-assoc=2
-latency=3
-replacement_policy=PSEUDO_LRU
-size=256
-
[system.ruby.network.topology.ext_links1]
type=ExtLink
-children=ext_node
bw_multiplier=64
-ext_node=system.ruby.network.topology.ext_links1.ext_node
+ext_node=system.l2_cntrl0
int_node=1
latency=1
weight=1
-[system.ruby.network.topology.ext_links1.ext_node]
-type=L2Cache_Controller
-children=L2cacheMemory
-L2cacheMemory=system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory
-buffer_size=0
-number_of_TBEs=256
-recycle_latency=10
-request_latency=2
-response_latency=2
-transitions_per_cycle=32
-version=0
-
-[system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory]
-type=RubyCache
-assoc=2
-latency=15
-replacement_policy=PSEUDO_LRU
-size=512
-
[system.ruby.network.topology.ext_links2]
type=ExtLink
-children=ext_node
bw_multiplier=64
-ext_node=system.ruby.network.topology.ext_links2.ext_node
+ext_node=system.dir_cntrl0
int_node=2
latency=1
weight=1
-[system.ruby.network.topology.ext_links2.ext_node]
-type=Directory_Controller
-children=directory memBuffer
-buffer_size=0
-directory=system.ruby.network.topology.ext_links2.ext_node.directory
-directory_latency=6
-memBuffer=system.ruby.network.topology.ext_links2.ext_node.memBuffer
-number_of_TBEs=256
-recycle_latency=10
-transitions_per_cycle=32
-version=0
-
-[system.ruby.network.topology.ext_links2.ext_node.directory]
-type=RubyDirectoryMemory
-size=134217728
-version=0
-
-[system.ruby.network.topology.ext_links2.ext_node.memBuffer]
-type=RubyMemoryControl
-bank_bit_0=8
-bank_busy_time=11
-bank_queue_size=12
-banks_per_rank=8
-basic_bus_busy_time=2
-dimm_bit_0=12
-dimms_per_channel=2
-mem_bus_cycle_multiplier=10
-mem_ctl_latency=12
-mem_fixed_delay=0
-mem_random_arbitrate=0
-rank_bit_0=11
-rank_rank_delay=1
-ranks_per_dimm=2
-read_write_delay=2
-refresh_period=1560
-tFaw=0
-version=0
-
[system.ruby.network.topology.int_links0]
type=IntLink
bw_multiplier=16
diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/ruby.stats b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/ruby.stats
index 6d22cb60b..86aa94fb6 100644
--- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/ruby.stats
+++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/ruby.stats
@@ -13,7 +13,7 @@ RubySystem config:
Network Configuration
---------------------
network: SIMPLE_NETWORK
-topology:
+topology: Crossbar
virtual_net_0: active, unordered
virtual_net_1: active, unordered
@@ -34,7 +34,7 @@ periodic_stats_period: 1000000
================ End RubySystem Configuration Print ================
-Real time: Jan/28/2010 15:08:15
+Real time: Aug/05/2010 10:37:10
Profiler Stats
--------------
@@ -43,31 +43,20 @@ Elapsed_time_in_minutes: 0
Elapsed_time_in_hours: 0
Elapsed_time_in_days: 0
-Virtual_time_in_seconds: 0.51
-Virtual_time_in_minutes: 0.0085
-Virtual_time_in_hours: 0.000141667
-Virtual_time_in_days: 5.90278e-06
+Virtual_time_in_seconds: 0.41
+Virtual_time_in_minutes: 0.00683333
+Virtual_time_in_hours: 0.000113889
+Virtual_time_in_days: 4.74537e-06
Ruby_current_time: 85988
Ruby_start_time: 0
Ruby_cycles: 85988
-mbytes_resident: 33.25
-mbytes_total: 33.2578
+mbytes_resident: 33.6484
+mbytes_total: 33.6562
resident_ratio: 1
-Total_misses: 0
-total_misses: 0 [ 0 ]
-user_misses: 0 [ 0 ]
-supervisor_misses: 0 [ 0 ]
-
-ruby_cycles_executed: 85989 [ 85989 ]
-
-transactions_started: 0 [ 0 ]
-transactions_ended: 0 [ 0 ]
-cycles_per_transaction: 0 [ 0 ]
-misses_per_transaction: 0 [ 0 ]
-
+ruby_cycles_executed: [ 85989 ]
Busy Controller Counts:
L2Cache-0:0
@@ -82,9 +71,23 @@ sequencer_requests_outstanding: [binsize: 1 max: 1 count: 3295 average: 1 |
All Non-Zero Cycle Demand Cache Accesses
----------------------------------------
miss_latency: [binsize: 2 max: 269 count: 3294 average: 25.1044 | standard deviation: 56.2234 | 0 2784 0 0 0 0 0 0 0 69 14 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 80 86 86 80 64 7 5 1 2 0 2 4 2 1 2 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
-miss_latency_1: [binsize: 2 max: 227 count: 2585 average: 18.8561 | standard deviation: 48.7313 | 0 2315 0 0 0 0 0 0 0 27 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 48 53 42 50 34 2 4 1 1 0 2 2 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
-miss_latency_2: [binsize: 2 max: 267 count: 415 average: 61.0506 | standard deviation: 78.3756 | 0 233 0 0 0 0 0 0 0 42 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 32 18 42 18 23 1 0 0 1 0 0 1 0 0 2 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
-miss_latency_3: [binsize: 2 max: 269 count: 294 average: 29.3027 | standard deviation: 60.9274 | 0 236 0 0 0 0 0 0 0 0 14 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 2 12 7 4 1 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency_IFETCH: [binsize: 2 max: 227 count: 2585 average: 18.8561 | standard deviation: 48.7313 | 0 2315 0 0 0 0 0 0 0 27 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 48 53 42 50 34 2 4 1 1 0 2 2 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency_LD: [binsize: 2 max: 267 count: 415 average: 61.0506 | standard deviation: 78.3756 | 0 233 0 0 0 0 0 0 0 42 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 32 18 42 18 23 1 0 0 1 0 0 1 0 0 2 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency_ST: [binsize: 2 max: 269 count: 294 average: 29.3027 | standard deviation: 60.9274 | 0 236 0 0 0 0 0 0 0 0 14 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 2 12 7 4 1 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency_NULL: [binsize: 2 max: 269 count: 3294 average: 25.1044 | standard deviation: 56.2234 | 0 2784 0 0 0 0 0 0 0 69 14 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 80 86 86 80 64 7 5 1 2 0 2 4 2 1 2 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency_wCC_issue_to_initial_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+miss_latency_wCC_initial_forward_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+miss_latency_wCC_forward_to_first_response: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+miss_latency_wCC_first_response_to_completion: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+imcomplete_wCC_Times: 0
+miss_latency_dir_issue_to_initial_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+miss_latency_dir_initial_forward_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+miss_latency_dir_forward_to_first_response: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+miss_latency_dir_first_response_to_completion: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+imcomplete_dir_Times: 0
+miss_latency_IFETCH_NULL: [binsize: 2 max: 227 count: 2585 average: 18.8561 | standard deviation: 48.7313 | 0 2315 0 0 0 0 0 0 0 27 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 48 53 42 50 34 2 4 1 1 0 2 2 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency_LD_NULL: [binsize: 2 max: 267 count: 415 average: 61.0506 | standard deviation: 78.3756 | 0 233 0 0 0 0 0 0 0 42 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 32 18 42 18 23 1 0 0 1 0 0 1 0 0 2 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency_ST_NULL: [binsize: 2 max: 269 count: 294 average: 29.3027 | standard deviation: 60.9274 | 0 236 0 0 0 0 0 0 0 0 14 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 2 12 7 4 1 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
All Non-Zero Cycle SW Prefetch Requests
------------------------------------
@@ -116,8 +119,8 @@ Resource Usage
page_size: 4096
user_time: 0
system_time: 0
-page_reclaims: 7143
-page_faults: 2153
+page_reclaims: 7386
+page_faults: 2090
swaps: 0
block_inputs: 0
block_outputs: 0
@@ -125,6 +128,14 @@ block_outputs: 0
Network Stats
-------------
+total_msg_count_Request_Control: 2811 22488
+total_msg_count_Response_Data: 2562 184464
+total_msg_count_ResponseL2hit_Data: 249 17928
+total_msg_count_Writeback_Data: 1737 125064
+total_msg_count_Writeback_Control: 6480 51840
+total_msg_count_Unblock_Control: 2810 22480
+total_msgs: 16649 total_bytes: 424264
+
switch_0_inlinks: 2
switch_0_outlinks: 2
links_utilized_percent_switch_0: 0.212617
@@ -190,972 +201,966 @@ links_utilized_percent_switch_3: 0.342645
outgoing_messages_switch_3_link_2_Writeback_Control: 745 5960 [ 0 411 334 0 0 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_3_link_2_Unblock_Control: 427 3416 [ 0 0 427 0 0 0 0 0 0 0 ] base_latency: 1
-Cache Stats: system.ruby.network.topology.ext_links0.ext_node.sequencer.icache
- system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_misses: 0
- system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_demand_misses: 0
- system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_prefetches: 0
- system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_sw_prefetches: 0
- system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_hw_prefetches: 0
- system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_misses_per_transaction: nan
+Cache Stats: system.l1_cntrl0.sequencer.icache
+ system.l1_cntrl0.sequencer.icache_total_misses: 0
+ system.l1_cntrl0.sequencer.icache_total_demand_misses: 0
+ system.l1_cntrl0.sequencer.icache_total_prefetches: 0
+ system.l1_cntrl0.sequencer.icache_total_sw_prefetches: 0
+ system.l1_cntrl0.sequencer.icache_total_hw_prefetches: 0
- system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
-Cache Stats: system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache
- system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_misses: 0
- system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_demand_misses: 0
- system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_prefetches: 0
- system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_sw_prefetches: 0
- system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_hw_prefetches: 0
- system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_misses_per_transaction: nan
+Cache Stats: system.l1_cntrl0.sequencer.dcache
+ system.l1_cntrl0.sequencer.dcache_total_misses: 0
+ system.l1_cntrl0.sequencer.dcache_total_demand_misses: 0
+ system.l1_cntrl0.sequencer.dcache_total_prefetches: 0
+ system.l1_cntrl0.sequencer.dcache_total_sw_prefetches: 0
+ system.l1_cntrl0.sequencer.dcache_total_hw_prefetches: 0
- system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
- --- L1Cache 0 ---
+ --- L1Cache ---
- Event Counts -
-Load 415
-Ifetch 2585
-Store 294
-L1_Replacement 506
-Own_GETX 0
-Fwd_GETX 0
-Fwd_GETS 0
-Fwd_DMA 0
-Inv 0
-Ack 0
-Data 0
-Exclusive_Data 510
-Writeback_Ack 0
-Writeback_Ack_Data 502
-Writeback_Nack 0
-All_acks 58
-Use_Timeout 509
+Load [415 ] 415
+Ifetch [2585 ] 2585
+Store [294 ] 294
+L1_Replacement [506 ] 506
+Own_GETX [0 ] 0
+Fwd_GETX [0 ] 0
+Fwd_GETS [0 ] 0
+Fwd_DMA [0 ] 0
+Inv [0 ] 0
+Ack [0 ] 0
+Data [0 ] 0
+Exclusive_Data [510 ] 510
+Writeback_Ack [0 ] 0
+Writeback_Ack_Data [502 ] 502
+Writeback_Nack [0 ] 0
+All_acks [58 ] 58
+Use_Timeout [509 ] 509
- Transitions -
-I Load 182
-I Ifetch 270
-I Store 58
-I L1_Replacement 0 <--
-I Inv 0 <--
-
-S Load 0 <--
-S Ifetch 0 <--
-S Store 0 <--
-S L1_Replacement 0 <--
-S Fwd_GETS 0 <--
-S Fwd_DMA 0 <--
-S Inv 0 <--
-
-O Load 0 <--
-O Ifetch 0 <--
-O Store 0 <--
-O L1_Replacement 0 <--
-O Fwd_GETX 0 <--
-O Fwd_GETS 0 <--
-O Fwd_DMA 0 <--
-
-M Load 82
-M Ifetch 1224
-M Store 33
-M L1_Replacement 406
-M Fwd_GETX 0 <--
-M Fwd_GETS 0 <--
-M Fwd_DMA 0 <--
-
-M_W Load 49
-M_W Ifetch 1091
-M_W Store 7
-M_W L1_Replacement 4
-M_W Own_GETX 0 <--
-M_W Fwd_GETX 0 <--
-M_W Fwd_GETS 0 <--
-M_W Fwd_DMA 0 <--
-M_W Inv 0 <--
-M_W Use_Timeout 444
-
-MM Load 99
-MM Ifetch 0 <--
-MM Store 114
-MM L1_Replacement 96
-MM Fwd_GETX 0 <--
-MM Fwd_GETS 0 <--
-MM Fwd_DMA 0 <--
-
-MM_W Load 3
-MM_W Ifetch 0 <--
-MM_W Store 82
-MM_W L1_Replacement 0 <--
-MM_W Own_GETX 0 <--
-MM_W Fwd_GETX 0 <--
-MM_W Fwd_GETS 0 <--
-MM_W Fwd_DMA 0 <--
-MM_W Inv 0 <--
-MM_W Use_Timeout 65
-
-IM Load 0 <--
-IM Ifetch 0 <--
-IM Store 0 <--
-IM L1_Replacement 0 <--
-IM Inv 0 <--
-IM Ack 0 <--
-IM Data 0 <--
-IM Exclusive_Data 58
-
-SM Load 0 <--
-SM Ifetch 0 <--
-SM Store 0 <--
-SM L1_Replacement 0 <--
-SM Fwd_GETS 0 <--
-SM Fwd_DMA 0 <--
-SM Inv 0 <--
-SM Ack 0 <--
-SM Data 0 <--
-SM Exclusive_Data 0 <--
-
-OM Load 0 <--
-OM Ifetch 0 <--
-OM Store 0 <--
-OM L1_Replacement 0 <--
-OM Own_GETX 0 <--
-OM Fwd_GETX 0 <--
-OM Fwd_GETS 0 <--
-OM Fwd_DMA 0 <--
-OM Ack 0 <--
-OM All_acks 58
-
-IS Load 0 <--
-IS Ifetch 0 <--
-IS Store 0 <--
-IS L1_Replacement 0 <--
-IS Inv 0 <--
-IS Data 0 <--
-IS Exclusive_Data 452
-
-SI Load 0 <--
-SI Ifetch 0 <--
-SI Store 0 <--
-SI L1_Replacement 0 <--
-SI Fwd_GETS 0 <--
-SI Fwd_DMA 0 <--
-SI Inv 0 <--
-SI Writeback_Ack 0 <--
-SI Writeback_Ack_Data 0 <--
-SI Writeback_Nack 0 <--
-
-OI Load 0 <--
-OI Ifetch 0 <--
-OI Store 0 <--
-OI L1_Replacement 0 <--
-OI Fwd_GETX 0 <--
-OI Fwd_GETS 0 <--
-OI Fwd_DMA 0 <--
-OI Writeback_Ack 0 <--
-OI Writeback_Ack_Data 0 <--
-OI Writeback_Nack 0 <--
-
-MI Load 0 <--
-MI Ifetch 0 <--
-MI Store 0 <--
-MI L1_Replacement 0 <--
-MI Fwd_GETX 0 <--
-MI Fwd_GETS 0 <--
-MI Fwd_DMA 0 <--
-MI Writeback_Ack 0 <--
-MI Writeback_Ack_Data 502
-MI Writeback_Nack 0 <--
-
-II Load 0 <--
-II Ifetch 0 <--
-II Store 0 <--
-II L1_Replacement 0 <--
-II Inv 0 <--
-II Writeback_Ack 0 <--
-II Writeback_Ack_Data 0 <--
-II Writeback_Nack 0 <--
-
-Cache Stats: system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory
- system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_total_misses: 0
- system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_total_demand_misses: 0
- system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_total_prefetches: 0
- system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_total_sw_prefetches: 0
- system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_total_hw_prefetches: 0
- system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_misses_per_transaction: nan
-
- system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
-
- --- L2Cache 0 ---
+I Load [182 ] 182
+I Ifetch [270 ] 270
+I Store [58 ] 58
+I L1_Replacement [0 ] 0
+I Inv [0 ] 0
+
+S Load [0 ] 0
+S Ifetch [0 ] 0
+S Store [0 ] 0
+S L1_Replacement [0 ] 0
+S Fwd_GETS [0 ] 0
+S Fwd_DMA [0 ] 0
+S Inv [0 ] 0
+
+O Load [0 ] 0
+O Ifetch [0 ] 0
+O Store [0 ] 0
+O L1_Replacement [0 ] 0
+O Fwd_GETX [0 ] 0
+O Fwd_GETS [0 ] 0
+O Fwd_DMA [0 ] 0
+
+M Load [82 ] 82
+M Ifetch [1224 ] 1224
+M Store [33 ] 33
+M L1_Replacement [406 ] 406
+M Fwd_GETX [0 ] 0
+M Fwd_GETS [0 ] 0
+M Fwd_DMA [0 ] 0
+
+M_W Load [49 ] 49
+M_W Ifetch [1091 ] 1091
+M_W Store [7 ] 7
+M_W L1_Replacement [4 ] 4
+M_W Own_GETX [0 ] 0
+M_W Fwd_GETX [0 ] 0
+M_W Fwd_GETS [0 ] 0
+M_W Fwd_DMA [0 ] 0
+M_W Inv [0 ] 0
+M_W Use_Timeout [444 ] 444
+
+MM Load [99 ] 99
+MM Ifetch [0 ] 0
+MM Store [114 ] 114
+MM L1_Replacement [96 ] 96
+MM Fwd_GETX [0 ] 0
+MM Fwd_GETS [0 ] 0
+MM Fwd_DMA [0 ] 0
+
+MM_W Load [3 ] 3
+MM_W Ifetch [0 ] 0
+MM_W Store [82 ] 82
+MM_W L1_Replacement [0 ] 0
+MM_W Own_GETX [0 ] 0
+MM_W Fwd_GETX [0 ] 0
+MM_W Fwd_GETS [0 ] 0
+MM_W Fwd_DMA [0 ] 0
+MM_W Inv [0 ] 0
+MM_W Use_Timeout [65 ] 65
+
+IM Load [0 ] 0
+IM Ifetch [0 ] 0
+IM Store [0 ] 0
+IM L1_Replacement [0 ] 0
+IM Inv [0 ] 0
+IM Ack [0 ] 0
+IM Data [0 ] 0
+IM Exclusive_Data [58 ] 58
+
+SM Load [0 ] 0
+SM Ifetch [0 ] 0
+SM Store [0 ] 0
+SM L1_Replacement [0 ] 0
+SM Fwd_GETS [0 ] 0
+SM Fwd_DMA [0 ] 0
+SM Inv [0 ] 0
+SM Ack [0 ] 0
+SM Data [0 ] 0
+SM Exclusive_Data [0 ] 0
+
+OM Load [0 ] 0
+OM Ifetch [0 ] 0
+OM Store [0 ] 0
+OM L1_Replacement [0 ] 0
+OM Own_GETX [0 ] 0
+OM Fwd_GETX [0 ] 0
+OM Fwd_GETS [0 ] 0
+OM Fwd_DMA [0 ] 0
+OM Ack [0 ] 0
+OM All_acks [58 ] 58
+
+IS Load [0 ] 0
+IS Ifetch [0 ] 0
+IS Store [0 ] 0
+IS L1_Replacement [0 ] 0
+IS Inv [0 ] 0
+IS Data [0 ] 0
+IS Exclusive_Data [452 ] 452
+
+SI Load [0 ] 0
+SI Ifetch [0 ] 0
+SI Store [0 ] 0
+SI L1_Replacement [0 ] 0
+SI Fwd_GETS [0 ] 0
+SI Fwd_DMA [0 ] 0
+SI Inv [0 ] 0
+SI Writeback_Ack [0 ] 0
+SI Writeback_Ack_Data [0 ] 0
+SI Writeback_Nack [0 ] 0
+
+OI Load [0 ] 0
+OI Ifetch [0 ] 0
+OI Store [0 ] 0
+OI L1_Replacement [0 ] 0
+OI Fwd_GETX [0 ] 0
+OI Fwd_GETS [0 ] 0
+OI Fwd_DMA [0 ] 0
+OI Writeback_Ack [0 ] 0
+OI Writeback_Ack_Data [0 ] 0
+OI Writeback_Nack [0 ] 0
+
+MI Load [0 ] 0
+MI Ifetch [0 ] 0
+MI Store [0 ] 0
+MI L1_Replacement [0 ] 0
+MI Fwd_GETX [0 ] 0
+MI Fwd_GETS [0 ] 0
+MI Fwd_DMA [0 ] 0
+MI Writeback_Ack [0 ] 0
+MI Writeback_Ack_Data [502 ] 502
+MI Writeback_Nack [0 ] 0
+
+II Load [0 ] 0
+II Ifetch [0 ] 0
+II Store [0 ] 0
+II L1_Replacement [0 ] 0
+II Inv [0 ] 0
+II Writeback_Ack [0 ] 0
+II Writeback_Ack_Data [0 ] 0
+II Writeback_Nack [0 ] 0
+
+Cache Stats: system.l2_cntrl0.L2cacheMemory
+ system.l2_cntrl0.L2cacheMemory_total_misses: 0
+ system.l2_cntrl0.L2cacheMemory_total_demand_misses: 0
+ system.l2_cntrl0.L2cacheMemory_total_prefetches: 0
+ system.l2_cntrl0.L2cacheMemory_total_sw_prefetches: 0
+ system.l2_cntrl0.L2cacheMemory_total_hw_prefetches: 0
+
+
+ --- L2Cache ---
- Event Counts -
-L1_GETS 455
-L1_GETX 58
-L1_PUTO 0
-L1_PUTX 502
-L1_PUTS_only 0
-L1_PUTS 0
-Fwd_GETX 0
-Fwd_GETS 0
-Fwd_DMA 0
-Own_GETX 0
-Inv 0
-IntAck 0
-ExtAck 0
-All_Acks 44
-Data 44
-Data_Exclusive 383
-L1_WBCLEANDATA 396
-L1_WBDIRTYDATA 106
-Writeback_Ack 411
-Writeback_Nack 0
-Unblock 0
-Exclusive_Unblock 510
-L2_Replacement 411
+L1_GETS [455 ] 455
+L1_GETX [58 ] 58
+L1_PUTO [0 ] 0
+L1_PUTX [502 ] 502
+L1_PUTS_only [0 ] 0
+L1_PUTS [0 ] 0
+Fwd_GETX [0 ] 0
+Fwd_GETS [0 ] 0
+Fwd_DMA [0 ] 0
+Own_GETX [0 ] 0
+Inv [0 ] 0
+IntAck [0 ] 0
+ExtAck [0 ] 0
+All_Acks [44 ] 44
+Data [44 ] 44
+Data_Exclusive [383 ] 383
+L1_WBCLEANDATA [396 ] 396
+L1_WBDIRTYDATA [106 ] 106
+Writeback_Ack [411 ] 411
+Writeback_Nack [0 ] 0
+Unblock [0 ] 0
+Exclusive_Unblock [510 ] 510
+L2_Replacement [411 ] 411
- Transitions -
-NP L1_GETS 383
-NP L1_GETX 44
-NP L1_PUTO 0 <--
-NP L1_PUTX 0 <--
-NP L1_PUTS 0 <--
-NP Inv 0 <--
-
-I L1_GETS 0 <--
-I L1_GETX 0 <--
-I L1_PUTO 0 <--
-I L1_PUTX 0 <--
-I L1_PUTS 0 <--
-I Inv 0 <--
-I L2_Replacement 0 <--
-
-ILS L1_GETS 0 <--
-ILS L1_GETX 0 <--
-ILS L1_PUTO 0 <--
-ILS L1_PUTX 0 <--
-ILS L1_PUTS_only 0 <--
-ILS L1_PUTS 0 <--
-ILS Inv 0 <--
-ILS L2_Replacement 0 <--
-
-ILX L1_GETS 0 <--
-ILX L1_GETX 0 <--
-ILX L1_PUTO 0 <--
-ILX L1_PUTX 502
-ILX L1_PUTS_only 0 <--
-ILX L1_PUTS 0 <--
-ILX Fwd_GETX 0 <--
-ILX Fwd_GETS 0 <--
-ILX Fwd_DMA 0 <--
-ILX Inv 0 <--
-ILX Data 0 <--
-ILX L2_Replacement 0 <--
-
-ILO L1_GETS 0 <--
-ILO L1_GETX 0 <--
-ILO L1_PUTO 0 <--
-ILO L1_PUTX 0 <--
-ILO L1_PUTS 0 <--
-ILO Fwd_GETX 0 <--
-ILO Fwd_GETS 0 <--
-ILO Fwd_DMA 0 <--
-ILO Inv 0 <--
-ILO Data 0 <--
-ILO L2_Replacement 0 <--
-
-ILOX L1_GETS 0 <--
-ILOX L1_GETX 0 <--
-ILOX L1_PUTO 0 <--
-ILOX L1_PUTX 0 <--
-ILOX L1_PUTS 0 <--
-ILOX Fwd_GETX 0 <--
-ILOX Fwd_GETS 0 <--
-ILOX Fwd_DMA 0 <--
-ILOX Data 0 <--
-
-ILOS L1_GETS 0 <--
-ILOS L1_GETX 0 <--
-ILOS L1_PUTO 0 <--
-ILOS L1_PUTX 0 <--
-ILOS L1_PUTS_only 0 <--
-ILOS L1_PUTS 0 <--
-ILOS Fwd_GETX 0 <--
-ILOS Fwd_GETS 0 <--
-ILOS Fwd_DMA 0 <--
-ILOS Data 0 <--
-ILOS L2_Replacement 0 <--
-
-ILOSX L1_GETS 0 <--
-ILOSX L1_GETX 0 <--
-ILOSX L1_PUTO 0 <--
-ILOSX L1_PUTX 0 <--
-ILOSX L1_PUTS_only 0 <--
-ILOSX L1_PUTS 0 <--
-ILOSX Fwd_GETX 0 <--
-ILOSX Fwd_GETS 0 <--
-ILOSX Fwd_DMA 0 <--
-ILOSX Data 0 <--
-
-S L1_GETS 0 <--
-S L1_GETX 0 <--
-S L1_PUTX 0 <--
-S L1_PUTS 0 <--
-S Inv 0 <--
-S L2_Replacement 0 <--
-
-O L1_GETS 0 <--
-O L1_GETX 0 <--
-O L1_PUTX 0 <--
-O Fwd_GETX 0 <--
-O Fwd_GETS 0 <--
-O Fwd_DMA 0 <--
-O L2_Replacement 0 <--
-
-OLS L1_GETS 0 <--
-OLS L1_GETX 0 <--
-OLS L1_PUTX 0 <--
-OLS L1_PUTS_only 0 <--
-OLS L1_PUTS 0 <--
-OLS Fwd_GETX 0 <--
-OLS Fwd_GETS 0 <--
-OLS Fwd_DMA 0 <--
-OLS L2_Replacement 0 <--
-
-OLSX L1_GETS 0 <--
-OLSX L1_GETX 0 <--
-OLSX L1_PUTO 0 <--
-OLSX L1_PUTX 0 <--
-OLSX L1_PUTS_only 0 <--
-OLSX L1_PUTS 0 <--
-OLSX Fwd_GETX 0 <--
-OLSX Fwd_GETS 0 <--
-OLSX Fwd_DMA 0 <--
-OLSX L2_Replacement 0 <--
-
-SLS L1_GETS 0 <--
-SLS L1_GETX 0 <--
-SLS L1_PUTX 0 <--
-SLS L1_PUTS_only 0 <--
-SLS L1_PUTS 0 <--
-SLS Inv 0 <--
-SLS L2_Replacement 0 <--
-
-M L1_GETS 69
-M L1_GETX 14
-M L1_PUTO 0 <--
-M L1_PUTX 0 <--
-M L1_PUTS 0 <--
-M Fwd_GETX 0 <--
-M Fwd_GETS 0 <--
-M Fwd_DMA 0 <--
-M L2_Replacement 411
-
-IFGX L1_GETS 0 <--
-IFGX L1_GETX 0 <--
-IFGX L1_PUTO 0 <--
-IFGX L1_PUTX 0 <--
-IFGX L1_PUTS_only 0 <--
-IFGX L1_PUTS 0 <--
-IFGX Fwd_GETX 0 <--
-IFGX Fwd_GETS 0 <--
-IFGX Fwd_DMA 0 <--
-IFGX Inv 0 <--
-IFGX Data 0 <--
-IFGX Data_Exclusive 0 <--
-IFGX L2_Replacement 0 <--
-
-IFGS L1_GETS 0 <--
-IFGS L1_GETX 0 <--
-IFGS L1_PUTO 0 <--
-IFGS L1_PUTX 0 <--
-IFGS L1_PUTS_only 0 <--
-IFGS L1_PUTS 0 <--
-IFGS Fwd_GETX 0 <--
-IFGS Fwd_GETS 0 <--
-IFGS Fwd_DMA 0 <--
-IFGS Inv 0 <--
-IFGS Data 0 <--
-IFGS Data_Exclusive 0 <--
-IFGS L2_Replacement 0 <--
-
-ISFGS L1_GETS 0 <--
-ISFGS L1_GETX 0 <--
-ISFGS L1_PUTO 0 <--
-ISFGS L1_PUTX 0 <--
-ISFGS L1_PUTS_only 0 <--
-ISFGS L1_PUTS 0 <--
-ISFGS Fwd_GETX 0 <--
-ISFGS Fwd_GETS 0 <--
-ISFGS Fwd_DMA 0 <--
-ISFGS Inv 0 <--
-ISFGS Data 0 <--
-ISFGS L2_Replacement 0 <--
-
-IFGXX L1_GETS 0 <--
-IFGXX L1_GETX 0 <--
-IFGXX L1_PUTO 0 <--
-IFGXX L1_PUTX 0 <--
-IFGXX L1_PUTS_only 0 <--
-IFGXX L1_PUTS 0 <--
-IFGXX Fwd_GETX 0 <--
-IFGXX Fwd_GETS 0 <--
-IFGXX Fwd_DMA 0 <--
-IFGXX Inv 0 <--
-IFGXX IntAck 0 <--
-IFGXX All_Acks 0 <--
-IFGXX Data_Exclusive 0 <--
-IFGXX L2_Replacement 0 <--
-
-OFGX L1_GETS 0 <--
-OFGX L1_GETX 0 <--
-OFGX L1_PUTO 0 <--
-OFGX L1_PUTX 0 <--
-OFGX L1_PUTS_only 0 <--
-OFGX L1_PUTS 0 <--
-OFGX Fwd_GETX 0 <--
-OFGX Fwd_GETS 0 <--
-OFGX Fwd_DMA 0 <--
-OFGX Inv 0 <--
-OFGX L2_Replacement 0 <--
-
-OLSF L1_GETS 0 <--
-OLSF L1_GETX 0 <--
-OLSF L1_PUTO 0 <--
-OLSF L1_PUTX 0 <--
-OLSF L1_PUTS_only 0 <--
-OLSF L1_PUTS 0 <--
-OLSF Fwd_GETX 0 <--
-OLSF Fwd_GETS 0 <--
-OLSF Fwd_DMA 0 <--
-OLSF Inv 0 <--
-OLSF IntAck 0 <--
-OLSF All_Acks 0 <--
-OLSF L2_Replacement 0 <--
-
-ILOW L1_GETS 0 <--
-ILOW L1_GETX 0 <--
-ILOW L1_PUTO 0 <--
-ILOW L1_PUTX 0 <--
-ILOW L1_PUTS_only 0 <--
-ILOW L1_PUTS 0 <--
-ILOW Fwd_GETX 0 <--
-ILOW Fwd_GETS 0 <--
-ILOW Fwd_DMA 0 <--
-ILOW Inv 0 <--
-ILOW L1_WBCLEANDATA 0 <--
-ILOW L1_WBDIRTYDATA 0 <--
-ILOW Unblock 0 <--
-ILOW L2_Replacement 0 <--
-
-ILOXW L1_GETS 0 <--
-ILOXW L1_GETX 0 <--
-ILOXW L1_PUTO 0 <--
-ILOXW L1_PUTX 0 <--
-ILOXW L1_PUTS_only 0 <--
-ILOXW L1_PUTS 0 <--
-ILOXW Fwd_GETX 0 <--
-ILOXW Fwd_GETS 0 <--
-ILOXW Fwd_DMA 0 <--
-ILOXW Inv 0 <--
-ILOXW L1_WBCLEANDATA 0 <--
-ILOXW L1_WBDIRTYDATA 0 <--
-ILOXW Unblock 0 <--
-ILOXW L2_Replacement 0 <--
-
-ILOSW L1_GETS 0 <--
-ILOSW L1_GETX 0 <--
-ILOSW L1_PUTO 0 <--
-ILOSW L1_PUTX 0 <--
-ILOSW L1_PUTS_only 0 <--
-ILOSW L1_PUTS 0 <--
-ILOSW Fwd_GETX 0 <--
-ILOSW Fwd_GETS 0 <--
-ILOSW Fwd_DMA 0 <--
-ILOSW Inv 0 <--
-ILOSW L1_WBCLEANDATA 0 <--
-ILOSW L1_WBDIRTYDATA 0 <--
-ILOSW Unblock 0 <--
-ILOSW L2_Replacement 0 <--
-
-ILOSXW L1_GETS 0 <--
-ILOSXW L1_GETX 0 <--
-ILOSXW L1_PUTO 0 <--
-ILOSXW L1_PUTX 0 <--
-ILOSXW L1_PUTS_only 0 <--
-ILOSXW L1_PUTS 0 <--
-ILOSXW Fwd_GETX 0 <--
-ILOSXW Fwd_GETS 0 <--
-ILOSXW Fwd_DMA 0 <--
-ILOSXW Inv 0 <--
-ILOSXW L1_WBCLEANDATA 0 <--
-ILOSXW L1_WBDIRTYDATA 0 <--
-ILOSXW Unblock 0 <--
-ILOSXW L2_Replacement 0 <--
-
-SLSW L1_GETS 0 <--
-SLSW L1_GETX 0 <--
-SLSW L1_PUTO 0 <--
-SLSW L1_PUTX 0 <--
-SLSW L1_PUTS_only 0 <--
-SLSW L1_PUTS 0 <--
-SLSW Fwd_GETX 0 <--
-SLSW Fwd_GETS 0 <--
-SLSW Fwd_DMA 0 <--
-SLSW Inv 0 <--
-SLSW Unblock 0 <--
-SLSW L2_Replacement 0 <--
-
-OLSW L1_GETS 0 <--
-OLSW L1_GETX 0 <--
-OLSW L1_PUTO 0 <--
-OLSW L1_PUTX 0 <--
-OLSW L1_PUTS_only 0 <--
-OLSW L1_PUTS 0 <--
-OLSW Fwd_GETX 0 <--
-OLSW Fwd_GETS 0 <--
-OLSW Fwd_DMA 0 <--
-OLSW Inv 0 <--
-OLSW Unblock 0 <--
-OLSW L2_Replacement 0 <--
-
-ILSW L1_GETS 0 <--
-ILSW L1_GETX 0 <--
-ILSW L1_PUTO 0 <--
-ILSW L1_PUTX 0 <--
-ILSW L1_PUTS_only 0 <--
-ILSW L1_PUTS 0 <--
-ILSW Fwd_GETX 0 <--
-ILSW Fwd_GETS 0 <--
-ILSW Fwd_DMA 0 <--
-ILSW Inv 0 <--
-ILSW L1_WBCLEANDATA 0 <--
-ILSW Unblock 0 <--
-ILSW L2_Replacement 0 <--
-
-IW L1_GETS 0 <--
-IW L1_GETX 0 <--
-IW L1_PUTO 0 <--
-IW L1_PUTX 0 <--
-IW L1_PUTS_only 0 <--
-IW L1_PUTS 0 <--
-IW Fwd_GETX 0 <--
-IW Fwd_GETS 0 <--
-IW Fwd_DMA 0 <--
-IW Inv 0 <--
-IW L1_WBCLEANDATA 0 <--
-IW L2_Replacement 0 <--
-
-OW L1_GETS 0 <--
-OW L1_GETX 0 <--
-OW L1_PUTO 0 <--
-OW L1_PUTX 0 <--
-OW L1_PUTS_only 0 <--
-OW L1_PUTS 0 <--
-OW Fwd_GETX 0 <--
-OW Fwd_GETS 0 <--
-OW Fwd_DMA 0 <--
-OW Inv 0 <--
-OW Unblock 0 <--
-OW L2_Replacement 0 <--
-
-SW L1_GETS 0 <--
-SW L1_GETX 0 <--
-SW L1_PUTO 0 <--
-SW L1_PUTX 0 <--
-SW L1_PUTS_only 0 <--
-SW L1_PUTS 0 <--
-SW Fwd_GETX 0 <--
-SW Fwd_GETS 0 <--
-SW Fwd_DMA 0 <--
-SW Inv 0 <--
-SW Unblock 0 <--
-SW L2_Replacement 0 <--
-
-OXW L1_GETS 0 <--
-OXW L1_GETX 0 <--
-OXW L1_PUTO 0 <--
-OXW L1_PUTX 0 <--
-OXW L1_PUTS_only 0 <--
-OXW L1_PUTS 0 <--
-OXW Fwd_GETX 0 <--
-OXW Fwd_GETS 0 <--
-OXW Fwd_DMA 0 <--
-OXW Inv 0 <--
-OXW Unblock 0 <--
-OXW L2_Replacement 0 <--
-
-OLSXW L1_GETS 0 <--
-OLSXW L1_GETX 0 <--
-OLSXW L1_PUTO 0 <--
-OLSXW L1_PUTX 0 <--
-OLSXW L1_PUTS_only 0 <--
-OLSXW L1_PUTS 0 <--
-OLSXW Fwd_GETX 0 <--
-OLSXW Fwd_GETS 0 <--
-OLSXW Fwd_DMA 0 <--
-OLSXW Inv 0 <--
-OLSXW Unblock 0 <--
-OLSXW L2_Replacement 0 <--
-
-ILXW L1_GETS 0 <--
-ILXW L1_GETX 0 <--
-ILXW L1_PUTO 0 <--
-ILXW L1_PUTX 0 <--
-ILXW L1_PUTS_only 0 <--
-ILXW L1_PUTS 0 <--
-ILXW Fwd_GETX 0 <--
-ILXW Fwd_GETS 0 <--
-ILXW Fwd_DMA 0 <--
-ILXW Inv 0 <--
-ILXW Data 0 <--
-ILXW L1_WBCLEANDATA 396
-ILXW L1_WBDIRTYDATA 106
-ILXW Unblock 0 <--
-ILXW L2_Replacement 0 <--
-
-IFLS L1_GETS 0 <--
-IFLS L1_GETX 0 <--
-IFLS L1_PUTO 0 <--
-IFLS L1_PUTX 0 <--
-IFLS L1_PUTS_only 0 <--
-IFLS L1_PUTS 0 <--
-IFLS Fwd_GETX 0 <--
-IFLS Fwd_GETS 0 <--
-IFLS Fwd_DMA 0 <--
-IFLS Inv 0 <--
-IFLS Unblock 0 <--
-IFLS L2_Replacement 0 <--
-
-IFLO L1_GETS 0 <--
-IFLO L1_GETX 0 <--
-IFLO L1_PUTO 0 <--
-IFLO L1_PUTX 0 <--
-IFLO L1_PUTS_only 0 <--
-IFLO L1_PUTS 0 <--
-IFLO Fwd_GETX 0 <--
-IFLO Fwd_GETS 0 <--
-IFLO Fwd_DMA 0 <--
-IFLO Inv 0 <--
-IFLO Unblock 0 <--
-IFLO L2_Replacement 0 <--
-
-IFLOX L1_GETS 0 <--
-IFLOX L1_GETX 0 <--
-IFLOX L1_PUTO 0 <--
-IFLOX L1_PUTX 0 <--
-IFLOX L1_PUTS_only 0 <--
-IFLOX L1_PUTS 0 <--
-IFLOX Fwd_GETX 0 <--
-IFLOX Fwd_GETS 0 <--
-IFLOX Fwd_DMA 0 <--
-IFLOX Inv 0 <--
-IFLOX Unblock 0 <--
-IFLOX Exclusive_Unblock 0 <--
-IFLOX L2_Replacement 0 <--
-
-IFLOXX L1_GETS 0 <--
-IFLOXX L1_GETX 0 <--
-IFLOXX L1_PUTO 0 <--
-IFLOXX L1_PUTX 0 <--
-IFLOXX L1_PUTS_only 0 <--
-IFLOXX L1_PUTS 0 <--
-IFLOXX Fwd_GETX 0 <--
-IFLOXX Fwd_GETS 0 <--
-IFLOXX Fwd_DMA 0 <--
-IFLOXX Inv 0 <--
-IFLOXX Unblock 0 <--
-IFLOXX Exclusive_Unblock 0 <--
-IFLOXX L2_Replacement 0 <--
-
-IFLOSX L1_GETS 0 <--
-IFLOSX L1_GETX 0 <--
-IFLOSX L1_PUTO 0 <--
-IFLOSX L1_PUTX 0 <--
-IFLOSX L1_PUTS_only 0 <--
-IFLOSX L1_PUTS 0 <--
-IFLOSX Fwd_GETX 0 <--
-IFLOSX Fwd_GETS 0 <--
-IFLOSX Fwd_DMA 0 <--
-IFLOSX Inv 0 <--
-IFLOSX Unblock 0 <--
-IFLOSX Exclusive_Unblock 0 <--
-IFLOSX L2_Replacement 0 <--
-
-IFLXO L1_GETS 0 <--
-IFLXO L1_GETX 0 <--
-IFLXO L1_PUTO 0 <--
-IFLXO L1_PUTX 0 <--
-IFLXO L1_PUTS_only 0 <--
-IFLXO L1_PUTS 0 <--
-IFLXO Fwd_GETX 0 <--
-IFLXO Fwd_GETS 0 <--
-IFLXO Fwd_DMA 0 <--
-IFLXO Inv 0 <--
-IFLXO Exclusive_Unblock 0 <--
-IFLXO L2_Replacement 0 <--
-
-IGS L1_GETS 0 <--
-IGS L1_GETX 0 <--
-IGS L1_PUTO 0 <--
-IGS L1_PUTX 0 <--
-IGS L1_PUTS_only 0 <--
-IGS L1_PUTS 0 <--
-IGS Fwd_GETX 0 <--
-IGS Fwd_GETS 0 <--
-IGS Fwd_DMA 0 <--
-IGS Own_GETX 0 <--
-IGS Inv 0 <--
-IGS Data 0 <--
-IGS Data_Exclusive 383
-IGS Unblock 0 <--
-IGS Exclusive_Unblock 383
-IGS L2_Replacement 0 <--
-
-IGM L1_GETS 0 <--
-IGM L1_GETX 0 <--
-IGM L1_PUTO 0 <--
-IGM L1_PUTX 0 <--
-IGM L1_PUTS_only 0 <--
-IGM L1_PUTS 0 <--
-IGM Fwd_GETX 0 <--
-IGM Fwd_GETS 0 <--
-IGM Fwd_DMA 0 <--
-IGM Own_GETX 0 <--
-IGM Inv 0 <--
-IGM ExtAck 0 <--
-IGM Data 44
-IGM Data_Exclusive 0 <--
-IGM L2_Replacement 0 <--
-
-IGMLS L1_GETS 0 <--
-IGMLS L1_GETX 0 <--
-IGMLS L1_PUTO 0 <--
-IGMLS L1_PUTX 0 <--
-IGMLS L1_PUTS_only 0 <--
-IGMLS L1_PUTS 0 <--
-IGMLS Inv 0 <--
-IGMLS IntAck 0 <--
-IGMLS ExtAck 0 <--
-IGMLS All_Acks 0 <--
-IGMLS Data 0 <--
-IGMLS Data_Exclusive 0 <--
-IGMLS L2_Replacement 0 <--
-
-IGMO L1_GETS 0 <--
-IGMO L1_GETX 0 <--
-IGMO L1_PUTO 0 <--
-IGMO L1_PUTX 0 <--
-IGMO L1_PUTS_only 0 <--
-IGMO L1_PUTS 0 <--
-IGMO Fwd_GETX 0 <--
-IGMO Fwd_GETS 0 <--
-IGMO Fwd_DMA 0 <--
-IGMO Own_GETX 0 <--
-IGMO ExtAck 0 <--
-IGMO All_Acks 44
-IGMO Exclusive_Unblock 44
-IGMO L2_Replacement 0 <--
-
-IGMIO L1_GETS 0 <--
-IGMIO L1_GETX 0 <--
-IGMIO L1_PUTO 0 <--
-IGMIO L1_PUTX 0 <--
-IGMIO L1_PUTS_only 0 <--
-IGMIO L1_PUTS 0 <--
-IGMIO Fwd_GETX 0 <--
-IGMIO Fwd_GETS 0 <--
-IGMIO Fwd_DMA 0 <--
-IGMIO Own_GETX 0 <--
-IGMIO ExtAck 0 <--
-IGMIO All_Acks 0 <--
-
-OGMIO L1_GETS 0 <--
-OGMIO L1_GETX 0 <--
-OGMIO L1_PUTO 0 <--
-OGMIO L1_PUTX 0 <--
-OGMIO L1_PUTS_only 0 <--
-OGMIO L1_PUTS 0 <--
-OGMIO Fwd_GETX 0 <--
-OGMIO Fwd_GETS 0 <--
-OGMIO Fwd_DMA 0 <--
-OGMIO Own_GETX 0 <--
-OGMIO ExtAck 0 <--
-OGMIO All_Acks 0 <--
-
-IGMIOF L1_GETS 0 <--
-IGMIOF L1_GETX 0 <--
-IGMIOF L1_PUTO 0 <--
-IGMIOF L1_PUTX 0 <--
-IGMIOF L1_PUTS_only 0 <--
-IGMIOF L1_PUTS 0 <--
-IGMIOF IntAck 0 <--
-IGMIOF All_Acks 0 <--
-IGMIOF Data_Exclusive 0 <--
-
-IGMIOFS L1_GETS 0 <--
-IGMIOFS L1_GETX 0 <--
-IGMIOFS L1_PUTO 0 <--
-IGMIOFS L1_PUTX 0 <--
-IGMIOFS L1_PUTS_only 0 <--
-IGMIOFS L1_PUTS 0 <--
-IGMIOFS Fwd_GETX 0 <--
-IGMIOFS Fwd_GETS 0 <--
-IGMIOFS Fwd_DMA 0 <--
-IGMIOFS Inv 0 <--
-IGMIOFS Data 0 <--
-IGMIOFS L2_Replacement 0 <--
-
-OGMIOF L1_GETS 0 <--
-OGMIOF L1_GETX 0 <--
-OGMIOF L1_PUTO 0 <--
-OGMIOF L1_PUTX 0 <--
-OGMIOF L1_PUTS_only 0 <--
-OGMIOF L1_PUTS 0 <--
-OGMIOF IntAck 0 <--
-OGMIOF All_Acks 0 <--
-
-II L1_GETS 0 <--
-II L1_GETX 0 <--
-II L1_PUTO 0 <--
-II L1_PUTX 0 <--
-II L1_PUTS_only 0 <--
-II L1_PUTS 0 <--
-II IntAck 0 <--
-II All_Acks 0 <--
-
-MM L1_GETS 0 <--
-MM L1_GETX 0 <--
-MM L1_PUTO 0 <--
-MM L1_PUTX 0 <--
-MM L1_PUTS_only 0 <--
-MM L1_PUTS 0 <--
-MM Fwd_GETX 0 <--
-MM Fwd_GETS 0 <--
-MM Fwd_DMA 0 <--
-MM Inv 0 <--
-MM Exclusive_Unblock 14
-MM L2_Replacement 0 <--
-
-SS L1_GETS 0 <--
-SS L1_GETX 0 <--
-SS L1_PUTO 0 <--
-SS L1_PUTX 0 <--
-SS L1_PUTS_only 0 <--
-SS L1_PUTS 0 <--
-SS Fwd_GETX 0 <--
-SS Fwd_GETS 0 <--
-SS Fwd_DMA 0 <--
-SS Inv 0 <--
-SS Unblock 0 <--
-SS L2_Replacement 0 <--
-
-OO L1_GETS 0 <--
-OO L1_GETX 0 <--
-OO L1_PUTO 0 <--
-OO L1_PUTX 0 <--
-OO L1_PUTS_only 0 <--
-OO L1_PUTS 0 <--
-OO Fwd_GETX 0 <--
-OO Fwd_GETS 0 <--
-OO Fwd_DMA 0 <--
-OO Inv 0 <--
-OO Unblock 0 <--
-OO Exclusive_Unblock 69
-OO L2_Replacement 0 <--
-
-OLSS L1_GETS 0 <--
-OLSS L1_GETX 0 <--
-OLSS L1_PUTO 0 <--
-OLSS L1_PUTX 0 <--
-OLSS L1_PUTS_only 0 <--
-OLSS L1_PUTS 0 <--
-OLSS Fwd_GETX 0 <--
-OLSS Fwd_GETS 0 <--
-OLSS Fwd_DMA 0 <--
-OLSS Inv 0 <--
-OLSS Unblock 0 <--
-OLSS L2_Replacement 0 <--
-
-OLSXS L1_GETS 0 <--
-OLSXS L1_GETX 0 <--
-OLSXS L1_PUTO 0 <--
-OLSXS L1_PUTX 0 <--
-OLSXS L1_PUTS_only 0 <--
-OLSXS L1_PUTS 0 <--
-OLSXS Fwd_GETX 0 <--
-OLSXS Fwd_GETS 0 <--
-OLSXS Fwd_DMA 0 <--
-OLSXS Inv 0 <--
-OLSXS Unblock 0 <--
-OLSXS L2_Replacement 0 <--
-
-SLSS L1_GETS 0 <--
-SLSS L1_GETX 0 <--
-SLSS L1_PUTO 0 <--
-SLSS L1_PUTX 0 <--
-SLSS L1_PUTS_only 0 <--
-SLSS L1_PUTS 0 <--
-SLSS Fwd_GETX 0 <--
-SLSS Fwd_GETS 0 <--
-SLSS Fwd_DMA 0 <--
-SLSS Inv 0 <--
-SLSS Unblock 0 <--
-SLSS L2_Replacement 0 <--
-
-OI L1_GETS 0 <--
-OI L1_GETX 0 <--
-OI L1_PUTO 0 <--
-OI L1_PUTX 0 <--
-OI L1_PUTS_only 0 <--
-OI L1_PUTS 0 <--
-OI Fwd_GETX 0 <--
-OI Fwd_GETS 0 <--
-OI Fwd_DMA 0 <--
-OI Writeback_Ack 0 <--
-OI Writeback_Nack 0 <--
-OI L2_Replacement 0 <--
-
-MI L1_GETS 3
-MI L1_GETX 0 <--
-MI L1_PUTO 0 <--
-MI L1_PUTX 0 <--
-MI L1_PUTS_only 0 <--
-MI L1_PUTS 0 <--
-MI Fwd_GETX 0 <--
-MI Fwd_GETS 0 <--
-MI Fwd_DMA 0 <--
-MI Writeback_Ack 411
-MI L2_Replacement 0 <--
-
-MII L1_GETS 0 <--
-MII L1_GETX 0 <--
-MII L1_PUTO 0 <--
-MII L1_PUTX 0 <--
-MII L1_PUTS_only 0 <--
-MII L1_PUTS 0 <--
-MII Writeback_Ack 0 <--
-MII Writeback_Nack 0 <--
-MII L2_Replacement 0 <--
-
-OLSI L1_GETS 0 <--
-OLSI L1_GETX 0 <--
-OLSI L1_PUTO 0 <--
-OLSI L1_PUTX 0 <--
-OLSI L1_PUTS_only 0 <--
-OLSI L1_PUTS 0 <--
-OLSI Fwd_GETX 0 <--
-OLSI Fwd_GETS 0 <--
-OLSI Fwd_DMA 0 <--
-OLSI Writeback_Ack 0 <--
-OLSI L2_Replacement 0 <--
-
-ILSI L1_GETS 0 <--
-ILSI L1_GETX 0 <--
-ILSI L1_PUTO 0 <--
-ILSI L1_PUTX 0 <--
-ILSI L1_PUTS_only 0 <--
-ILSI L1_PUTS 0 <--
-ILSI IntAck 0 <--
-ILSI All_Acks 0 <--
-ILSI Writeback_Ack 0 <--
-ILSI L2_Replacement 0 <--
-
-Memory controller: system.ruby.network.topology.ext_links2.ext_node.memBuffer:
+NP L1_GETS [383 ] 383
+NP L1_GETX [44 ] 44
+NP L1_PUTO [0 ] 0
+NP L1_PUTX [0 ] 0
+NP L1_PUTS [0 ] 0
+NP Inv [0 ] 0
+
+I L1_GETS [0 ] 0
+I L1_GETX [0 ] 0
+I L1_PUTO [0 ] 0
+I L1_PUTX [0 ] 0
+I L1_PUTS [0 ] 0
+I Inv [0 ] 0
+I L2_Replacement [0 ] 0
+
+ILS L1_GETS [0 ] 0
+ILS L1_GETX [0 ] 0
+ILS L1_PUTO [0 ] 0
+ILS L1_PUTX [0 ] 0
+ILS L1_PUTS_only [0 ] 0
+ILS L1_PUTS [0 ] 0
+ILS Inv [0 ] 0
+ILS L2_Replacement [0 ] 0
+
+ILX L1_GETS [0 ] 0
+ILX L1_GETX [0 ] 0
+ILX L1_PUTO [0 ] 0
+ILX L1_PUTX [502 ] 502
+ILX L1_PUTS_only [0 ] 0
+ILX L1_PUTS [0 ] 0
+ILX Fwd_GETX [0 ] 0
+ILX Fwd_GETS [0 ] 0
+ILX Fwd_DMA [0 ] 0
+ILX Inv [0 ] 0
+ILX Data [0 ] 0
+ILX L2_Replacement [0 ] 0
+
+ILO L1_GETS [0 ] 0
+ILO L1_GETX [0 ] 0
+ILO L1_PUTO [0 ] 0
+ILO L1_PUTX [0 ] 0
+ILO L1_PUTS [0 ] 0
+ILO Fwd_GETX [0 ] 0
+ILO Fwd_GETS [0 ] 0
+ILO Fwd_DMA [0 ] 0
+ILO Inv [0 ] 0
+ILO Data [0 ] 0
+ILO L2_Replacement [0 ] 0
+
+ILOX L1_GETS [0 ] 0
+ILOX L1_GETX [0 ] 0
+ILOX L1_PUTO [0 ] 0
+ILOX L1_PUTX [0 ] 0
+ILOX L1_PUTS [0 ] 0
+ILOX Fwd_GETX [0 ] 0
+ILOX Fwd_GETS [0 ] 0
+ILOX Fwd_DMA [0 ] 0
+ILOX Data [0 ] 0
+
+ILOS L1_GETS [0 ] 0
+ILOS L1_GETX [0 ] 0
+ILOS L1_PUTO [0 ] 0
+ILOS L1_PUTX [0 ] 0
+ILOS L1_PUTS_only [0 ] 0
+ILOS L1_PUTS [0 ] 0
+ILOS Fwd_GETX [0 ] 0
+ILOS Fwd_GETS [0 ] 0
+ILOS Fwd_DMA [0 ] 0
+ILOS Data [0 ] 0
+ILOS L2_Replacement [0 ] 0
+
+ILOSX L1_GETS [0 ] 0
+ILOSX L1_GETX [0 ] 0
+ILOSX L1_PUTO [0 ] 0
+ILOSX L1_PUTX [0 ] 0
+ILOSX L1_PUTS_only [0 ] 0
+ILOSX L1_PUTS [0 ] 0
+ILOSX Fwd_GETX [0 ] 0
+ILOSX Fwd_GETS [0 ] 0
+ILOSX Fwd_DMA [0 ] 0
+ILOSX Data [0 ] 0
+
+S L1_GETS [0 ] 0
+S L1_GETX [0 ] 0
+S L1_PUTX [0 ] 0
+S L1_PUTS [0 ] 0
+S Inv [0 ] 0
+S L2_Replacement [0 ] 0
+
+O L1_GETS [0 ] 0
+O L1_GETX [0 ] 0
+O L1_PUTX [0 ] 0
+O Fwd_GETX [0 ] 0
+O Fwd_GETS [0 ] 0
+O Fwd_DMA [0 ] 0
+O L2_Replacement [0 ] 0
+
+OLS L1_GETS [0 ] 0
+OLS L1_GETX [0 ] 0
+OLS L1_PUTX [0 ] 0
+OLS L1_PUTS_only [0 ] 0
+OLS L1_PUTS [0 ] 0
+OLS Fwd_GETX [0 ] 0
+OLS Fwd_GETS [0 ] 0
+OLS Fwd_DMA [0 ] 0
+OLS L2_Replacement [0 ] 0
+
+OLSX L1_GETS [0 ] 0
+OLSX L1_GETX [0 ] 0
+OLSX L1_PUTO [0 ] 0
+OLSX L1_PUTX [0 ] 0
+OLSX L1_PUTS_only [0 ] 0
+OLSX L1_PUTS [0 ] 0
+OLSX Fwd_GETX [0 ] 0
+OLSX Fwd_GETS [0 ] 0
+OLSX Fwd_DMA [0 ] 0
+OLSX L2_Replacement [0 ] 0
+
+SLS L1_GETS [0 ] 0
+SLS L1_GETX [0 ] 0
+SLS L1_PUTX [0 ] 0
+SLS L1_PUTS_only [0 ] 0
+SLS L1_PUTS [0 ] 0
+SLS Inv [0 ] 0
+SLS L2_Replacement [0 ] 0
+
+M L1_GETS [69 ] 69
+M L1_GETX [14 ] 14
+M L1_PUTO [0 ] 0
+M L1_PUTX [0 ] 0
+M L1_PUTS [0 ] 0
+M Fwd_GETX [0 ] 0
+M Fwd_GETS [0 ] 0
+M Fwd_DMA [0 ] 0
+M L2_Replacement [411 ] 411
+
+IFGX L1_GETS [0 ] 0
+IFGX L1_GETX [0 ] 0
+IFGX L1_PUTO [0 ] 0
+IFGX L1_PUTX [0 ] 0
+IFGX L1_PUTS_only [0 ] 0
+IFGX L1_PUTS [0 ] 0
+IFGX Fwd_GETX [0 ] 0
+IFGX Fwd_GETS [0 ] 0
+IFGX Fwd_DMA [0 ] 0
+IFGX Inv [0 ] 0
+IFGX Data [0 ] 0
+IFGX Data_Exclusive [0 ] 0
+IFGX L2_Replacement [0 ] 0
+
+IFGS L1_GETS [0 ] 0
+IFGS L1_GETX [0 ] 0
+IFGS L1_PUTO [0 ] 0
+IFGS L1_PUTX [0 ] 0
+IFGS L1_PUTS_only [0 ] 0
+IFGS L1_PUTS [0 ] 0
+IFGS Fwd_GETX [0 ] 0
+IFGS Fwd_GETS [0 ] 0
+IFGS Fwd_DMA [0 ] 0
+IFGS Inv [0 ] 0
+IFGS Data [0 ] 0
+IFGS Data_Exclusive [0 ] 0
+IFGS L2_Replacement [0 ] 0
+
+ISFGS L1_GETS [0 ] 0
+ISFGS L1_GETX [0 ] 0
+ISFGS L1_PUTO [0 ] 0
+ISFGS L1_PUTX [0 ] 0
+ISFGS L1_PUTS_only [0 ] 0
+ISFGS L1_PUTS [0 ] 0
+ISFGS Fwd_GETX [0 ] 0
+ISFGS Fwd_GETS [0 ] 0
+ISFGS Fwd_DMA [0 ] 0
+ISFGS Inv [0 ] 0
+ISFGS Data [0 ] 0
+ISFGS L2_Replacement [0 ] 0
+
+IFGXX L1_GETS [0 ] 0
+IFGXX L1_GETX [0 ] 0
+IFGXX L1_PUTO [0 ] 0
+IFGXX L1_PUTX [0 ] 0
+IFGXX L1_PUTS_only [0 ] 0
+IFGXX L1_PUTS [0 ] 0
+IFGXX Fwd_GETX [0 ] 0
+IFGXX Fwd_GETS [0 ] 0
+IFGXX Fwd_DMA [0 ] 0
+IFGXX Inv [0 ] 0
+IFGXX IntAck [0 ] 0
+IFGXX All_Acks [0 ] 0
+IFGXX Data_Exclusive [0 ] 0
+IFGXX L2_Replacement [0 ] 0
+
+OFGX L1_GETS [0 ] 0
+OFGX L1_GETX [0 ] 0
+OFGX L1_PUTO [0 ] 0
+OFGX L1_PUTX [0 ] 0
+OFGX L1_PUTS_only [0 ] 0
+OFGX L1_PUTS [0 ] 0
+OFGX Fwd_GETX [0 ] 0
+OFGX Fwd_GETS [0 ] 0
+OFGX Fwd_DMA [0 ] 0
+OFGX Inv [0 ] 0
+OFGX L2_Replacement [0 ] 0
+
+OLSF L1_GETS [0 ] 0
+OLSF L1_GETX [0 ] 0
+OLSF L1_PUTO [0 ] 0
+OLSF L1_PUTX [0 ] 0
+OLSF L1_PUTS_only [0 ] 0
+OLSF L1_PUTS [0 ] 0
+OLSF Fwd_GETX [0 ] 0
+OLSF Fwd_GETS [0 ] 0
+OLSF Fwd_DMA [0 ] 0
+OLSF Inv [0 ] 0
+OLSF IntAck [0 ] 0
+OLSF All_Acks [0 ] 0
+OLSF L2_Replacement [0 ] 0
+
+ILOW L1_GETS [0 ] 0
+ILOW L1_GETX [0 ] 0
+ILOW L1_PUTO [0 ] 0
+ILOW L1_PUTX [0 ] 0
+ILOW L1_PUTS_only [0 ] 0
+ILOW L1_PUTS [0 ] 0
+ILOW Fwd_GETX [0 ] 0
+ILOW Fwd_GETS [0 ] 0
+ILOW Fwd_DMA [0 ] 0
+ILOW Inv [0 ] 0
+ILOW L1_WBCLEANDATA [0 ] 0
+ILOW L1_WBDIRTYDATA [0 ] 0
+ILOW Unblock [0 ] 0
+ILOW L2_Replacement [0 ] 0
+
+ILOXW L1_GETS [0 ] 0
+ILOXW L1_GETX [0 ] 0
+ILOXW L1_PUTO [0 ] 0
+ILOXW L1_PUTX [0 ] 0
+ILOXW L1_PUTS_only [0 ] 0
+ILOXW L1_PUTS [0 ] 0
+ILOXW Fwd_GETX [0 ] 0
+ILOXW Fwd_GETS [0 ] 0
+ILOXW Fwd_DMA [0 ] 0
+ILOXW Inv [0 ] 0
+ILOXW L1_WBCLEANDATA [0 ] 0
+ILOXW L1_WBDIRTYDATA [0 ] 0
+ILOXW Unblock [0 ] 0
+ILOXW L2_Replacement [0 ] 0
+
+ILOSW L1_GETS [0 ] 0
+ILOSW L1_GETX [0 ] 0
+ILOSW L1_PUTO [0 ] 0
+ILOSW L1_PUTX [0 ] 0
+ILOSW L1_PUTS_only [0 ] 0
+ILOSW L1_PUTS [0 ] 0
+ILOSW Fwd_GETX [0 ] 0
+ILOSW Fwd_GETS [0 ] 0
+ILOSW Fwd_DMA [0 ] 0
+ILOSW Inv [0 ] 0
+ILOSW L1_WBCLEANDATA [0 ] 0
+ILOSW L1_WBDIRTYDATA [0 ] 0
+ILOSW Unblock [0 ] 0
+ILOSW L2_Replacement [0 ] 0
+
+ILOSXW L1_GETS [0 ] 0
+ILOSXW L1_GETX [0 ] 0
+ILOSXW L1_PUTO [0 ] 0
+ILOSXW L1_PUTX [0 ] 0
+ILOSXW L1_PUTS_only [0 ] 0
+ILOSXW L1_PUTS [0 ] 0
+ILOSXW Fwd_GETX [0 ] 0
+ILOSXW Fwd_GETS [0 ] 0
+ILOSXW Fwd_DMA [0 ] 0
+ILOSXW Inv [0 ] 0
+ILOSXW L1_WBCLEANDATA [0 ] 0
+ILOSXW L1_WBDIRTYDATA [0 ] 0
+ILOSXW Unblock [0 ] 0
+ILOSXW L2_Replacement [0 ] 0
+
+SLSW L1_GETS [0 ] 0
+SLSW L1_GETX [0 ] 0
+SLSW L1_PUTO [0 ] 0
+SLSW L1_PUTX [0 ] 0
+SLSW L1_PUTS_only [0 ] 0
+SLSW L1_PUTS [0 ] 0
+SLSW Fwd_GETX [0 ] 0
+SLSW Fwd_GETS [0 ] 0
+SLSW Fwd_DMA [0 ] 0
+SLSW Inv [0 ] 0
+SLSW Unblock [0 ] 0
+SLSW L2_Replacement [0 ] 0
+
+OLSW L1_GETS [0 ] 0
+OLSW L1_GETX [0 ] 0
+OLSW L1_PUTO [0 ] 0
+OLSW L1_PUTX [0 ] 0
+OLSW L1_PUTS_only [0 ] 0
+OLSW L1_PUTS [0 ] 0
+OLSW Fwd_GETX [0 ] 0
+OLSW Fwd_GETS [0 ] 0
+OLSW Fwd_DMA [0 ] 0
+OLSW Inv [0 ] 0
+OLSW Unblock [0 ] 0
+OLSW L2_Replacement [0 ] 0
+
+ILSW L1_GETS [0 ] 0
+ILSW L1_GETX [0 ] 0
+ILSW L1_PUTO [0 ] 0
+ILSW L1_PUTX [0 ] 0
+ILSW L1_PUTS_only [0 ] 0
+ILSW L1_PUTS [0 ] 0
+ILSW Fwd_GETX [0 ] 0
+ILSW Fwd_GETS [0 ] 0
+ILSW Fwd_DMA [0 ] 0
+ILSW Inv [0 ] 0
+ILSW L1_WBCLEANDATA [0 ] 0
+ILSW Unblock [0 ] 0
+ILSW L2_Replacement [0 ] 0
+
+IW L1_GETS [0 ] 0
+IW L1_GETX [0 ] 0
+IW L1_PUTO [0 ] 0
+IW L1_PUTX [0 ] 0
+IW L1_PUTS_only [0 ] 0
+IW L1_PUTS [0 ] 0
+IW Fwd_GETX [0 ] 0
+IW Fwd_GETS [0 ] 0
+IW Fwd_DMA [0 ] 0
+IW Inv [0 ] 0
+IW L1_WBCLEANDATA [0 ] 0
+IW L2_Replacement [0 ] 0
+
+OW L1_GETS [0 ] 0
+OW L1_GETX [0 ] 0
+OW L1_PUTO [0 ] 0
+OW L1_PUTX [0 ] 0
+OW L1_PUTS_only [0 ] 0
+OW L1_PUTS [0 ] 0
+OW Fwd_GETX [0 ] 0
+OW Fwd_GETS [0 ] 0
+OW Fwd_DMA [0 ] 0
+OW Inv [0 ] 0
+OW Unblock [0 ] 0
+OW L2_Replacement [0 ] 0
+
+SW L1_GETS [0 ] 0
+SW L1_GETX [0 ] 0
+SW L1_PUTO [0 ] 0
+SW L1_PUTX [0 ] 0
+SW L1_PUTS_only [0 ] 0
+SW L1_PUTS [0 ] 0
+SW Fwd_GETX [0 ] 0
+SW Fwd_GETS [0 ] 0
+SW Fwd_DMA [0 ] 0
+SW Inv [0 ] 0
+SW Unblock [0 ] 0
+SW L2_Replacement [0 ] 0
+
+OXW L1_GETS [0 ] 0
+OXW L1_GETX [0 ] 0
+OXW L1_PUTO [0 ] 0
+OXW L1_PUTX [0 ] 0
+OXW L1_PUTS_only [0 ] 0
+OXW L1_PUTS [0 ] 0
+OXW Fwd_GETX [0 ] 0
+OXW Fwd_GETS [0 ] 0
+OXW Fwd_DMA [0 ] 0
+OXW Inv [0 ] 0
+OXW Unblock [0 ] 0
+OXW L2_Replacement [0 ] 0
+
+OLSXW L1_GETS [0 ] 0
+OLSXW L1_GETX [0 ] 0
+OLSXW L1_PUTO [0 ] 0
+OLSXW L1_PUTX [0 ] 0
+OLSXW L1_PUTS_only [0 ] 0
+OLSXW L1_PUTS [0 ] 0
+OLSXW Fwd_GETX [0 ] 0
+OLSXW Fwd_GETS [0 ] 0
+OLSXW Fwd_DMA [0 ] 0
+OLSXW Inv [0 ] 0
+OLSXW Unblock [0 ] 0
+OLSXW L2_Replacement [0 ] 0
+
+ILXW L1_GETS [0 ] 0
+ILXW L1_GETX [0 ] 0
+ILXW L1_PUTO [0 ] 0
+ILXW L1_PUTX [0 ] 0
+ILXW L1_PUTS_only [0 ] 0
+ILXW L1_PUTS [0 ] 0
+ILXW Fwd_GETX [0 ] 0
+ILXW Fwd_GETS [0 ] 0
+ILXW Fwd_DMA [0 ] 0
+ILXW Inv [0 ] 0
+ILXW Data [0 ] 0
+ILXW L1_WBCLEANDATA [396 ] 396
+ILXW L1_WBDIRTYDATA [106 ] 106
+ILXW Unblock [0 ] 0
+ILXW L2_Replacement [0 ] 0
+
+IFLS L1_GETS [0 ] 0
+IFLS L1_GETX [0 ] 0
+IFLS L1_PUTO [0 ] 0
+IFLS L1_PUTX [0 ] 0
+IFLS L1_PUTS_only [0 ] 0
+IFLS L1_PUTS [0 ] 0
+IFLS Fwd_GETX [0 ] 0
+IFLS Fwd_GETS [0 ] 0
+IFLS Fwd_DMA [0 ] 0
+IFLS Inv [0 ] 0
+IFLS Unblock [0 ] 0
+IFLS L2_Replacement [0 ] 0
+
+IFLO L1_GETS [0 ] 0
+IFLO L1_GETX [0 ] 0
+IFLO L1_PUTO [0 ] 0
+IFLO L1_PUTX [0 ] 0
+IFLO L1_PUTS_only [0 ] 0
+IFLO L1_PUTS [0 ] 0
+IFLO Fwd_GETX [0 ] 0
+IFLO Fwd_GETS [0 ] 0
+IFLO Fwd_DMA [0 ] 0
+IFLO Inv [0 ] 0
+IFLO Unblock [0 ] 0
+IFLO L2_Replacement [0 ] 0
+
+IFLOX L1_GETS [0 ] 0
+IFLOX L1_GETX [0 ] 0
+IFLOX L1_PUTO [0 ] 0
+IFLOX L1_PUTX [0 ] 0
+IFLOX L1_PUTS_only [0 ] 0
+IFLOX L1_PUTS [0 ] 0
+IFLOX Fwd_GETX [0 ] 0
+IFLOX Fwd_GETS [0 ] 0
+IFLOX Fwd_DMA [0 ] 0
+IFLOX Inv [0 ] 0
+IFLOX Unblock [0 ] 0
+IFLOX Exclusive_Unblock [0 ] 0
+IFLOX L2_Replacement [0 ] 0
+
+IFLOXX L1_GETS [0 ] 0
+IFLOXX L1_GETX [0 ] 0
+IFLOXX L1_PUTO [0 ] 0
+IFLOXX L1_PUTX [0 ] 0
+IFLOXX L1_PUTS_only [0 ] 0
+IFLOXX L1_PUTS [0 ] 0
+IFLOXX Fwd_GETX [0 ] 0
+IFLOXX Fwd_GETS [0 ] 0
+IFLOXX Fwd_DMA [0 ] 0
+IFLOXX Inv [0 ] 0
+IFLOXX Unblock [0 ] 0
+IFLOXX Exclusive_Unblock [0 ] 0
+IFLOXX L2_Replacement [0 ] 0
+
+IFLOSX L1_GETS [0 ] 0
+IFLOSX L1_GETX [0 ] 0
+IFLOSX L1_PUTO [0 ] 0
+IFLOSX L1_PUTX [0 ] 0
+IFLOSX L1_PUTS_only [0 ] 0
+IFLOSX L1_PUTS [0 ] 0
+IFLOSX Fwd_GETX [0 ] 0
+IFLOSX Fwd_GETS [0 ] 0
+IFLOSX Fwd_DMA [0 ] 0
+IFLOSX Inv [0 ] 0
+IFLOSX Unblock [0 ] 0
+IFLOSX Exclusive_Unblock [0 ] 0
+IFLOSX L2_Replacement [0 ] 0
+
+IFLXO L1_GETS [0 ] 0
+IFLXO L1_GETX [0 ] 0
+IFLXO L1_PUTO [0 ] 0
+IFLXO L1_PUTX [0 ] 0
+IFLXO L1_PUTS_only [0 ] 0
+IFLXO L1_PUTS [0 ] 0
+IFLXO Fwd_GETX [0 ] 0
+IFLXO Fwd_GETS [0 ] 0
+IFLXO Fwd_DMA [0 ] 0
+IFLXO Inv [0 ] 0
+IFLXO Exclusive_Unblock [0 ] 0
+IFLXO L2_Replacement [0 ] 0
+
+IGS L1_GETS [0 ] 0
+IGS L1_GETX [0 ] 0
+IGS L1_PUTO [0 ] 0
+IGS L1_PUTX [0 ] 0
+IGS L1_PUTS_only [0 ] 0
+IGS L1_PUTS [0 ] 0
+IGS Fwd_GETX [0 ] 0
+IGS Fwd_GETS [0 ] 0
+IGS Fwd_DMA [0 ] 0
+IGS Own_GETX [0 ] 0
+IGS Inv [0 ] 0
+IGS Data [0 ] 0
+IGS Data_Exclusive [383 ] 383
+IGS Unblock [0 ] 0
+IGS Exclusive_Unblock [383 ] 383
+IGS L2_Replacement [0 ] 0
+
+IGM L1_GETS [0 ] 0
+IGM L1_GETX [0 ] 0
+IGM L1_PUTO [0 ] 0
+IGM L1_PUTX [0 ] 0
+IGM L1_PUTS_only [0 ] 0
+IGM L1_PUTS [0 ] 0
+IGM Fwd_GETX [0 ] 0
+IGM Fwd_GETS [0 ] 0
+IGM Fwd_DMA [0 ] 0
+IGM Own_GETX [0 ] 0
+IGM Inv [0 ] 0
+IGM ExtAck [0 ] 0
+IGM Data [44 ] 44
+IGM Data_Exclusive [0 ] 0
+IGM L2_Replacement [0 ] 0
+
+IGMLS L1_GETS [0 ] 0
+IGMLS L1_GETX [0 ] 0
+IGMLS L1_PUTO [0 ] 0
+IGMLS L1_PUTX [0 ] 0
+IGMLS L1_PUTS_only [0 ] 0
+IGMLS L1_PUTS [0 ] 0
+IGMLS Inv [0 ] 0
+IGMLS IntAck [0 ] 0
+IGMLS ExtAck [0 ] 0
+IGMLS All_Acks [0 ] 0
+IGMLS Data [0 ] 0
+IGMLS Data_Exclusive [0 ] 0
+IGMLS L2_Replacement [0 ] 0
+
+IGMO L1_GETS [0 ] 0
+IGMO L1_GETX [0 ] 0
+IGMO L1_PUTO [0 ] 0
+IGMO L1_PUTX [0 ] 0
+IGMO L1_PUTS_only [0 ] 0
+IGMO L1_PUTS [0 ] 0
+IGMO Fwd_GETX [0 ] 0
+IGMO Fwd_GETS [0 ] 0
+IGMO Fwd_DMA [0 ] 0
+IGMO Own_GETX [0 ] 0
+IGMO ExtAck [0 ] 0
+IGMO All_Acks [44 ] 44
+IGMO Exclusive_Unblock [44 ] 44
+IGMO L2_Replacement [0 ] 0
+
+IGMIO L1_GETS [0 ] 0
+IGMIO L1_GETX [0 ] 0
+IGMIO L1_PUTO [0 ] 0
+IGMIO L1_PUTX [0 ] 0
+IGMIO L1_PUTS_only [0 ] 0
+IGMIO L1_PUTS [0 ] 0
+IGMIO Fwd_GETX [0 ] 0
+IGMIO Fwd_GETS [0 ] 0
+IGMIO Fwd_DMA [0 ] 0
+IGMIO Own_GETX [0 ] 0
+IGMIO ExtAck [0 ] 0
+IGMIO All_Acks [0 ] 0
+
+OGMIO L1_GETS [0 ] 0
+OGMIO L1_GETX [0 ] 0
+OGMIO L1_PUTO [0 ] 0
+OGMIO L1_PUTX [0 ] 0
+OGMIO L1_PUTS_only [0 ] 0
+OGMIO L1_PUTS [0 ] 0
+OGMIO Fwd_GETX [0 ] 0
+OGMIO Fwd_GETS [0 ] 0
+OGMIO Fwd_DMA [0 ] 0
+OGMIO Own_GETX [0 ] 0
+OGMIO ExtAck [0 ] 0
+OGMIO All_Acks [0 ] 0
+
+IGMIOF L1_GETS [0 ] 0
+IGMIOF L1_GETX [0 ] 0
+IGMIOF L1_PUTO [0 ] 0
+IGMIOF L1_PUTX [0 ] 0
+IGMIOF L1_PUTS_only [0 ] 0
+IGMIOF L1_PUTS [0 ] 0
+IGMIOF IntAck [0 ] 0
+IGMIOF All_Acks [0 ] 0
+IGMIOF Data_Exclusive [0 ] 0
+
+IGMIOFS L1_GETS [0 ] 0
+IGMIOFS L1_GETX [0 ] 0
+IGMIOFS L1_PUTO [0 ] 0
+IGMIOFS L1_PUTX [0 ] 0
+IGMIOFS L1_PUTS_only [0 ] 0
+IGMIOFS L1_PUTS [0 ] 0
+IGMIOFS Fwd_GETX [0 ] 0
+IGMIOFS Fwd_GETS [0 ] 0
+IGMIOFS Fwd_DMA [0 ] 0
+IGMIOFS Inv [0 ] 0
+IGMIOFS Data [0 ] 0
+IGMIOFS L2_Replacement [0 ] 0
+
+OGMIOF L1_GETS [0 ] 0
+OGMIOF L1_GETX [0 ] 0
+OGMIOF L1_PUTO [0 ] 0
+OGMIOF L1_PUTX [0 ] 0
+OGMIOF L1_PUTS_only [0 ] 0
+OGMIOF L1_PUTS [0 ] 0
+OGMIOF IntAck [0 ] 0
+OGMIOF All_Acks [0 ] 0
+
+II L1_GETS [0 ] 0
+II L1_GETX [0 ] 0
+II L1_PUTO [0 ] 0
+II L1_PUTX [0 ] 0
+II L1_PUTS_only [0 ] 0
+II L1_PUTS [0 ] 0
+II IntAck [0 ] 0
+II All_Acks [0 ] 0
+
+MM L1_GETS [0 ] 0
+MM L1_GETX [0 ] 0
+MM L1_PUTO [0 ] 0
+MM L1_PUTX [0 ] 0
+MM L1_PUTS_only [0 ] 0
+MM L1_PUTS [0 ] 0
+MM Fwd_GETX [0 ] 0
+MM Fwd_GETS [0 ] 0
+MM Fwd_DMA [0 ] 0
+MM Inv [0 ] 0
+MM Exclusive_Unblock [14 ] 14
+MM L2_Replacement [0 ] 0
+
+SS L1_GETS [0 ] 0
+SS L1_GETX [0 ] 0
+SS L1_PUTO [0 ] 0
+SS L1_PUTX [0 ] 0
+SS L1_PUTS_only [0 ] 0
+SS L1_PUTS [0 ] 0
+SS Fwd_GETX [0 ] 0
+SS Fwd_GETS [0 ] 0
+SS Fwd_DMA [0 ] 0
+SS Inv [0 ] 0
+SS Unblock [0 ] 0
+SS L2_Replacement [0 ] 0
+
+OO L1_GETS [0 ] 0
+OO L1_GETX [0 ] 0
+OO L1_PUTO [0 ] 0
+OO L1_PUTX [0 ] 0
+OO L1_PUTS_only [0 ] 0
+OO L1_PUTS [0 ] 0
+OO Fwd_GETX [0 ] 0
+OO Fwd_GETS [0 ] 0
+OO Fwd_DMA [0 ] 0
+OO Inv [0 ] 0
+OO Unblock [0 ] 0
+OO Exclusive_Unblock [69 ] 69
+OO L2_Replacement [0 ] 0
+
+OLSS L1_GETS [0 ] 0
+OLSS L1_GETX [0 ] 0
+OLSS L1_PUTO [0 ] 0
+OLSS L1_PUTX [0 ] 0
+OLSS L1_PUTS_only [0 ] 0
+OLSS L1_PUTS [0 ] 0
+OLSS Fwd_GETX [0 ] 0
+OLSS Fwd_GETS [0 ] 0
+OLSS Fwd_DMA [0 ] 0
+OLSS Inv [0 ] 0
+OLSS Unblock [0 ] 0
+OLSS L2_Replacement [0 ] 0
+
+OLSXS L1_GETS [0 ] 0
+OLSXS L1_GETX [0 ] 0
+OLSXS L1_PUTO [0 ] 0
+OLSXS L1_PUTX [0 ] 0
+OLSXS L1_PUTS_only [0 ] 0
+OLSXS L1_PUTS [0 ] 0
+OLSXS Fwd_GETX [0 ] 0
+OLSXS Fwd_GETS [0 ] 0
+OLSXS Fwd_DMA [0 ] 0
+OLSXS Inv [0 ] 0
+OLSXS Unblock [0 ] 0
+OLSXS L2_Replacement [0 ] 0
+
+SLSS L1_GETS [0 ] 0
+SLSS L1_GETX [0 ] 0
+SLSS L1_PUTO [0 ] 0
+SLSS L1_PUTX [0 ] 0
+SLSS L1_PUTS_only [0 ] 0
+SLSS L1_PUTS [0 ] 0
+SLSS Fwd_GETX [0 ] 0
+SLSS Fwd_GETS [0 ] 0
+SLSS Fwd_DMA [0 ] 0
+SLSS Inv [0 ] 0
+SLSS Unblock [0 ] 0
+SLSS L2_Replacement [0 ] 0
+
+OI L1_GETS [0 ] 0
+OI L1_GETX [0 ] 0
+OI L1_PUTO [0 ] 0
+OI L1_PUTX [0 ] 0
+OI L1_PUTS_only [0 ] 0
+OI L1_PUTS [0 ] 0
+OI Fwd_GETX [0 ] 0
+OI Fwd_GETS [0 ] 0
+OI Fwd_DMA [0 ] 0
+OI Writeback_Ack [0 ] 0
+OI Writeback_Nack [0 ] 0
+OI L2_Replacement [0 ] 0
+
+MI L1_GETS [3 ] 3
+MI L1_GETX [0 ] 0
+MI L1_PUTO [0 ] 0
+MI L1_PUTX [0 ] 0
+MI L1_PUTS_only [0 ] 0
+MI L1_PUTS [0 ] 0
+MI Fwd_GETX [0 ] 0
+MI Fwd_GETS [0 ] 0
+MI Fwd_DMA [0 ] 0
+MI Writeback_Ack [411 ] 411
+MI L2_Replacement [0 ] 0
+
+MII L1_GETS [0 ] 0
+MII L1_GETX [0 ] 0
+MII L1_PUTO [0 ] 0
+MII L1_PUTX [0 ] 0
+MII L1_PUTS_only [0 ] 0
+MII L1_PUTS [0 ] 0
+MII Writeback_Ack [0 ] 0
+MII Writeback_Nack [0 ] 0
+MII L2_Replacement [0 ] 0
+
+OLSI L1_GETS [0 ] 0
+OLSI L1_GETX [0 ] 0
+OLSI L1_PUTO [0 ] 0
+OLSI L1_PUTX [0 ] 0
+OLSI L1_PUTS_only [0 ] 0
+OLSI L1_PUTS [0 ] 0
+OLSI Fwd_GETX [0 ] 0
+OLSI Fwd_GETS [0 ] 0
+OLSI Fwd_DMA [0 ] 0
+OLSI Writeback_Ack [0 ] 0
+OLSI L2_Replacement [0 ] 0
+
+ILSI L1_GETS [0 ] 0
+ILSI L1_GETX [0 ] 0
+ILSI L1_PUTO [0 ] 0
+ILSI L1_PUTX [0 ] 0
+ILSI L1_PUTS_only [0 ] 0
+ILSI L1_PUTS [0 ] 0
+ILSI IntAck [0 ] 0
+ILSI All_Acks [0 ] 0
+ILSI Writeback_Ack [0 ] 0
+ILSI L2_Replacement [0 ] 0
+
+Memory controller: system.dir_cntrl0.memBuffer:
memory_total_requests: 504
memory_reads: 427
memory_writes: 77
@@ -1175,201 +1180,200 @@ Memory controller: system.ruby.network.topology.ext_links2.ext_node.memBuffer:
memory_stalls_for_read_read_turnaround: 0
accesses_per_bank: 18 10 0 35 20 20 28 21 5 3 6 4 21 40 20 3 4 5 7 13 10 16 14 41 16 5 5 12 12 18 14 58
- --- Directory 0 ---
+ --- Directory ---
- Event Counts -
-GETX 44
-GETS 383
-PUTX 411
-PUTO 0
-PUTO_SHARERS 0
-Unblock 0
-Last_Unblock 0
-Exclusive_Unblock 426
-Clean_Writeback 334
-Dirty_Writeback 77
-Memory_Data 427
-Memory_Ack 77
-DMA_READ 0
-DMA_WRITE 0
-Data 0
+GETX [44 ] 44
+GETS [383 ] 383
+PUTX [411 ] 411
+PUTO [0 ] 0
+PUTO_SHARERS [0 ] 0
+Unblock [0 ] 0
+Last_Unblock [0 ] 0
+Exclusive_Unblock [426 ] 426
+Clean_Writeback [334 ] 334
+Dirty_Writeback [77 ] 77
+Memory_Data [427 ] 427
+Memory_Ack [77 ] 77
+DMA_READ [0 ] 0
+DMA_WRITE [0 ] 0
+Data [0 ] 0
- Transitions -
-I GETX 44
-I GETS 383
-I PUTX 0 <--
-I PUTO 0 <--
-I Memory_Data 0 <--
-I Memory_Ack 75
-I DMA_READ 0 <--
-I DMA_WRITE 0 <--
-
-S GETX 0 <--
-S GETS 0 <--
-S PUTX 0 <--
-S PUTO 0 <--
-S Memory_Data 0 <--
-S Memory_Ack 0 <--
-S DMA_READ 0 <--
-S DMA_WRITE 0 <--
-
-O GETX 0 <--
-O GETS 0 <--
-O PUTX 0 <--
-O PUTO 0 <--
-O PUTO_SHARERS 0 <--
-O Memory_Data 0 <--
-O Memory_Ack 0 <--
-O DMA_READ 0 <--
-O DMA_WRITE 0 <--
-
-M GETX 0 <--
-M GETS 0 <--
-M PUTX 411
-M PUTO 0 <--
-M PUTO_SHARERS 0 <--
-M Memory_Data 0 <--
-M Memory_Ack 0 <--
-M DMA_READ 0 <--
-M DMA_WRITE 0 <--
-
-IS GETX 0 <--
-IS GETS 0 <--
-IS PUTX 0 <--
-IS PUTO 0 <--
-IS PUTO_SHARERS 0 <--
-IS Unblock 0 <--
-IS Exclusive_Unblock 382
-IS Memory_Data 383
-IS Memory_Ack 1
-IS DMA_READ 0 <--
-IS DMA_WRITE 0 <--
-
-SS GETX 0 <--
-SS GETS 0 <--
-SS PUTX 0 <--
-SS PUTO 0 <--
-SS PUTO_SHARERS 0 <--
-SS Unblock 0 <--
-SS Last_Unblock 0 <--
-SS Memory_Data 0 <--
-SS Memory_Ack 0 <--
-SS DMA_READ 0 <--
-SS DMA_WRITE 0 <--
-
-OO GETX 0 <--
-OO GETS 0 <--
-OO PUTX 0 <--
-OO PUTO 0 <--
-OO PUTO_SHARERS 0 <--
-OO Unblock 0 <--
-OO Last_Unblock 0 <--
-OO Memory_Data 0 <--
-OO Memory_Ack 0 <--
-OO DMA_READ 0 <--
-OO DMA_WRITE 0 <--
-
-MO GETX 0 <--
-MO GETS 0 <--
-MO PUTX 0 <--
-MO PUTO 0 <--
-MO PUTO_SHARERS 0 <--
-MO Unblock 0 <--
-MO Exclusive_Unblock 0 <--
-MO Memory_Data 0 <--
-MO Memory_Ack 0 <--
-MO DMA_READ 0 <--
-MO DMA_WRITE 0 <--
-
-MM GETX 0 <--
-MM GETS 0 <--
-MM PUTX 0 <--
-MM PUTO 0 <--
-MM PUTO_SHARERS 0 <--
-MM Exclusive_Unblock 44
-MM Memory_Data 44
-MM Memory_Ack 1
-MM DMA_READ 0 <--
-MM DMA_WRITE 0 <--
-
-
-MI GETX 0 <--
-MI GETS 0 <--
-MI PUTX 0 <--
-MI PUTO 0 <--
-MI PUTO_SHARERS 0 <--
-MI Unblock 0 <--
-MI Clean_Writeback 334
-MI Dirty_Writeback 77
-MI Memory_Data 0 <--
-MI Memory_Ack 0 <--
-MI DMA_READ 0 <--
-MI DMA_WRITE 0 <--
-
-MIS GETX 0 <--
-MIS GETS 0 <--
-MIS PUTX 0 <--
-MIS PUTO 0 <--
-MIS PUTO_SHARERS 0 <--
-MIS Unblock 0 <--
-MIS Clean_Writeback 0 <--
-MIS Dirty_Writeback 0 <--
-MIS Memory_Data 0 <--
-MIS Memory_Ack 0 <--
-MIS DMA_READ 0 <--
-MIS DMA_WRITE 0 <--
-
-OS GETX 0 <--
-OS GETS 0 <--
-OS PUTX 0 <--
-OS PUTO 0 <--
-OS PUTO_SHARERS 0 <--
-OS Unblock 0 <--
-OS Clean_Writeback 0 <--
-OS Dirty_Writeback 0 <--
-OS Memory_Data 0 <--
-OS Memory_Ack 0 <--
-OS DMA_READ 0 <--
-OS DMA_WRITE 0 <--
-
-OSS GETX 0 <--
-OSS GETS 0 <--
-OSS PUTX 0 <--
-OSS PUTO 0 <--
-OSS PUTO_SHARERS 0 <--
-OSS Unblock 0 <--
-OSS Clean_Writeback 0 <--
-OSS Dirty_Writeback 0 <--
-OSS Memory_Data 0 <--
-OSS Memory_Ack 0 <--
-OSS DMA_READ 0 <--
-OSS DMA_WRITE 0 <--
-
-XI_M GETX 0 <--
-XI_M GETS 0 <--
-XI_M PUTX 0 <--
-XI_M PUTO 0 <--
-XI_M PUTO_SHARERS 0 <--
-XI_M Memory_Data 0 <--
-XI_M Memory_Ack 0 <--
-XI_M DMA_READ 0 <--
-XI_M DMA_WRITE 0 <--
-
-XI_U GETX 0 <--
-XI_U GETS 0 <--
-XI_U PUTX 0 <--
-XI_U PUTO 0 <--
-XI_U PUTO_SHARERS 0 <--
-XI_U Exclusive_Unblock 0 <--
-XI_U Memory_Ack 0 <--
-XI_U DMA_READ 0 <--
-XI_U DMA_WRITE 0 <--
-
-OI_D GETX 0 <--
-OI_D GETS 0 <--
-OI_D PUTX 0 <--
-OI_D PUTO 0 <--
-OI_D PUTO_SHARERS 0 <--
-OI_D DMA_READ 0 <--
-OI_D DMA_WRITE 0 <--
-OI_D Data 0 <--
-
+I GETX [44 ] 44
+I GETS [383 ] 383
+I PUTX [0 ] 0
+I PUTO [0 ] 0
+I Memory_Data [0 ] 0
+I Memory_Ack [75 ] 75
+I DMA_READ [0 ] 0
+I DMA_WRITE [0 ] 0
+
+S GETX [0 ] 0
+S GETS [0 ] 0
+S PUTX [0 ] 0
+S PUTO [0 ] 0
+S Memory_Data [0 ] 0
+S Memory_Ack [0 ] 0
+S DMA_READ [0 ] 0
+S DMA_WRITE [0 ] 0
+
+O GETX [0 ] 0
+O GETS [0 ] 0
+O PUTX [0 ] 0
+O PUTO [0 ] 0
+O PUTO_SHARERS [0 ] 0
+O Memory_Data [0 ] 0
+O Memory_Ack [0 ] 0
+O DMA_READ [0 ] 0
+O DMA_WRITE [0 ] 0
+
+M GETX [0 ] 0
+M GETS [0 ] 0
+M PUTX [411 ] 411
+M PUTO [0 ] 0
+M PUTO_SHARERS [0 ] 0
+M Memory_Data [0 ] 0
+M Memory_Ack [0 ] 0
+M DMA_READ [0 ] 0
+M DMA_WRITE [0 ] 0
+
+IS GETX [0 ] 0
+IS GETS [0 ] 0
+IS PUTX [0 ] 0
+IS PUTO [0 ] 0
+IS PUTO_SHARERS [0 ] 0
+IS Unblock [0 ] 0
+IS Exclusive_Unblock [382 ] 382
+IS Memory_Data [383 ] 383
+IS Memory_Ack [1 ] 1
+IS DMA_READ [0 ] 0
+IS DMA_WRITE [0 ] 0
+
+SS GETX [0 ] 0
+SS GETS [0 ] 0
+SS PUTX [0 ] 0
+SS PUTO [0 ] 0
+SS PUTO_SHARERS [0 ] 0
+SS Unblock [0 ] 0
+SS Last_Unblock [0 ] 0
+SS Memory_Data [0 ] 0
+SS Memory_Ack [0 ] 0
+SS DMA_READ [0 ] 0
+SS DMA_WRITE [0 ] 0
+
+OO GETX [0 ] 0
+OO GETS [0 ] 0
+OO PUTX [0 ] 0
+OO PUTO [0 ] 0
+OO PUTO_SHARERS [0 ] 0
+OO Unblock [0 ] 0
+OO Last_Unblock [0 ] 0
+OO Memory_Data [0 ] 0
+OO Memory_Ack [0 ] 0
+OO DMA_READ [0 ] 0
+OO DMA_WRITE [0 ] 0
+
+MO GETX [0 ] 0
+MO GETS [0 ] 0
+MO PUTX [0 ] 0
+MO PUTO [0 ] 0
+MO PUTO_SHARERS [0 ] 0
+MO Unblock [0 ] 0
+MO Exclusive_Unblock [0 ] 0
+MO Memory_Data [0 ] 0
+MO Memory_Ack [0 ] 0
+MO DMA_READ [0 ] 0
+MO DMA_WRITE [0 ] 0
+
+MM GETX [0 ] 0
+MM GETS [0 ] 0
+MM PUTX [0 ] 0
+MM PUTO [0 ] 0
+MM PUTO_SHARERS [0 ] 0
+MM Exclusive_Unblock [44 ] 44
+MM Memory_Data [44 ] 44
+MM Memory_Ack [1 ] 1
+MM DMA_READ [0 ] 0
+MM DMA_WRITE [0 ] 0
+
+
+MI GETX [0 ] 0
+MI GETS [0 ] 0
+MI PUTX [0 ] 0
+MI PUTO [0 ] 0
+MI PUTO_SHARERS [0 ] 0
+MI Unblock [0 ] 0
+MI Clean_Writeback [334 ] 334
+MI Dirty_Writeback [77 ] 77
+MI Memory_Data [0 ] 0
+MI Memory_Ack [0 ] 0
+MI DMA_READ [0 ] 0
+MI DMA_WRITE [0 ] 0
+
+MIS GETX [0 ] 0
+MIS GETS [0 ] 0
+MIS PUTX [0 ] 0
+MIS PUTO [0 ] 0
+MIS PUTO_SHARERS [0 ] 0
+MIS Unblock [0 ] 0
+MIS Clean_Writeback [0 ] 0
+MIS Dirty_Writeback [0 ] 0
+MIS Memory_Data [0 ] 0
+MIS Memory_Ack [0 ] 0
+MIS DMA_READ [0 ] 0
+MIS DMA_WRITE [0 ] 0
+
+OS GETX [0 ] 0
+OS GETS [0 ] 0
+OS PUTX [0 ] 0
+OS PUTO [0 ] 0
+OS PUTO_SHARERS [0 ] 0
+OS Unblock [0 ] 0
+OS Clean_Writeback [0 ] 0
+OS Dirty_Writeback [0 ] 0
+OS Memory_Data [0 ] 0
+OS Memory_Ack [0 ] 0
+OS DMA_READ [0 ] 0
+OS DMA_WRITE [0 ] 0
+
+OSS GETX [0 ] 0
+OSS GETS [0 ] 0
+OSS PUTX [0 ] 0
+OSS PUTO [0 ] 0
+OSS PUTO_SHARERS [0 ] 0
+OSS Unblock [0 ] 0
+OSS Clean_Writeback [0 ] 0
+OSS Dirty_Writeback [0 ] 0
+OSS Memory_Data [0 ] 0
+OSS Memory_Ack [0 ] 0
+OSS DMA_READ [0 ] 0
+OSS DMA_WRITE [0 ] 0
+
+XI_M GETX [0 ] 0
+XI_M GETS [0 ] 0
+XI_M PUTX [0 ] 0
+XI_M PUTO [0 ] 0
+XI_M PUTO_SHARERS [0 ] 0
+XI_M Memory_Data [0 ] 0
+XI_M Memory_Ack [0 ] 0
+XI_M DMA_READ [0 ] 0
+XI_M DMA_WRITE [0 ] 0
+
+XI_U GETX [0 ] 0
+XI_U GETS [0 ] 0
+XI_U PUTX [0 ] 0
+XI_U PUTO [0 ] 0
+XI_U PUTO_SHARERS [0 ] 0
+XI_U Exclusive_Unblock [0 ] 0
+XI_U Memory_Ack [0 ] 0
+XI_U DMA_READ [0 ] 0
+XI_U DMA_WRITE [0 ] 0
+
+OI_D GETX [0 ] 0
+OI_D GETS [0 ] 0
+OI_D PUTX [0 ] 0
+OI_D PUTO [0 ] 0
+OI_D PUTO_SHARERS [0 ] 0
+OI_D DMA_READ [0 ] 0
+OI_D DMA_WRITE [0 ] 0
+OI_D Data \ No newline at end of file
diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/simout b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/simout
index 52848bd4a..c8e6b0646 100755
--- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/simout
+++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/simout
@@ -5,10 +5,10 @@ The Regents of The University of Michigan
All Rights Reserved
-M5 compiled Jan 28 2010 14:49:51
-M5 revision 6068d4fc30d3+ 6931+ default qtip tip brad/rubycfg_regress_udpate
-M5 started Jan 28 2010 15:08:15
-M5 executing on svvint05
+M5 compiled Aug 5 2010 10:34:54
+M5 revision 1cd2a169499f+ 7535+ default brad/hammer_merge_gets qtip tip
+M5 started Aug 5 2010 10:37:10
+M5 executing on svvint09
command line: build/ALPHA_SE_MOESI_CMP_directory/m5.fast -d build/ALPHA_SE_MOESI_CMP_directory/tests/fast/quick/00.hello/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory -re tests/run.py build/ALPHA_SE_MOESI_CMP_directory/tests/fast/quick/00.hello/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory
Global frequency set at 1000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/stats.txt b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/stats.txt
index b9dc234c1..bc9801bf7 100644
--- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/stats.txt
+++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/stats.txt
@@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
-host_inst_rate 14317 # Simulator instruction rate (inst/s)
-host_mem_usage 214996 # Number of bytes of host memory used
-host_seconds 0.18 # Real time elapsed on the host
-host_tick_rate 477706 # Simulator tick rate (ticks/s)
+host_inst_rate 19822 # Simulator instruction rate (inst/s)
+host_mem_usage 211548 # Number of bytes of host memory used
+host_seconds 0.13 # Real time elapsed on the host
+host_tick_rate 661411 # Simulator tick rate (ticks/s)
sim_freq 1000000000 # Frequency of simulated ticks
sim_insts 2577 # Number of instructions simulated
sim_seconds 0.000086 # Number of seconds simulated
diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/config.ini b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/config.ini
index 2b037e55f..1971d2a44 100644
--- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/config.ini
+++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/config.ini
@@ -5,7 +5,7 @@ dummy=0
[system]
type=System
-children=cpu physmem ruby
+children=cpu dir_cntrl0 l1_cntrl0 l2_cntrl0 physmem ruby
mem_mode=timing
physmem=system.physmem
@@ -32,8 +32,8 @@ progress_interval=0
system=system
tracer=system.cpu.tracer
workload=system.cpu.workload
-dcache_port=system.ruby.network.topology.ext_links0.ext_node.sequencer.port[1]
-icache_port=system.ruby.network.topology.ext_links0.ext_node.sequencer.port[0]
+dcache_port=system.l1_cntrl0.sequencer.port[1]
+icache_port=system.l1_cntrl0.sequencer.port[0]
[system.cpu.dtb]
type=AlphaTLB
@@ -54,7 +54,7 @@ egid=100
env=
errout=cerr
euid=100
-executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/hello/bin/alpha/tru64/hello
+executable=tests/test-progs/hello/bin/alpha/tru64/hello
gid=100
input=cin
max_stack_size=67108864
@@ -65,6 +65,121 @@ simpoint=0
system=system
uid=100
+[system.dir_cntrl0]
+type=Directory_Controller
+children=directory memBuffer
+buffer_size=0
+directory=system.dir_cntrl0.directory
+directory_latency=5
+distributed_persistent=true
+fixed_timeout_latency=100
+l2_select_num_bits=0
+memBuffer=system.dir_cntrl0.memBuffer
+number_of_TBEs=256
+recycle_latency=10
+transitions_per_cycle=32
+version=0
+
+[system.dir_cntrl0.directory]
+type=RubyDirectoryMemory
+map_levels=4
+numa_high_bit=6
+size=134217728
+use_map=false
+version=0
+
+[system.dir_cntrl0.memBuffer]
+type=RubyMemoryControl
+bank_bit_0=8
+bank_busy_time=11
+bank_queue_size=12
+banks_per_rank=8
+basic_bus_busy_time=2
+dimm_bit_0=12
+dimms_per_channel=2
+mem_bus_cycle_multiplier=10
+mem_ctl_latency=12
+mem_fixed_delay=0
+mem_random_arbitrate=0
+rank_bit_0=11
+rank_rank_delay=1
+ranks_per_dimm=2
+read_write_delay=2
+refresh_period=1560
+tFaw=0
+version=0
+
+[system.l1_cntrl0]
+type=L1Cache_Controller
+children=sequencer
+L1DcacheMemory=system.l1_cntrl0.sequencer.dcache
+L1IcacheMemory=system.l1_cntrl0.sequencer.icache
+N_tokens=2
+buffer_size=0
+dynamic_timeout_enabled=true
+fixed_timeout_latency=300
+l1_request_latency=2
+l1_response_latency=2
+l2_select_num_bits=0
+no_mig_atomic=true
+number_of_TBEs=256
+recycle_latency=10
+retry_threshold=1
+sequencer=system.l1_cntrl0.sequencer
+transitions_per_cycle=32
+version=0
+
+[system.l1_cntrl0.sequencer]
+type=RubySequencer
+children=dcache icache
+dcache=system.l1_cntrl0.sequencer.dcache
+deadlock_threshold=500000
+icache=system.l1_cntrl0.sequencer.icache
+max_outstanding_requests=16
+physmem=system.physmem
+using_ruby_tester=false
+version=0
+physMemPort=system.physmem.port[0]
+port=system.cpu.icache_port system.cpu.dcache_port
+
+[system.l1_cntrl0.sequencer.dcache]
+type=RubyCache
+assoc=2
+latency=2
+replacement_policy=PSEUDO_LRU
+size=256
+start_index_bit=6
+
+[system.l1_cntrl0.sequencer.icache]
+type=RubyCache
+assoc=2
+latency=2
+replacement_policy=PSEUDO_LRU
+size=256
+start_index_bit=6
+
+[system.l2_cntrl0]
+type=L2Cache_Controller
+children=L2cacheMemory
+L2cacheMemory=system.l2_cntrl0.L2cacheMemory
+N_tokens=2
+buffer_size=0
+filtering_enabled=true
+l2_request_latency=5
+l2_response_latency=5
+number_of_TBEs=256
+recycle_latency=10
+transitions_per_cycle=32
+version=0
+
+[system.l2_cntrl0.L2cacheMemory]
+type=RubyCache
+assoc=2
+latency=10
+replacement_policy=PSEUDO_LRU
+size=512
+start_index_bit=0
+
[system.physmem]
type=PhysicalMemory
file=
@@ -73,7 +188,7 @@ latency_var=0
null=false
range=0:134217727
zero=false
-port=system.ruby.network.topology.ext_links0.ext_node.sequencer.physMemPort
+port=system.l1_cntrl0.sequencer.physMemPort
[system.ruby]
type=RubySystem
@@ -83,6 +198,7 @@ clock=1
debug=system.ruby.debug
mem_size=134217728
network=system.ruby.network
+no_mem_vec=false
profiler=system.ruby.profiler
random_seed=1234
randomization=false
@@ -100,7 +216,7 @@ verbosity_string=none
[system.ruby.network]
type=SimpleNetwork
children=topology
-adaptive_routing=true
+adaptive_routing=false
buffer_size=0
control_msg_size=8
endpoint_bandwidth=10000
@@ -113,144 +229,34 @@ type=Topology
children=ext_links0 ext_links1 ext_links2 int_links0 int_links1 int_links2
ext_links=system.ruby.network.topology.ext_links0 system.ruby.network.topology.ext_links1 system.ruby.network.topology.ext_links2
int_links=system.ruby.network.topology.int_links0 system.ruby.network.topology.int_links1 system.ruby.network.topology.int_links2
+name=Crossbar
num_int_nodes=4
print_config=false
[system.ruby.network.topology.ext_links0]
type=ExtLink
-children=ext_node
bw_multiplier=64
-ext_node=system.ruby.network.topology.ext_links0.ext_node
+ext_node=system.l1_cntrl0
int_node=0
latency=1
weight=1
-[system.ruby.network.topology.ext_links0.ext_node]
-type=L1Cache_Controller
-children=sequencer
-L1DcacheMemory=system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache
-L1IcacheMemory=system.ruby.network.topology.ext_links0.ext_node.sequencer.icache
-N_tokens=2
-buffer_size=0
-dynamic_timeout_enabled=true
-fixed_timeout_latency=300
-l1_request_latency=2
-l1_response_latency=2
-l2_select_num_bits=0
-number_of_TBEs=256
-recycle_latency=10
-retry_threshold=1
-sequencer=system.ruby.network.topology.ext_links0.ext_node.sequencer
-transitions_per_cycle=32
-version=0
-
-[system.ruby.network.topology.ext_links0.ext_node.sequencer]
-type=RubySequencer
-children=dcache icache
-dcache=system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache
-deadlock_threshold=500000
-icache=system.ruby.network.topology.ext_links0.ext_node.sequencer.icache
-max_outstanding_requests=16
-physmem=system.physmem
-using_ruby_tester=false
-version=0
-physMemPort=system.physmem.port[0]
-port=system.cpu.icache_port system.cpu.dcache_port
-
-[system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache]
-type=RubyCache
-assoc=2
-latency=3
-replacement_policy=PSEUDO_LRU
-size=256
-
-[system.ruby.network.topology.ext_links0.ext_node.sequencer.icache]
-type=RubyCache
-assoc=2
-latency=3
-replacement_policy=PSEUDO_LRU
-size=256
-
[system.ruby.network.topology.ext_links1]
type=ExtLink
-children=ext_node
bw_multiplier=64
-ext_node=system.ruby.network.topology.ext_links1.ext_node
+ext_node=system.l2_cntrl0
int_node=1
latency=1
weight=1
-[system.ruby.network.topology.ext_links1.ext_node]
-type=L2Cache_Controller
-children=L2cacheMemory
-L2cacheMemory=system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory
-N_tokens=2
-buffer_size=0
-filtering_enabled=true
-l2_request_latency=10
-l2_response_latency=10
-number_of_TBEs=256
-recycle_latency=10
-transitions_per_cycle=32
-version=0
-
-[system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory]
-type=RubyCache
-assoc=2
-latency=15
-replacement_policy=PSEUDO_LRU
-size=512
-
[system.ruby.network.topology.ext_links2]
type=ExtLink
-children=ext_node
bw_multiplier=64
-ext_node=system.ruby.network.topology.ext_links2.ext_node
+ext_node=system.dir_cntrl0
int_node=2
latency=1
weight=1
-[system.ruby.network.topology.ext_links2.ext_node]
-type=Directory_Controller
-children=directory memBuffer
-buffer_size=0
-directory=system.ruby.network.topology.ext_links2.ext_node.directory
-directory_latency=6
-distributed_persistent=true
-fixed_timeout_latency=300
-l2_select_num_bits=0
-memBuffer=system.ruby.network.topology.ext_links2.ext_node.memBuffer
-number_of_TBEs=256
-recycle_latency=10
-transitions_per_cycle=32
-version=0
-
-[system.ruby.network.topology.ext_links2.ext_node.directory]
-type=RubyDirectoryMemory
-size=134217728
-version=0
-
-[system.ruby.network.topology.ext_links2.ext_node.memBuffer]
-type=RubyMemoryControl
-bank_bit_0=8
-bank_busy_time=11
-bank_queue_size=12
-banks_per_rank=8
-basic_bus_busy_time=2
-dimm_bit_0=12
-dimms_per_channel=2
-mem_bus_cycle_multiplier=10
-mem_ctl_latency=12
-mem_fixed_delay=0
-mem_random_arbitrate=0
-rank_bit_0=11
-rank_rank_delay=1
-ranks_per_dimm=2
-read_write_delay=2
-refresh_period=1560
-tFaw=0
-version=0
-
[system.ruby.network.topology.int_links0]
type=IntLink
bw_multiplier=16
diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/ruby.stats b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/ruby.stats
index 3eaa7bb2f..dbdcc6601 100644
--- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/ruby.stats
+++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/ruby.stats
@@ -13,12 +13,12 @@ RubySystem config:
Network Configuration
---------------------
network: SIMPLE_NETWORK
-topology:
+topology: Crossbar
virtual_net_0: active, ordered
virtual_net_1: active, unordered
-virtual_net_2: active, ordered
-virtual_net_3: active, unordered
+virtual_net_2: active, unordered
+virtual_net_3: active, ordered
virtual_net_4: active, unordered
virtual_net_5: active, ordered
virtual_net_6: inactive
@@ -34,7 +34,7 @@ periodic_stats_period: 1000000
================ End RubySystem Configuration Print ================
-Real time: Jan/28/2010 15:55:46
+Real time: Aug/05/2010 10:43:25
Profiler Stats
--------------
@@ -43,31 +43,20 @@ Elapsed_time_in_minutes: 0
Elapsed_time_in_hours: 0
Elapsed_time_in_days: 0
-Virtual_time_in_seconds: 0.35
-Virtual_time_in_minutes: 0.00583333
-Virtual_time_in_hours: 9.72222e-05
-Virtual_time_in_days: 4.05093e-06
+Virtual_time_in_seconds: 0.25
+Virtual_time_in_minutes: 0.00416667
+Virtual_time_in_hours: 6.94444e-05
+Virtual_time_in_days: 2.89352e-06
-Ruby_current_time: 90308
+Ruby_current_time: 92099
Ruby_start_time: 0
-Ruby_cycles: 90308
+Ruby_cycles: 92099
-mbytes_resident: 33.1172
-mbytes_total: 33.125
+mbytes_resident: 33.5859
+mbytes_total: 33.5938
resident_ratio: 1
-Total_misses: 0
-total_misses: 0 [ 0 ]
-user_misses: 0 [ 0 ]
-supervisor_misses: 0 [ 0 ]
-
-ruby_cycles_executed: 90309 [ 90309 ]
-
-transactions_started: 0 [ 0 ]
-transactions_ended: 0 [ 0 ]
-cycles_per_transaction: 0 [ 0 ]
-misses_per_transaction: 0 [ 0 ]
-
+ruby_cycles_executed: [ 92100 ]
Busy Controller Counts:
L1Cache-0:0
@@ -81,10 +70,32 @@ sequencer_requests_outstanding: [binsize: 1 max: 1 count: 3295 average: 1 |
All Non-Zero Cycle Demand Cache Accesses
----------------------------------------
-miss_latency: [binsize: 2 max: 283 count: 3294 average: 26.4159 | standard deviation: 58.1846 | 0 2776 0 0 0 0 0 0 0 0 0 0 0 76 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 89 61 81 78 45 5 4 1 0 2 20 13 13 11 10 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
-miss_latency_1: [binsize: 2 max: 283 count: 2585 average: 19.2785 | standard deviation: 49.8133 | 0 2315 0 0 0 0 0 0 0 0 0 0 0 26 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 44 44 38 49 22 3 4 0 0 0 9 11 3 8 6 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
-miss_latency_2: [binsize: 2 max: 273 count: 415 average: 66.3494 | standard deviation: 81.4668 | 0 233 0 0 0 0 0 0 0 0 0 0 0 33 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 15 34 18 20 1 0 1 0 2 6 2 10 2 2 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
-miss_latency_3: [binsize: 2 max: 259 count: 294 average: 32.8027 | standard deviation: 63.5503 | 0 228 0 0 0 0 0 0 0 0 0 0 0 17 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 14 2 9 11 3 1 0 0 0 0 5 0 0 1 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency: [binsize: 2 max: 293 count: 3294 average: 26.9596 | standard deviation: 59.7209 | 0 2781 0 0 0 0 0 0 0 0 23 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 79 76 50 53 117 4 3 4 1 6 13 21 19 9 22 0 1 0 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 2 0 1 1 3 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency_IFETCH: [binsize: 2 max: 293 count: 2585 average: 18.7741 | standard deviation: 50.0281 | 0 2315 0 0 0 0 0 0 0 0 9 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 38 49 27 34 54 2 1 3 1 3 3 15 14 5 9 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency_LD: [binsize: 2 max: 277 count: 415 average: 72.1108 | standard deviation: 82.9193 | 0 233 0 0 0 0 0 0 0 0 9 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 35 15 18 15 50 1 2 0 0 2 10 4 3 2 10 0 0 0 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency_ST: [binsize: 2 max: 277 count: 294 average: 35.1973 | standard deviation: 68.9222 | 0 233 0 0 0 0 0 0 0 0 5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 6 12 5 4 13 1 0 1 0 1 0 2 2 2 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency_L1Cache: [binsize: 1 max: 2 count: 2781 average: 2 | standard deviation: 0 | 0 0 2781 ]
+miss_latency_L2Cache: [binsize: 1 max: 21 count: 23 average: 21 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 23 ]
+miss_latency_Directory: [binsize: 2 max: 293 count: 490 average: 168.898 | standard deviation: 16.9003 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 79 76 50 53 117 4 3 4 1 6 13 21 19 9 22 0 1 0 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 2 0 1 1 3 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency_wCC_issue_to_initial_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+miss_latency_wCC_initial_forward_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+miss_latency_wCC_forward_to_first_response: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+miss_latency_wCC_first_response_to_completion: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+imcomplete_wCC_Times: 0
+miss_latency_dir_issue_to_initial_request: [binsize: 1 max: 0 count: 1 average: 0 | standard deviation: 0 | 1 ]
+miss_latency_dir_initial_forward_request: [binsize: 1 max: 0 count: 1 average: 0 | standard deviation: 0 | 1 ]
+miss_latency_dir_forward_to_first_response: [binsize: 1 max: 0 count: 1 average: 0 | standard deviation: 0 | 1 ]
+miss_latency_dir_first_response_to_completion: [binsize: 1 max: 169 count: 1 average: 169 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ]
+imcomplete_dir_Times: 489
+miss_latency_IFETCH_L1Cache: [binsize: 1 max: 2 count: 2315 average: 2 | standard deviation: 0 | 0 0 2315 ]
+miss_latency_IFETCH_L2Cache: [binsize: 1 max: 21 count: 9 average: 21 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 9 ]
+miss_latency_IFETCH_Directory: [binsize: 2 max: 293 count: 261 average: 167.479 | standard deviation: 13.0564 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 38 49 27 34 54 2 1 3 1 3 3 15 14 5 9 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency_LD_L1Cache: [binsize: 1 max: 2 count: 233 average: 2 | standard deviation: 0 | 0 0 233 ]
+miss_latency_LD_L2Cache: [binsize: 1 max: 21 count: 9 average: 21 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 9 ]
+miss_latency_LD_Directory: [binsize: 2 max: 277 count: 173 average: 169.197 | standard deviation: 16.5371 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 35 15 18 15 50 1 2 0 0 2 10 4 3 2 10 0 0 0 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency_ST_L1Cache: [binsize: 1 max: 2 count: 233 average: 2 | standard deviation: 0 | 0 0 233 ]
+miss_latency_ST_L2Cache: [binsize: 1 max: 21 count: 5 average: 21 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5 ]
+miss_latency_ST_Directory: [binsize: 2 max: 277 count: 56 average: 174.589 | standard deviation: 28.9061 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 6 12 5 4 13 1 0 1 0 1 0 2 2 2 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
All Non-Zero Cycle SW Prefetch Requests
------------------------------------
@@ -116,8 +127,8 @@ Resource Usage
page_size: 4096
user_time: 0
system_time: 0
-page_reclaims: 7136
-page_faults: 2141
+page_reclaims: 7341
+page_faults: 2084
swaps: 0
block_inputs: 0
block_outputs: 0
@@ -125,788 +136,896 @@ block_outputs: 0
Network Stats
-------------
+total_msg_count_Request_Control: 3012 24096
+total_msg_count_Response_Data: 1470 105840
+total_msg_count_ResponseL2hit_Data: 69 4968
+total_msg_count_Writeback_Data: 1782 128304
+total_msg_count_Writeback_Control: 1206 9648
+total_msgs: 7539 total_bytes: 272856
+
switch_0_inlinks: 2
switch_0_outlinks: 2
-links_utilized_percent_switch_0: 0.160659
- links_utilized_percent_switch_0_link_0: 0.0646399 bw: 640000 base_latency: 1
- links_utilized_percent_switch_0_link_1: 0.256677 bw: 160000 base_latency: 1
+links_utilized_percent_switch_0: 0.167897
+ links_utilized_percent_switch_0_link_0: 0.0626635 bw: 640000 base_latency: 1
+ links_utilized_percent_switch_0_link_1: 0.27313 bw: 160000 base_latency: 1
- outgoing_messages_switch_0_link_0_Response_Data: 442 31824 [ 0 442 0 0 0 0 0 0 0 0 ] base_latency: 1
- outgoing_messages_switch_0_link_0_ResponseL2hit_Data: 76 5472 [ 0 76 0 0 0 0 0 0 0 0 ] base_latency: 1
- outgoing_messages_switch_0_link_0_Response_Control: 8 64 [ 0 8 0 0 0 0 0 0 0 0 ] base_latency: 1
- outgoing_messages_switch_0_link_1_Request_Control: 518 4144 [ 0 0 0 0 518 0 0 0 0 0 ] base_latency: 1
- outgoing_messages_switch_0_link_1_Writeback_Data: 452 32544 [ 0 452 0 0 0 0 0 0 0 0 ] base_latency: 1
- outgoing_messages_switch_0_link_1_Writeback_Control: 50 400 [ 0 50 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_0_link_0_Response_Data: 490 35280 [ 0 0 0 0 490 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_0_link_0_ResponseL2hit_Data: 23 1656 [ 0 0 0 0 23 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_0_link_1_Request_Control: 513 4104 [ 0 513 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_0_link_1_Writeback_Data: 502 36144 [ 0 0 0 0 502 0 0 0 0 0 ] base_latency: 1
switch_1_inlinks: 2
switch_1_outlinks: 2
-links_utilized_percent_switch_1: 0.0939286
- links_utilized_percent_switch_1_link_0: 0.0641693 bw: 640000 base_latency: 1
- links_utilized_percent_switch_1_link_1: 0.123688 bw: 160000 base_latency: 1
-
- outgoing_messages_switch_1_link_0_Request_Control: 518 4144 [ 0 0 0 0 518 0 0 0 0 0 ] base_latency: 1
- outgoing_messages_switch_1_link_0_Writeback_Data: 452 32544 [ 0 452 0 0 0 0 0 0 0 0 ] base_latency: 1
- outgoing_messages_switch_1_link_0_Writeback_Control: 50 400 [ 0 50 0 0 0 0 0 0 0 0 ] base_latency: 1
- outgoing_messages_switch_1_link_1_Request_Control: 447 3576 [ 0 0 0 447 0 0 0 0 0 0 ] base_latency: 1
- outgoing_messages_switch_1_link_1_ResponseL2hit_Data: 76 5472 [ 0 76 0 0 0 0 0 0 0 0 ] base_latency: 1
- outgoing_messages_switch_1_link_1_Response_Control: 8 64 [ 0 8 0 0 0 0 0 0 0 0 ] base_latency: 1
- outgoing_messages_switch_1_link_1_Writeback_Data: 81 5832 [ 0 81 0 0 0 0 0 0 0 0 ] base_latency: 1
- outgoing_messages_switch_1_link_1_Writeback_Control: 366 2928 [ 0 366 0 0 0 0 0 0 0 0 ] base_latency: 1
+links_utilized_percent_switch_1: 0.0864762
+ links_utilized_percent_switch_1_link_0: 0.0682825 bw: 640000 base_latency: 1
+ links_utilized_percent_switch_1_link_1: 0.10467 bw: 160000 base_latency: 1
+
+ outgoing_messages_switch_1_link_0_Request_Control: 513 4104 [ 0 513 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_1_link_0_Writeback_Data: 502 36144 [ 0 0 0 0 502 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_1_link_1_Request_Control: 491 3928 [ 0 0 491 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_1_link_1_ResponseL2hit_Data: 23 1656 [ 0 0 0 0 23 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_1_link_1_Writeback_Data: 92 6624 [ 0 0 0 0 92 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_1_link_1_Writeback_Control: 402 3216 [ 0 0 0 0 402 0 0 0 0 0 ] base_latency: 1
switch_2_inlinks: 2
switch_2_outlinks: 2
-links_utilized_percent_switch_2: 0.120795
- links_utilized_percent_switch_2_link_0: 0.0213436 bw: 640000 base_latency: 1
- links_utilized_percent_switch_2_link_1: 0.220246 bw: 160000 base_latency: 1
+links_utilized_percent_switch_2: 0.131387
+ links_utilized_percent_switch_2_link_0: 0.023358 bw: 640000 base_latency: 1
+ links_utilized_percent_switch_2_link_1: 0.239416 bw: 160000 base_latency: 1
- outgoing_messages_switch_2_link_0_Request_Control: 447 3576 [ 0 0 0 447 0 0 0 0 0 0 ] base_latency: 1
- outgoing_messages_switch_2_link_0_Writeback_Data: 81 5832 [ 0 81 0 0 0 0 0 0 0 0 ] base_latency: 1
- outgoing_messages_switch_2_link_0_Writeback_Control: 366 2928 [ 0 366 0 0 0 0 0 0 0 0 ] base_latency: 1
- outgoing_messages_switch_2_link_1_Response_Data: 442 31824 [ 0 442 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_2_link_0_Request_Control: 491 3928 [ 0 0 491 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_2_link_0_Writeback_Data: 92 6624 [ 0 0 0 0 92 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_2_link_0_Writeback_Control: 402 3216 [ 0 0 0 0 402 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_2_link_1_Response_Data: 490 35280 [ 0 0 0 0 490 0 0 0 0 0 ] base_latency: 1
switch_3_inlinks: 3
switch_3_outlinks: 3
-links_utilized_percent_switch_3: 0.200204
- links_utilized_percent_switch_3_link_0: 0.25856 bw: 160000 base_latency: 1
- links_utilized_percent_switch_3_link_1: 0.256677 bw: 160000 base_latency: 1
- links_utilized_percent_switch_3_link_2: 0.0853745 bw: 160000 base_latency: 1
-
- outgoing_messages_switch_3_link_0_Response_Data: 442 31824 [ 0 442 0 0 0 0 0 0 0 0 ] base_latency: 1
- outgoing_messages_switch_3_link_0_ResponseL2hit_Data: 76 5472 [ 0 76 0 0 0 0 0 0 0 0 ] base_latency: 1
- outgoing_messages_switch_3_link_0_Response_Control: 8 64 [ 0 8 0 0 0 0 0 0 0 0 ] base_latency: 1
- outgoing_messages_switch_3_link_1_Request_Control: 518 4144 [ 0 0 0 0 518 0 0 0 0 0 ] base_latency: 1
- outgoing_messages_switch_3_link_1_Writeback_Data: 452 32544 [ 0 452 0 0 0 0 0 0 0 0 ] base_latency: 1
- outgoing_messages_switch_3_link_1_Writeback_Control: 50 400 [ 0 50 0 0 0 0 0 0 0 0 ] base_latency: 1
- outgoing_messages_switch_3_link_2_Request_Control: 447 3576 [ 0 0 0 447 0 0 0 0 0 0 ] base_latency: 1
- outgoing_messages_switch_3_link_2_Writeback_Data: 81 5832 [ 0 81 0 0 0 0 0 0 0 0 ] base_latency: 1
- outgoing_messages_switch_3_link_2_Writeback_Control: 366 2928 [ 0 366 0 0 0 0 0 0 0 0 ] base_latency: 1
-
-Cache Stats: system.ruby.network.topology.ext_links0.ext_node.sequencer.icache
- system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_misses: 0
- system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_demand_misses: 0
- system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_prefetches: 0
- system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_sw_prefetches: 0
- system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_hw_prefetches: 0
- system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_misses_per_transaction: nan
-
- system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
-
-Cache Stats: system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache
- system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_misses: 0
- system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_demand_misses: 0
- system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_prefetches: 0
- system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_sw_prefetches: 0
- system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_hw_prefetches: 0
- system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_misses_per_transaction: nan
-
- system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
-
- --- L1Cache 0 ---
+links_utilized_percent_switch_3: 0.205739
+ links_utilized_percent_switch_3_link_0: 0.250654 bw: 160000 base_latency: 1
+ links_utilized_percent_switch_3_link_1: 0.27313 bw: 160000 base_latency: 1
+ links_utilized_percent_switch_3_link_2: 0.0934321 bw: 160000 base_latency: 1
+
+ outgoing_messages_switch_3_link_0_Response_Data: 490 35280 [ 0 0 0 0 490 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_3_link_0_ResponseL2hit_Data: 23 1656 [ 0 0 0 0 23 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_3_link_1_Request_Control: 513 4104 [ 0 513 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_3_link_1_Writeback_Data: 502 36144 [ 0 0 0 0 502 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_3_link_2_Request_Control: 491 3928 [ 0 0 491 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_3_link_2_Writeback_Data: 92 6624 [ 0 0 0 0 92 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_3_link_2_Writeback_Control: 402 3216 [ 0 0 0 0 402 0 0 0 0 0 ] base_latency: 1
+
+Cache Stats: system.l1_cntrl0.sequencer.icache
+ system.l1_cntrl0.sequencer.icache_total_misses: 270
+ system.l1_cntrl0.sequencer.icache_total_demand_misses: 270
+ system.l1_cntrl0.sequencer.icache_total_prefetches: 0
+ system.l1_cntrl0.sequencer.icache_total_sw_prefetches: 0
+ system.l1_cntrl0.sequencer.icache_total_hw_prefetches: 0
+
+ system.l1_cntrl0.sequencer.icache_request_type_IFETCH: 100%
+
+ system.l1_cntrl0.sequencer.icache_access_mode_type_SupervisorMode: 270 100%
+
+Cache Stats: system.l1_cntrl0.sequencer.dcache
+ system.l1_cntrl0.sequencer.dcache_total_misses: 243
+ system.l1_cntrl0.sequencer.dcache_total_demand_misses: 243
+ system.l1_cntrl0.sequencer.dcache_total_prefetches: 0
+ system.l1_cntrl0.sequencer.dcache_total_sw_prefetches: 0
+ system.l1_cntrl0.sequencer.dcache_total_hw_prefetches: 0
+
+ system.l1_cntrl0.sequencer.dcache_request_type_LD: 74.8971%
+ system.l1_cntrl0.sequencer.dcache_request_type_ST: 25.1029%
+
+ system.l1_cntrl0.sequencer.dcache_access_mode_type_SupervisorMode: 243 100%
+
+ --- L1Cache ---
- Event Counts -
-Load 415
-Ifetch 2585
-Store 294
-L1_Replacement 502
-Data_Shared 59
-Data_Owner 0
-Data_All_Tokens 459
-Ack 8
-Ack_All_Tokens 0
-Transient_GETX 0
-Transient_Local_GETX 0
-Transient_GETS 0
-Transient_Local_GETS 0
-Transient_GETS_Last_Token 0
-Transient_Local_GETS_Last_Token 0
-Persistent_GETX 0
-Persistent_GETS 0
-Own_Lock_or_Unlock 0
-Request_Timeout 0
-Use_TimeoutStarverX 0
-Use_TimeoutStarverS 0
-Use_TimeoutNoStarvers 458
+Load [415 ] 415
+Ifetch [2585 ] 2585
+Store [294 ] 294
+Atomic [0 ] 0
+L1_Replacement [506 ] 506
+Data_Shared [18 ] 18
+Data_Owner [0 ] 0
+Data_All_Tokens [495 ] 495
+Ack [0 ] 0
+Ack_All_Tokens [0 ] 0
+Transient_GETX [0 ] 0
+Transient_Local_GETX [0 ] 0
+Transient_GETS [0 ] 0
+Transient_Local_GETS [0 ] 0
+Transient_GETS_Last_Token [0 ] 0
+Transient_Local_GETS_Last_Token [0 ] 0
+Persistent_GETX [0 ] 0
+Persistent_GETS [0 ] 0
+Persistent_GETS_Last_Token [0 ] 0
+Own_Lock_or_Unlock [0 ] 0
+Request_Timeout [0 ] 0
+Use_TimeoutStarverX [0 ] 0
+Use_TimeoutStarverS [0 ] 0
+Use_TimeoutNoStarvers [494 ] 494
+Use_TimeoutNoStarvers_NoMig [0 ] 0
- Transitions -
-NP Load 182
-NP Ifetch 270
-NP Store 58
-NP Data_Shared 0 <--
-NP Data_Owner 0 <--
-NP Data_All_Tokens 0 <--
-NP Ack 0 <--
-NP Transient_GETX 0 <--
-NP Transient_Local_GETX 0 <--
-NP Transient_GETS 0 <--
-NP Transient_Local_GETS 0 <--
-NP Persistent_GETX 0 <--
-NP Persistent_GETS 0 <--
-NP Own_Lock_or_Unlock 0 <--
-
-I Load 0 <--
-I Ifetch 0 <--
-I Store 0 <--
-I L1_Replacement 0 <--
-I Data_Shared 0 <--
-I Data_Owner 0 <--
-I Data_All_Tokens 0 <--
-I Ack 0 <--
-I Transient_GETX 0 <--
-I Transient_Local_GETX 0 <--
-I Transient_GETS 0 <--
-I Transient_Local_GETS 0 <--
-I Transient_GETS_Last_Token 0 <--
-I Transient_Local_GETS_Last_Token 0 <--
-I Persistent_GETX 0 <--
-I Persistent_GETS 0 <--
-I Own_Lock_or_Unlock 0 <--
-
-S Load 30
-S Ifetch 188
-S Store 8
-S L1_Replacement 50
-S Data_Shared 0 <--
-S Data_Owner 0 <--
-S Data_All_Tokens 0 <--
-S Ack 0 <--
-S Transient_GETX 0 <--
-S Transient_Local_GETX 0 <--
-S Transient_GETS 0 <--
-S Transient_Local_GETS 0 <--
-S Transient_GETS_Last_Token 0 <--
-S Transient_Local_GETS_Last_Token 0 <--
-S Persistent_GETX 0 <--
-S Persistent_GETS 0 <--
-S Own_Lock_or_Unlock 0 <--
-
-O Load 0 <--
-O Ifetch 0 <--
-O Store 0 <--
-O L1_Replacement 0 <--
-O Data_Shared 0 <--
-O Data_All_Tokens 0 <--
-O Ack 0 <--
-O Ack_All_Tokens 0 <--
-O Transient_GETX 0 <--
-O Transient_Local_GETX 0 <--
-O Transient_GETS 0 <--
-O Transient_Local_GETS 0 <--
-O Transient_GETS_Last_Token 0 <--
-O Transient_Local_GETS_Last_Token 0 <--
-O Persistent_GETX 0 <--
-O Persistent_GETS 0 <--
-O Own_Lock_or_Unlock 0 <--
-
-M Load 67
-M Ifetch 1196
-M Store 29
-M L1_Replacement 356
-M Transient_GETX 0 <--
-M Transient_Local_GETX 0 <--
-M Transient_GETS 0 <--
-M Transient_Local_GETS 0 <--
-M Persistent_GETX 0 <--
-M Persistent_GETS 0 <--
-M Own_Lock_or_Unlock 0 <--
-
-MM Load 96
-MM Ifetch 0 <--
-MM Store 111
-MM L1_Replacement 96
-MM Transient_GETX 0 <--
-MM Transient_Local_GETX 0 <--
-MM Transient_GETS 0 <--
-MM Transient_Local_GETS 0 <--
-MM Persistent_GETX 0 <--
-MM Persistent_GETS 0 <--
-MM Own_Lock_or_Unlock 0 <--
-
-M_W Load 34
-M_W Ifetch 931
-M_W Store 3
-M_W L1_Replacement 0 <--
-M_W Transient_GETX 0 <--
-M_W Transient_Local_GETX 0 <--
-M_W Transient_GETS 0 <--
-M_W Transient_Local_GETS 0 <--
-M_W Persistent_GETX 0 <--
-M_W Persistent_GETS 0 <--
-M_W Own_Lock_or_Unlock 0 <--
-M_W Use_TimeoutStarverX 0 <--
-M_W Use_TimeoutStarverS 0 <--
-M_W Use_TimeoutNoStarvers 389
-
-MM_W Load 6
-MM_W Ifetch 0 <--
-MM_W Store 85
-MM_W L1_Replacement 0 <--
-MM_W Transient_GETX 0 <--
-MM_W Transient_Local_GETX 0 <--
-MM_W Transient_GETS 0 <--
-MM_W Transient_Local_GETS 0 <--
-MM_W Persistent_GETX 0 <--
-MM_W Persistent_GETS 0 <--
-MM_W Own_Lock_or_Unlock 0 <--
-MM_W Use_TimeoutStarverX 0 <--
-MM_W Use_TimeoutStarverS 0 <--
-MM_W Use_TimeoutNoStarvers 69
-
-IM Load 0 <--
-IM Ifetch 0 <--
-IM Store 0 <--
-IM L1_Replacement 0 <--
-IM Data_Shared 0 <--
-IM Data_Owner 0 <--
-IM Data_All_Tokens 58
-IM Ack 1
-IM Transient_GETX 0 <--
-IM Transient_Local_GETX 0 <--
-IM Transient_GETS 0 <--
-IM Transient_Local_GETS 0 <--
-IM Transient_GETS_Last_Token 0 <--
-IM Transient_Local_GETS_Last_Token 0 <--
-IM Persistent_GETX 0 <--
-IM Persistent_GETS 0 <--
-IM Own_Lock_or_Unlock 0 <--
-IM Request_Timeout 0 <--
-
-SM Load 0 <--
-SM Ifetch 0 <--
-SM Store 0 <--
-SM L1_Replacement 0 <--
-SM Data_Shared 0 <--
-SM Data_Owner 0 <--
-SM Data_All_Tokens 8
-SM Ack 0 <--
-SM Transient_GETX 0 <--
-SM Transient_Local_GETX 0 <--
-SM Transient_GETS 0 <--
-SM Transient_Local_GETS 0 <--
-SM Transient_GETS_Last_Token 0 <--
-SM Transient_Local_GETS_Last_Token 0 <--
-SM Persistent_GETX 0 <--
-SM Persistent_GETS 0 <--
-SM Own_Lock_or_Unlock 0 <--
-SM Request_Timeout 0 <--
-
-OM Load 0 <--
-OM Ifetch 0 <--
-OM Store 0 <--
-OM L1_Replacement 0 <--
-OM Data_Shared 0 <--
-OM Data_All_Tokens 0 <--
-OM Ack 0 <--
-OM Ack_All_Tokens 0 <--
-OM Transient_GETX 0 <--
-OM Transient_Local_GETX 0 <--
-OM Transient_GETS 0 <--
-OM Transient_Local_GETS 0 <--
-OM Transient_GETS_Last_Token 0 <--
-OM Transient_Local_GETS_Last_Token 0 <--
-OM Persistent_GETX 0 <--
-OM Persistent_GETS 0 <--
-OM Own_Lock_or_Unlock 0 <--
-OM Request_Timeout 0 <--
-
-IS Load 0 <--
-IS Ifetch 0 <--
-IS Store 0 <--
-IS L1_Replacement 0 <--
-IS Data_Shared 59
-IS Data_Owner 0 <--
-IS Data_All_Tokens 393
-IS Ack 7
-IS Transient_GETX 0 <--
-IS Transient_Local_GETX 0 <--
-IS Transient_GETS 0 <--
-IS Transient_Local_GETS 0 <--
-IS Transient_GETS_Last_Token 0 <--
-IS Transient_Local_GETS_Last_Token 0 <--
-IS Persistent_GETX 0 <--
-IS Persistent_GETS 0 <--
-IS Own_Lock_or_Unlock 0 <--
-IS Request_Timeout 0 <--
-
-I_L Load 0 <--
-I_L Ifetch 0 <--
-I_L Store 0 <--
-I_L L1_Replacement 0 <--
-I_L Data_Shared 0 <--
-I_L Data_Owner 0 <--
-I_L Data_All_Tokens 0 <--
-I_L Ack 0 <--
-I_L Transient_GETX 0 <--
-I_L Transient_Local_GETX 0 <--
-I_L Transient_GETS 0 <--
-I_L Transient_Local_GETS 0 <--
-I_L Transient_GETS_Last_Token 0 <--
-I_L Transient_Local_GETS_Last_Token 0 <--
-I_L Persistent_GETX 0 <--
-I_L Persistent_GETS 0 <--
-I_L Own_Lock_or_Unlock 0 <--
-
-S_L Load 0 <--
-S_L Ifetch 0 <--
-S_L Store 0 <--
-S_L L1_Replacement 0 <--
-S_L Data_Shared 0 <--
-S_L Data_Owner 0 <--
-S_L Data_All_Tokens 0 <--
-S_L Ack 0 <--
-S_L Transient_GETX 0 <--
-S_L Transient_Local_GETX 0 <--
-S_L Transient_GETS 0 <--
-S_L Transient_Local_GETS 0 <--
-S_L Transient_GETS_Last_Token 0 <--
-S_L Transient_Local_GETS_Last_Token 0 <--
-S_L Persistent_GETX 0 <--
-S_L Persistent_GETS 0 <--
-S_L Own_Lock_or_Unlock 0 <--
-
-IM_L Load 0 <--
-IM_L Ifetch 0 <--
-IM_L Store 0 <--
-IM_L L1_Replacement 0 <--
-IM_L Data_Shared 0 <--
-IM_L Data_Owner 0 <--
-IM_L Data_All_Tokens 0 <--
-IM_L Ack 0 <--
-IM_L Transient_GETX 0 <--
-IM_L Transient_Local_GETX 0 <--
-IM_L Transient_GETS 0 <--
-IM_L Transient_Local_GETS 0 <--
-IM_L Transient_GETS_Last_Token 0 <--
-IM_L Transient_Local_GETS_Last_Token 0 <--
-IM_L Persistent_GETX 0 <--
-IM_L Persistent_GETS 0 <--
-IM_L Own_Lock_or_Unlock 0 <--
-IM_L Request_Timeout 0 <--
-
-SM_L Load 0 <--
-SM_L Ifetch 0 <--
-SM_L Store 0 <--
-SM_L L1_Replacement 0 <--
-SM_L Data_Shared 0 <--
-SM_L Data_Owner 0 <--
-SM_L Data_All_Tokens 0 <--
-SM_L Ack 0 <--
-SM_L Transient_GETX 0 <--
-SM_L Transient_Local_GETX 0 <--
-SM_L Transient_GETS 0 <--
-SM_L Transient_Local_GETS 0 <--
-SM_L Transient_GETS_Last_Token 0 <--
-SM_L Transient_Local_GETS_Last_Token 0 <--
-SM_L Persistent_GETX 0 <--
-SM_L Persistent_GETS 0 <--
-SM_L Own_Lock_or_Unlock 0 <--
-SM_L Request_Timeout 0 <--
-
-IS_L Load 0 <--
-IS_L Ifetch 0 <--
-IS_L Store 0 <--
-IS_L L1_Replacement 0 <--
-IS_L Data_Shared 0 <--
-IS_L Data_Owner 0 <--
-IS_L Data_All_Tokens 0 <--
-IS_L Ack 0 <--
-IS_L Transient_GETX 0 <--
-IS_L Transient_Local_GETX 0 <--
-IS_L Transient_GETS 0 <--
-IS_L Transient_Local_GETS 0 <--
-IS_L Transient_GETS_Last_Token 0 <--
-IS_L Transient_Local_GETS_Last_Token 0 <--
-IS_L Persistent_GETX 0 <--
-IS_L Persistent_GETS 0 <--
-IS_L Own_Lock_or_Unlock 0 <--
-IS_L Request_Timeout 0 <--
-
-Cache Stats: system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory
- system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_total_misses: 0
- system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_total_demand_misses: 0
- system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_total_prefetches: 0
- system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_total_sw_prefetches: 0
- system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_total_hw_prefetches: 0
- system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_misses_per_transaction: nan
-
- system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
-
- --- L2Cache 0 ---
+NP Load [182 ] 182
+NP Ifetch [270 ] 270
+NP Store [58 ] 58
+NP Atomic [0 ] 0
+NP Data_Shared [0 ] 0
+NP Data_Owner [0 ] 0
+NP Data_All_Tokens [0 ] 0
+NP Ack [0 ] 0
+NP Transient_GETX [0 ] 0
+NP Transient_Local_GETX [0 ] 0
+NP Transient_GETS [0 ] 0
+NP Transient_Local_GETS [0 ] 0
+NP Persistent_GETX [0 ] 0
+NP Persistent_GETS [0 ] 0
+NP Persistent_GETS_Last_Token [0 ] 0
+NP Own_Lock_or_Unlock [0 ] 0
+
+I Load [0 ] 0
+I Ifetch [0 ] 0
+I Store [0 ] 0
+I Atomic [0 ] 0
+I L1_Replacement [0 ] 0
+I Data_Shared [0 ] 0
+I Data_Owner [0 ] 0
+I Data_All_Tokens [0 ] 0
+I Ack [0 ] 0
+I Transient_GETX [0 ] 0
+I Transient_Local_GETX [0 ] 0
+I Transient_GETS [0 ] 0
+I Transient_Local_GETS [0 ] 0
+I Transient_GETS_Last_Token [0 ] 0
+I Transient_Local_GETS_Last_Token [0 ] 0
+I Persistent_GETX [0 ] 0
+I Persistent_GETS [0 ] 0
+I Persistent_GETS_Last_Token [0 ] 0
+I Own_Lock_or_Unlock [0 ] 0
+
+S Load [6 ] 6
+S Ifetch [44 ] 44
+S Store [3 ] 3
+S Atomic [0 ] 0
+S L1_Replacement [15 ] 15
+S Data_Shared [0 ] 0
+S Data_Owner [0 ] 0
+S Data_All_Tokens [0 ] 0
+S Ack [0 ] 0
+S Transient_GETX [0 ] 0
+S Transient_Local_GETX [0 ] 0
+S Transient_GETS [0 ] 0
+S Transient_Local_GETS [0 ] 0
+S Transient_GETS_Last_Token [0 ] 0
+S Transient_Local_GETS_Last_Token [0 ] 0
+S Persistent_GETX [0 ] 0
+S Persistent_GETS [0 ] 0
+S Persistent_GETS_Last_Token [0 ] 0
+S Own_Lock_or_Unlock [0 ] 0
+
+O Load [0 ] 0
+O Ifetch [0 ] 0
+O Store [0 ] 0
+O Atomic [0 ] 0
+O L1_Replacement [0 ] 0
+O Data_Shared [0 ] 0
+O Data_All_Tokens [0 ] 0
+O Ack [0 ] 0
+O Ack_All_Tokens [0 ] 0
+O Transient_GETX [0 ] 0
+O Transient_Local_GETX [0 ] 0
+O Transient_GETS [0 ] 0
+O Transient_Local_GETS [0 ] 0
+O Transient_GETS_Last_Token [0 ] 0
+O Transient_Local_GETS_Last_Token [0 ] 0
+O Persistent_GETX [0 ] 0
+O Persistent_GETS [0 ] 0
+O Persistent_GETS_Last_Token [0 ] 0
+O Own_Lock_or_Unlock [0 ] 0
+
+M Load [78 ] 78
+M Ifetch [1233 ] 1233
+M Store [31 ] 31
+M Atomic [0 ] 0
+M L1_Replacement [391 ] 391
+M Transient_GETX [0 ] 0
+M Transient_Local_GETX [0 ] 0
+M Transient_GETS [0 ] 0
+M Transient_Local_GETS [0 ] 0
+M Persistent_GETX [0 ] 0
+M Persistent_GETS [0 ] 0
+M Own_Lock_or_Unlock [0 ] 0
+
+MM Load [98 ] 98
+MM Ifetch [0 ] 0
+MM Store [107 ] 107
+MM Atomic [0 ] 0
+MM L1_Replacement [96 ] 96
+MM Transient_GETX [0 ] 0
+MM Transient_Local_GETX [0 ] 0
+MM Transient_GETS [0 ] 0
+MM Transient_Local_GETS [0 ] 0
+MM Persistent_GETX [0 ] 0
+MM Persistent_GETS [0 ] 0
+MM Own_Lock_or_Unlock [0 ] 0
+
+M_W Load [47 ] 47
+M_W Ifetch [1038 ] 1038
+M_W Store [6 ] 6
+M_W Atomic [0 ] 0
+M_W L1_Replacement [4 ] 4
+M_W Transient_GETX [0 ] 0
+M_W Transient_Local_GETX [0 ] 0
+M_W Transient_GETS [0 ] 0
+M_W Transient_Local_GETS [0 ] 0
+M_W Persistent_GETX [0 ] 0
+M_W Persistent_GETS [0 ] 0
+M_W Own_Lock_or_Unlock [0 ] 0
+M_W Use_TimeoutStarverX [0 ] 0
+M_W Use_TimeoutStarverS [0 ] 0
+M_W Use_TimeoutNoStarvers [427 ] 427
+M_W Use_TimeoutNoStarvers_NoMig [0 ] 0
+
+MM_W Load [4 ] 4
+MM_W Ifetch [0 ] 0
+MM_W Store [89 ] 89
+MM_W Atomic [0 ] 0
+MM_W L1_Replacement [0 ] 0
+MM_W Transient_GETX [0 ] 0
+MM_W Transient_Local_GETX [0 ] 0
+MM_W Transient_GETS [0 ] 0
+MM_W Transient_Local_GETS [0 ] 0
+MM_W Persistent_GETX [0 ] 0
+MM_W Persistent_GETS [0 ] 0
+MM_W Own_Lock_or_Unlock [0 ] 0
+MM_W Use_TimeoutStarverX [0 ] 0
+MM_W Use_TimeoutStarverS [0 ] 0
+MM_W Use_TimeoutNoStarvers [67 ] 67
+MM_W Use_TimeoutNoStarvers_NoMig [0 ] 0
+
+IM Load [0 ] 0
+IM Ifetch [0 ] 0
+IM Store [0 ] 0
+IM Atomic [0 ] 0
+IM L1_Replacement [0 ] 0
+IM Data_Shared [0 ] 0
+IM Data_Owner [0 ] 0
+IM Data_All_Tokens [58 ] 58
+IM Ack [0 ] 0
+IM Transient_GETX [0 ] 0
+IM Transient_Local_GETX [0 ] 0
+IM Transient_GETS [0 ] 0
+IM Transient_Local_GETS [0 ] 0
+IM Transient_GETS_Last_Token [0 ] 0
+IM Transient_Local_GETS_Last_Token [0 ] 0
+IM Persistent_GETX [0 ] 0
+IM Persistent_GETS [0 ] 0
+IM Persistent_GETS_Last_Token [0 ] 0
+IM Own_Lock_or_Unlock [0 ] 0
+IM Request_Timeout [0 ] 0
+
+SM Load [0 ] 0
+SM Ifetch [0 ] 0
+SM Store [0 ] 0
+SM Atomic [0 ] 0
+SM L1_Replacement [0 ] 0
+SM Data_Shared [0 ] 0
+SM Data_Owner [0 ] 0
+SM Data_All_Tokens [3 ] 3
+SM Ack [0 ] 0
+SM Transient_GETX [0 ] 0
+SM Transient_Local_GETX [0 ] 0
+SM Transient_GETS [0 ] 0
+SM Transient_Local_GETS [0 ] 0
+SM Transient_GETS_Last_Token [0 ] 0
+SM Transient_Local_GETS_Last_Token [0 ] 0
+SM Persistent_GETX [0 ] 0
+SM Persistent_GETS [0 ] 0
+SM Persistent_GETS_Last_Token [0 ] 0
+SM Own_Lock_or_Unlock [0 ] 0
+SM Request_Timeout [0 ] 0
+
+OM Load [0 ] 0
+OM Ifetch [0 ] 0
+OM Store [0 ] 0
+OM Atomic [0 ] 0
+OM L1_Replacement [0 ] 0
+OM Data_Shared [0 ] 0
+OM Data_All_Tokens [0 ] 0
+OM Ack [0 ] 0
+OM Ack_All_Tokens [0 ] 0
+OM Transient_GETX [0 ] 0
+OM Transient_Local_GETX [0 ] 0
+OM Transient_GETS [0 ] 0
+OM Transient_Local_GETS [0 ] 0
+OM Transient_GETS_Last_Token [0 ] 0
+OM Transient_Local_GETS_Last_Token [0 ] 0
+OM Persistent_GETX [0 ] 0
+OM Persistent_GETS [0 ] 0
+OM Persistent_GETS_Last_Token [0 ] 0
+OM Own_Lock_or_Unlock [0 ] 0
+OM Request_Timeout [0 ] 0
+
+IS Load [0 ] 0
+IS Ifetch [0 ] 0
+IS Store [0 ] 0
+IS Atomic [0 ] 0
+IS L1_Replacement [0 ] 0
+IS Data_Shared [18 ] 18
+IS Data_Owner [0 ] 0
+IS Data_All_Tokens [434 ] 434
+IS Ack [0 ] 0
+IS Transient_GETX [0 ] 0
+IS Transient_Local_GETX [0 ] 0
+IS Transient_GETS [0 ] 0
+IS Transient_Local_GETS [0 ] 0
+IS Transient_GETS_Last_Token [0 ] 0
+IS Transient_Local_GETS_Last_Token [0 ] 0
+IS Persistent_GETX [0 ] 0
+IS Persistent_GETS [0 ] 0
+IS Persistent_GETS_Last_Token [0 ] 0
+IS Own_Lock_or_Unlock [0 ] 0
+IS Request_Timeout [0 ] 0
+
+I_L Load [0 ] 0
+I_L Ifetch [0 ] 0
+I_L Store [0 ] 0
+I_L Atomic [0 ] 0
+I_L L1_Replacement [0 ] 0
+I_L Data_Shared [0 ] 0
+I_L Data_Owner [0 ] 0
+I_L Data_All_Tokens [0 ] 0
+I_L Ack [0 ] 0
+I_L Transient_GETX [0 ] 0
+I_L Transient_Local_GETX [0 ] 0
+I_L Transient_GETS [0 ] 0
+I_L Transient_Local_GETS [0 ] 0
+I_L Transient_GETS_Last_Token [0 ] 0
+I_L Transient_Local_GETS_Last_Token [0 ] 0
+I_L Persistent_GETX [0 ] 0
+I_L Persistent_GETS [0 ] 0
+I_L Persistent_GETS_Last_Token [0 ] 0
+I_L Own_Lock_or_Unlock [0 ] 0
+
+S_L Load [0 ] 0
+S_L Ifetch [0 ] 0
+S_L Store [0 ] 0
+S_L Atomic [0 ] 0
+S_L L1_Replacement [0 ] 0
+S_L Data_Shared [0 ] 0
+S_L Data_Owner [0 ] 0
+S_L Data_All_Tokens [0 ] 0
+S_L Ack [0 ] 0
+S_L Transient_GETX [0 ] 0
+S_L Transient_Local_GETX [0 ] 0
+S_L Transient_GETS [0 ] 0
+S_L Transient_Local_GETS [0 ] 0
+S_L Transient_GETS_Last_Token [0 ] 0
+S_L Transient_Local_GETS_Last_Token [0 ] 0
+S_L Persistent_GETX [0 ] 0
+S_L Persistent_GETS [0 ] 0
+S_L Persistent_GETS_Last_Token [0 ] 0
+S_L Own_Lock_or_Unlock [0 ] 0
+
+IM_L Load [0 ] 0
+IM_L Ifetch [0 ] 0
+IM_L Store [0 ] 0
+IM_L Atomic [0 ] 0
+IM_L L1_Replacement [0 ] 0
+IM_L Data_Shared [0 ] 0
+IM_L Data_Owner [0 ] 0
+IM_L Data_All_Tokens [0 ] 0
+IM_L Ack [0 ] 0
+IM_L Transient_GETX [0 ] 0
+IM_L Transient_Local_GETX [0 ] 0
+IM_L Transient_GETS [0 ] 0
+IM_L Transient_Local_GETS [0 ] 0
+IM_L Transient_GETS_Last_Token [0 ] 0
+IM_L Transient_Local_GETS_Last_Token [0 ] 0
+IM_L Persistent_GETX [0 ] 0
+IM_L Persistent_GETS [0 ] 0
+IM_L Own_Lock_or_Unlock [0 ] 0
+IM_L Request_Timeout [0 ] 0
+
+SM_L Load [0 ] 0
+SM_L Ifetch [0 ] 0
+SM_L Store [0 ] 0
+SM_L Atomic [0 ] 0
+SM_L L1_Replacement [0 ] 0
+SM_L Data_Shared [0 ] 0
+SM_L Data_Owner [0 ] 0
+SM_L Data_All_Tokens [0 ] 0
+SM_L Ack [0 ] 0
+SM_L Transient_GETX [0 ] 0
+SM_L Transient_Local_GETX [0 ] 0
+SM_L Transient_GETS [0 ] 0
+SM_L Transient_Local_GETS [0 ] 0
+SM_L Transient_GETS_Last_Token [0 ] 0
+SM_L Transient_Local_GETS_Last_Token [0 ] 0
+SM_L Persistent_GETX [0 ] 0
+SM_L Persistent_GETS [0 ] 0
+SM_L Persistent_GETS_Last_Token [0 ] 0
+SM_L Own_Lock_or_Unlock [0 ] 0
+SM_L Request_Timeout [0 ] 0
+
+IS_L Load [0 ] 0
+IS_L Ifetch [0 ] 0
+IS_L Store [0 ] 0
+IS_L Atomic [0 ] 0
+IS_L L1_Replacement [0 ] 0
+IS_L Data_Shared [0 ] 0
+IS_L Data_Owner [0 ] 0
+IS_L Data_All_Tokens [0 ] 0
+IS_L Ack [0 ] 0
+IS_L Transient_GETX [0 ] 0
+IS_L Transient_Local_GETX [0 ] 0
+IS_L Transient_GETS [0 ] 0
+IS_L Transient_Local_GETS [0 ] 0
+IS_L Transient_GETS_Last_Token [0 ] 0
+IS_L Transient_Local_GETS_Last_Token [0 ] 0
+IS_L Persistent_GETX [0 ] 0
+IS_L Persistent_GETS [0 ] 0
+IS_L Own_Lock_or_Unlock [0 ] 0
+IS_L Request_Timeout [0 ] 0
+
+Cache Stats: system.l2_cntrl0.L2cacheMemory
+ system.l2_cntrl0.L2cacheMemory_total_misses: 491
+ system.l2_cntrl0.L2cacheMemory_total_demand_misses: 491
+ system.l2_cntrl0.L2cacheMemory_total_prefetches: 0
+ system.l2_cntrl0.L2cacheMemory_total_sw_prefetches: 0
+ system.l2_cntrl0.L2cacheMemory_total_hw_prefetches: 0
+
+ system.l2_cntrl0.L2cacheMemory_request_type_GETS: 88.391%
+ system.l2_cntrl0.L2cacheMemory_request_type_GETX: 11.609%
+
+ system.l2_cntrl0.L2cacheMemory_access_mode_type_SupervisorMode: 491 100%
+
+ --- L2Cache ---
- Event Counts -
-L1_GETS 445
-L1_GETS_Last_Token 7
-L1_GETX 66
-L1_INV 0
-Transient_GETX 0
-Transient_GETS 0
-Transient_GETS_Last_Token 0
-L2_Replacement 463
-Writeback_Tokens 27
-Writeback_Shared_Data 0
-Writeback_All_Tokens 475
-Writeback_Owned 0
-Data_Shared 0
-Data_Owner 0
-Data_All_Tokens 0
-Ack 0
-Ack_All_Tokens 0
-Persistent_GETX 0
-Persistent_GETS 0
-Own_Lock_or_Unlock 0
+L1_GETS [451 ] 451
+L1_GETS_Last_Token [1 ] 1
+L1_GETX [61 ] 61
+L1_INV [0 ] 0
+Transient_GETX [0 ] 0
+Transient_GETS [0 ] 0
+Transient_GETS_Last_Token [0 ] 0
+L2_Replacement [500 ] 500
+Writeback_Tokens [0 ] 0
+Writeback_Shared_Data [15 ] 15
+Writeback_All_Tokens [487 ] 487
+Writeback_Owned [0 ] 0
+Data_Shared [0 ] 0
+Data_Owner [0 ] 0
+Data_All_Tokens [0 ] 0
+Ack [0 ] 0
+Ack_All_Tokens [0 ] 0
+Persistent_GETX [0 ] 0
+Persistent_GETS [0 ] 0
+Persistent_GETS_Last_Token [0 ] 0
+Own_Lock_or_Unlock [0 ] 0
- Transitions -
-NP L1_GETS 386
-NP L1_GETX 48
-NP L1_INV 0 <--
-NP Transient_GETX 0 <--
-NP Transient_GETS 0 <--
-NP Writeback_Tokens 27
-NP Writeback_Shared_Data 0 <--
-NP Writeback_All_Tokens 444
-NP Writeback_Owned 0 <--
-NP Data_Shared 0 <--
-NP Data_Owner 0 <--
-NP Data_All_Tokens 0 <--
-NP Ack 0 <--
-NP Persistent_GETX 0 <--
-NP Persistent_GETS 0 <--
-NP Own_Lock_or_Unlock 0 <--
-
-I L1_GETS 0 <--
-I L1_GETS_Last_Token 7
-I L1_GETX 1
-I L1_INV 0 <--
-I Transient_GETX 0 <--
-I Transient_GETS 0 <--
-I Transient_GETS_Last_Token 0 <--
-I L2_Replacement 34
-I Writeback_Tokens 0 <--
-I Writeback_Shared_Data 0 <--
-I Writeback_All_Tokens 8
-I Writeback_Owned 0 <--
-I Data_Shared 0 <--
-I Data_Owner 0 <--
-I Data_All_Tokens 0 <--
-I Ack 0 <--
-I Persistent_GETX 0 <--
-I Persistent_GETS 0 <--
-I Own_Lock_or_Unlock 0 <--
-
-S L1_GETS 0 <--
-S L1_GETS_Last_Token 0 <--
-S L1_GETX 0 <--
-S L1_INV 0 <--
-S Transient_GETX 0 <--
-S Transient_GETS 0 <--
-S Transient_GETS_Last_Token 0 <--
-S L2_Replacement 0 <--
-S Writeback_Tokens 0 <--
-S Writeback_Shared_Data 0 <--
-S Writeback_All_Tokens 0 <--
-S Writeback_Owned 0 <--
-S Data_Shared 0 <--
-S Data_Owner 0 <--
-S Data_All_Tokens 0 <--
-S Ack 0 <--
-S Persistent_GETX 0 <--
-S Persistent_GETS 0 <--
-S Own_Lock_or_Unlock 0 <--
-
-O L1_GETS 0 <--
-O L1_GETS_Last_Token 0 <--
-O L1_GETX 5
-O L1_INV 0 <--
-O Transient_GETX 0 <--
-O Transient_GETS 0 <--
-O Transient_GETS_Last_Token 0 <--
-O L2_Replacement 31
-O Writeback_Tokens 0 <--
-O Writeback_Shared_Data 0 <--
-O Writeback_All_Tokens 23
-O Data_Shared 0 <--
-O Data_All_Tokens 0 <--
-O Ack 0 <--
-O Ack_All_Tokens 0 <--
-O Persistent_GETX 0 <--
-O Persistent_GETS 0 <--
-O Own_Lock_or_Unlock 0 <--
-
-M L1_GETS 59
-M L1_GETX 12
-M L1_INV 0 <--
-M Transient_GETX 0 <--
-M Transient_GETS 0 <--
-M L2_Replacement 398
-M Persistent_GETX 0 <--
-M Persistent_GETS 0 <--
-M Own_Lock_or_Unlock 0 <--
-
-I_L L1_GETS 0 <--
-I_L L1_GETX 0 <--
-I_L L1_INV 0 <--
-I_L Transient_GETX 0 <--
-I_L Transient_GETS 0 <--
-I_L Transient_GETS_Last_Token 0 <--
-I_L L2_Replacement 0 <--
-I_L Writeback_Tokens 0 <--
-I_L Writeback_Shared_Data 0 <--
-I_L Writeback_All_Tokens 0 <--
-I_L Writeback_Owned 0 <--
-I_L Data_Shared 0 <--
-I_L Data_Owner 0 <--
-I_L Data_All_Tokens 0 <--
-I_L Ack 0 <--
-I_L Persistent_GETX 0 <--
-I_L Persistent_GETS 0 <--
-I_L Own_Lock_or_Unlock 0 <--
-
-S_L L1_GETS 0 <--
-S_L L1_GETS_Last_Token 0 <--
-S_L L1_GETX 0 <--
-S_L L1_INV 0 <--
-S_L Transient_GETX 0 <--
-S_L Transient_GETS 0 <--
-S_L Transient_GETS_Last_Token 0 <--
-S_L L2_Replacement 0 <--
-S_L Writeback_Tokens 0 <--
-S_L Writeback_Shared_Data 0 <--
-S_L Writeback_All_Tokens 0 <--
-S_L Writeback_Owned 0 <--
-S_L Data_Shared 0 <--
-S_L Data_Owner 0 <--
-S_L Data_All_Tokens 0 <--
-S_L Ack 0 <--
-S_L Persistent_GETX 0 <--
-S_L Persistent_GETS 0 <--
-S_L Own_Lock_or_Unlock 0 <--
-
-Memory controller: system.ruby.network.topology.ext_links2.ext_node.memBuffer:
- memory_total_requests: 523
- memory_reads: 442
- memory_writes: 81
- memory_refreshes: 189
- memory_total_request_delays: 199
- memory_delays_per_request: 0.380497
- memory_delays_in_input_queue: 67
+NP L1_GETS [434 ] 434
+NP L1_GETX [56 ] 56
+NP L1_INV [0 ] 0
+NP Transient_GETX [0 ] 0
+NP Transient_GETS [0 ] 0
+NP Writeback_Tokens [0 ] 0
+NP Writeback_Shared_Data [15 ] 15
+NP Writeback_All_Tokens [487 ] 487
+NP Writeback_Owned [0 ] 0
+NP Data_Shared [0 ] 0
+NP Data_Owner [0 ] 0
+NP Data_All_Tokens [0 ] 0
+NP Ack [0 ] 0
+NP Persistent_GETX [0 ] 0
+NP Persistent_GETS [0 ] 0
+NP Persistent_GETS_Last_Token [0 ] 0
+NP Own_Lock_or_Unlock [0 ] 0
+
+I L1_GETS [0 ] 0
+I L1_GETS_Last_Token [0 ] 0
+I L1_GETX [0 ] 0
+I L1_INV [0 ] 0
+I Transient_GETX [0 ] 0
+I Transient_GETS [0 ] 0
+I Transient_GETS_Last_Token [0 ] 0
+I L2_Replacement [6 ] 6
+I Writeback_Tokens [0 ] 0
+I Writeback_Shared_Data [0 ] 0
+I Writeback_All_Tokens [0 ] 0
+I Writeback_Owned [0 ] 0
+I Data_Shared [0 ] 0
+I Data_Owner [0 ] 0
+I Data_All_Tokens [0 ] 0
+I Ack [0 ] 0
+I Persistent_GETX [0 ] 0
+I Persistent_GETS [0 ] 0
+I Persistent_GETS_Last_Token [0 ] 0
+I Own_Lock_or_Unlock [0 ] 0
+
+S L1_GETS [0 ] 0
+S L1_GETS_Last_Token [1 ] 1
+S L1_GETX [0 ] 0
+S L1_INV [0 ] 0
+S Transient_GETX [0 ] 0
+S Transient_GETS [0 ] 0
+S Transient_GETS_Last_Token [0 ] 0
+S L2_Replacement [14 ] 14
+S Writeback_Tokens [0 ] 0
+S Writeback_Shared_Data [0 ] 0
+S Writeback_All_Tokens [0 ] 0
+S Writeback_Owned [0 ] 0
+S Data_Shared [0 ] 0
+S Data_Owner [0 ] 0
+S Data_All_Tokens [0 ] 0
+S Ack [0 ] 0
+S Persistent_GETX [0 ] 0
+S Persistent_GETS [0 ] 0
+S Persistent_GETS_Last_Token [0 ] 0
+S Own_Lock_or_Unlock [0 ] 0
+
+O L1_GETS [0 ] 0
+O L1_GETS_Last_Token [0 ] 0
+O L1_GETX [1 ] 1
+O L1_INV [0 ] 0
+O Transient_GETX [0 ] 0
+O Transient_GETS [0 ] 0
+O Transient_GETS_Last_Token [0 ] 0
+O L2_Replacement [16 ] 16
+O Writeback_Tokens [0 ] 0
+O Writeback_Shared_Data [0 ] 0
+O Writeback_All_Tokens [0 ] 0
+O Data_Shared [0 ] 0
+O Data_All_Tokens [0 ] 0
+O Ack [0 ] 0
+O Ack_All_Tokens [0 ] 0
+O Persistent_GETX [0 ] 0
+O Persistent_GETS [0 ] 0
+O Persistent_GETS_Last_Token [0 ] 0
+O Own_Lock_or_Unlock [0 ] 0
+
+M L1_GETS [17 ] 17
+M L1_GETX [4 ] 4
+M L1_INV [0 ] 0
+M Transient_GETX [0 ] 0
+M Transient_GETS [0 ] 0
+M L2_Replacement [464 ] 464
+M Persistent_GETX [0 ] 0
+M Persistent_GETS [0 ] 0
+M Own_Lock_or_Unlock [0 ] 0
+
+I_L L1_GETS [0 ] 0
+I_L L1_GETX [0 ] 0
+I_L L1_INV [0 ] 0
+I_L Transient_GETX [0 ] 0
+I_L Transient_GETS [0 ] 0
+I_L Transient_GETS_Last_Token [0 ] 0
+I_L L2_Replacement [0 ] 0
+I_L Writeback_Tokens [0 ] 0
+I_L Writeback_Shared_Data [0 ] 0
+I_L Writeback_All_Tokens [0 ] 0
+I_L Writeback_Owned [0 ] 0
+I_L Data_Shared [0 ] 0
+I_L Data_Owner [0 ] 0
+I_L Data_All_Tokens [0 ] 0
+I_L Ack [0 ] 0
+I_L Persistent_GETX [0 ] 0
+I_L Persistent_GETS [0 ] 0
+I_L Own_Lock_or_Unlock [0 ] 0
+
+S_L L1_GETS [0 ] 0
+S_L L1_GETS_Last_Token [0 ] 0
+S_L L1_GETX [0 ] 0
+S_L L1_INV [0 ] 0
+S_L Transient_GETX [0 ] 0
+S_L Transient_GETS [0 ] 0
+S_L Transient_GETS_Last_Token [0 ] 0
+S_L L2_Replacement [0 ] 0
+S_L Writeback_Tokens [0 ] 0
+S_L Writeback_Shared_Data [0 ] 0
+S_L Writeback_All_Tokens [0 ] 0
+S_L Writeback_Owned [0 ] 0
+S_L Data_Shared [0 ] 0
+S_L Data_Owner [0 ] 0
+S_L Data_All_Tokens [0 ] 0
+S_L Ack [0 ] 0
+S_L Persistent_GETX [0 ] 0
+S_L Persistent_GETS [0 ] 0
+S_L Persistent_GETS_Last_Token [0 ] 0
+S_L Own_Lock_or_Unlock [0 ] 0
+
+Memory controller: system.dir_cntrl0.memBuffer:
+ memory_total_requests: 582
+ memory_reads: 490
+ memory_writes: 92
+ memory_refreshes: 192
+ memory_total_request_delays: 314
+ memory_delays_per_request: 0.539519
+ memory_delays_in_input_queue: 90
memory_delays_behind_head_of_bank_queue: 0
- memory_delays_stalled_at_head_of_bank_queue: 132
- memory_stalls_for_bank_busy: 41
+ memory_delays_stalled_at_head_of_bank_queue: 224
+ memory_stalls_for_bank_busy: 106
memory_stalls_for_random_busy: 0
memory_stalls_for_anti_starvation: 0
- memory_stalls_for_arbitration: 7
- memory_stalls_for_bus: 80
+ memory_stalls_for_arbitration: 8
+ memory_stalls_for_bus: 104
memory_stalls_for_tfaw: 0
- memory_stalls_for_read_write_turnaround: 4
+ memory_stalls_for_read_write_turnaround: 6
memory_stalls_for_read_read_turnaround: 0
- accesses_per_bank: 19 10 0 41 20 19 31 22 5 3 6 4 21 40 20 3 4 6 7 14 10 16 14 41 16 5 5 12 12 18 14 65
+ accesses_per_bank: 20 13 0 46 20 20 38 23 5 5 7 4 24 42 25 3 4 6 7 14 10 21 14 46 16 5 5 12 14 18 16 79
- --- Directory 0 ---
+ --- Directory ---
- Event Counts -
-GETX 63
-GETS 409
-Lockdown 0
-Unlockdown 0
-Own_Lock_or_Unlock 0
-Data_Owner 6
-Data_All_Tokens 75
-Ack_Owner 25
-Ack_Owner_All_Tokens 323
-Tokens 0
-Ack_All_Tokens 18
-Request_Timeout 0
-Memory_Data 442
-Memory_Ack 81
-DMA_READ 0
-DMA_WRITE 0
-DMA_WRITE_All_Tokens 0
+GETX [57 ] 57
+GETS [434 ] 434
+Lockdown [0 ] 0
+Unlockdown [0 ] 0
+Own_Lock_or_Unlock [0 ] 0
+Own_Lock_or_Unlock_Tokens [0 ] 0
+Data_Owner [2 ] 2
+Data_All_Tokens [90 ] 90
+Ack_Owner [14 ] 14
+Ack_Owner_All_Tokens [374 ] 374
+Tokens [0 ] 0
+Ack_All_Tokens [14 ] 14
+Request_Timeout [0 ] 0
+Memory_Data [490 ] 490
+Memory_Ack [92 ] 92
+DMA_READ [0 ] 0
+DMA_WRITE [0 ] 0
+DMA_WRITE_All_Tokens [0 ] 0
- Transitions -
-O GETX 49
-O GETS 393
-O Lockdown 0 <--
-O Own_Lock_or_Unlock 0 <--
-O Data_Owner 0 <--
-O Data_All_Tokens 0 <--
-O Tokens 0 <--
-O Ack_All_Tokens 18
-O DMA_READ 0 <--
-O DMA_WRITE 0 <--
-O DMA_WRITE_All_Tokens 0 <--
-
-NO GETX 5
-NO GETS 0 <--
-NO Lockdown 0 <--
-NO Own_Lock_or_Unlock 0 <--
-NO Data_Owner 6
-NO Data_All_Tokens 75
-NO Ack_Owner 25
-NO Ack_Owner_All_Tokens 323
-NO Tokens 0 <--
-NO DMA_READ 0 <--
-NO DMA_WRITE 0 <--
-
-L GETX 0 <--
-L GETS 0 <--
-L Lockdown 0 <--
-L Unlockdown 0 <--
-L Own_Lock_or_Unlock 0 <--
-L Data_Owner 0 <--
-L Data_All_Tokens 0 <--
-L Ack_Owner 0 <--
-L Ack_Owner_All_Tokens 0 <--
-L Tokens 0 <--
-L DMA_READ 0 <--
-L DMA_WRITE 0 <--
-
-O_W GETX 9
-O_W GETS 16
-O_W Lockdown 0 <--
-O_W Unlockdown 0 <--
-O_W Own_Lock_or_Unlock 0 <--
-O_W Data_Owner 0 <--
-O_W Ack_Owner 0 <--
-O_W Tokens 0 <--
-O_W Ack_All_Tokens 0 <--
-O_W Memory_Data 0 <--
-O_W Memory_Ack 81
-O_W DMA_READ 0 <--
-O_W DMA_WRITE 0 <--
-
-L_O_W GETX 0 <--
-L_O_W GETS 0 <--
-L_O_W Lockdown 0 <--
-L_O_W Unlockdown 0 <--
-L_O_W Own_Lock_or_Unlock 0 <--
-L_O_W Data_Owner 0 <--
-L_O_W Ack_Owner 0 <--
-L_O_W Tokens 0 <--
-L_O_W Ack_All_Tokens 0 <--
-L_O_W Memory_Data 0 <--
-L_O_W Memory_Ack 0 <--
-L_O_W DMA_READ 0 <--
-L_O_W DMA_WRITE 0 <--
-
-L_NO_W GETX 0 <--
-L_NO_W GETS 0 <--
-L_NO_W Lockdown 0 <--
-L_NO_W Unlockdown 0 <--
-L_NO_W Own_Lock_or_Unlock 0 <--
-L_NO_W Data_Owner 0 <--
-L_NO_W Ack_Owner 0 <--
-L_NO_W Tokens 0 <--
-L_NO_W Ack_All_Tokens 0 <--
-L_NO_W Memory_Data 0 <--
-L_NO_W DMA_READ 0 <--
-L_NO_W DMA_WRITE 0 <--
-
-DR_L_W GETX 0 <--
-DR_L_W GETS 0 <--
-DR_L_W Lockdown 0 <--
-DR_L_W Unlockdown 0 <--
-DR_L_W Own_Lock_or_Unlock 0 <--
-DR_L_W Data_Owner 0 <--
-DR_L_W Ack_Owner 0 <--
-DR_L_W Tokens 0 <--
-DR_L_W Ack_All_Tokens 0 <--
-DR_L_W Request_Timeout 0 <--
-DR_L_W Memory_Data 0 <--
-DR_L_W DMA_READ 0 <--
-DR_L_W DMA_WRITE 0 <--
-
-NO_W GETX 0 <--
-NO_W GETS 0 <--
-NO_W Lockdown 0 <--
-NO_W Unlockdown 0 <--
-NO_W Own_Lock_or_Unlock 0 <--
-NO_W Data_Owner 0 <--
-NO_W Ack_Owner 0 <--
-NO_W Tokens 0 <--
-NO_W Ack_All_Tokens 0 <--
-NO_W Memory_Data 442
-NO_W DMA_READ 0 <--
-NO_W DMA_WRITE 0 <--
-
-O_DW_W GETX 0 <--
-O_DW_W GETS 0 <--
-O_DW_W Data_Owner 0 <--
-O_DW_W Ack_Owner 0 <--
-O_DW_W Tokens 0 <--
-O_DW_W Ack_All_Tokens 0 <--
-O_DW_W Memory_Ack 0 <--
-O_DW_W DMA_READ 0 <--
-O_DW_W DMA_WRITE 0 <--
-
-O_DR_W GETX 0 <--
-O_DR_W GETS 0 <--
-O_DR_W Lockdown 0 <--
-O_DR_W Unlockdown 0 <--
-O_DR_W Own_Lock_or_Unlock 0 <--
-O_DR_W Data_Owner 0 <--
-O_DR_W Ack_Owner 0 <--
-O_DR_W Tokens 0 <--
-O_DR_W Ack_All_Tokens 0 <--
-O_DR_W Memory_Data 0 <--
-O_DR_W DMA_READ 0 <--
-O_DR_W DMA_WRITE 0 <--
-
-O_DW GETX 0 <--
-O_DW GETS 0 <--
-O_DW Lockdown 0 <--
-O_DW Own_Lock_or_Unlock 0 <--
-O_DW Data_Owner 0 <--
-O_DW Data_All_Tokens 0 <--
-O_DW Ack_Owner 0 <--
-O_DW Ack_Owner_All_Tokens 0 <--
-O_DW Tokens 0 <--
-O_DW Ack_All_Tokens 0 <--
-O_DW DMA_READ 0 <--
-O_DW DMA_WRITE 0 <--
-
-NO_DW GETX 0 <--
-NO_DW GETS 0 <--
-NO_DW Lockdown 0 <--
-NO_DW Own_Lock_or_Unlock 0 <--
-NO_DW Data_Owner 0 <--
-NO_DW Data_All_Tokens 0 <--
-NO_DW Tokens 0 <--
-NO_DW Request_Timeout 0 <--
-NO_DW DMA_READ 0 <--
-NO_DW DMA_WRITE 0 <--
-
-NO_DR GETX 0 <--
-NO_DR GETS 0 <--
-NO_DR Lockdown 0 <--
-NO_DR Own_Lock_or_Unlock 0 <--
-NO_DR Data_Owner 0 <--
-NO_DR Data_All_Tokens 0 <--
-NO_DR Tokens 0 <--
-NO_DR Request_Timeout 0 <--
-NO_DR DMA_READ 0 <--
-NO_DR DMA_WRITE 0 <--
-
-DW_L GETX 0 <--
-DW_L GETS 0 <--
-DW_L Lockdown 0 <--
-DW_L Unlockdown 0 <--
-DW_L Own_Lock_or_Unlock 0 <--
-DW_L Data_Owner 0 <--
-DW_L Data_All_Tokens 0 <--
-DW_L Ack_Owner 0 <--
-DW_L Ack_Owner_All_Tokens 0 <--
-DW_L Tokens 0 <--
-DW_L Request_Timeout 0 <--
-DW_L DMA_READ 0 <--
-DW_L DMA_WRITE 0 <--
-
-DR_L GETX 0 <--
-DR_L GETS 0 <--
-DR_L Lockdown 0 <--
-DR_L Unlockdown 0 <--
-DR_L Own_Lock_or_Unlock 0 <--
-DR_L Data_Owner 0 <--
-DR_L Data_All_Tokens 0 <--
-DR_L Ack_Owner 0 <--
-DR_L Ack_Owner_All_Tokens 0 <--
-DR_L Tokens 0 <--
-DR_L Request_Timeout 0 <--
-DR_L DMA_READ 0 <--
-DR_L DMA_WRITE 0 <--
-
+O GETX [56 ] 56
+O GETS [434 ] 434
+O Lockdown [0 ] 0
+O Unlockdown [0 ] 0
+O Own_Lock_or_Unlock [0 ] 0
+O Own_Lock_or_Unlock_Tokens [0 ] 0
+O Data_Owner [0 ] 0
+O Data_All_Tokens [0 ] 0
+O Tokens [0 ] 0
+O Ack_All_Tokens [14 ] 14
+O DMA_READ [0 ] 0
+O DMA_WRITE [0 ] 0
+O DMA_WRITE_All_Tokens [0 ] 0
+
+NO GETX [1 ] 1
+NO GETS [0 ] 0
+NO Lockdown [0 ] 0
+NO Unlockdown [0 ] 0
+NO Own_Lock_or_Unlock [0 ] 0
+NO Own_Lock_or_Unlock_Tokens [0 ] 0
+NO Data_Owner [2 ] 2
+NO Data_All_Tokens [90 ] 90
+NO Ack_Owner [14 ] 14
+NO Ack_Owner_All_Tokens [374 ] 374
+NO Tokens [0 ] 0
+NO DMA_READ [0 ] 0
+NO DMA_WRITE [0 ] 0
+
+L GETX [0 ] 0
+L GETS [0 ] 0
+L Lockdown [0 ] 0
+L Unlockdown [0 ] 0
+L Own_Lock_or_Unlock [0 ] 0
+L Own_Lock_or_Unlock_Tokens [0 ] 0
+L Data_Owner [0 ] 0
+L Data_All_Tokens [0 ] 0
+L Ack_Owner [0 ] 0
+L Ack_Owner_All_Tokens [0 ] 0
+L Tokens [0 ] 0
+L DMA_READ [0 ] 0
+L DMA_WRITE [0 ] 0
+L DMA_WRITE_All_Tokens [0 ] 0
+
+O_W GETX [0 ] 0
+O_W GETS [0 ] 0
+O_W Lockdown [0 ] 0
+O_W Unlockdown [0 ] 0
+O_W Own_Lock_or_Unlock [0 ] 0
+O_W Own_Lock_or_Unlock_Tokens [0 ] 0
+O_W Data_Owner [0 ] 0
+O_W Data_All_Tokens [0 ] 0
+O_W Ack_Owner [0 ] 0
+O_W Tokens [0 ] 0
+O_W Ack_All_Tokens [0 ] 0
+O_W Memory_Data [0 ] 0
+O_W Memory_Ack [92 ] 92
+O_W DMA_READ [0 ] 0
+O_W DMA_WRITE [0 ] 0
+O_W DMA_WRITE_All_Tokens [0 ] 0
+
+L_O_W GETX [0 ] 0
+L_O_W GETS [0 ] 0
+L_O_W Lockdown [0 ] 0
+L_O_W Unlockdown [0 ] 0
+L_O_W Own_Lock_or_Unlock [0 ] 0
+L_O_W Own_Lock_or_Unlock_Tokens [0 ] 0
+L_O_W Data_Owner [0 ] 0
+L_O_W Data_All_Tokens [0 ] 0
+L_O_W Ack_Owner [0 ] 0
+L_O_W Tokens [0 ] 0
+L_O_W Ack_All_Tokens [0 ] 0
+L_O_W Memory_Data [0 ] 0
+L_O_W Memory_Ack [0 ] 0
+L_O_W DMA_READ [0 ] 0
+L_O_W DMA_WRITE [0 ] 0
+L_O_W DMA_WRITE_All_Tokens [0 ] 0
+
+L_NO_W GETX [0 ] 0
+L_NO_W GETS [0 ] 0
+L_NO_W Lockdown [0 ] 0
+L_NO_W Unlockdown [0 ] 0
+L_NO_W Own_Lock_or_Unlock [0 ] 0
+L_NO_W Own_Lock_or_Unlock_Tokens [0 ] 0
+L_NO_W Data_Owner [0 ] 0
+L_NO_W Data_All_Tokens [0 ] 0
+L_NO_W Ack_Owner [0 ] 0
+L_NO_W Tokens [0 ] 0
+L_NO_W Ack_All_Tokens [0 ] 0
+L_NO_W Memory_Data [0 ] 0
+L_NO_W DMA_READ [0 ] 0
+L_NO_W DMA_WRITE [0 ] 0
+L_NO_W DMA_WRITE_All_Tokens [0 ] 0
+
+DR_L_W GETX [0 ] 0
+DR_L_W GETS [0 ] 0
+DR_L_W Lockdown [0 ] 0
+DR_L_W Unlockdown [0 ] 0
+DR_L_W Own_Lock_or_Unlock [0 ] 0
+DR_L_W Own_Lock_or_Unlock_Tokens [0 ] 0
+DR_L_W Data_Owner [0 ] 0
+DR_L_W Data_All_Tokens [0 ] 0
+DR_L_W Ack_Owner [0 ] 0
+DR_L_W Tokens [0 ] 0
+DR_L_W Ack_All_Tokens [0 ] 0
+DR_L_W Request_Timeout [0 ] 0
+DR_L_W Memory_Data [0 ] 0
+DR_L_W DMA_READ [0 ] 0
+DR_L_W DMA_WRITE [0 ] 0
+DR_L_W DMA_WRITE_All_Tokens [0 ] 0
+
+DW_L_W GETX [0 ] 0
+DW_L_W GETS [0 ] 0
+DW_L_W Lockdown [0 ] 0
+DW_L_W Unlockdown [0 ] 0
+DW_L_W Own_Lock_or_Unlock [0 ] 0
+DW_L_W Own_Lock_or_Unlock_Tokens [0 ] 0
+DW_L_W Data_Owner [0 ] 0
+DW_L_W Data_All_Tokens [0 ] 0
+DW_L_W Ack_Owner [0 ] 0
+DW_L_W Tokens [0 ] 0
+DW_L_W Ack_All_Tokens [0 ] 0
+DW_L_W Request_Timeout [0 ] 0
+DW_L_W Memory_Ack [0 ] 0
+DW_L_W DMA_READ [0 ] 0
+DW_L_W DMA_WRITE [0 ] 0
+DW_L_W DMA_WRITE_All_Tokens [0 ] 0
+
+NO_W GETX [0 ] 0
+NO_W GETS [0 ] 0
+NO_W Lockdown [0 ] 0
+NO_W Unlockdown [0 ] 0
+NO_W Own_Lock_or_Unlock [0 ] 0
+NO_W Own_Lock_or_Unlock_Tokens [0 ] 0
+NO_W Data_Owner [0 ] 0
+NO_W Data_All_Tokens [0 ] 0
+NO_W Ack_Owner [0 ] 0
+NO_W Tokens [0 ] 0
+NO_W Ack_All_Tokens [0 ] 0
+NO_W Memory_Data [490 ] 490
+NO_W DMA_READ [0 ] 0
+NO_W DMA_WRITE [0 ] 0
+NO_W DMA_WRITE_All_Tokens [0 ] 0
+
+O_DW_W GETX [0 ] 0
+O_DW_W GETS [0 ] 0
+O_DW_W Lockdown [0 ] 0
+O_DW_W Unlockdown [0 ] 0
+O_DW_W Own_Lock_or_Unlock [0 ] 0
+O_DW_W Own_Lock_or_Unlock_Tokens [0 ] 0
+O_DW_W Data_Owner [0 ] 0
+O_DW_W Data_All_Tokens [0 ] 0
+O_DW_W Ack_Owner [0 ] 0
+O_DW_W Tokens [0 ] 0
+O_DW_W Ack_All_Tokens [0 ] 0
+O_DW_W Request_Timeout [0 ] 0
+O_DW_W Memory_Ack [0 ] 0
+O_DW_W DMA_READ [0 ] 0
+O_DW_W DMA_WRITE [0 ] 0
+O_DW_W DMA_WRITE_All_Tokens [0 ] 0
+
+O_DR_W GETX [0 ] 0
+O_DR_W GETS [0 ] 0
+O_DR_W Lockdown [0 ] 0
+O_DR_W Unlockdown [0 ] 0
+O_DR_W Own_Lock_or_Unlock [0 ] 0
+O_DR_W Own_Lock_or_Unlock_Tokens [0 ] 0
+O_DR_W Data_Owner [0 ] 0
+O_DR_W Data_All_Tokens [0 ] 0
+O_DR_W Ack_Owner [0 ] 0
+O_DR_W Tokens [0 ] 0
+O_DR_W Ack_All_Tokens [0 ] 0
+O_DR_W Request_Timeout [0 ] 0
+O_DR_W Memory_Data [0 ] 0
+O_DR_W DMA_READ [0 ] 0
+O_DR_W DMA_WRITE [0 ] 0
+O_DR_W DMA_WRITE_All_Tokens [0 ] 0
+
+O_DW GETX [0 ] 0
+O_DW GETS [0 ] 0
+O_DW Lockdown [0 ] 0
+O_DW Unlockdown [0 ] 0
+O_DW Own_Lock_or_Unlock [0 ] 0
+O_DW Own_Lock_or_Unlock_Tokens [0 ] 0
+O_DW Data_Owner [0 ] 0
+O_DW Data_All_Tokens [0 ] 0
+O_DW Ack_Owner [0 ] 0
+O_DW Ack_Owner_All_Tokens [0 ] 0
+O_DW Tokens [0 ] 0
+O_DW Ack_All_Tokens [0 ] 0
+O_DW Request_Timeout [0 ] 0
+O_DW DMA_READ [0 ] 0
+O_DW DMA_WRITE [0 ] 0
+O_DW DMA_WRITE_All_Tokens [0 ] 0
+
+NO_DW GETX [0 ] 0
+NO_DW GETS [0 ] 0
+NO_DW Lockdown [0 ] 0
+NO_DW Unlockdown [0 ] 0
+NO_DW Own_Lock_or_Unlock [0 ] 0
+NO_DW Own_Lock_or_Unlock_Tokens [0 ] 0
+NO_DW Data_Owner [0 ] 0
+NO_DW Data_All_Tokens [0 ] 0
+NO_DW Tokens [0 ] 0
+NO_DW Request_Timeout [0 ] 0
+NO_DW DMA_READ [0 ] 0
+NO_DW DMA_WRITE [0 ] 0
+NO_DW DMA_WRITE_All_Tokens [0 ] 0
+
+NO_DR GETX [0 ] 0
+NO_DR GETS [0 ] 0
+NO_DR Lockdown [0 ] 0
+NO_DR Unlockdown [0 ] 0
+NO_DR Own_Lock_or_Unlock [0 ] 0
+NO_DR Own_Lock_or_Unlock_Tokens [0 ] 0
+NO_DR Data_Owner [0 ] 0
+NO_DR Data_All_Tokens [0 ] 0
+NO_DR Tokens [0 ] 0
+NO_DR Request_Timeout [0 ] 0
+NO_DR DMA_READ [0 ] 0
+NO_DR DMA_WRITE [0 ] 0
+NO_DR DMA_WRITE_All_Tokens [0 ] 0
+
+DW_L GETX [0 ] 0
+DW_L GETS [0 ] 0
+DW_L Lockdown [0 ] 0
+DW_L Unlockdown [0 ] 0
+DW_L Own_Lock_or_Unlock [0 ] 0
+DW_L Own_Lock_or_Unlock_Tokens [0 ] 0
+DW_L Data_Owner [0 ] 0
+DW_L Data_All_Tokens [0 ] 0
+DW_L Ack_Owner [0 ] 0
+DW_L Ack_Owner_All_Tokens [0 ] 0
+DW_L Tokens [0 ] 0
+DW_L Request_Timeout [0 ] 0
+DW_L DMA_READ [0 ] 0
+DW_L DMA_WRITE [0 ] 0
+DW_L DMA_WRITE_All_Tokens [0 ] 0
+
+DR_L GETX [0 ] 0
+DR_L GETS [0 ] 0
+DR_L Lockdown [0 ] 0
+DR_L Unlockdown [0 ] 0
+DR_L Own_Lock_or_Unlock [0 ] 0
+DR_L Own_Lock_or_Unlock_Tokens [0 ] 0
+DR_L Data_Owner [0 ] 0
+DR_L Data_All_Tokens [0 ] 0
+DR_L Ack_Owner [0 ] 0
+DR_L Ack_Owner_All_Tokens [0 ] 0
+DR_L Tokens [0 ] 0
+DR_L Request_Timeout [0 ] 0
+DR_L DMA_READ [0 ] 0
+DR_L DMA_WRITE [0 ] 0
+DR_L DMA_WRITE_All_Tokens \ No newline at end of file
diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/simout b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/simout
index 5cc182def..9cf458143 100755
--- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/simout
+++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/simout
@@ -5,13 +5,13 @@ The Regents of The University of Michigan
All Rights Reserved
-M5 compiled Jan 28 2010 15:54:34
-M5 revision 6068d4fc30d3+ 6931+ default qtip tip brad/rubycfg_regress_udpate
-M5 started Jan 28 2010 15:55:46
-M5 executing on svvint04
+M5 compiled Aug 5 2010 10:41:36
+M5 revision 1cd2a169499f+ 7535+ default brad/hammer_merge_gets qtip tip
+M5 started Aug 5 2010 10:43:25
+M5 executing on svvint09
command line: build/ALPHA_SE_MOESI_CMP_token/m5.fast -d build/ALPHA_SE_MOESI_CMP_token/tests/fast/quick/00.hello/alpha/tru64/simple-timing-ruby-MOESI_CMP_token -re tests/run.py build/ALPHA_SE_MOESI_CMP_token/tests/fast/quick/00.hello/alpha/tru64/simple-timing-ruby-MOESI_CMP_token
Global frequency set at 1000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
Hello world!
-Exiting @ tick 90308 because target called exit()
+Exiting @ tick 92099 because target called exit()
diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/stats.txt b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/stats.txt
index d8ff49b26..e8b218502 100644
--- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/stats.txt
+++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/stats.txt
@@ -1,13 +1,13 @@
---------- Begin Simulation Statistics ----------
-host_inst_rate 18406 # Simulator instruction rate (inst/s)
-host_mem_usage 214900 # Number of bytes of host memory used
-host_seconds 0.15 # Real time elapsed on the host
-host_tick_rate 602029 # Simulator tick rate (ticks/s)
+host_inst_rate 42948 # Simulator instruction rate (inst/s)
+host_mem_usage 211392 # Number of bytes of host memory used
+host_seconds 0.06 # Real time elapsed on the host
+host_tick_rate 1534907 # Simulator tick rate (ticks/s)
sim_freq 1000000000 # Frequency of simulated ticks
sim_insts 2577 # Number of instructions simulated
-sim_seconds 0.000090 # Number of seconds simulated
-sim_ticks 90308 # Number of ticks simulated
+sim_seconds 0.000092 # Number of seconds simulated
+sim_ticks 92099 # Number of ticks simulated
system.cpu.dtb.data_accesses 717 # DTB accesses
system.cpu.dtb.data_acv 0 # DTB access violations
system.cpu.dtb.data_hits 709 # DTB hits
@@ -42,7 +42,7 @@ system.cpu.itb.write_acv 0 # DT
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
-system.cpu.numCycles 90308 # number of cpu cycles simulated
+system.cpu.numCycles 92099 # number of cpu cycles simulated
system.cpu.num_insts 2577 # Number of instructions executed
system.cpu.num_refs 717 # Number of memory references
system.cpu.workload.PROG:num_syscalls 4 # Number of system calls
diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/config.ini b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/config.ini
index 14740fd64..4d36728d7 100644
--- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/config.ini
+++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/config.ini
@@ -5,7 +5,7 @@ dummy=0
[system]
type=System
-children=cpu physmem ruby
+children=cpu dir_cntrl0 l1_cntrl0 physmem ruby
mem_mode=timing
physmem=system.physmem
@@ -32,8 +32,8 @@ progress_interval=0
system=system
tracer=system.cpu.tracer
workload=system.cpu.workload
-dcache_port=system.ruby.network.topology.ext_links0.ext_node.sequencer.port[1]
-icache_port=system.ruby.network.topology.ext_links0.ext_node.sequencer.port[0]
+dcache_port=system.l1_cntrl0.sequencer.port[1]
+icache_port=system.l1_cntrl0.sequencer.port[0]
[system.cpu.dtb]
type=AlphaTLB
@@ -54,7 +54,7 @@ egid=100
env=
errout=cerr
euid=100
-executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/hello/bin/alpha/tru64/hello
+executable=tests/test-progs/hello/bin/alpha/tru64/hello
gid=100
input=cin
max_stack_size=67108864
@@ -65,6 +65,110 @@ simpoint=0
system=system
uid=100
+[system.dir_cntrl0]
+type=Directory_Controller
+children=directory memBuffer probeFilter
+buffer_size=0
+directory=system.dir_cntrl0.directory
+memBuffer=system.dir_cntrl0.memBuffer
+memory_controller_latency=2
+number_of_TBEs=256
+probeFilter=system.dir_cntrl0.probeFilter
+probe_filter_enabled=false
+recycle_latency=10
+transitions_per_cycle=32
+version=0
+
+[system.dir_cntrl0.directory]
+type=RubyDirectoryMemory
+map_levels=4
+numa_high_bit=6
+size=134217728
+use_map=false
+version=0
+
+[system.dir_cntrl0.memBuffer]
+type=RubyMemoryControl
+bank_bit_0=8
+bank_busy_time=11
+bank_queue_size=12
+banks_per_rank=8
+basic_bus_busy_time=2
+dimm_bit_0=12
+dimms_per_channel=2
+mem_bus_cycle_multiplier=10
+mem_ctl_latency=12
+mem_fixed_delay=0
+mem_random_arbitrate=0
+rank_bit_0=11
+rank_rank_delay=1
+ranks_per_dimm=2
+read_write_delay=2
+refresh_period=1560
+tFaw=0
+version=0
+
+[system.dir_cntrl0.probeFilter]
+type=RubyCache
+assoc=4
+latency=1
+replacement_policy=PSEUDO_LRU
+size=1024
+start_index_bit=6
+
+[system.l1_cntrl0]
+type=L1Cache_Controller
+children=L2cacheMemory sequencer
+L1DcacheMemory=system.l1_cntrl0.sequencer.dcache
+L1IcacheMemory=system.l1_cntrl0.sequencer.icache
+L2cacheMemory=system.l1_cntrl0.L2cacheMemory
+buffer_size=0
+cache_response_latency=10
+issue_latency=2
+no_mig_atomic=true
+number_of_TBEs=256
+recycle_latency=10
+sequencer=system.l1_cntrl0.sequencer
+transitions_per_cycle=32
+version=0
+
+[system.l1_cntrl0.L2cacheMemory]
+type=RubyCache
+assoc=2
+latency=10
+replacement_policy=PSEUDO_LRU
+size=512
+start_index_bit=6
+
+[system.l1_cntrl0.sequencer]
+type=RubySequencer
+children=dcache icache
+dcache=system.l1_cntrl0.sequencer.dcache
+deadlock_threshold=500000
+icache=system.l1_cntrl0.sequencer.icache
+max_outstanding_requests=16
+physmem=system.physmem
+using_ruby_tester=false
+version=0
+physMemPort=system.physmem.port[0]
+port=system.cpu.icache_port system.cpu.dcache_port
+
+[system.l1_cntrl0.sequencer.dcache]
+type=RubyCache
+assoc=2
+latency=2
+replacement_policy=PSEUDO_LRU
+size=256
+start_index_bit=6
+
+[system.l1_cntrl0.sequencer.icache]
+type=RubyCache
+assoc=2
+latency=2
+replacement_policy=PSEUDO_LRU
+size=256
+start_index_bit=6
+
[system.physmem]
type=PhysicalMemory
file=
@@ -73,7 +177,7 @@ latency_var=0
null=false
range=0:134217727
zero=false
-port=system.ruby.network.topology.ext_links0.ext_node.sequencer.physMemPort
+port=system.l1_cntrl0.sequencer.physMemPort
[system.ruby]
type=RubySystem
@@ -83,6 +187,7 @@ clock=1
debug=system.ruby.debug
mem_size=134217728
network=system.ruby.network
+no_mem_vec=false
profiler=system.ruby.profiler
random_seed=1234
randomization=false
@@ -100,7 +205,7 @@ verbosity_string=none
[system.ruby.network]
type=SimpleNetwork
children=topology
-adaptive_routing=true
+adaptive_routing=false
buffer_size=0
control_msg_size=8
endpoint_bandwidth=10000
@@ -113,114 +218,26 @@ type=Topology
children=ext_links0 ext_links1 int_links0 int_links1
ext_links=system.ruby.network.topology.ext_links0 system.ruby.network.topology.ext_links1
int_links=system.ruby.network.topology.int_links0 system.ruby.network.topology.int_links1
+name=Crossbar
num_int_nodes=3
print_config=false
[system.ruby.network.topology.ext_links0]
type=ExtLink
-children=ext_node
bw_multiplier=64
-ext_node=system.ruby.network.topology.ext_links0.ext_node
+ext_node=system.l1_cntrl0
int_node=0
latency=1
weight=1
-[system.ruby.network.topology.ext_links0.ext_node]
-type=L1Cache_Controller
-children=L2cacheMemory sequencer
-L1DcacheMemory=system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache
-L1IcacheMemory=system.ruby.network.topology.ext_links0.ext_node.sequencer.icache
-L2cacheMemory=system.ruby.network.topology.ext_links0.ext_node.L2cacheMemory
-buffer_size=0
-cache_response_latency=12
-issue_latency=2
-number_of_TBEs=256
-recycle_latency=10
-sequencer=system.ruby.network.topology.ext_links0.ext_node.sequencer
-transitions_per_cycle=32
-version=0
-
-[system.ruby.network.topology.ext_links0.ext_node.L2cacheMemory]
-type=RubyCache
-assoc=2
-latency=15
-replacement_policy=PSEUDO_LRU
-size=512
-
-[system.ruby.network.topology.ext_links0.ext_node.sequencer]
-type=RubySequencer
-children=dcache icache
-dcache=system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache
-deadlock_threshold=500000
-icache=system.ruby.network.topology.ext_links0.ext_node.sequencer.icache
-max_outstanding_requests=16
-physmem=system.physmem
-using_ruby_tester=false
-version=0
-physMemPort=system.physmem.port[0]
-port=system.cpu.icache_port system.cpu.dcache_port
-
-[system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache]
-type=RubyCache
-assoc=2
-latency=3
-replacement_policy=PSEUDO_LRU
-size=256
-
-[system.ruby.network.topology.ext_links0.ext_node.sequencer.icache]
-type=RubyCache
-assoc=2
-latency=3
-replacement_policy=PSEUDO_LRU
-size=256
-
[system.ruby.network.topology.ext_links1]
type=ExtLink
-children=ext_node
bw_multiplier=64
-ext_node=system.ruby.network.topology.ext_links1.ext_node
+ext_node=system.dir_cntrl0
int_node=1
latency=1
weight=1
-[system.ruby.network.topology.ext_links1.ext_node]
-type=Directory_Controller
-children=directory memBuffer
-buffer_size=0
-directory=system.ruby.network.topology.ext_links1.ext_node.directory
-memBuffer=system.ruby.network.topology.ext_links1.ext_node.memBuffer
-memory_controller_latency=12
-number_of_TBEs=256
-recycle_latency=10
-transitions_per_cycle=32
-version=0
-
-[system.ruby.network.topology.ext_links1.ext_node.directory]
-type=RubyDirectoryMemory
-size=134217728
-version=0
-
-[system.ruby.network.topology.ext_links1.ext_node.memBuffer]
-type=RubyMemoryControl
-bank_bit_0=8
-bank_busy_time=11
-bank_queue_size=12
-banks_per_rank=8
-basic_bus_busy_time=2
-dimm_bit_0=12
-dimms_per_channel=2
-mem_bus_cycle_multiplier=10
-mem_ctl_latency=12
-mem_fixed_delay=0
-mem_random_arbitrate=0
-rank_bit_0=11
-rank_rank_delay=1
-ranks_per_dimm=2
-read_write_delay=2
-refresh_period=1560
-tFaw=0
-version=0
-
[system.ruby.network.topology.int_links0]
type=IntLink
bw_multiplier=16
diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/ruby.stats b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/ruby.stats
index 9db9e0aa2..6e53a933a 100644
--- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/ruby.stats
+++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/ruby.stats
@@ -13,14 +13,14 @@ RubySystem config:
Network Configuration
---------------------
network: SIMPLE_NETWORK
-topology:
+topology: Crossbar
-virtual_net_0: active, unordered
-virtual_net_1: active, unordered
+virtual_net_0: active, ordered
+virtual_net_1: active, ordered
virtual_net_2: active, unordered
virtual_net_3: active, unordered
-virtual_net_4: active, ordered
-virtual_net_5: active, ordered
+virtual_net_4: active, unordered
+virtual_net_5: active, unordered
virtual_net_6: inactive
virtual_net_7: inactive
virtual_net_8: inactive
@@ -34,7 +34,7 @@ periodic_stats_period: 1000000
================ End RubySystem Configuration Print ================
-Real time: Jan/28/2010 11:48:25
+Real time: Aug/05/2010 14:44:19
Profiler Stats
--------------
@@ -43,31 +43,20 @@ Elapsed_time_in_minutes: 0
Elapsed_time_in_hours: 0
Elapsed_time_in_days: 0
-Virtual_time_in_seconds: 0.33
-Virtual_time_in_minutes: 0.0055
-Virtual_time_in_hours: 9.16667e-05
-Virtual_time_in_days: 3.81944e-06
+Virtual_time_in_seconds: 0.21
+Virtual_time_in_minutes: 0.0035
+Virtual_time_in_hours: 5.83333e-05
+Virtual_time_in_days: 2.43056e-06
-Ruby_current_time: 81672
+Ruby_current_time: 78408
Ruby_start_time: 0
-Ruby_cycles: 81672
+Ruby_cycles: 78408
-mbytes_resident: 31.8555
-mbytes_total: 31.8633
+mbytes_resident: 33.3242
+mbytes_total: 33.332
resident_ratio: 1
-Total_misses: 0
-total_misses: 0 [ 0 ]
-user_misses: 0 [ 0 ]
-supervisor_misses: 0 [ 0 ]
-
-ruby_cycles_executed: 81673 [ 81673 ]
-
-transactions_started: 0 [ 0 ]
-transactions_ended: 0 [ 0 ]
-cycles_per_transaction: 0 [ 0 ]
-misses_per_transaction: 0 [ 0 ]
-
+ruby_cycles_executed: [ 78409 ]
Busy Controller Counts:
L1Cache-0:0
@@ -80,10 +69,32 @@ sequencer_requests_outstanding: [binsize: 1 max: 1 count: 3295 average: 1 |
All Non-Zero Cycle Demand Cache Accesses
----------------------------------------
-miss_latency: [binsize: 2 max: 333 count: 3294 average: 23.7942 | standard deviation: 53.6415 | 0 2853 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 87 74 46 111 83 4 0 4 2 0 2 2 0 0 1 1 2 0 0 0 2 2 2 3 2 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 2 1 1 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
-miss_latency_1: [binsize: 2 max: 243 count: 2585 average: 17.6507 | standard deviation: 45.0947 | 0 2337 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 38 47 26 56 63 2 0 2 1 0 1 2 0 0 0 1 1 0 0 0 1 1 1 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
-miss_latency_2: [binsize: 2 max: 333 count: 415 average: 57.9108 | standard deviation: 76.4181 | 0 269 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 41 16 18 39 18 1 0 1 0 0 1 0 0 0 1 0 1 0 0 0 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
-miss_latency_3: [binsize: 2 max: 333 count: 294 average: 29.6531 | standard deviation: 64.3241 | 0 247 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 8 11 2 16 2 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 1 0 0 1 ]
+miss_latency: [binsize: 2 max: 320 count: 3294 average: 22.8033 | standard deviation: 52.924 | 0 2784 0 0 0 0 69 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 35 77 96 65 60 75 2 0 2 1 4 0 1 2 4 4 1 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 3 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency_IFETCH: [binsize: 1 max: 181 count: 2585 average: 16.5544 | standard deviation: 44.4412 | 0 0 2315 0 0 0 0 0 0 0 0 0 22 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 17 19 16 48 18 11 31 24 15 37 0 1 0 0 0 0 0 0 0 3 0 0 0 0 0 0 1 1 0 0 2 0 1 1 2 ]
+miss_latency_LD: [binsize: 2 max: 319 count: 415 average: 57.4602 | standard deviation: 75.1127 | 0 233 0 0 0 0 36 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 34 23 16 17 26 1 0 2 0 1 0 0 1 3 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency_ST: [binsize: 2 max: 320 count: 294 average: 28.8265 | standard deviation: 63.3064 | 0 236 0 0 0 0 11 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 8 7 7 4 12 0 0 0 1 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 2 0 1 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency_L1Cache: [binsize: 1 max: 2 count: 2784 average: 2 | standard deviation: 0 | 0 0 2784 ]
+miss_latency_L2Cache: [binsize: 1 max: 12 count: 69 average: 12 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 69 ]
+miss_latency_Directory: [binsize: 2 max: 320 count: 441 average: 155.823 | standard deviation: 21.7136 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 35 77 96 65 60 75 2 0 2 1 4 0 1 2 4 4 1 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 3 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency_wCC_issue_to_initial_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+miss_latency_wCC_initial_forward_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+miss_latency_wCC_forward_to_first_response: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+miss_latency_wCC_first_response_to_completion: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+imcomplete_wCC_Times: 0
+miss_latency_dir_issue_to_initial_request: [binsize: 1 max: 0 count: 1 average: 0 | standard deviation: 0 | 1 ]
+miss_latency_dir_initial_forward_request: [binsize: 1 max: 0 count: 1 average: 0 | standard deviation: 0 | 1 ]
+miss_latency_dir_forward_to_first_response: [binsize: 1 max: 158 count: 1 average: 158 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ]
+miss_latency_dir_first_response_to_completion: [binsize: 1 max: 0 count: 1 average: 0 | standard deviation: 0 | 1 ]
+imcomplete_dir_Times: 440
+miss_latency_IFETCH_L1Cache: [binsize: 1 max: 2 count: 2315 average: 2 | standard deviation: 0 | 0 0 2315 ]
+miss_latency_IFETCH_L2Cache: [binsize: 1 max: 12 count: 22 average: 12 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 22 ]
+miss_latency_IFETCH_Directory: [binsize: 1 max: 181 count: 248 average: 152.819 | standard deviation: 5.60689 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 17 19 16 48 18 11 31 24 15 37 0 1 0 0 0 0 0 0 0 3 0 0 0 0 0 0 1 1 0 0 2 0 1 1 2 ]
+miss_latency_LD_L1Cache: [binsize: 1 max: 2 count: 233 average: 2 | standard deviation: 0 | 0 0 233 ]
+miss_latency_LD_L2Cache: [binsize: 1 max: 12 count: 36 average: 12 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 36 ]
+miss_latency_LD_Directory: [binsize: 2 max: 319 count: 146 average: 157.178 | standard deviation: 25.3138 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 34 23 16 17 26 1 0 2 0 1 0 0 1 3 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency_ST_L1Cache: [binsize: 1 max: 2 count: 236 average: 2 | standard deviation: 0 | 0 0 236 ]
+miss_latency_ST_L2Cache: [binsize: 1 max: 12 count: 11 average: 12 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 11 ]
+miss_latency_ST_Directory: [binsize: 2 max: 320 count: 47 average: 167.468 | standard deviation: 46.1312 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 8 7 7 4 12 0 0 0 1 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 2 0 1 0 0 0 0 0 0 0 0 0 0 0 ]
All Non-Zero Cycle SW Prefetch Requests
------------------------------------
@@ -115,8 +126,8 @@ Resource Usage
page_size: 4096
user_time: 0
system_time: 0
-page_reclaims: 6878
-page_faults: 2029
+page_reclaims: 7298
+page_faults: 2071
swaps: 0
block_inputs: 0
block_outputs: 0
@@ -124,453 +135,665 @@ block_outputs: 0
Network Stats
-------------
+total_msg_count_Request_Control: 1323 10584
+total_msg_count_Response_Data: 1323 95256
+total_msg_count_Writeback_Data: 243 17496
+total_msg_count_Writeback_Control: 3582 28656
+total_msg_count_Unblock_Control: 1320 10560
+total_msgs: 7791 total_bytes: 162552
+
switch_0_inlinks: 2
switch_0_outlinks: 2
-links_utilized_percent_switch_0: 0.106447
- links_utilized_percent_switch_0_link_0: 0.0672507 bw: 640000 base_latency: 1
- links_utilized_percent_switch_0_link_1: 0.145644 bw: 160000 base_latency: 1
+links_utilized_percent_switch_0: 0.110878
+ links_utilized_percent_switch_0_link_0: 0.0700502 bw: 640000 base_latency: 1
+ links_utilized_percent_switch_0_link_1: 0.151706 bw: 160000 base_latency: 1
- outgoing_messages_switch_0_link_0_Response_Data: 441 31752 [ 0 441 0 0 0 0 0 0 0 0 ] base_latency: 1
- outgoing_messages_switch_0_link_0_Writeback_Control: 425 3400 [ 0 0 425 0 0 0 0 0 0 0 ] base_latency: 1
- outgoing_messages_switch_0_link_1_Request_Control: 441 3528 [ 0 0 0 441 0 0 0 0 0 0 ] base_latency: 1
- outgoing_messages_switch_0_link_1_Writeback_Data: 81 5832 [ 81 0 0 0 0 0 0 0 0 0 ] base_latency: 1
- outgoing_messages_switch_0_link_1_Writeback_Control: 769 6152 [ 344 0 0 425 0 0 0 0 0 0 ] base_latency: 1
- outgoing_messages_switch_0_link_1_Unblock_Control: 440 3520 [ 440 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_0_link_0_Response_Data: 441 31752 [ 0 0 0 0 441 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_0_link_0_Writeback_Control: 425 3400 [ 0 0 0 425 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_0_link_1_Request_Control: 441 3528 [ 0 0 441 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_0_link_1_Writeback_Data: 81 5832 [ 0 0 0 0 0 81 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_0_link_1_Writeback_Control: 769 6152 [ 0 0 425 0 0 344 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_0_link_1_Unblock_Control: 440 3520 [ 0 0 0 0 0 440 0 0 0 0 ] base_latency: 1
switch_1_inlinks: 2
switch_1_outlinks: 2
-links_utilized_percent_switch_1: 0.152707
- links_utilized_percent_switch_1_link_0: 0.0364109 bw: 640000 base_latency: 1
- links_utilized_percent_switch_1_link_1: 0.269003 bw: 160000 base_latency: 1
+links_utilized_percent_switch_1: 0.159064
+ links_utilized_percent_switch_1_link_0: 0.0379266 bw: 640000 base_latency: 1
+ links_utilized_percent_switch_1_link_1: 0.280201 bw: 160000 base_latency: 1
- outgoing_messages_switch_1_link_0_Request_Control: 441 3528 [ 0 0 0 441 0 0 0 0 0 0 ] base_latency: 1
- outgoing_messages_switch_1_link_0_Writeback_Data: 81 5832 [ 81 0 0 0 0 0 0 0 0 0 ] base_latency: 1
- outgoing_messages_switch_1_link_0_Writeback_Control: 769 6152 [ 344 0 0 425 0 0 0 0 0 0 ] base_latency: 1
- outgoing_messages_switch_1_link_0_Unblock_Control: 440 3520 [ 440 0 0 0 0 0 0 0 0 0 ] base_latency: 1
- outgoing_messages_switch_1_link_1_Response_Data: 441 31752 [ 0 441 0 0 0 0 0 0 0 0 ] base_latency: 1
- outgoing_messages_switch_1_link_1_Writeback_Control: 425 3400 [ 0 0 425 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_1_link_0_Request_Control: 441 3528 [ 0 0 441 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_1_link_0_Writeback_Data: 81 5832 [ 0 0 0 0 0 81 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_1_link_0_Writeback_Control: 769 6152 [ 0 0 425 0 0 344 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_1_link_0_Unblock_Control: 440 3520 [ 0 0 0 0 0 440 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_1_link_1_Response_Data: 441 31752 [ 0 0 0 0 441 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_1_link_1_Writeback_Control: 425 3400 [ 0 0 0 425 0 0 0 0 0 0 ] base_latency: 1
switch_2_inlinks: 2
switch_2_outlinks: 2
-links_utilized_percent_switch_2: 0.207323
- links_utilized_percent_switch_2_link_0: 0.269003 bw: 160000 base_latency: 1
- links_utilized_percent_switch_2_link_1: 0.145644 bw: 160000 base_latency: 1
-
- outgoing_messages_switch_2_link_0_Response_Data: 441 31752 [ 0 441 0 0 0 0 0 0 0 0 ] base_latency: 1
- outgoing_messages_switch_2_link_0_Writeback_Control: 425 3400 [ 0 0 425 0 0 0 0 0 0 0 ] base_latency: 1
- outgoing_messages_switch_2_link_1_Request_Control: 441 3528 [ 0 0 0 441 0 0 0 0 0 0 ] base_latency: 1
- outgoing_messages_switch_2_link_1_Writeback_Data: 81 5832 [ 81 0 0 0 0 0 0 0 0 0 ] base_latency: 1
- outgoing_messages_switch_2_link_1_Writeback_Control: 769 6152 [ 344 0 0 425 0 0 0 0 0 0 ] base_latency: 1
- outgoing_messages_switch_2_link_1_Unblock_Control: 440 3520 [ 440 0 0 0 0 0 0 0 0 0 ] base_latency: 1
-
-Cache Stats: system.ruby.network.topology.ext_links0.ext_node.sequencer.icache
- system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_misses: 248
- system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_demand_misses: 248
- system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_prefetches: 0
- system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_sw_prefetches: 0
- system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_hw_prefetches: 0
- system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_misses_per_transaction: inf
-
- system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_request_type_IFETCH: 100%
-
- system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_access_mode_type_SupervisorMode: 248 100%
- system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_request_size: [binsize: 1 max: 4 count: 248 average: 4 | standard deviation: 0 | 0 0 0 0 248 ]
-
-Cache Stats: system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache
- system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_misses: 193
- system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_demand_misses: 193
- system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_prefetches: 0
- system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_sw_prefetches: 0
- system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_hw_prefetches: 0
- system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_misses_per_transaction: inf
-
- system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_request_type_LD: 75.6477%
- system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_request_type_ST: 24.3523%
-
- system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_access_mode_type_SupervisorMode: 193 100%
- system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_request_size: [binsize: 1 max: 8 count: 193 average: 7.25389 | standard deviation: 1.56292 | 0 0 0 0 36 0 0 0 157 ]
-
-Cache Stats: system.ruby.network.topology.ext_links0.ext_node.L2cacheMemory
- system.ruby.network.topology.ext_links0.ext_node.L2cacheMemory_total_misses: 0
- system.ruby.network.topology.ext_links0.ext_node.L2cacheMemory_total_demand_misses: 0
- system.ruby.network.topology.ext_links0.ext_node.L2cacheMemory_total_prefetches: 0
- system.ruby.network.topology.ext_links0.ext_node.L2cacheMemory_total_sw_prefetches: 0
- system.ruby.network.topology.ext_links0.ext_node.L2cacheMemory_total_hw_prefetches: 0
- system.ruby.network.topology.ext_links0.ext_node.L2cacheMemory_misses_per_transaction: nan
-
- system.ruby.network.topology.ext_links0.ext_node.L2cacheMemory_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
-
- --- L1Cache 0 ---
+links_utilized_percent_switch_2: 0.215954
+ links_utilized_percent_switch_2_link_0: 0.280201 bw: 160000 base_latency: 1
+ links_utilized_percent_switch_2_link_1: 0.151706 bw: 160000 base_latency: 1
+
+ outgoing_messages_switch_2_link_0_Response_Data: 441 31752 [ 0 0 0 0 441 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_2_link_0_Writeback_Control: 425 3400 [ 0 0 0 425 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_2_link_1_Request_Control: 441 3528 [ 0 0 441 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_2_link_1_Writeback_Data: 81 5832 [ 0 0 0 0 0 81 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_2_link_1_Writeback_Control: 769 6152 [ 0 0 425 0 0 344 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_2_link_1_Unblock_Control: 440 3520 [ 0 0 0 0 0 440 0 0 0 0 ] base_latency: 1
+
+Cache Stats: system.l1_cntrl0.sequencer.icache
+ system.l1_cntrl0.sequencer.icache_total_misses: 270
+ system.l1_cntrl0.sequencer.icache_total_demand_misses: 270
+ system.l1_cntrl0.sequencer.icache_total_prefetches: 0
+ system.l1_cntrl0.sequencer.icache_total_sw_prefetches: 0
+ system.l1_cntrl0.sequencer.icache_total_hw_prefetches: 0
+
+ system.l1_cntrl0.sequencer.icache_request_type_IFETCH: 100%
+
+ system.l1_cntrl0.sequencer.icache_access_mode_type_SupervisorMode: 270 100%
+
+Cache Stats: system.l1_cntrl0.sequencer.dcache
+ system.l1_cntrl0.sequencer.dcache_total_misses: 240
+ system.l1_cntrl0.sequencer.dcache_total_demand_misses: 240
+ system.l1_cntrl0.sequencer.dcache_total_prefetches: 0
+ system.l1_cntrl0.sequencer.dcache_total_sw_prefetches: 0
+ system.l1_cntrl0.sequencer.dcache_total_hw_prefetches: 0
+
+ system.l1_cntrl0.sequencer.dcache_request_type_LD: 75.8333%
+ system.l1_cntrl0.sequencer.dcache_request_type_ST: 24.1667%
+
+ system.l1_cntrl0.sequencer.dcache_access_mode_type_SupervisorMode: 240 100%
+
+Cache Stats: system.l1_cntrl0.L2cacheMemory
+ system.l1_cntrl0.L2cacheMemory_total_misses: 441
+ system.l1_cntrl0.L2cacheMemory_total_demand_misses: 441
+ system.l1_cntrl0.L2cacheMemory_total_prefetches: 0
+ system.l1_cntrl0.L2cacheMemory_total_sw_prefetches: 0
+ system.l1_cntrl0.L2cacheMemory_total_hw_prefetches: 0
+
+ system.l1_cntrl0.L2cacheMemory_request_type_LD: 33.1066%
+ system.l1_cntrl0.L2cacheMemory_request_type_ST: 10.6576%
+ system.l1_cntrl0.L2cacheMemory_request_type_IFETCH: 56.2358%
+
+ system.l1_cntrl0.L2cacheMemory_access_mode_type_SupervisorMode: 441 100%
+
+ --- L1Cache ---
- Event Counts -
-Load 437
-Ifetch 2603
-Store 306
-L2_Replacement 425
-L1_to_L2 502
-L2_to_L1D 47
-L2_to_L1I 22
-Other_GETX 0
-Other_GETS 0
-Ack 0
-Shared_Ack 0
-Data 0
-Shared_Data 0
-Exclusive_Data 441
-Writeback_Ack 425
-Writeback_Nack 0
-All_acks 0
-All_acks_no_sharers 441
+Load [428 ] 428
+Ifetch [2597 ] 2597
+Store [302 ] 302
+L2_Replacement [425 ] 425
+L1_to_L2 [502 ] 502
+Trigger_L2_to_L1D [47 ] 47
+Trigger_L2_to_L1I [22 ] 22
+Complete_L2_to_L1 [69 ] 69
+Other_GETX [0 ] 0
+Other_GETS [0 ] 0
+Merged_GETS [0 ] 0
+Other_GETS_No_Mig [0 ] 0
+Invalidate [0 ] 0
+Ack [0 ] 0
+Shared_Ack [0 ] 0
+Data [0 ] 0
+Shared_Data [0 ] 0
+Exclusive_Data [441 ] 441
+Writeback_Ack [425 ] 425
+Writeback_Nack [0 ] 0
+All_acks [0 ] 0
+All_acks_no_sharers [441 ] 441
- Transitions -
-I Load 146
-I Ifetch 248
-I Store 47
-I L2_Replacement 0 <--
-I L1_to_L2 0 <--
-I L2_to_L1D 0 <--
-I L2_to_L1I 0 <--
-I Other_GETX 0 <--
-I Other_GETS 0 <--
-
-S Load 0 <--
-S Ifetch 0 <--
-S Store 0 <--
-S L2_Replacement 0 <--
-S L1_to_L2 0 <--
-S L2_to_L1D 0 <--
-S L2_to_L1I 0 <--
-S Other_GETX 0 <--
-S Other_GETS 0 <--
-
-O Load 0 <--
-O Ifetch 0 <--
-O Store 0 <--
-O L2_Replacement 0 <--
-O L1_to_L2 0 <--
-O L2_to_L1D 0 <--
-O L2_to_L1I 0 <--
-O Other_GETX 0 <--
-O Other_GETS 0 <--
-
-M Load 131
-M Ifetch 2337
-M Store 36
-M L2_Replacement 344
-M L1_to_L2 397
-M L2_to_L1D 23
-M L2_to_L1I 22
-M Other_GETX 0 <--
-M Other_GETS 0 <--
-
-MM Load 138
-MM Ifetch 0 <--
-MM Store 211
-MM L2_Replacement 81
-MM L1_to_L2 105
-MM L2_to_L1D 24
-MM L2_to_L1I 0 <--
-MM Other_GETX 0 <--
-MM Other_GETS 0 <--
-
-IM Load 0 <--
-IM Ifetch 0 <--
-IM Store 0 <--
-IM L2_Replacement 0 <--
-IM L1_to_L2 0 <--
-IM Other_GETX 0 <--
-IM Other_GETS 0 <--
-IM Ack 0 <--
-IM Data 0 <--
-IM Exclusive_Data 47
-
-SM Load 0 <--
-SM Ifetch 0 <--
-SM Store 0 <--
-SM L2_Replacement 0 <--
-SM L1_to_L2 0 <--
-SM Other_GETX 0 <--
-SM Other_GETS 0 <--
-SM Ack 0 <--
-SM Data 0 <--
-
-OM Load 0 <--
-OM Ifetch 0 <--
-OM Store 0 <--
-OM L2_Replacement 0 <--
-OM L1_to_L2 0 <--
-OM Other_GETX 0 <--
-OM Other_GETS 0 <--
-OM Ack 0 <--
-OM All_acks 0 <--
-OM All_acks_no_sharers 0 <--
-
-ISM Load 0 <--
-ISM Ifetch 0 <--
-ISM Store 0 <--
-ISM L2_Replacement 0 <--
-ISM L1_to_L2 0 <--
-ISM Ack 0 <--
-ISM All_acks_no_sharers 0 <--
-
-M_W Load 0 <--
-M_W Ifetch 0 <--
-M_W Store 0 <--
-M_W L2_Replacement 0 <--
-M_W L1_to_L2 0 <--
-M_W Ack 0 <--
-M_W All_acks_no_sharers 394
-
-MM_W Load 0 <--
-MM_W Ifetch 0 <--
-MM_W Store 0 <--
-MM_W L2_Replacement 0 <--
-MM_W L1_to_L2 0 <--
-MM_W Ack 0 <--
-MM_W All_acks_no_sharers 47
-
-IS Load 0 <--
-IS Ifetch 0 <--
-IS Store 0 <--
-IS L2_Replacement 0 <--
-IS L1_to_L2 0 <--
-IS Other_GETX 0 <--
-IS Other_GETS 0 <--
-IS Ack 0 <--
-IS Shared_Ack 0 <--
-IS Data 0 <--
-IS Shared_Data 0 <--
-IS Exclusive_Data 394
-
-SS Load 0 <--
-SS Ifetch 0 <--
-SS Store 0 <--
-SS L2_Replacement 0 <--
-SS L1_to_L2 0 <--
-SS Ack 0 <--
-SS Shared_Ack 0 <--
-SS All_acks 0 <--
-SS All_acks_no_sharers 0 <--
-
-OI Load 0 <--
-OI Ifetch 0 <--
-OI Store 0 <--
-OI L2_Replacement 0 <--
-OI L1_to_L2 0 <--
-OI Other_GETX 0 <--
-OI Other_GETS 0 <--
-OI Writeback_Ack 0 <--
-
-MI Load 22
-MI Ifetch 18
-MI Store 12
-MI L2_Replacement 0 <--
-MI L1_to_L2 0 <--
-MI Other_GETX 0 <--
-MI Other_GETS 0 <--
-MI Writeback_Ack 425
-
-II Load 0 <--
-II Ifetch 0 <--
-II Store 0 <--
-II L2_Replacement 0 <--
-II L1_to_L2 0 <--
-II Other_GETX 0 <--
-II Other_GETS 0 <--
-II Writeback_Ack 0 <--
-II Writeback_Nack 0 <--
-
-Memory controller: system.ruby.network.topology.ext_links1.ext_node.memBuffer:
+I Load [146 ] 146
+I Ifetch [248 ] 248
+I Store [47 ] 47
+I L2_Replacement [0 ] 0
+I L1_to_L2 [0 ] 0
+I Trigger_L2_to_L1D [0 ] 0
+I Trigger_L2_to_L1I [0 ] 0
+I Other_GETX [0 ] 0
+I Other_GETS [0 ] 0
+I Other_GETS_No_Mig [0 ] 0
+I Invalidate [0 ] 0
+
+S Load [0 ] 0
+S Ifetch [0 ] 0
+S Store [0 ] 0
+S L2_Replacement [0 ] 0
+S L1_to_L2 [0 ] 0
+S Trigger_L2_to_L1D [0 ] 0
+S Trigger_L2_to_L1I [0 ] 0
+S Other_GETX [0 ] 0
+S Other_GETS [0 ] 0
+S Other_GETS_No_Mig [0 ] 0
+S Invalidate [0 ] 0
+
+O Load [0 ] 0
+O Ifetch [0 ] 0
+O Store [0 ] 0
+O L2_Replacement [0 ] 0
+O L1_to_L2 [0 ] 0
+O Trigger_L2_to_L1D [0 ] 0
+O Trigger_L2_to_L1I [0 ] 0
+O Other_GETX [0 ] 0
+O Other_GETS [0 ] 0
+O Merged_GETS [0 ] 0
+O Other_GETS_No_Mig [0 ] 0
+O Invalidate [0 ] 0
+
+M Load [131 ] 131
+M Ifetch [2337 ] 2337
+M Store [36 ] 36
+M L2_Replacement [344 ] 344
+M L1_to_L2 [397 ] 397
+M Trigger_L2_to_L1D [23 ] 23
+M Trigger_L2_to_L1I [22 ] 22
+M Other_GETX [0 ] 0
+M Other_GETS [0 ] 0
+M Merged_GETS [0 ] 0
+M Other_GETS_No_Mig [0 ] 0
+M Invalidate [0 ] 0
+
+MM Load [138 ] 138
+MM Ifetch [0 ] 0
+MM Store [211 ] 211
+MM L2_Replacement [81 ] 81
+MM L1_to_L2 [105 ] 105
+MM Trigger_L2_to_L1D [24 ] 24
+MM Trigger_L2_to_L1I [0 ] 0
+MM Other_GETX [0 ] 0
+MM Other_GETS [0 ] 0
+MM Merged_GETS [0 ] 0
+MM Other_GETS_No_Mig [0 ] 0
+MM Invalidate [0 ] 0
+
+IM Load [0 ] 0
+IM Ifetch [0 ] 0
+IM Store [0 ] 0
+IM L2_Replacement [0 ] 0
+IM L1_to_L2 [0 ] 0
+IM Other_GETX [0 ] 0
+IM Other_GETS [0 ] 0
+IM Other_GETS_No_Mig [0 ] 0
+IM Invalidate [0 ] 0
+IM Ack [0 ] 0
+IM Data [0 ] 0
+IM Exclusive_Data [47 ] 47
+
+SM Load [0 ] 0
+SM Ifetch [0 ] 0
+SM Store [0 ] 0
+SM L2_Replacement [0 ] 0
+SM L1_to_L2 [0 ] 0
+SM Other_GETX [0 ] 0
+SM Other_GETS [0 ] 0
+SM Other_GETS_No_Mig [0 ] 0
+SM Invalidate [0 ] 0
+SM Ack [0 ] 0
+SM Data [0 ] 0
+
+OM Load [0 ] 0
+OM Ifetch [0 ] 0
+OM Store [0 ] 0
+OM L2_Replacement [0 ] 0
+OM L1_to_L2 [0 ] 0
+OM Other_GETX [0 ] 0
+OM Other_GETS [0 ] 0
+OM Merged_GETS [0 ] 0
+OM Other_GETS_No_Mig [0 ] 0
+OM Invalidate [0 ] 0
+OM Ack [0 ] 0
+OM All_acks [0 ] 0
+OM All_acks_no_sharers [0 ] 0
+
+ISM Load [0 ] 0
+ISM Ifetch [0 ] 0
+ISM Store [0 ] 0
+ISM L2_Replacement [0 ] 0
+ISM L1_to_L2 [0 ] 0
+ISM Ack [0 ] 0
+ISM All_acks_no_sharers [0 ] 0
+
+M_W Load [0 ] 0
+M_W Ifetch [0 ] 0
+M_W Store [0 ] 0
+M_W L2_Replacement [0 ] 0
+M_W L1_to_L2 [0 ] 0
+M_W Ack [0 ] 0
+M_W All_acks_no_sharers [394 ] 394
+
+MM_W Load [0 ] 0
+MM_W Ifetch [0 ] 0
+MM_W Store [0 ] 0
+MM_W L2_Replacement [0 ] 0
+MM_W L1_to_L2 [0 ] 0
+MM_W Ack [0 ] 0
+MM_W All_acks_no_sharers [47 ] 47
+
+IS Load [0 ] 0
+IS Ifetch [0 ] 0
+IS Store [0 ] 0
+IS L2_Replacement [0 ] 0
+IS L1_to_L2 [0 ] 0
+IS Other_GETX [0 ] 0
+IS Other_GETS [0 ] 0
+IS Other_GETS_No_Mig [0 ] 0
+IS Invalidate [0 ] 0
+IS Ack [0 ] 0
+IS Shared_Ack [0 ] 0
+IS Data [0 ] 0
+IS Shared_Data [0 ] 0
+IS Exclusive_Data [394 ] 394
+
+SS Load [0 ] 0
+SS Ifetch [0 ] 0
+SS Store [0 ] 0
+SS L2_Replacement [0 ] 0
+SS L1_to_L2 [0 ] 0
+SS Ack [0 ] 0
+SS Shared_Ack [0 ] 0
+SS All_acks [0 ] 0
+SS All_acks_no_sharers [0 ] 0
+
+OI Load [0 ] 0
+OI Ifetch [0 ] 0
+OI Store [0 ] 0
+OI L2_Replacement [0 ] 0
+OI L1_to_L2 [0 ] 0
+OI Other_GETX [0 ] 0
+OI Other_GETS [0 ] 0
+OI Merged_GETS [0 ] 0
+OI Other_GETS_No_Mig [0 ] 0
+OI Invalidate [0 ] 0
+OI Writeback_Ack [0 ] 0
+
+MI Load [13 ] 13
+MI Ifetch [12 ] 12
+MI Store [8 ] 8
+MI L2_Replacement [0 ] 0
+MI L1_to_L2 [0 ] 0
+MI Other_GETX [0 ] 0
+MI Other_GETS [0 ] 0
+MI Merged_GETS [0 ] 0
+MI Other_GETS_No_Mig [0 ] 0
+MI Invalidate [0 ] 0
+MI Writeback_Ack [425 ] 425
+
+II Load [0 ] 0
+II Ifetch [0 ] 0
+II Store [0 ] 0
+II L2_Replacement [0 ] 0
+II L1_to_L2 [0 ] 0
+II Other_GETX [0 ] 0
+II Other_GETS [0 ] 0
+II Other_GETS_No_Mig [0 ] 0
+II Invalidate [0 ] 0
+II Writeback_Ack [0 ] 0
+II Writeback_Nack [0 ] 0
+
+IT Load [0 ] 0
+IT Ifetch [0 ] 0
+IT Store [0 ] 0
+IT L2_Replacement [0 ] 0
+IT L1_to_L2 [0 ] 0
+IT Complete_L2_to_L1 [0 ] 0
+IT Other_GETX [0 ] 0
+IT Other_GETS [0 ] 0
+IT Merged_GETS [0 ] 0
+IT Other_GETS_No_Mig [0 ] 0
+IT Invalidate [0 ] 0
+
+ST Load [0 ] 0
+ST Ifetch [0 ] 0
+ST Store [0 ] 0
+ST L2_Replacement [0 ] 0
+ST L1_to_L2 [0 ] 0
+ST Complete_L2_to_L1 [0 ] 0
+ST Other_GETX [0 ] 0
+ST Other_GETS [0 ] 0
+ST Merged_GETS [0 ] 0
+ST Other_GETS_No_Mig [0 ] 0
+ST Invalidate [0 ] 0
+
+OT Load [0 ] 0
+OT Ifetch [0 ] 0
+OT Store [0 ] 0
+OT L2_Replacement [0 ] 0
+OT L1_to_L2 [0 ] 0
+OT Complete_L2_to_L1 [0 ] 0
+OT Other_GETX [0 ] 0
+OT Other_GETS [0 ] 0
+OT Merged_GETS [0 ] 0
+OT Other_GETS_No_Mig [0 ] 0
+OT Invalidate [0 ] 0
+
+MT Load [0 ] 0
+MT Ifetch [0 ] 0
+MT Store [0 ] 0
+MT L2_Replacement [0 ] 0
+MT L1_to_L2 [0 ] 0
+MT Complete_L2_to_L1 [45 ] 45
+MT Other_GETX [0 ] 0
+MT Other_GETS [0 ] 0
+MT Merged_GETS [0 ] 0
+MT Other_GETS_No_Mig [0 ] 0
+MT Invalidate [0 ] 0
+
+MMT Load [0 ] 0
+MMT Ifetch [0 ] 0
+MMT Store [0 ] 0
+MMT L2_Replacement [0 ] 0
+MMT L1_to_L2 [0 ] 0
+MMT Complete_L2_to_L1 [24 ] 24
+MMT Other_GETX [0 ] 0
+MMT Other_GETS [0 ] 0
+MMT Merged_GETS [0 ] 0
+MMT Other_GETS_No_Mig [0 ] 0
+MMT Invalidate [0 ] 0
+
+Cache Stats: system.dir_cntrl0.probeFilter
+ system.dir_cntrl0.probeFilter_total_misses: 0
+ system.dir_cntrl0.probeFilter_total_demand_misses: 0
+ system.dir_cntrl0.probeFilter_total_prefetches: 0
+ system.dir_cntrl0.probeFilter_total_sw_prefetches: 0
+ system.dir_cntrl0.probeFilter_total_hw_prefetches: 0
+
+
+Memory controller: system.dir_cntrl0.memBuffer:
memory_total_requests: 522
memory_reads: 441
memory_writes: 81
- memory_refreshes: 171
- memory_total_request_delays: 124
- memory_delays_per_request: 0.237548
+ memory_refreshes: 164
+ memory_total_request_delays: 147
+ memory_delays_per_request: 0.281609
memory_delays_in_input_queue: 2
memory_delays_behind_head_of_bank_queue: 0
- memory_delays_stalled_at_head_of_bank_queue: 122
- memory_stalls_for_bank_busy: 45
+ memory_delays_stalled_at_head_of_bank_queue: 145
+ memory_stalls_for_bank_busy: 27
memory_stalls_for_random_busy: 0
memory_stalls_for_anti_starvation: 0
- memory_stalls_for_arbitration: 8
+ memory_stalls_for_arbitration: 6
memory_stalls_for_bus: 23
memory_stalls_for_tfaw: 0
- memory_stalls_for_read_write_turnaround: 46
+ memory_stalls_for_read_write_turnaround: 89
memory_stalls_for_read_read_turnaround: 0
accesses_per_bank: 18 10 0 36 20 19 31 22 5 4 7 4 22 41 22 3 4 6 7 13 10 18 14 41 16 5 5 12 13 18 14 62
- --- Directory 0 ---
+ --- Directory ---
- Event Counts -
-GETX 106
-GETS 464
-PUT 425
-Unblock 440
-Writeback_Clean 0
-Writeback_Dirty 0
-Writeback_Exclusive_Clean 344
-Writeback_Exclusive_Dirty 81
-DMA_READ 0
-DMA_WRITE 0
-Memory_Data 441
-Memory_Ack 81
-Ack 0
-Shared_Ack 0
-Shared_Data 0
-Exclusive_Data 0
-All_acks_and_data 0
-All_acks_and_data_no_sharers 0
+GETX [53 ] 53
+GETS [410 ] 410
+PUT [425 ] 425
+Unblock [0 ] 0
+UnblockS [0 ] 0
+UnblockM [440 ] 440
+Writeback_Clean [0 ] 0
+Writeback_Dirty [0 ] 0
+Writeback_Exclusive_Clean [344 ] 344
+Writeback_Exclusive_Dirty [81 ] 81
+Pf_Replacement [0 ] 0
+DMA_READ [0 ] 0
+DMA_WRITE [0 ] 0
+Memory_Data [441 ] 441
+Memory_Ack [81 ] 81
+Ack [0 ] 0
+Shared_Ack [0 ] 0
+Shared_Data [0 ] 0
+Data [0 ] 0
+Exclusive_Data [0 ] 0
+All_acks_and_shared_data [0 ] 0
+All_acks_and_owner_data [0 ] 0
+All_acks_and_data_no_sharers [0 ] 0
+All_Unblocks [0 ] 0
- Transitions -
-NO GETX 0 <--
-NO GETS 0 <--
-NO PUT 425
-NO DMA_READ 0 <--
-NO DMA_WRITE 0 <--
-
-O GETX 0 <--
-O GETS 0 <--
-O PUT 0 <--
-O DMA_READ 0 <--
-O DMA_WRITE 0 <--
-
-E GETX 47
-E GETS 394
-E PUT 0 <--
-E DMA_READ 0 <--
-E DMA_WRITE 0 <--
-
-NO_B GETX 0 <--
-NO_B GETS 0 <--
-NO_B PUT 0 <--
-NO_B Unblock 440
-NO_B DMA_READ 0 <--
-NO_B DMA_WRITE 0 <--
-
-O_B GETX 0 <--
-O_B GETS 0 <--
-O_B PUT 0 <--
-O_B Unblock 0 <--
-O_B DMA_READ 0 <--
-O_B DMA_WRITE 0 <--
-
-NO_B_W GETX 0 <--
-NO_B_W GETS 0 <--
-NO_B_W PUT 0 <--
-NO_B_W Unblock 0 <--
-NO_B_W DMA_READ 0 <--
-NO_B_W DMA_WRITE 0 <--
-NO_B_W Memory_Data 441
-
-O_B_W GETX 0 <--
-O_B_W GETS 0 <--
-O_B_W PUT 0 <--
-O_B_W Unblock 0 <--
-O_B_W DMA_READ 0 <--
-O_B_W DMA_WRITE 0 <--
-O_B_W Memory_Data 0 <--
-
-NO_W GETX 0 <--
-NO_W GETS 0 <--
-NO_W PUT 0 <--
-NO_W DMA_READ 0 <--
-NO_W DMA_WRITE 0 <--
-NO_W Memory_Data 0 <--
-
-O_W GETX 0 <--
-O_W GETS 0 <--
-O_W PUT 0 <--
-O_W DMA_READ 0 <--
-O_W DMA_WRITE 0 <--
-O_W Memory_Data 0 <--
-
-NO_DW_B_W GETX 0 <--
-NO_DW_B_W GETS 0 <--
-NO_DW_B_W PUT 0 <--
-NO_DW_B_W DMA_READ 0 <--
-NO_DW_B_W DMA_WRITE 0 <--
-NO_DW_B_W Ack 0 <--
-NO_DW_B_W Exclusive_Data 0 <--
-NO_DW_B_W All_acks_and_data_no_sharers 0 <--
-
-NO_DR_B_W GETX 0 <--
-NO_DR_B_W GETS 0 <--
-NO_DR_B_W PUT 0 <--
-NO_DR_B_W DMA_READ 0 <--
-NO_DR_B_W DMA_WRITE 0 <--
-NO_DR_B_W Memory_Data 0 <--
-NO_DR_B_W Ack 0 <--
-NO_DR_B_W Shared_Ack 0 <--
-NO_DR_B_W Shared_Data 0 <--
-NO_DR_B_W Exclusive_Data 0 <--
-
-NO_DR_B_D GETX 0 <--
-NO_DR_B_D GETS 0 <--
-NO_DR_B_D PUT 0 <--
-NO_DR_B_D DMA_READ 0 <--
-NO_DR_B_D DMA_WRITE 0 <--
-NO_DR_B_D Ack 0 <--
-NO_DR_B_D Shared_Ack 0 <--
-NO_DR_B_D Shared_Data 0 <--
-NO_DR_B_D Exclusive_Data 0 <--
-NO_DR_B_D All_acks_and_data 0 <--
-NO_DR_B_D All_acks_and_data_no_sharers 0 <--
-
-NO_DR_B GETX 0 <--
-NO_DR_B GETS 0 <--
-NO_DR_B PUT 0 <--
-NO_DR_B DMA_READ 0 <--
-NO_DR_B DMA_WRITE 0 <--
-NO_DR_B Ack 0 <--
-NO_DR_B Shared_Ack 0 <--
-NO_DR_B Shared_Data 0 <--
-NO_DR_B Exclusive_Data 0 <--
-NO_DR_B All_acks_and_data 0 <--
-NO_DR_B All_acks_and_data_no_sharers 0 <--
-
-NO_DW_W GETX 0 <--
-NO_DW_W GETS 0 <--
-NO_DW_W PUT 0 <--
-NO_DW_W DMA_READ 0 <--
-NO_DW_W DMA_WRITE 0 <--
-NO_DW_W Memory_Ack 0 <--
-
-O_DR_B_W GETX 0 <--
-O_DR_B_W GETS 0 <--
-O_DR_B_W PUT 0 <--
-O_DR_B_W DMA_READ 0 <--
-O_DR_B_W DMA_WRITE 0 <--
-O_DR_B_W Memory_Data 0 <--
-
-O_DR_B GETX 0 <--
-O_DR_B GETS 0 <--
-O_DR_B PUT 0 <--
-O_DR_B DMA_READ 0 <--
-O_DR_B DMA_WRITE 0 <--
-O_DR_B Ack 0 <--
-O_DR_B All_acks_and_data_no_sharers 0 <--
-
-WB GETX 4
-WB GETS 15
-WB PUT 0 <--
-WB Unblock 0 <--
-WB Writeback_Clean 0 <--
-WB Writeback_Dirty 0 <--
-WB Writeback_Exclusive_Clean 344
-WB Writeback_Exclusive_Dirty 81
-WB DMA_READ 0 <--
-WB DMA_WRITE 0 <--
-
-WB_O_W GETX 0 <--
-WB_O_W GETS 0 <--
-WB_O_W PUT 0 <--
-WB_O_W DMA_READ 0 <--
-WB_O_W DMA_WRITE 0 <--
-WB_O_W Memory_Ack 0 <--
-
-WB_E_W GETX 55
-WB_E_W GETS 55
-WB_E_W PUT 0 <--
-WB_E_W DMA_READ 0 <--
-WB_E_W DMA_WRITE 0 <--
-WB_E_W Memory_Ack 81
-
+NX GETX [0 ] 0
+NX GETS [0 ] 0
+NX PUT [0 ] 0
+NX Pf_Replacement [0 ] 0
+NX DMA_READ [0 ] 0
+NX DMA_WRITE [0 ] 0
+
+NO GETX [0 ] 0
+NO GETS [0 ] 0
+NO PUT [425 ] 425
+NO Pf_Replacement [0 ] 0
+NO DMA_READ [0 ] 0
+NO DMA_WRITE [0 ] 0
+
+S GETX [0 ] 0
+S GETS [0 ] 0
+S PUT [0 ] 0
+S Pf_Replacement [0 ] 0
+S DMA_READ [0 ] 0
+S DMA_WRITE [0 ] 0
+
+O GETX [0 ] 0
+O GETS [0 ] 0
+O PUT [0 ] 0
+O Pf_Replacement [0 ] 0
+O DMA_READ [0 ] 0
+O DMA_WRITE [0 ] 0
+
+E GETX [47 ] 47
+E GETS [394 ] 394
+E PUT [0 ] 0
+E DMA_READ [0 ] 0
+E DMA_WRITE [0 ] 0
+
+O_R GETX [0 ] 0
+O_R GETS [0 ] 0
+O_R PUT [0 ] 0
+O_R Pf_Replacement [0 ] 0
+O_R DMA_READ [0 ] 0
+O_R DMA_WRITE [0 ] 0
+O_R Ack [0 ] 0
+O_R All_acks_and_data_no_sharers [0 ] 0
+
+S_R GETX [0 ] 0
+S_R GETS [0 ] 0
+S_R PUT [0 ] 0
+S_R Pf_Replacement [0 ] 0
+S_R DMA_READ [0 ] 0
+S_R DMA_WRITE [0 ] 0
+S_R Ack [0 ] 0
+S_R Data [0 ] 0
+S_R All_acks_and_data_no_sharers [0 ] 0
+
+NO_R GETX [0 ] 0
+NO_R GETS [0 ] 0
+NO_R PUT [0 ] 0
+NO_R Pf_Replacement [0 ] 0
+NO_R DMA_READ [0 ] 0
+NO_R DMA_WRITE [0 ] 0
+NO_R Ack [0 ] 0
+NO_R Data [0 ] 0
+NO_R Exclusive_Data [0 ] 0
+NO_R All_acks_and_data_no_sharers [0 ] 0
+
+NO_B GETX [0 ] 0
+NO_B GETS [0 ] 0
+NO_B PUT [0 ] 0
+NO_B UnblockS [0 ] 0
+NO_B UnblockM [440 ] 440
+NO_B Pf_Replacement [0 ] 0
+NO_B DMA_READ [0 ] 0
+NO_B DMA_WRITE [0 ] 0
+
+NO_B_X GETX [0 ] 0
+NO_B_X GETS [0 ] 0
+NO_B_X PUT [0 ] 0
+NO_B_X UnblockS [0 ] 0
+NO_B_X UnblockM [0 ] 0
+NO_B_X Pf_Replacement [0 ] 0
+
+NO_B_S GETX [0 ] 0
+NO_B_S GETS [0 ] 0
+NO_B_S PUT [0 ] 0
+NO_B_S UnblockS [0 ] 0
+NO_B_S UnblockM [0 ] 0
+NO_B_S Pf_Replacement [0 ] 0
+NO_B_S DMA_READ [0 ] 0
+NO_B_S DMA_WRITE [0 ] 0
+
+NO_B_S_W GETX [0 ] 0
+NO_B_S_W GETS [0 ] 0
+NO_B_S_W PUT [0 ] 0
+NO_B_S_W UnblockS [0 ] 0
+NO_B_S_W Pf_Replacement [0 ] 0
+NO_B_S_W DMA_READ [0 ] 0
+NO_B_S_W DMA_WRITE [0 ] 0
+NO_B_S_W All_Unblocks [0 ] 0
+
+O_B GETX [0 ] 0
+O_B GETS [0 ] 0
+O_B PUT [0 ] 0
+O_B UnblockS [0 ] 0
+O_B Pf_Replacement [0 ] 0
+O_B DMA_READ [0 ] 0
+O_B DMA_WRITE [0 ] 0
+
+NO_B_W GETX [0 ] 0
+NO_B_W GETS [0 ] 0
+NO_B_W PUT [0 ] 0
+NO_B_W UnblockS [0 ] 0
+NO_B_W UnblockM [0 ] 0
+NO_B_W Pf_Replacement [0 ] 0
+NO_B_W DMA_READ [0 ] 0
+NO_B_W DMA_WRITE [0 ] 0
+NO_B_W Memory_Data [441 ] 441
+
+O_B_W GETX [0 ] 0
+O_B_W GETS [0 ] 0
+O_B_W PUT [0 ] 0
+O_B_W UnblockS [0 ] 0
+O_B_W Pf_Replacement [0 ] 0
+O_B_W DMA_READ [0 ] 0
+O_B_W DMA_WRITE [0 ] 0
+O_B_W Memory_Data [0 ] 0
+
+NO_W GETX [0 ] 0
+NO_W GETS [0 ] 0
+NO_W PUT [0 ] 0
+NO_W Pf_Replacement [0 ] 0
+NO_W DMA_READ [0 ] 0
+NO_W DMA_WRITE [0 ] 0
+NO_W Memory_Data [0 ] 0
+
+O_W GETX [0 ] 0
+O_W GETS [0 ] 0
+O_W PUT [0 ] 0
+O_W Pf_Replacement [0 ] 0
+O_W DMA_READ [0 ] 0
+O_W DMA_WRITE [0 ] 0
+O_W Memory_Data [0 ] 0
+
+NO_DW_B_W GETX [0 ] 0
+NO_DW_B_W GETS [0 ] 0
+NO_DW_B_W PUT [0 ] 0
+NO_DW_B_W Pf_Replacement [0 ] 0
+NO_DW_B_W DMA_READ [0 ] 0
+NO_DW_B_W DMA_WRITE [0 ] 0
+NO_DW_B_W Ack [0 ] 0
+NO_DW_B_W Data [0 ] 0
+NO_DW_B_W Exclusive_Data [0 ] 0
+NO_DW_B_W All_acks_and_data_no_sharers [0 ] 0
+
+NO_DR_B_W GETX [0 ] 0
+NO_DR_B_W GETS [0 ] 0
+NO_DR_B_W PUT [0 ] 0
+NO_DR_B_W Pf_Replacement [0 ] 0
+NO_DR_B_W DMA_READ [0 ] 0
+NO_DR_B_W DMA_WRITE [0 ] 0
+NO_DR_B_W Memory_Data [0 ] 0
+NO_DR_B_W Ack [0 ] 0
+NO_DR_B_W Shared_Ack [0 ] 0
+NO_DR_B_W Shared_Data [0 ] 0
+NO_DR_B_W Data [0 ] 0
+NO_DR_B_W Exclusive_Data [0 ] 0
+
+NO_DR_B_D GETX [0 ] 0
+NO_DR_B_D GETS [0 ] 0
+NO_DR_B_D PUT [0 ] 0
+NO_DR_B_D Pf_Replacement [0 ] 0
+NO_DR_B_D DMA_READ [0 ] 0
+NO_DR_B_D DMA_WRITE [0 ] 0
+NO_DR_B_D Ack [0 ] 0
+NO_DR_B_D Shared_Ack [0 ] 0
+NO_DR_B_D Shared_Data [0 ] 0
+NO_DR_B_D Data [0 ] 0
+NO_DR_B_D Exclusive_Data [0 ] 0
+NO_DR_B_D All_acks_and_shared_data [0 ] 0
+NO_DR_B_D All_acks_and_owner_data [0 ] 0
+NO_DR_B_D All_acks_and_data_no_sharers [0 ] 0
+
+NO_DR_B GETX [0 ] 0
+NO_DR_B GETS [0 ] 0
+NO_DR_B PUT [0 ] 0
+NO_DR_B Pf_Replacement [0 ] 0
+NO_DR_B DMA_READ [0 ] 0
+NO_DR_B DMA_WRITE [0 ] 0
+NO_DR_B Ack [0 ] 0
+NO_DR_B Shared_Ack [0 ] 0
+NO_DR_B Shared_Data [0 ] 0
+NO_DR_B Data [0 ] 0
+NO_DR_B Exclusive_Data [0 ] 0
+NO_DR_B All_acks_and_shared_data [0 ] 0
+NO_DR_B All_acks_and_owner_data [0 ] 0
+NO_DR_B All_acks_and_data_no_sharers [0 ] 0
+
+NO_DW_W GETX [0 ] 0
+NO_DW_W GETS [0 ] 0
+NO_DW_W PUT [0 ] 0
+NO_DW_W Pf_Replacement [0 ] 0
+NO_DW_W DMA_READ [0 ] 0
+NO_DW_W DMA_WRITE [0 ] 0
+NO_DW_W Memory_Ack [0 ] 0
+
+O_DR_B_W GETX [0 ] 0
+O_DR_B_W GETS [0 ] 0
+O_DR_B_W PUT [0 ] 0
+O_DR_B_W Pf_Replacement [0 ] 0
+O_DR_B_W DMA_READ [0 ] 0
+O_DR_B_W DMA_WRITE [0 ] 0
+O_DR_B_W Memory_Data [0 ] 0
+O_DR_B_W Ack [0 ] 0
+O_DR_B_W Shared_Ack [0 ] 0
+
+O_DR_B GETX [0 ] 0
+O_DR_B GETS [0 ] 0
+O_DR_B PUT [0 ] 0
+O_DR_B Pf_Replacement [0 ] 0
+O_DR_B DMA_READ [0 ] 0
+O_DR_B DMA_WRITE [0 ] 0
+O_DR_B Ack [0 ] 0
+O_DR_B Shared_Ack [0 ] 0
+O_DR_B All_acks_and_owner_data [0 ] 0
+O_DR_B All_acks_and_data_no_sharers [0 ] 0
+
+WB GETX [4 ] 4
+WB GETS [14 ] 14
+WB PUT [0 ] 0
+WB Unblock [0 ] 0
+WB Writeback_Clean [0 ] 0
+WB Writeback_Dirty [0 ] 0
+WB Writeback_Exclusive_Clean [344 ] 344
+WB Writeback_Exclusive_Dirty [81 ] 81
+WB Pf_Replacement [0 ] 0
+WB DMA_READ [0 ] 0
+WB DMA_WRITE [0 ] 0
+
+WB_O_W GETX [0 ] 0
+WB_O_W GETS [0 ] 0
+WB_O_W PUT [0 ] 0
+WB_O_W Pf_Replacement [0 ] 0
+WB_O_W DMA_READ [0 ] 0
+WB_O_W DMA_WRITE [0 ] 0
+WB_O_W Memory_Ack [0 ] 0
+
+WB_E_W GETX [2 ] 2
+WB_E_W GETS [2 ] 2
+WB_E_W PUT [0 ] 0
+WB_E_W Pf_Replacement [0 ] 0
+WB_E_W DMA_READ [0 ] 0
+WB_E_W DMA_WRITE [0 ] 0
+WB_E_W Memory_Ack \ No newline at end of file
diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/simout b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/simout
index 275f04f5f..76a97a409 100755
--- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/simout
+++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/simout
@@ -5,13 +5,13 @@ The Regents of The University of Michigan
All Rights Reserved
-M5 compiled Jan 28 2010 11:30:01
-M5 revision 6068d4fc30d3+ 6931+ default qtip tip brad/rubycfg_regress_udpate
-M5 started Jan 28 2010 11:48:25
-M5 executing on svvint06
+M5 compiled Aug 5 2010 14:43:33
+M5 revision c5f5b5533e96+ 7536+ default qtip tip brad/regress_updates
+M5 started Aug 5 2010 14:44:19
+M5 executing on svvint09
command line: build/ALPHA_SE_MOESI_hammer/m5.fast -d build/ALPHA_SE_MOESI_hammer/tests/fast/quick/00.hello/alpha/tru64/simple-timing-ruby-MOESI_hammer -re tests/run.py build/ALPHA_SE_MOESI_hammer/tests/fast/quick/00.hello/alpha/tru64/simple-timing-ruby-MOESI_hammer
Global frequency set at 1000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
Hello world!
-Exiting @ tick 81672 because target called exit()
+Exiting @ tick 78408 because target called exit()
diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/stats.txt b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/stats.txt
index 82f130963..58de899ed 100644
--- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/stats.txt
+++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/stats.txt
@@ -1,13 +1,13 @@
---------- Begin Simulation Statistics ----------
-host_inst_rate 32212 # Simulator instruction rate (inst/s)
-host_mem_usage 212236 # Number of bytes of host memory used
-host_seconds 0.08 # Real time elapsed on the host
-host_tick_rate 1020887 # Simulator tick rate (ticks/s)
+host_inst_rate 42947 # Simulator instruction rate (inst/s)
+host_mem_usage 211060 # Number of bytes of host memory used
+host_seconds 0.06 # Real time elapsed on the host
+host_tick_rate 1306713 # Simulator tick rate (ticks/s)
sim_freq 1000000000 # Frequency of simulated ticks
sim_insts 2577 # Number of instructions simulated
-sim_seconds 0.000082 # Number of seconds simulated
-sim_ticks 81672 # Number of ticks simulated
+sim_seconds 0.000078 # Number of seconds simulated
+sim_ticks 78408 # Number of ticks simulated
system.cpu.dtb.data_accesses 717 # DTB accesses
system.cpu.dtb.data_acv 0 # DTB access violations
system.cpu.dtb.data_hits 709 # DTB hits
@@ -42,7 +42,7 @@ system.cpu.itb.write_acv 0 # DT
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
-system.cpu.numCycles 81672 # number of cpu cycles simulated
+system.cpu.numCycles 78408 # number of cpu cycles simulated
system.cpu.num_insts 2577 # Number of instructions executed
system.cpu.num_refs 717 # Number of memory references
system.cpu.workload.PROG:num_syscalls 4 # Number of system calls