diff options
Diffstat (limited to 'tests/quick/00.hello')
| -rwxr-xr-x | tests/quick/00.hello/ref/x86/linux/o3-timing/simout | 10 | ||||
| -rw-r--r-- | tests/quick/00.hello/ref/x86/linux/o3-timing/stats.txt | 685 |
2 files changed, 348 insertions, 347 deletions
diff --git a/tests/quick/00.hello/ref/x86/linux/o3-timing/simout b/tests/quick/00.hello/ref/x86/linux/o3-timing/simout index b2dde915e..1943466e8 100755 --- a/tests/quick/00.hello/ref/x86/linux/o3-timing/simout +++ b/tests/quick/00.hello/ref/x86/linux/o3-timing/simout @@ -5,13 +5,13 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 8 2011 00:58:32 -M5 revision 705a4d351a43 7939 default qtip resforflagsstats.patch tip -M5 started Feb 8 2011 00:58:34 +M5 compiled Feb 12 2011 02:22:23 +M5 revision 5e76f9de6972 7961 default qtip tip x86branchdetectstats.patch +M5 started Feb 12 2011 02:22:27 M5 executing on burrito -command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/quick/00.hello/x86/linux/o3-timing -re tests/run.py build/X86_SE/tests/fast/quick/00.hello/x86/linux/o3-timing +command line: build/X86_SE/m5.opt -d build/X86_SE/tests/opt/quick/00.hello/x86/linux/o3-timing -re tests/run.py build/X86_SE/tests/opt/quick/00.hello/x86/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. Hello world! -Exiting @ tick 13637500 because target called exit() +Exiting @ tick 11421500 because target called exit() diff --git a/tests/quick/00.hello/ref/x86/linux/o3-timing/stats.txt b/tests/quick/00.hello/ref/x86/linux/o3-timing/stats.txt index bdaed3cec..c2dfaa3ff 100644 --- a/tests/quick/00.hello/ref/x86/linux/o3-timing/stats.txt +++ b/tests/quick/00.hello/ref/x86/linux/o3-timing/stats.txt @@ -1,41 +1,41 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 59245 # Simulator instruction rate (inst/s) -host_mem_usage 228168 # Number of bytes of host memory used -host_seconds 0.17 # Real time elapsed on the host -host_tick_rate 82238527 # Simulator tick rate (ticks/s) +host_inst_rate 47598 # Simulator instruction rate (inst/s) +host_mem_usage 231896 # Number of bytes of host memory used +host_seconds 0.21 # Real time elapsed on the host +host_tick_rate 55349277 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 9809 # Number of instructions simulated -sim_seconds 0.000014 # Number of seconds simulated -sim_ticks 13637500 # Number of ticks simulated +sim_seconds 0.000011 # Number of seconds simulated +sim_ticks 11421500 # Number of ticks simulated system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.BTBHits 715 # Number of BTB hits -system.cpu.BPredUnit.BTBLookups 1829 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 944 # Number of BTB hits +system.cpu.BPredUnit.BTBLookups 2550 # Number of BTB lookups system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. -system.cpu.BPredUnit.condIncorrect 455 # Number of conditional branches incorrect -system.cpu.BPredUnit.condPredicted 1876 # Number of conditional branches predicted -system.cpu.BPredUnit.lookups 1876 # Number of BP lookups +system.cpu.BPredUnit.condIncorrect 485 # Number of conditional branches incorrect +system.cpu.BPredUnit.condPredicted 2777 # Number of conditional branches predicted +system.cpu.BPredUnit.lookups 2777 # Number of BP lookups system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. system.cpu.commit.COM:branches 1214 # Number of branches committed -system.cpu.commit.COM:bw_lim_events 22 # number cycles where commit BW limit reached +system.cpu.commit.COM:bw_lim_events 139 # number cycles where commit BW limit reached system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits -system.cpu.commit.COM:committed_per_cycle::samples 15018 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::mean 0.653150 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::stdev 1.090994 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::samples 11906 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::mean 0.823870 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::stdev 1.588166 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::0 9552 63.60% 63.60% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::1 2996 19.95% 83.55% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::2 1196 7.96% 91.52% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::3 909 6.05% 97.57% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::4 244 1.62% 99.19% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::5 60 0.40% 99.59% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::6 31 0.21% 99.80% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::7 8 0.05% 99.85% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::8 22 0.15% 100.00% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::0 8274 69.49% 69.49% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::1 1230 10.33% 79.83% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::2 588 4.94% 84.76% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::3 963 8.09% 92.85% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::4 395 3.32% 96.17% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::5 136 1.14% 97.31% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::6 125 1.05% 98.36% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::7 56 0.47% 98.83% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::8 139 1.17% 100.00% # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::total 15018 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::total 11906 # Number of insts commited each cycle system.cpu.commit.COM:count 9809 # Number of instructions committed system.cpu.commit.COM:fp_insts 0 # Number of committed floating point instructions. system.cpu.commit.COM:function_calls 0 # Number of function calls committed. @@ -44,416 +44,417 @@ system.cpu.commit.COM:loads 1056 # Nu system.cpu.commit.COM:membars 0 # Number of memory barriers committed system.cpu.commit.COM:refs 1990 # Number of memory references committed system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.branchMispredicts 455 # The number of times a branch was mispredicted +system.cpu.commit.branchMispredicts 485 # The number of times a branch was mispredicted system.cpu.commit.commitCommittedInsts 9809 # The number of committed instructions system.cpu.commit.commitNonSpecStalls 13 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 3810 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 9374 # The number of squashed insts skipped by commit system.cpu.committedInsts 9809 # Number of Instructions Simulated system.cpu.committedInsts_total 9809 # Number of Instructions Simulated -system.cpu.cpi 2.780712 # CPI: Cycles Per Instruction -system.cpu.cpi_total 2.780712 # CPI: Total CPI of All Threads -system.cpu.dcache.ReadReq_accesses 1299 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 34989.361702 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 34992.307692 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 1205 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 3289000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.072363 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 94 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits 29 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency 2274500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.050038 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 65 # number of ReadReq MSHR misses +system.cpu.cpi 2.328882 # CPI: Cycles Per Instruction +system.cpu.cpi_total 2.328882 # CPI: Total CPI of All Threads +system.cpu.dcache.ReadReq_accesses 1541 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 34473.684211 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 35119.402985 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 1427 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 3930000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.073978 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 114 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_hits 47 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_miss_latency 2353000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.043478 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_misses 67 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 934 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 33138.977636 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35814.102564 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 34089.456869 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 36012.987013 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_hits 621 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 10372500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 10670000 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_rate 0.335118 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_misses 313 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_hits 235 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency 2793500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.083512 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 78 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_hits 236 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_miss_latency 2773000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate 0.082441 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses 77 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 12.859155 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 14.321678 # Average number of references to valid blocks. system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 2233 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 33566.339066 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 35440.559441 # average overall mshr miss latency -system.cpu.dcache.demand_hits 1826 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 13661500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.182266 # miss rate for demand accesses -system.cpu.dcache.demand_misses 407 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 264 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 5068000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.064039 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 143 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_accesses 2475 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 34192.037471 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 35597.222222 # average overall mshr miss latency +system.cpu.dcache.demand_hits 2048 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 14600000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.172525 # miss rate for demand accesses +system.cpu.dcache.demand_misses 427 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 283 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 5126000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.058182 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 144 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_%::0 0.021266 # Average percentage of cache occupancy -system.cpu.dcache.occ_blocks::0 87.104239 # Average occupied blocks per context -system.cpu.dcache.overall_accesses 2233 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 33566.339066 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 35440.559441 # average overall mshr miss latency +system.cpu.dcache.occ_%::0 0.020970 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::0 85.892970 # Average occupied blocks per context +system.cpu.dcache.overall_accesses 2475 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 34192.037471 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 35597.222222 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 1826 # number of overall hits -system.cpu.dcache.overall_miss_latency 13661500 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.182266 # miss rate for overall accesses -system.cpu.dcache.overall_misses 407 # number of overall misses -system.cpu.dcache.overall_mshr_hits 264 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 5068000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.064039 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 143 # number of overall MSHR misses +system.cpu.dcache.overall_hits 2048 # number of overall hits +system.cpu.dcache.overall_miss_latency 14600000 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.172525 # miss rate for overall accesses +system.cpu.dcache.overall_misses 427 # number of overall misses +system.cpu.dcache.overall_mshr_hits 283 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 5126000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.058182 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 144 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.sampled_refs 142 # Sample count of references to valid blocks. +system.cpu.dcache.sampled_refs 143 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 87.104239 # Cycle average of tags in use -system.cpu.dcache.total_refs 1826 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 85.892970 # Cycle average of tags in use +system.cpu.dcache.total_refs 2048 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 0 # number of writebacks -system.cpu.decode.DECODE:BlockedCycles 420 # Number of cycles decode is blocked -system.cpu.decode.DECODE:DecodedInsts 15296 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 6181 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 8360 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 701 # Number of cycles decode is squashing -system.cpu.decode.DECODE:UnblockCycles 57 # Number of cycles decode is unblocking -system.cpu.fetch.Branches 1876 # Number of branches that fetch encountered -system.cpu.fetch.CacheLines 1264 # Number of cache lines fetched -system.cpu.fetch.Cycles 9026 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.IcacheSquashes 121 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.Insts 8825 # Number of instructions fetch has processed -system.cpu.fetch.MiscStallCycles 2 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.SquashCycles 464 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.068778 # Number of branch fetches per cycle -system.cpu.fetch.icacheStallCycles 1264 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.predictedBranches 715 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 0.323545 # Number of inst fetches per cycle -system.cpu.fetch.rateDist::samples 15719 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.009352 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.179835 # Number of instructions fetched each cycle (Total) +system.cpu.decode.DECODE:BlockedCycles 1367 # Number of cycles decode is blocked +system.cpu.decode.DECODE:DecodedInsts 22275 # Number of instructions handled by decode +system.cpu.decode.DECODE:IdleCycles 7155 # Number of cycles decode is idle +system.cpu.decode.DECODE:RunCycles 3308 # Number of cycles decode is running +system.cpu.decode.DECODE:SquashCycles 1504 # Number of cycles decode is squashing +system.cpu.decode.DECODE:UnblockCycles 76 # Number of cycles decode is unblocking +system.cpu.fetch.Branches 2777 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 1732 # Number of cache lines fetched +system.cpu.fetch.Cycles 3623 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 245 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.Insts 12976 # Number of instructions fetch has processed +system.cpu.fetch.MiscStallCycles 4 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.SquashCycles 508 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.121564 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 1732 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 944 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 0.568027 # Number of inst fetches per cycle +system.cpu.fetch.rateDist::samples 13410 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.734526 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.109133 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 7007 44.58% 44.58% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 4504 28.65% 73.23% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1838 11.69% 84.92% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 2072 13.18% 98.10% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 57 0.36% 98.47% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 222 1.41% 99.88% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 6 0.04% 99.92% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 8 0.05% 99.97% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 5 0.03% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 9877 73.65% 73.65% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 162 1.21% 74.86% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 123 0.92% 75.78% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 227 1.69% 77.47% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 192 1.43% 78.90% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 174 1.30% 80.20% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 266 1.98% 82.18% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 175 1.30% 83.49% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 2214 16.51% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 15719 # Number of instructions fetched each cycle (Total) -system.cpu.fp_regfile_reads 2 # number of floating regfile reads -system.cpu.icache.ReadReq_accesses 1264 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 37405.594406 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 35046.332046 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 978 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 10698000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.226266 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 286 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_hits 27 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 9077000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.204905 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 259 # number of ReadReq MSHR misses +system.cpu.fetch.rateDist::total 13410 # Number of instructions fetched each cycle (Total) +system.cpu.fp_regfile_reads 4 # number of floating regfile reads +system.cpu.icache.ReadReq_accesses 1732 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 36454.794521 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 35105.084746 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 1367 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 13306000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.210739 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 365 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_hits 70 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_miss_latency 10356000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.170323 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_misses 295 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.icache.avg_refs 3.776062 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 4.633898 # Average number of references to valid blocks. system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 1264 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 37405.594406 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 35046.332046 # average overall mshr miss latency -system.cpu.icache.demand_hits 978 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 10698000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.226266 # miss rate for demand accesses -system.cpu.icache.demand_misses 286 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 27 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 9077000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.204905 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 259 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_accesses 1732 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 36454.794521 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 35105.084746 # average overall mshr miss latency +system.cpu.icache.demand_hits 1367 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 13306000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.210739 # miss rate for demand accesses +system.cpu.icache.demand_misses 365 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 70 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 10356000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0.170323 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_misses 295 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_%::0 0.062320 # Average percentage of cache occupancy -system.cpu.icache.occ_blocks::0 127.631724 # Average occupied blocks per context -system.cpu.icache.overall_accesses 1264 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 37405.594406 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 35046.332046 # average overall mshr miss latency +system.cpu.icache.occ_%::0 0.070726 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::0 144.846093 # Average occupied blocks per context +system.cpu.icache.overall_accesses 1732 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 36454.794521 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 35105.084746 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 978 # number of overall hits -system.cpu.icache.overall_miss_latency 10698000 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.226266 # miss rate for overall accesses -system.cpu.icache.overall_misses 286 # number of overall misses -system.cpu.icache.overall_mshr_hits 27 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 9077000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.204905 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 259 # number of overall MSHR misses +system.cpu.icache.overall_hits 1367 # number of overall hits +system.cpu.icache.overall_miss_latency 13306000 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.210739 # miss rate for overall accesses +system.cpu.icache.overall_misses 365 # number of overall misses +system.cpu.icache.overall_mshr_hits 70 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 10356000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0.170323 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_misses 295 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.sampled_refs 259 # Sample count of references to valid blocks. +system.cpu.icache.sampled_refs 295 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 127.631724 # Cycle average of tags in use -system.cpu.icache.total_refs 978 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 144.846093 # Cycle average of tags in use +system.cpu.icache.total_refs 1367 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idleCycles 11557 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.EXEC:branches 1339 # Number of branches executed +system.cpu.idleCycles 9434 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.EXEC:branches 1551 # Number of branches executed system.cpu.iew.EXEC:nop 0 # number of nop insts executed -system.cpu.iew.EXEC:rate 0.445373 # Inst execution rate -system.cpu.iew.EXEC:refs 2437 # number of memory reference insts executed -system.cpu.iew.EXEC:stores 1088 # Number of stores executed +system.cpu.iew.EXEC:rate 0.676151 # Inst execution rate +system.cpu.iew.EXEC:refs 2971 # number of memory reference insts executed +system.cpu.iew.EXEC:stores 1306 # Number of stores executed system.cpu.iew.EXEC:swp 0 # number of swp insts executed -system.cpu.iew.WB:consumers 9192 # num instructions consuming a value -system.cpu.iew.WB:count 11991 # cumulative count of insts written-back -system.cpu.iew.WB:fanout 0.803198 # average fanout of values written-back +system.cpu.iew.WB:consumers 14704 # num instructions consuming a value +system.cpu.iew.WB:count 15138 # cumulative count of insts written-back +system.cpu.iew.WB:fanout 0.679747 # average fanout of values written-back system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 7383 # num instructions producing a value -system.cpu.iew.WB:rate 0.439617 # insts written-back per cycle -system.cpu.iew.WB:sent 12024 # cumulative count of insts sent to commit -system.cpu.iew.branchMispredicts 474 # Number of branch mispredicts detected at execute -system.cpu.iew.iewBlockCycles 40 # Number of cycles IEW is blocking -system.cpu.iew.iewDispLoadInsts 1510 # Number of dispatched load instructions -system.cpu.iew.iewDispNonSpecInsts 16 # Number of dispatched non-speculative instructions -system.cpu.iew.iewDispSquashedInsts 424 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispStoreInsts 1230 # Number of dispatched store instructions -system.cpu.iew.iewDispatchedInsts 13620 # Number of instructions dispatched to IQ -system.cpu.iew.iewExecLoadInsts 1349 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 556 # Number of squashed instructions skipped in execute -system.cpu.iew.iewExecutedInsts 12148 # Number of executed instructions -system.cpu.iew.iewIQFullEvents 2 # Number of times the IQ has become full, causing a stall +system.cpu.iew.WB:producers 9995 # num instructions producing a value +system.cpu.iew.WB:rate 0.662669 # insts written-back per cycle +system.cpu.iew.WB:sent 15263 # cumulative count of insts sent to commit +system.cpu.iew.branchMispredicts 565 # Number of branch mispredicts detected at execute +system.cpu.iew.iewBlockCycles 187 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 2105 # Number of dispatched load instructions +system.cpu.iew.iewDispNonSpecInsts 30 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispSquashedInsts 207 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 1639 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 19184 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 1665 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 710 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 15446 # Number of executed instructions +system.cpu.iew.iewIQFullEvents 12 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.iewSquashCycles 701 # Number of cycles IEW is squashing -system.cpu.iew.iewUnblockCycles 5 # Number of cycles IEW is unblocking +system.cpu.iew.iewSquashCycles 1504 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 20 # Number of cycles IEW is unblocking system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread.0.forwLoads 23 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread.0.ignoredResponses 1 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread.0.forwLoads 68 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread.0.ignoredResponses 12 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.0.memOrderViolation 10 # Number of memory ordering violations -system.cpu.iew.lsq.thread.0.rescheduledLoads 0 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 454 # Number of loads squashed -system.cpu.iew.lsq.thread.0.squashedStores 296 # Number of stores squashed -system.cpu.iew.memOrderViolationEvents 10 # Number of memory order violations -system.cpu.iew.predictedNotTakenIncorrect 385 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.predictedTakenIncorrect 89 # Number of branches that were predicted taken incorrectly -system.cpu.int_regfile_reads 19557 # number of integer regfile reads -system.cpu.int_regfile_writes 11326 # number of integer regfile writes -system.cpu.ipc 0.359620 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.359620 # IPC: Total IPC of All Threads -system.cpu.iq.ISSUE:FU_type_0::No_OpClass 3 0.02% 0.02% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntAlu 10141 79.83% 79.85% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntMult 0 0.00% 79.85% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 79.85% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatAdd 0 0.00% 79.85% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 79.85% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 79.85% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 79.85% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 79.85% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 79.85% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdAdd 0 0.00% 79.85% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 79.85% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 79.85% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 79.85% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 79.85% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 79.85% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 79.85% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 79.85% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 79.85% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 79.85% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 79.85% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd 0 0.00% 79.85% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 79.85% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp 0 0.00% 79.85% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt 0 0.00% 79.85% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv 0 0.00% 79.85% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc 0 0.00% 79.85% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 79.85% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc 0 0.00% 79.85% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 79.85% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::MemRead 1414 11.13% 90.98% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::MemWrite 1146 9.02% 100.00% # Type of FU issued +system.cpu.iew.lsq.thread.0.memOrderViolation 31 # Number of memory ordering violations +system.cpu.iew.lsq.thread.0.rescheduledLoads 1 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread.0.squashedLoads 1049 # Number of loads squashed +system.cpu.iew.lsq.thread.0.squashedStores 705 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 31 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 496 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 69 # Number of branches that were predicted taken incorrectly +system.cpu.int_regfile_reads 23051 # number of integer regfile reads +system.cpu.int_regfile_writes 14062 # number of integer regfile writes +system.cpu.ipc 0.429391 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.429391 # IPC: Total IPC of All Threads +system.cpu.iq.ISSUE:FU_type_0::No_OpClass 4 0.02% 0.02% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntAlu 12967 80.26% 80.29% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntMult 0 0.00% 80.29% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 80.29% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatAdd 0 0.00% 80.29% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 80.29% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 80.29% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 80.29% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 80.29% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 80.29% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdAdd 0 0.00% 80.29% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 80.29% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 80.29% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 80.29% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 80.29% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 80.29% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 80.29% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 80.29% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 80.29% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 80.29% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 80.29% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd 0 0.00% 80.29% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 80.29% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp 0 0.00% 80.29% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt 0 0.00% 80.29% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv 0 0.00% 80.29% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc 0 0.00% 80.29% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 80.29% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc 0 0.00% 80.29% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 80.29% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::MemRead 1786 11.05% 91.34% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::MemWrite 1399 8.66% 100.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::total 12704 # Type of FU issued -system.cpu.iq.ISSUE:fu_busy_cnt 4 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_rate 0.000315 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:FU_type_0::total 16156 # Type of FU issued +system.cpu.iq.ISSUE:fu_busy_cnt 142 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_rate 0.008789 # FU busy rate (busy events/executed inst) system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntAlu 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdAdd 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdAlu 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdCmp 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdCvt 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdMisc 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdMult 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdShift 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::MemRead 4 100.00% 100.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::MemWrite 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntAlu 97 68.31% 68.31% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 68.31% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 68.31% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 68.31% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 68.31% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 68.31% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 68.31% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 68.31% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 68.31% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdAdd 0 0.00% 68.31% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 68.31% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdAlu 0 0.00% 68.31% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdCmp 0 0.00% 68.31% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdCvt 0 0.00% 68.31% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdMisc 0 0.00% 68.31% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdMult 0 0.00% 68.31% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 68.31% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdShift 0 0.00% 68.31% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 68.31% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 68.31% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 68.31% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 68.31% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 68.31% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 68.31% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 68.31% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 68.31% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 68.31% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 68.31% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 68.31% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::MemRead 26 18.31% 86.62% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::MemWrite 19 13.38% 100.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:issued_per_cycle::samples 15719 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::mean 0.808194 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::stdev 0.980491 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::samples 13410 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::mean 1.204773 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.912582 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::0 7896 50.23% 50.23% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::1 4146 26.38% 76.61% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::2 2688 17.10% 93.71% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::3 806 5.13% 98.84% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::4 156 0.99% 99.83% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::5 22 0.14% 99.97% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::6 5 0.03% 100.00% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::0 8282 61.76% 61.76% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::1 1307 9.75% 71.51% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::2 986 7.35% 78.86% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::3 745 5.56% 84.41% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::4 787 5.87% 90.28% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::5 588 4.38% 94.67% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::6 498 3.71% 98.38% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::7 170 1.27% 99.65% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::8 47 0.35% 100.00% # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::max_value 6 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::total 15719 # Number of insts issued each cycle -system.cpu.iq.ISSUE:rate 0.465757 # Inst issue rate -system.cpu.iq.fp_alu_accesses 4 # Number of floating point alu accesses -system.cpu.iq.fp_inst_queue_reads 8 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_wakeup_accesses 2 # Number of floating instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_writes 8 # Number of floating instruction queue writes -system.cpu.iq.int_alu_accesses 12701 # Number of integer alu accesses -system.cpu.iq.int_inst_queue_reads 41124 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_wakeup_accesses 11989 # Number of integer instruction queue wakeup accesses -system.cpu.iq.int_inst_queue_writes 16903 # Number of integer instruction queue writes -system.cpu.iq.iqInstsAdded 13604 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 12704 # Number of instructions issued -system.cpu.iq.iqNonSpecInstsAdded 16 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 3282 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedInstsIssued 1 # Number of squashed instructions issued -system.cpu.iq.iqSquashedNonSpecRemoved 3 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 3903 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.l2cache.ReadExReq_accesses 78 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency 34512.820513 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31358.974359 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_miss_latency 2692000 # number of ReadExReq miss cycles +system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::total 13410 # Number of insts issued each cycle +system.cpu.iq.ISSUE:rate 0.707232 # Inst issue rate +system.cpu.iq.fp_alu_accesses 5 # Number of floating point alu accesses +system.cpu.iq.fp_inst_queue_reads 9 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_wakeup_accesses 4 # Number of floating instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_writes 4 # Number of floating instruction queue writes +system.cpu.iq.int_alu_accesses 16289 # Number of integer alu accesses +system.cpu.iq.int_inst_queue_reads 45908 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_wakeup_accesses 15134 # Number of integer instruction queue wakeup accesses +system.cpu.iq.int_inst_queue_writes 27963 # Number of integer instruction queue writes +system.cpu.iq.iqInstsAdded 19154 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 16156 # Number of instructions issued +system.cpu.iq.iqNonSpecInstsAdded 30 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqSquashedInstsExamined 8758 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 53 # Number of squashed instructions issued +system.cpu.iq.iqSquashedNonSpecRemoved 17 # Number of squashed non-spec instructions that were removed +system.cpu.iq.iqSquashedOperandsExamined 11067 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.l2cache.ReadExReq_accesses 77 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_avg_miss_latency 34616.883117 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31389.610390 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_miss_latency 2665500 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_misses 78 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 2446000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_misses 77 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency 2417000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_misses 78 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadReq_accesses 324 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 34181.677019 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 30998.447205 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_mshr_misses 77 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadReq_accesses 362 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 34245.833333 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31040.277778 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_hits 2 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 11006500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.993827 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 322 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 9981500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.993827 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 322 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_miss_latency 12328500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.994475 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 360 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 11174500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.994475 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 360 # number of ReadReq MSHR misses system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 0.006231 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 0.005571 # Average number of references to valid blocks. system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 402 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 34246.250000 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31068.750000 # average overall mshr miss latency +system.cpu.l2cache.demand_accesses 439 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 34311.212815 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 31101.830664 # average overall mshr miss latency system.cpu.l2cache.demand_hits 2 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 13698500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.995025 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 400 # number of demand (read+write) misses +system.cpu.l2cache.demand_miss_latency 14994000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.995444 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 437 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 12427500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.995025 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 400 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_miss_latency 13591500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.995444 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 437 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.occ_%::0 0.004917 # Average percentage of cache occupancy -system.cpu.l2cache.occ_blocks::0 161.123348 # Average occupied blocks per context -system.cpu.l2cache.overall_accesses 402 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 34246.250000 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31068.750000 # average overall mshr miss latency +system.cpu.l2cache.occ_%::0 0.005436 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::0 178.138745 # Average occupied blocks per context +system.cpu.l2cache.overall_accesses 439 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 34311.212815 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 31101.830664 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.l2cache.overall_hits 2 # number of overall hits -system.cpu.l2cache.overall_miss_latency 13698500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.995025 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 400 # number of overall misses +system.cpu.l2cache.overall_miss_latency 14994000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.995444 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 437 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 12427500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.995025 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 400 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_miss_latency 13591500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.995444 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 437 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.sampled_refs 321 # Sample count of references to valid blocks. +system.cpu.l2cache.sampled_refs 359 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 161.123348 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 178.138745 # Cycle average of tags in use system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks -system.cpu.memDep0.conflictingLoads 7 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 2 # Number of conflicting stores. -system.cpu.memDep0.insertedLoads 1510 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1230 # Number of stores inserted to the mem dependence unit. -system.cpu.misc_regfile_reads 5444 # number of misc regfile reads -system.cpu.numCycles 27276 # number of cpu cycles simulated +system.cpu.memDep0.conflictingLoads 24 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 3 # Number of conflicting stores. +system.cpu.memDep0.insertedLoads 2105 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1639 # Number of stores inserted to the mem dependence unit. +system.cpu.misc_regfile_reads 6857 # number of misc regfile reads +system.cpu.numCycles 22844 # number of cpu cycles simulated system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.rename.RENAME:BlockCycles 87 # Number of cycles rename is blocking +system.cpu.rename.RENAME:BlockCycles 565 # Number of cycles rename is blocking system.cpu.rename.RENAME:CommittedMaps 9368 # Number of HB maps that are committed -system.cpu.rename.RENAME:IQFullEvents 6 # Number of times rename has blocked due to IQ full -system.cpu.rename.RENAME:IdleCycles 6548 # Number of cycles rename is idle -system.cpu.rename.RENAME:LSQFullEvents 15 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RENAME:RenameLookups 31415 # Number of register rename lookups that rename has made -system.cpu.rename.RENAME:RenamedInsts 14729 # Number of instructions processed by rename -system.cpu.rename.RENAME:RenamedOperands 13866 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 8021 # Number of cycles rename is running -system.cpu.rename.RENAME:SquashCycles 701 # Number of cycles rename is squashing -system.cpu.rename.RENAME:UnblockCycles 105 # Number of cycles rename is unblocking -system.cpu.rename.RENAME:UndoneMaps 4498 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:IQFullEvents 51 # Number of times rename has blocked due to IQ full +system.cpu.rename.RENAME:IdleCycles 7399 # Number of cycles rename is idle +system.cpu.rename.RENAME:LSQFullEvents 247 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RENAME:ROBFullEvents 3 # Number of times rename has blocked due to ROB full +system.cpu.rename.RENAME:RenameLookups 44700 # Number of register rename lookups that rename has made +system.cpu.rename.RENAME:RenamedInsts 21187 # Number of instructions processed by rename +system.cpu.rename.RENAME:RenamedOperands 19905 # Number of destination operands rename has renamed +system.cpu.rename.RENAME:RunCycles 3124 # Number of cycles rename is running +system.cpu.rename.RENAME:SquashCycles 1504 # Number of cycles rename is squashing +system.cpu.rename.RENAME:UnblockCycles 378 # Number of cycles rename is unblocking +system.cpu.rename.RENAME:UndoneMaps 10537 # Number of HB maps that are undone due to squashing system.cpu.rename.RENAME:fp_rename_lookups 16 # Number of floating rename lookups -system.cpu.rename.RENAME:int_rename_lookups 31399 # Number of integer rename lookups -system.cpu.rename.RENAME:serializeStallCycles 257 # count of cycles rename stalled for serializing inst -system.cpu.rename.RENAME:serializingInsts 19 # count of serializing insts renamed -system.cpu.rename.RENAME:skidInsts 159 # count of insts added to the skid buffer -system.cpu.rename.RENAME:tempSerializingInsts 16 # count of temporary serializing insts renamed -system.cpu.rob.rob_reads 28615 # The number of ROB reads -system.cpu.rob.rob_writes 27943 # The number of ROB writes -system.cpu.timesIdled 206 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.rename.RENAME:int_rename_lookups 44684 # Number of integer rename lookups +system.cpu.rename.RENAME:serializeStallCycles 440 # count of cycles rename stalled for serializing inst +system.cpu.rename.RENAME:serializingInsts 32 # count of serializing insts renamed +system.cpu.rename.RENAME:skidInsts 1476 # count of insts added to the skid buffer +system.cpu.rename.RENAME:tempSerializingInsts 31 # count of temporary serializing insts renamed +system.cpu.rob.rob_reads 30950 # The number of ROB reads +system.cpu.rob.rob_writes 39896 # The number of ROB writes +system.cpu.timesIdled 184 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.workload.PROG:num_syscalls 11 # Number of system calls ---------- End Simulation Statistics ---------- |