1 files changed, 133 insertions, 8 deletions

diff --git a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini
index bd25cdab9..5b6a4c7ff 100644
--- a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini
+++ b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini
@@ -49,12 +49,12 @@ text_file=m5stats.txt
 [system]
 type=System
 children=cpu membus physmem
-mem_mode=timing
+mem_mode=atomic
 physmem=system.physmem
 
 [system.cpu]
 type=DerivO3CPU
-children=fuPool workload0 workload1
+children=dcache fuPool icache l2cache toL2Bus workload0 workload1
 BTBEntries=4096
 BTBTagSize=16
 LFSTSize=1024
@@ -102,7 +102,7 @@ max_insts_all_threads=0
 max_insts_any_thread=0
 max_loads_all_threads=0
 max_loads_any_thread=0
-mem=system.physmem
+mem=system.cpu.dcache
 numIQEntries=64
 numPhysFloatRegs=256
 numPhysIntRegs=256
@@ -122,8 +122,48 @@ trapLatency=13
 wbDepth=1
 wbWidth=8
 workload=system.cpu.workload0 system.cpu.workload1
-dcache_port=system.membus.port[2]
-icache_port=system.membus.port[1]
+dcache_port=system.cpu.dcache.cpu_side
+icache_port=system.cpu.icache.cpu_side
+
+[system.cpu.dcache]
+type=BaseCache
+adaptive_compression=false
+assoc=2
+block_size=64
+compressed_bus=false
+compression_latency=0
+do_copy=false
+hash_delay=1
+hit_latency=1
+latency=1
+lifo=false
+max_miss_count=0
+mshrs=10
+prefetch_access=false
+prefetch_cache_check_push=true
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=10
+prefetch_miss=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+protocol=Null
+repl=Null
+size=262144
+split=false
+split_size=0
+store_compressed=false
+subblock_size=0
+tgts_per_mshr=5
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.dcache_port
+mem_side=system.cpu.toL2Bus.port[1]
 
 [system.cpu.fuPool]
 type=FUPool
@@ -262,9 +302,94 @@ issueLat=3
 opClass=IprAccess
 opLat=3
 
+[system.cpu.icache]
+type=BaseCache
+adaptive_compression=false
+assoc=2
+block_size=64
+compressed_bus=false
+compression_latency=0
+do_copy=false
+hash_delay=1
+hit_latency=1
+latency=1
+lifo=false
+max_miss_count=0
+mshrs=10
+prefetch_access=false
+prefetch_cache_check_push=true
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=10
+prefetch_miss=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+protocol=Null
+repl=Null
+size=131072
+split=false
+split_size=0
+store_compressed=false
+subblock_size=0
+tgts_per_mshr=5
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.icache_port
+mem_side=system.cpu.toL2Bus.port[0]
+
+[system.cpu.l2cache]
+type=BaseCache
+adaptive_compression=false
+assoc=2
+block_size=64
+compressed_bus=false
+compression_latency=0
+do_copy=false
+hash_delay=1
+hit_latency=1
+latency=1
+lifo=false
+max_miss_count=0
+mshrs=10
+prefetch_access=false
+prefetch_cache_check_push=true
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=10
+prefetch_miss=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+protocol=Null
+repl=Null
+size=2097152
+split=false
+split_size=0
+store_compressed=false
+subblock_size=0
+tgts_per_mshr=5
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.toL2Bus.port[2]
+mem_side=system.membus.port[1]
+
+[system.cpu.toL2Bus]
+type=Bus
+bus_id=0
+port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
+
 [system.cpu.workload0]
 type=LiveProcess
-cmd=tests/test-progs/hello/bin/alpha/linux/hello 
+cmd=hello
 egid=100
 env=
 euid=100
@@ -279,7 +404,7 @@ uid=100
 
 [system.cpu.workload1]
 type=LiveProcess
-cmd=tests/test-progs/hello/bin/alpha/linux/hello 
+cmd=hello
 egid=100
 env=
 euid=100
@@ -295,7 +420,7 @@ uid=100
 [system.membus]
 type=Bus
 bus_id=0
-port=system.physmem.port system.cpu.icache_port system.cpu.dcache_port
+port=system.physmem.port system.cpu.l2cache.mem_side
 
 [system.physmem]
 type=PhysicalMemory