diff options
Diffstat (limited to 'tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing')
5 files changed, 1635 insertions, 0 deletions
diff --git a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini new file mode 100644 index 000000000..9dad57e13 --- /dev/null +++ b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini @@ -0,0 +1,444 @@ +[root] +type=Root +children=system +checkpoint= +clock=1000000000000 +max_tick=0 +output_file=cout +progress_interval=0 + +[debug] +break_cycles= + +[exetrace] +intel_format=false +pc_symbol=true +print_cpseq=false +print_cycle=true +print_data=true +print_effaddr=true +print_fetchseq=false +print_iregs=false +print_opclass=true +print_thread=true +speculative=true +trace_system=client + +[serialize] +count=10 +cycle=0 +dir=cpt.%012d +period=0 + +[stats] +descriptions=true +dump_cycle=0 +dump_period=0 +dump_reset=false +ignore_events= +mysql_db= +mysql_host= +mysql_password= +mysql_user= +project_name=test +simulation_name=test +simulation_sample=0 +text_compat=true +text_file=m5stats.txt + +[system] +type=System +children=cpu membus physmem +mem_mode=atomic +physmem=system.physmem + +[system.cpu] +type=DerivO3CPU +children=dcache fuPool icache l2cache toL2Bus workload0 workload1 +BTBEntries=4096 +BTBTagSize=16 +LFSTSize=1024 +LQEntries=32 +RASSize=16 +SQEntries=32 +SSITSize=1024 +activity=0 +backComSize=5 +choiceCtrBits=2 +choicePredictorSize=8192 +clock=1 +commitToDecodeDelay=1 +commitToFetchDelay=1 +commitToIEWDelay=1 +commitToRenameDelay=1 +commitWidth=8 +decodeToFetchDelay=1 +decodeToRenameDelay=1 +decodeWidth=8 +defer_registration=false +dispatchWidth=8 +fetchToDecodeDelay=1 +fetchTrapLatency=1 +fetchWidth=8 +forwardComSize=5 +fuPool=system.cpu.fuPool +function_trace=false +function_trace_start=0 +globalCtrBits=2 +globalHistoryBits=13 +globalPredictorSize=8192 +iewToCommitDelay=1 +iewToDecodeDelay=1 +iewToFetchDelay=1 +iewToRenameDelay=1 +instShiftAmt=2 +issueToExecuteDelay=1 +issueWidth=8 +localCtrBits=2 +localHistoryBits=11 +localHistoryTableSize=2048 +localPredictorSize=2048 +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +mem=system.cpu.dcache +numIQEntries=64 +numPhysFloatRegs=256 +numPhysIntRegs=256 +numROBEntries=192 +numRobs=1 +numThreads=1 +predType=tournament +progress_interval=0 +renameToDecodeDelay=1 +renameToFetchDelay=1 +renameToIEWDelay=2 +renameToROBDelay=1 +renameWidth=8 +squashWidth=8 +system=system +trapLatency=13 +wbDepth=1 +wbWidth=8 +workload=system.cpu.workload0 system.cpu.workload1 +dcache_port=system.cpu.dcache.cpu_side +icache_port=system.cpu.icache.cpu_side + +[system.cpu.dcache] +type=BaseCache +adaptive_compression=false +assoc=2 +block_size=64 +compressed_bus=false +compression_latency=0 +do_copy=false +hash_delay=1 +hit_latency=1 +latency=1 +lifo=false +max_miss_count=0 +mshrs=10 +prefetch_access=false +prefetch_cache_check_push=true +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10 +prefetch_miss=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +protocol=Null +repl=Null +size=262144 +split=false +split_size=0 +store_compressed=false +subblock_size=0 +tgts_per_mshr=5 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.dcache_port +mem_side=system.cpu.toL2Bus.port[1] + +[system.cpu.fuPool] +type=FUPool +children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 +FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 + +[system.cpu.fuPool.FUList0] +type=FUDesc +children=opList0 +count=6 +opList=system.cpu.fuPool.FUList0.opList0 + +[system.cpu.fuPool.FUList0.opList0] +type=OpDesc +issueLat=1 +opClass=IntAlu +opLat=1 + +[system.cpu.fuPool.FUList1] +type=FUDesc +children=opList0 opList1 +count=2 +opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 + +[system.cpu.fuPool.FUList1.opList0] +type=OpDesc +issueLat=1 +opClass=IntMult +opLat=3 + +[system.cpu.fuPool.FUList1.opList1] +type=OpDesc +issueLat=19 +opClass=IntDiv +opLat=20 + +[system.cpu.fuPool.FUList2] +type=FUDesc +children=opList0 opList1 opList2 +count=4 +opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 + +[system.cpu.fuPool.FUList2.opList0] +type=OpDesc +issueLat=1 +opClass=FloatAdd +opLat=2 + +[system.cpu.fuPool.FUList2.opList1] +type=OpDesc +issueLat=1 +opClass=FloatCmp +opLat=2 + +[system.cpu.fuPool.FUList2.opList2] +type=OpDesc +issueLat=1 +opClass=FloatCvt +opLat=2 + +[system.cpu.fuPool.FUList3] +type=FUDesc +children=opList0 opList1 opList2 +count=2 +opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 + +[system.cpu.fuPool.FUList3.opList0] +type=OpDesc +issueLat=1 +opClass=FloatMult +opLat=4 + +[system.cpu.fuPool.FUList3.opList1] +type=OpDesc +issueLat=12 +opClass=FloatDiv +opLat=12 + +[system.cpu.fuPool.FUList3.opList2] +type=OpDesc +issueLat=24 +opClass=FloatSqrt +opLat=24 + +[system.cpu.fuPool.FUList4] +type=FUDesc +children=opList0 +count=0 +opList=system.cpu.fuPool.FUList4.opList0 + +[system.cpu.fuPool.FUList4.opList0] +type=OpDesc +issueLat=1 +opClass=MemRead +opLat=1 + +[system.cpu.fuPool.FUList5] +type=FUDesc +children=opList0 +count=0 +opList=system.cpu.fuPool.FUList5.opList0 + +[system.cpu.fuPool.FUList5.opList0] +type=OpDesc +issueLat=1 +opClass=MemWrite +opLat=1 + +[system.cpu.fuPool.FUList6] +type=FUDesc +children=opList0 opList1 +count=4 +opList=system.cpu.fuPool.FUList6.opList0 system.cpu.fuPool.FUList6.opList1 + +[system.cpu.fuPool.FUList6.opList0] +type=OpDesc +issueLat=1 +opClass=MemRead +opLat=1 + +[system.cpu.fuPool.FUList6.opList1] +type=OpDesc +issueLat=1 +opClass=MemWrite +opLat=1 + +[system.cpu.fuPool.FUList7] +type=FUDesc +children=opList0 +count=1 +opList=system.cpu.fuPool.FUList7.opList0 + +[system.cpu.fuPool.FUList7.opList0] +type=OpDesc +issueLat=3 +opClass=IprAccess +opLat=3 + +[system.cpu.icache] +type=BaseCache +adaptive_compression=false +assoc=2 +block_size=64 +compressed_bus=false +compression_latency=0 +do_copy=false +hash_delay=1 +hit_latency=1 +latency=1 +lifo=false +max_miss_count=0 +mshrs=10 +prefetch_access=false +prefetch_cache_check_push=true +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10 +prefetch_miss=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +protocol=Null +repl=Null +size=131072 +split=false +split_size=0 +store_compressed=false +subblock_size=0 +tgts_per_mshr=5 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.icache_port +mem_side=system.cpu.toL2Bus.port[0] + +[system.cpu.l2cache] +type=BaseCache +adaptive_compression=false +assoc=2 +block_size=64 +compressed_bus=false +compression_latency=0 +do_copy=false +hash_delay=1 +hit_latency=1 +latency=1 +lifo=false +max_miss_count=0 +mshrs=10 +prefetch_access=false +prefetch_cache_check_push=true +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10 +prefetch_miss=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +protocol=Null +repl=Null +size=2097152 +split=false +split_size=0 +store_compressed=false +subblock_size=0 +tgts_per_mshr=5 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.toL2Bus.port[2] +mem_side=system.membus.port[1] + +[system.cpu.toL2Bus] +type=Bus +bus_id=0 +clock=1000 +width=64 +port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side + +[system.cpu.workload0] +type=LiveProcess +cmd=hello +egid=100 +env= +euid=100 +executable=tests/test-progs/hello/bin/alpha/linux/hello +gid=100 +input=cin +output=cout +pid=100 +ppid=99 +system=system +uid=100 + +[system.cpu.workload1] +type=LiveProcess +cmd=hello +egid=100 +env= +euid=100 +executable=tests/test-progs/hello/bin/alpha/linux/hello +gid=100 +input=cin +output=cout +pid=100 +ppid=99 +system=system +uid=100 + +[system.membus] +type=Bus +bus_id=0 +clock=1000 +width=64 +port=system.physmem.port system.cpu.l2cache.mem_side + +[system.physmem] +type=PhysicalMemory +file= +latency=1 +range=0:134217727 +port=system.membus.port[0] + +[trace] +bufsize=0 +cycle=0 +dump_on_exit=false +file=cout +flags= +ignore= +start=0 + diff --git a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.out b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.out new file mode 100644 index 000000000..bb55a2b69 --- /dev/null +++ b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.out @@ -0,0 +1,433 @@ +[root] +type=Root +clock=1000000000000 +max_tick=0 +progress_interval=0 +output_file=cout + +[system.physmem] +type=PhysicalMemory +file= +range=[0,134217727] +latency=1 + +[system] +type=System +physmem=system.physmem +mem_mode=atomic + +[system.membus] +type=Bus +bus_id=0 +clock=1000 +width=64 + +[system.cpu.workload0] +type=LiveProcess +cmd=hello +executable=tests/test-progs/hello/bin/alpha/linux/hello +input=cin +output=cout +env= +system=system +uid=100 +euid=100 +gid=100 +egid=100 +pid=100 +ppid=99 + +[system.cpu.workload1] +type=LiveProcess +cmd=hello +executable=tests/test-progs/hello/bin/alpha/linux/hello +input=cin +output=cout +env= +system=system +uid=100 +euid=100 +gid=100 +egid=100 +pid=100 +ppid=99 + +[system.cpu.dcache] +type=BaseCache +size=262144 +assoc=2 +block_size=64 +latency=1 +mshrs=10 +tgts_per_mshr=5 +write_buffers=8 +prioritizeRequests=false +do_copy=false +protocol=null +trace_addr=0 +hash_delay=1 +repl=null +compressed_bus=false +store_compressed=false +adaptive_compression=false +compression_latency=0 +block_size=64 +max_miss_count=0 +addr_range=[0,18446744073709551615] +split=false +split_size=0 +lifo=false +two_queue=false +prefetch_miss=false +prefetch_access=false +prefetcher_size=100 +prefetch_past_page=false +prefetch_serial_squash=false +prefetch_latency=10 +prefetch_degree=1 +prefetch_policy=none +prefetch_cache_check_push=true +prefetch_use_cpu_id=true +prefetch_data_accesses_only=false +hit_latency=1 + +[system.cpu.fuPool.FUList0.opList0] +type=OpDesc +opClass=IntAlu +opLat=1 +issueLat=1 + +[system.cpu.fuPool.FUList0] +type=FUDesc +opList=system.cpu.fuPool.FUList0.opList0 +count=6 + +[system.cpu.fuPool.FUList1.opList0] +type=OpDesc +opClass=IntMult +opLat=3 +issueLat=1 + +[system.cpu.fuPool.FUList1.opList1] +type=OpDesc +opClass=IntDiv +opLat=20 +issueLat=19 + +[system.cpu.fuPool.FUList1] +type=FUDesc +opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 +count=2 + +[system.cpu.fuPool.FUList2.opList0] +type=OpDesc +opClass=FloatAdd +opLat=2 +issueLat=1 + +[system.cpu.fuPool.FUList2.opList1] +type=OpDesc +opClass=FloatCmp +opLat=2 +issueLat=1 + +[system.cpu.fuPool.FUList2.opList2] +type=OpDesc +opClass=FloatCvt +opLat=2 +issueLat=1 + +[system.cpu.fuPool.FUList2] +type=FUDesc +opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 +count=4 + +[system.cpu.fuPool.FUList3.opList0] +type=OpDesc +opClass=FloatMult +opLat=4 +issueLat=1 + +[system.cpu.fuPool.FUList3.opList1] +type=OpDesc +opClass=FloatDiv +opLat=12 +issueLat=12 + +[system.cpu.fuPool.FUList3.opList2] +type=OpDesc +opClass=FloatSqrt +opLat=24 +issueLat=24 + +[system.cpu.fuPool.FUList3] +type=FUDesc +opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 +count=2 + +[system.cpu.fuPool.FUList4.opList0] +type=OpDesc +opClass=MemRead +opLat=1 +issueLat=1 + +[system.cpu.fuPool.FUList4] +type=FUDesc +opList=system.cpu.fuPool.FUList4.opList0 +count=0 + +[system.cpu.fuPool.FUList5.opList0] +type=OpDesc +opClass=MemWrite +opLat=1 +issueLat=1 + +[system.cpu.fuPool.FUList5] +type=FUDesc +opList=system.cpu.fuPool.FUList5.opList0 +count=0 + +[system.cpu.fuPool.FUList6.opList0] +type=OpDesc +opClass=MemRead +opLat=1 +issueLat=1 + +[system.cpu.fuPool.FUList6.opList1] +type=OpDesc +opClass=MemWrite +opLat=1 +issueLat=1 + +[system.cpu.fuPool.FUList6] +type=FUDesc +opList=system.cpu.fuPool.FUList6.opList0 system.cpu.fuPool.FUList6.opList1 +count=4 + +[system.cpu.fuPool.FUList7.opList0] +type=OpDesc +opClass=IprAccess +opLat=3 +issueLat=3 + +[system.cpu.fuPool.FUList7] +type=FUDesc +opList=system.cpu.fuPool.FUList7.opList0 +count=1 + +[system.cpu.fuPool] +type=FUPool +FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 + +[system.cpu] +type=DerivO3CPU +clock=1 +numThreads=1 +activity=0 +workload=system.cpu.workload0 system.cpu.workload1 +mem=system.cpu.dcache +checker=null +max_insts_any_thread=0 +max_insts_all_threads=0 +max_loads_any_thread=0 +max_loads_all_threads=0 +progress_interval=0 +cachePorts=200 +decodeToFetchDelay=1 +renameToFetchDelay=1 +iewToFetchDelay=1 +commitToFetchDelay=1 +fetchWidth=8 +renameToDecodeDelay=1 +iewToDecodeDelay=1 +commitToDecodeDelay=1 +fetchToDecodeDelay=1 +decodeWidth=8 +iewToRenameDelay=1 +commitToRenameDelay=1 +decodeToRenameDelay=1 +renameWidth=8 +commitToIEWDelay=1 +renameToIEWDelay=2 +issueToExecuteDelay=1 +dispatchWidth=8 +issueWidth=8 +wbWidth=8 +wbDepth=1 +fuPool=system.cpu.fuPool +iewToCommitDelay=1 +renameToROBDelay=1 +commitWidth=8 +squashWidth=8 +trapLatency=13 +backComSize=5 +forwardComSize=5 +predType=tournament +localPredictorSize=2048 +localCtrBits=2 +localHistoryTableSize=2048 +localHistoryBits=11 +globalPredictorSize=8192 +globalCtrBits=2 +globalHistoryBits=13 +choicePredictorSize=8192 +choiceCtrBits=2 +BTBEntries=4096 +BTBTagSize=16 +RASSize=16 +LQEntries=32 +SQEntries=32 +LFSTSize=1024 +SSITSize=1024 +numPhysIntRegs=256 +numPhysFloatRegs=256 +numIQEntries=64 +numROBEntries=192 +smtNumFetchingThreads=1 +smtFetchPolicy=SingleThread +smtLSQPolicy=Partitioned +smtLSQThreshold=100 +smtIQPolicy=Partitioned +smtIQThreshold=100 +smtROBPolicy=Partitioned +smtROBThreshold=100 +smtCommitPolicy=RoundRobin +instShiftAmt=2 +defer_registration=false +function_trace=false +function_trace_start=0 + +[system.cpu.icache] +type=BaseCache +size=131072 +assoc=2 +block_size=64 +latency=1 +mshrs=10 +tgts_per_mshr=5 +write_buffers=8 +prioritizeRequests=false +do_copy=false +protocol=null +trace_addr=0 +hash_delay=1 +repl=null +compressed_bus=false +store_compressed=false +adaptive_compression=false +compression_latency=0 +block_size=64 +max_miss_count=0 +addr_range=[0,18446744073709551615] +split=false +split_size=0 +lifo=false +two_queue=false +prefetch_miss=false +prefetch_access=false +prefetcher_size=100 +prefetch_past_page=false +prefetch_serial_squash=false +prefetch_latency=10 +prefetch_degree=1 +prefetch_policy=none +prefetch_cache_check_push=true +prefetch_use_cpu_id=true +prefetch_data_accesses_only=false +hit_latency=1 + +[system.cpu.l2cache] +type=BaseCache +size=2097152 +assoc=2 +block_size=64 +latency=1 +mshrs=10 +tgts_per_mshr=5 +write_buffers=8 +prioritizeRequests=false +do_copy=false +protocol=null +trace_addr=0 +hash_delay=1 +repl=null +compressed_bus=false +store_compressed=false +adaptive_compression=false +compression_latency=0 +block_size=64 +max_miss_count=0 +addr_range=[0,18446744073709551615] +split=false +split_size=0 +lifo=false +two_queue=false +prefetch_miss=false +prefetch_access=false +prefetcher_size=100 +prefetch_past_page=false +prefetch_serial_squash=false +prefetch_latency=10 +prefetch_degree=1 +prefetch_policy=none +prefetch_cache_check_push=true +prefetch_use_cpu_id=true +prefetch_data_accesses_only=false +hit_latency=1 + +[system.cpu.toL2Bus] +type=Bus +bus_id=0 +clock=1000 +width=64 + +[trace] +flags= +start=0 +cycle=0 +bufsize=0 +file=cout +dump_on_exit=false +ignore= + +[stats] +descriptions=true +project_name=test +simulation_name=test +simulation_sample=0 +text_file=m5stats.txt +text_compat=true +mysql_db= +mysql_user= +mysql_password= +mysql_host= +events_start=-1 +dump_reset=false +dump_cycle=0 +dump_period=0 +ignore_events= + +[random] +seed=1 + +[exetrace] +speculative=true +print_cycle=true +print_opclass=true +print_thread=true +print_effaddr=true +print_data=true +print_iregs=false +print_fetchseq=false +print_cpseq=false +print_reg_delta=false +pc_symbol=true +intel_format=false +trace_system=client + +[debug] +break_cycles= + +[statsreset] +reset_cycle=0 + diff --git a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/m5stats.txt b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/m5stats.txt new file mode 100644 index 000000000..e5fad9159 --- /dev/null +++ b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/m5stats.txt @@ -0,0 +1,722 @@ + +---------- Begin Simulation Statistics ---------- +global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. +global.BPredUnit.BTBHits 640 # Number of BTB hits +global.BPredUnit.BTBLookups 3595 # Number of BTB lookups +global.BPredUnit.RASInCorrect 99 # Number of incorrect RAS predictions. +global.BPredUnit.condIncorrect 1081 # Number of conditional branches incorrect +global.BPredUnit.condPredicted 2447 # Number of conditional branches predicted +global.BPredUnit.lookups 4169 # Number of BP lookups +global.BPredUnit.usedRAS 550 # Number of times the RAS was used to get a target. +host_inst_rate 8624 # Simulator instruction rate (inst/s) +host_mem_usage 167824 # Number of bytes of host memory used +host_seconds 1.30 # Real time elapsed on the host +host_tick_rate 6469 # Simulator tick rate (ticks/s) +memdepunit.memDep.conflictingLoads 41 # Number of conflicting loads. +memdepunit.memDep.conflictingLoads 39 # Number of conflicting loads. +memdepunit.memDep.conflictingStores 194 # Number of conflicting stores. +memdepunit.memDep.conflictingStores 198 # Number of conflicting stores. +memdepunit.memDep.insertedLoads 1868 # Number of loads inserted to the mem dependence unit. +memdepunit.memDep.insertedLoads 1833 # Number of loads inserted to the mem dependence unit. +memdepunit.memDep.insertedStores 1106 # Number of stores inserted to the mem dependence unit. +memdepunit.memDep.insertedStores 1108 # Number of stores inserted to the mem dependence unit. +sim_freq 1000000000000 # Frequency of simulated ticks +sim_insts 11247 # Number of instructions simulated +sim_seconds 0.000000 # Number of seconds simulated +sim_ticks 8439 # Number of ticks simulated +system.cpu.commit.COM:branches 1724 # Number of branches committed +system.cpu.commit.COM:branches_0 862 # Number of branches committed +system.cpu.commit.COM:branches_1 862 # Number of branches committed +system.cpu.commit.COM:bw_lim_events 126 # number cycles where commit BW limit reached +system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits +system.cpu.commit.COM:bw_limited_0 0 # number of insts not committed due to BW limits +system.cpu.commit.COM:bw_limited_1 0 # number of insts not committed due to BW limits +system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle.samples 8391 +system.cpu.commit.COM:committed_per_cycle.min_value 0 + 0 3954 4712.19% + 1 1909 2275.06% + 2 920 1096.41% + 3 516 614.94% + 4 376 448.10% + 5 235 280.06% + 6 188 224.05% + 7 167 199.02% + 8 126 150.16% +system.cpu.commit.COM:committed_per_cycle.max_value 8 +system.cpu.commit.COM:committed_per_cycle.end_dist + +system.cpu.commit.COM:count 11281 # Number of instructions committed +system.cpu.commit.COM:count_0 5640 # Number of instructions committed +system.cpu.commit.COM:count_1 5641 # Number of instructions committed +system.cpu.commit.COM:loads 1958 # Number of loads committed +system.cpu.commit.COM:loads_0 979 # Number of loads committed +system.cpu.commit.COM:loads_1 979 # Number of loads committed +system.cpu.commit.COM:membars 0 # Number of memory barriers committed +system.cpu.commit.COM:membars_0 0 # Number of memory barriers committed +system.cpu.commit.COM:membars_1 0 # Number of memory barriers committed +system.cpu.commit.COM:refs 3582 # Number of memory references committed +system.cpu.commit.COM:refs_0 1791 # Number of memory references committed +system.cpu.commit.COM:refs_1 1791 # Number of memory references committed +system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed +system.cpu.commit.COM:swp_count_0 0 # Number of s/w prefetches committed +system.cpu.commit.COM:swp_count_1 0 # Number of s/w prefetches committed +system.cpu.commit.branchMispredicts 832 # The number of times a branch was mispredicted +system.cpu.commit.commitCommittedInsts 11281 # The number of committed instructions +system.cpu.commit.commitNonSpecStalls 34 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.commitSquashedInsts 7510 # The number of squashed insts skipped by commit +system.cpu.committedInsts_0 5623 # Number of Instructions Simulated +system.cpu.committedInsts_1 5624 # Number of Instructions Simulated +system.cpu.committedInsts_total 11247 # Number of Instructions Simulated +system.cpu.cpi_0 1.500800 # CPI: Cycles Per Instruction +system.cpu.cpi_1 1.500533 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.750333 # CPI: Total CPI of All Threads +system.cpu.dcache.ReadReq_accesses 2911 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses_0 2911 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 3.077253 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency_0 3.077253 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2.232323 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency_0 2.232323 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 2678 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits_0 2678 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 717 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency_0 717 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.080041 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate_0 0.080041 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 233 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses_0 233 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_hits 35 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits_0 35 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_miss_latency 442 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency_0 442 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.068018 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate_0 0.068018 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_misses 198 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses_0 198 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_accesses 1624 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses_0 1624 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_avg_miss_latency 2.762376 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency_0 2.762376 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 2.062500 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency_0 2.062500 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 1321 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits_0 1321 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 837 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency_0 837 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.186576 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate_0 0.186576 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 303 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses_0 303 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_hits 159 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits_0 159 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_miss_latency 297 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency_0 297 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate 0.088670 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate_0 0.088670 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses 144 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses_0 144 # number of WriteReq MSHR misses +system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles_no_targets 1 # average number of cycles each access was blocked +system.cpu.dcache.avg_refs 11.692982 # Average number of references to valid blocks. +system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_no_targets 7 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles_no_targets 7 # number of cycles access was blocked +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.demand_accesses 4535 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses_0 4535 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses_1 0 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 2.899254 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency_0 2.899254 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency_1 <err: div-0> # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 2.160819 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency_0 2.160819 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency_1 <err: div-0> # average overall mshr miss latency +system.cpu.dcache.demand_hits 3999 # number of demand (read+write) hits +system.cpu.dcache.demand_hits_0 3999 # number of demand (read+write) hits +system.cpu.dcache.demand_hits_1 0 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 1554 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency_0 1554 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency_1 0 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.118192 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate_0 0.118192 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate_1 <err: div-0> # miss rate for demand accesses +system.cpu.dcache.demand_misses 536 # number of demand (read+write) misses +system.cpu.dcache.demand_misses_0 536 # number of demand (read+write) misses +system.cpu.dcache.demand_misses_1 0 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 194 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits_0 194 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits_1 0 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 739 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency_0 739 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency_1 0 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.075413 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate_0 0.075413 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate_1 <err: div-0> # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 342 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses_0 342 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses_1 0 # number of demand (read+write) MSHR misses +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.dcache.mshr_cap_events_0 0 # number of times MSHR cap was activated +system.cpu.dcache.mshr_cap_events_1 0 # number of times MSHR cap was activated +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.overall_accesses 4535 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses_0 4535 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses_1 0 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 2.899254 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency_0 2.899254 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency_1 <err: div-0> # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 2.160819 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency_0 2.160819 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency_1 <err: div-0> # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency_0 <err: div-0> # average overall mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency_1 <err: div-0> # average overall mshr uncacheable latency +system.cpu.dcache.overall_hits 3999 # number of overall hits +system.cpu.dcache.overall_hits_0 3999 # number of overall hits +system.cpu.dcache.overall_hits_1 0 # number of overall hits +system.cpu.dcache.overall_miss_latency 1554 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency_0 1554 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency_1 0 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.118192 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate_0 0.118192 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate_1 <err: div-0> # miss rate for overall accesses +system.cpu.dcache.overall_misses 536 # number of overall misses +system.cpu.dcache.overall_misses_0 536 # number of overall misses +system.cpu.dcache.overall_misses_1 0 # number of overall misses +system.cpu.dcache.overall_mshr_hits 194 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits_0 194 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits_1 0 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 739 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency_0 739 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency_1 0 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.075413 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate_0 0.075413 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate_1 <err: div-0> # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 342 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses_0 342 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses_1 0 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency_0 0 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency_1 0 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.dcache.overall_mshr_uncacheable_misses_0 0 # number of overall MSHR uncacheable misses +system.cpu.dcache.overall_mshr_uncacheable_misses_1 0 # number of overall MSHR uncacheable misses +system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu.dcache.replacements 0 # number of replacements +system.cpu.dcache.replacements_0 0 # number of replacements +system.cpu.dcache.replacements_1 0 # number of replacements +system.cpu.dcache.sampled_refs 342 # Sample count of references to valid blocks. +system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.dcache.soft_prefetch_mshr_full_0 0 # number of mshr full events for SW prefetching instrutions +system.cpu.dcache.soft_prefetch_mshr_full_1 0 # number of mshr full events for SW prefetching instrutions +system.cpu.dcache.tagsinuse 226.387441 # Cycle average of tags in use +system.cpu.dcache.total_refs 3999 # Total number of references to valid blocks. +system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.writebacks 0 # number of writebacks +system.cpu.dcache.writebacks_0 0 # number of writebacks +system.cpu.dcache.writebacks_1 0 # number of writebacks +system.cpu.decode.DECODE:BlockedCycles 1691 # Number of cycles decode is blocked +system.cpu.decode.DECODE:BranchMispred 271 # Number of times decode detected a branch misprediction +system.cpu.decode.DECODE:BranchResolved 367 # Number of times decode resolved a branch +system.cpu.decode.DECODE:DecodedInsts 22675 # Number of instructions handled by decode +system.cpu.decode.DECODE:IdleCycles 9659 # Number of cycles decode is idle +system.cpu.decode.DECODE:RunCycles 3750 # Number of cycles decode is running +system.cpu.decode.DECODE:SquashCycles 1395 # Number of cycles decode is squashing +system.cpu.decode.DECODE:SquashedInsts 233 # Number of squashed instructions handled by decode +system.cpu.decode.DECODE:UnblockCycles 107 # Number of cycles decode is unblocking +system.cpu.fetch.Branches 4169 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 2866 # Number of cache lines fetched +system.cpu.fetch.Cycles 6955 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 200 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.Insts 25228 # Number of instructions fetch has processed +system.cpu.fetch.SquashCycles 1143 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.493957 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 2866 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 1190 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 2.989100 # Number of inst fetches per cycle +system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist.samples 8440 +system.cpu.fetch.rateDist.min_value 0 + 0 4352 5156.40% + 1 273 323.46% + 2 228 270.14% + 3 247 292.65% + 4 313 370.85% + 5 277 328.20% + 6 294 348.34% + 7 291 344.79% + 8 2165 2565.17% +system.cpu.fetch.rateDist.max_value 8 +system.cpu.fetch.rateDist.end_dist + +system.cpu.icache.ReadReq_accesses 2866 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses_0 2866 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 2.982343 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency_0 2.982343 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 1.995153 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency_0 1.995153 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 2243 # number of ReadReq hits +system.cpu.icache.ReadReq_hits_0 2243 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 1858 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency_0 1858 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.217376 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate_0 0.217376 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 623 # number of ReadReq misses +system.cpu.icache.ReadReq_misses_0 623 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_hits 4 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits_0 4 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_miss_latency 1235 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency_0 1235 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.215980 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate_0 0.215980 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_misses 619 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses_0 619 # number of ReadReq MSHR misses +system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu.icache.avg_refs 3.623586 # Average number of references to valid blocks. +system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.icache.cache_copies 0 # number of cache copies performed +system.cpu.icache.demand_accesses 2866 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses_0 2866 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses_1 0 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 2.982343 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency_0 2.982343 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency_1 <err: div-0> # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 1.995153 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency_0 1.995153 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency_1 <err: div-0> # average overall mshr miss latency +system.cpu.icache.demand_hits 2243 # number of demand (read+write) hits +system.cpu.icache.demand_hits_0 2243 # number of demand (read+write) hits +system.cpu.icache.demand_hits_1 0 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 1858 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency_0 1858 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency_1 0 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.217376 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate_0 0.217376 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate_1 <err: div-0> # miss rate for demand accesses +system.cpu.icache.demand_misses 623 # number of demand (read+write) misses +system.cpu.icache.demand_misses_0 623 # number of demand (read+write) misses +system.cpu.icache.demand_misses_1 0 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 4 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits_0 4 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits_1 0 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 1235 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency_0 1235 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency_1 0 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0.215980 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate_0 0.215980 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate_1 <err: div-0> # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_misses 619 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses_0 619 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses_1 0 # number of demand (read+write) MSHR misses +system.cpu.icache.fast_writes 0 # number of fast writes performed +system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.icache.mshr_cap_events_0 0 # number of times MSHR cap was activated +system.cpu.icache.mshr_cap_events_1 0 # number of times MSHR cap was activated +system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.icache.overall_accesses 2866 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses_0 2866 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses_1 0 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 2.982343 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency_0 2.982343 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency_1 <err: div-0> # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 1.995153 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency_0 1.995153 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency_1 <err: div-0> # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency_0 <err: div-0> # average overall mshr uncacheable latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency_1 <err: div-0> # average overall mshr uncacheable latency +system.cpu.icache.overall_hits 2243 # number of overall hits +system.cpu.icache.overall_hits_0 2243 # number of overall hits +system.cpu.icache.overall_hits_1 0 # number of overall hits +system.cpu.icache.overall_miss_latency 1858 # number of overall miss cycles +system.cpu.icache.overall_miss_latency_0 1858 # number of overall miss cycles +system.cpu.icache.overall_miss_latency_1 0 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.217376 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate_0 0.217376 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate_1 no value # miss rate for overall accesses +system.cpu.icache.overall_misses 623 # number of overall misses +system.cpu.icache.overall_misses_0 623 # number of overall misses +system.cpu.icache.overall_misses_1 0 # number of overall misses +system.cpu.icache.overall_mshr_hits 4 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits_0 4 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits_1 0 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 1235 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency_0 1235 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency_1 0 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0.215980 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate_0 0.215980 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate_1 <err: div-0> # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_misses 619 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses_0 619 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses_1 0 # number of overall MSHR misses +system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_latency_0 0 # number of overall MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_latency_1 0 # number of overall MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.icache.overall_mshr_uncacheable_misses_0 0 # number of overall MSHR uncacheable misses +system.cpu.icache.overall_mshr_uncacheable_misses_1 0 # number of overall MSHR uncacheable misses +system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu.icache.replacements 9 # number of replacements +system.cpu.icache.replacements_0 9 # number of replacements +system.cpu.icache.replacements_1 0 # number of replacements +system.cpu.icache.sampled_refs 619 # Sample count of references to valid blocks. +system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.icache.soft_prefetch_mshr_full_0 0 # number of mshr full events for SW prefetching instrutions +system.cpu.icache.soft_prefetch_mshr_full_1 0 # number of mshr full events for SW prefetching instrutions +system.cpu.icache.tagsinuse 332.363626 # Cycle average of tags in use +system.cpu.icache.total_refs 2243 # Total number of references to valid blocks. +system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.writebacks 0 # number of writebacks +system.cpu.icache.writebacks_0 0 # number of writebacks +system.cpu.icache.writebacks_1 0 # number of writebacks +system.cpu.iew.EXEC:branches 2318 # Number of branches executed +system.cpu.iew.EXEC:branches_0 1160 # Number of branches executed +system.cpu.iew.EXEC:branches_1 1158 # Number of branches executed +system.cpu.iew.EXEC:nop 65 # number of nop insts executed +system.cpu.iew.EXEC:nop_0 31 # number of nop insts executed +system.cpu.iew.EXEC:nop_1 34 # number of nop insts executed +system.cpu.iew.EXEC:rate 1.813863 # Inst execution rate +system.cpu.iew.EXEC:refs 4922 # number of memory reference insts executed +system.cpu.iew.EXEC:refs_0 2464 # number of memory reference insts executed +system.cpu.iew.EXEC:refs_1 2458 # number of memory reference insts executed +system.cpu.iew.EXEC:stores 1868 # Number of stores executed +system.cpu.iew.EXEC:stores_0 932 # Number of stores executed +system.cpu.iew.EXEC:stores_1 936 # Number of stores executed +system.cpu.iew.EXEC:swp 0 # number of swp insts executed +system.cpu.iew.EXEC:swp_0 0 # number of swp insts executed +system.cpu.iew.EXEC:swp_1 0 # number of swp insts executed +system.cpu.iew.WB:consumers 10001 # num instructions consuming a value +system.cpu.iew.WB:consumers_0 5003 # num instructions consuming a value +system.cpu.iew.WB:consumers_1 4998 # num instructions consuming a value +system.cpu.iew.WB:count 14799 # cumulative count of insts written-back +system.cpu.iew.WB:count_0 7402 # cumulative count of insts written-back +system.cpu.iew.WB:count_1 7397 # cumulative count of insts written-back +system.cpu.iew.WB:fanout 0.777122 # average fanout of values written-back +system.cpu.iew.WB:fanout_0 0.776134 # average fanout of values written-back +system.cpu.iew.WB:fanout_1 0.778111 # average fanout of values written-back +system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ +system.cpu.iew.WB:penalized_0 0 # number of instrctions required to write to 'other' IQ +system.cpu.iew.WB:penalized_1 0 # number of instrctions required to write to 'other' IQ +system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ +system.cpu.iew.WB:penalized_rate_0 0 # fraction of instructions written-back that wrote to 'other' IQ +system.cpu.iew.WB:penalized_rate_1 0 # fraction of instructions written-back that wrote to 'other' IQ +system.cpu.iew.WB:producers 7772 # num instructions producing a value +system.cpu.iew.WB:producers_0 3883 # num instructions producing a value +system.cpu.iew.WB:producers_1 3889 # num instructions producing a value +system.cpu.iew.WB:rate 1.753436 # insts written-back per cycle +system.cpu.iew.WB:rate_0 0.877014 # insts written-back per cycle +system.cpu.iew.WB:rate_1 0.876422 # insts written-back per cycle +system.cpu.iew.WB:sent 14932 # cumulative count of insts sent to commit +system.cpu.iew.WB:sent_0 7467 # cumulative count of insts sent to commit +system.cpu.iew.WB:sent_1 7465 # cumulative count of insts sent to commit +system.cpu.iew.branchMispredicts 926 # Number of branch mispredicts detected at execute +system.cpu.iew.iewBlockCycles 4 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 3701 # Number of dispatched load instructions +system.cpu.iew.iewDispNonSpecInsts 40 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispSquashedInsts 604 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 2214 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 18792 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 3054 # Number of load instructions executed +system.cpu.iew.iewExecLoadInsts_0 1532 # Number of load instructions executed +system.cpu.iew.iewExecLoadInsts_1 1522 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 916 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 15309 # Number of executed instructions +system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle +system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 1395 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 0 # Number of cycles IEW is unblocking +system.cpu.iew.lsq.thread.0.blockedLoads 1 # Number of blocked loads due to partial load-store forwarding +system.cpu.iew.lsq.thread.0.cacheBlocked 4 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread.0.forwLoads 45 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread.0.ignoredResponses 2 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address +system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address +system.cpu.iew.lsq.thread.0.memOrderViolation 32 # Number of memory ordering violations +system.cpu.iew.lsq.thread.0.rescheduledLoads 1 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread.0.squashedLoads 889 # Number of loads squashed +system.cpu.iew.lsq.thread.0.squashedStores 294 # Number of stores squashed +system.cpu.iew.lsq.thread.1.blockedLoads 1 # Number of blocked loads due to partial load-store forwarding +system.cpu.iew.lsq.thread.1.cacheBlocked 6 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread.1.forwLoads 45 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread.1.ignoredResponses 2 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread.1.invAddrLoads 0 # Number of loads ignored due to an invalid address +system.cpu.iew.lsq.thread.1.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address +system.cpu.iew.lsq.thread.1.memOrderViolation 35 # Number of memory ordering violations +system.cpu.iew.lsq.thread.1.rescheduledLoads 1 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread.1.squashedLoads 854 # Number of loads squashed +system.cpu.iew.lsq.thread.1.squashedStores 296 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 67 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 764 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 162 # Number of branches that were predicted taken incorrectly +system.cpu.ipc_0 0.666311 # IPC: Instructions Per Cycle +system.cpu.ipc_1 0.666430 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.332741 # IPC: Total IPC of All Threads +system.cpu.iq.ISSUE:FU_type_0 8135 # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0.start_dist + (null) 2 0.02% # Type of FU issued + IntAlu 5505 67.67% # Type of FU issued + IntMult 1 0.01% # Type of FU issued + IntDiv 0 0.00% # Type of FU issued + FloatAdd 2 0.02% # Type of FU issued + FloatCmp 0 0.00% # Type of FU issued + FloatCvt 0 0.00% # Type of FU issued + FloatMult 0 0.00% # Type of FU issued + FloatDiv 0 0.00% # Type of FU issued + FloatSqrt 0 0.00% # Type of FU issued + MemRead 1656 20.36% # Type of FU issued + MemWrite 969 11.91% # Type of FU issued + IprAccess 0 0.00% # Type of FU issued + InstPrefetch 0 0.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0.end_dist +system.cpu.iq.ISSUE:FU_type_1 8090 # Type of FU issued +system.cpu.iq.ISSUE:FU_type_1.start_dist + (null) 2 0.02% # Type of FU issued + IntAlu 5481 67.75% # Type of FU issued + IntMult 1 0.01% # Type of FU issued + IntDiv 0 0.00% # Type of FU issued + FloatAdd 2 0.02% # Type of FU issued + FloatCmp 0 0.00% # Type of FU issued + FloatCvt 0 0.00% # Type of FU issued + FloatMult 0 0.00% # Type of FU issued + FloatDiv 0 0.00% # Type of FU issued + FloatSqrt 0 0.00% # Type of FU issued + MemRead 1640 20.27% # Type of FU issued + MemWrite 964 11.92% # Type of FU issued + IprAccess 0 0.00% # Type of FU issued + InstPrefetch 0 0.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_1.end_dist +system.cpu.iq.ISSUE:FU_type 16225 # Type of FU issued +system.cpu.iq.ISSUE:FU_type.start_dist + (null) 4 0.02% # Type of FU issued + IntAlu 10986 67.71% # Type of FU issued + IntMult 2 0.01% # Type of FU issued + IntDiv 0 0.00% # Type of FU issued + FloatAdd 4 0.02% # Type of FU issued + FloatCmp 0 0.00% # Type of FU issued + FloatCvt 0 0.00% # Type of FU issued + FloatMult 0 0.00% # Type of FU issued + FloatDiv 0 0.00% # Type of FU issued + FloatSqrt 0 0.00% # Type of FU issued + MemRead 3296 20.31% # Type of FU issued + MemWrite 1933 11.91% # Type of FU issued + IprAccess 0 0.00% # Type of FU issued + InstPrefetch 0 0.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type.end_dist +system.cpu.iq.ISSUE:fu_busy_cnt 181 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_cnt_0 103 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_cnt_1 78 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_rate 0.011156 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:fu_busy_rate_0 0.006348 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:fu_busy_rate_1 0.004807 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:fu_full.start_dist + (null) 0 0.00% # attempts to use FU when none available + IntAlu 10 5.52% # attempts to use FU when none available + IntMult 0 0.00% # attempts to use FU when none available + IntDiv 0 0.00% # attempts to use FU when none available + FloatAdd 0 0.00% # attempts to use FU when none available + FloatCmp 0 0.00% # attempts to use FU when none available + FloatCvt 0 0.00% # attempts to use FU when none available + FloatMult 0 0.00% # attempts to use FU when none available + FloatDiv 0 0.00% # attempts to use FU when none available + FloatSqrt 0 0.00% # attempts to use FU when none available + MemRead 100 55.25% # attempts to use FU when none available + MemWrite 71 39.23% # attempts to use FU when none available + IprAccess 0 0.00% # attempts to use FU when none available + InstPrefetch 0 0.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full.end_dist +system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle.samples 8440 +system.cpu.iq.ISSUE:issued_per_cycle.min_value 0 + 0 2689 3186.02% + 1 1457 1726.30% + 2 1432 1696.68% + 3 1110 1315.17% + 4 757 896.92% + 5 583 690.76% + 6 287 340.05% + 7 91 107.82% + 8 34 40.28% +system.cpu.iq.ISSUE:issued_per_cycle.max_value 8 +system.cpu.iq.ISSUE:issued_per_cycle.end_dist + +system.cpu.iq.ISSUE:rate 1.922393 # Inst issue rate +system.cpu.iq.iqInstsAdded 18687 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 16225 # Number of instructions issued +system.cpu.iq.iqNonSpecInstsAdded 40 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqSquashedInstsExamined 6645 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 31 # Number of squashed instructions issued +system.cpu.iq.iqSquashedNonSpecRemoved 6 # Number of squashed non-spec instructions that were removed +system.cpu.iq.iqSquashedOperandsExamined 4127 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.l2cache.ReadReq_accesses 961 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses_0 961 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 2.059623 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency_0 2.059623 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency_0 1 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_hits 5 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits_0 5 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency 1969 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency_0 1969 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.994797 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate_0 0.994797 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 956 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses_0 956 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 956 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency_0 956 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.994797 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate_0 0.994797 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 956 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses_0 956 # number of ReadReq MSHR misses +system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu.l2cache.avg_refs 0.005230 # Average number of references to valid blocks. +system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.cache_copies 0 # number of cache copies performed +system.cpu.l2cache.demand_accesses 961 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses_0 961 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses_1 0 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 2.059623 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency_0 2.059623 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency_1 <err: div-0> # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 1 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency_0 1 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency_1 <err: div-0> # average overall mshr miss latency +system.cpu.l2cache.demand_hits 5 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits_0 5 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits_1 0 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 1969 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency_0 1969 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency_1 0 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.994797 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate_0 0.994797 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate_1 <err: div-0> # miss rate for demand accesses +system.cpu.l2cache.demand_misses 956 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses_0 956 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses_1 0 # number of demand (read+write) misses +system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits_0 0 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits_1 0 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_miss_latency 956 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency_0 956 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency_1 0 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.994797 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate_0 0.994797 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate_1 <err: div-0> # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 956 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses_0 956 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses_1 0 # number of demand (read+write) MSHR misses +system.cpu.l2cache.fast_writes 0 # number of fast writes performed +system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.l2cache.mshr_cap_events_0 0 # number of times MSHR cap was activated +system.cpu.l2cache.mshr_cap_events_1 0 # number of times MSHR cap was activated +system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.l2cache.overall_accesses 961 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses_0 961 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses_1 0 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 2.059623 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency_0 2.059623 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency_1 <err: div-0> # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 1 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency_0 1 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency_1 <err: div-0> # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency_0 <err: div-0> # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency_1 <err: div-0> # average overall mshr uncacheable latency +system.cpu.l2cache.overall_hits 5 # number of overall hits +system.cpu.l2cache.overall_hits_0 5 # number of overall hits +system.cpu.l2cache.overall_hits_1 0 # number of overall hits +system.cpu.l2cache.overall_miss_latency 1969 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency_0 1969 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency_1 0 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.994797 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate_0 0.994797 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate_1 <err: div-0> # miss rate for overall accesses +system.cpu.l2cache.overall_misses 956 # number of overall misses +system.cpu.l2cache.overall_misses_0 956 # number of overall misses +system.cpu.l2cache.overall_misses_1 0 # number of overall misses +system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits_0 0 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits_1 0 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_miss_latency 956 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency_0 956 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency_1 0 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.994797 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate_0 0.994797 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate_1 <err: div-0> # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 956 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses_0 956 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses_1 0 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency_0 0 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency_1 0 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.l2cache.overall_mshr_uncacheable_misses_0 0 # number of overall MSHR uncacheable misses +system.cpu.l2cache.overall_mshr_uncacheable_misses_1 0 # number of overall MSHR uncacheable misses +system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu.l2cache.replacements 0 # number of replacements +system.cpu.l2cache.replacements_0 0 # number of replacements +system.cpu.l2cache.replacements_1 0 # number of replacements +system.cpu.l2cache.sampled_refs 956 # Sample count of references to valid blocks. +system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.l2cache.soft_prefetch_mshr_full_0 0 # number of mshr full events for SW prefetching instrutions +system.cpu.l2cache.soft_prefetch_mshr_full_1 0 # number of mshr full events for SW prefetching instrutions +system.cpu.l2cache.tagsinuse 558.812441 # Cycle average of tags in use +system.cpu.l2cache.total_refs 5 # Total number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.writebacks 0 # number of writebacks +system.cpu.l2cache.writebacks_0 0 # number of writebacks +system.cpu.l2cache.writebacks_1 0 # number of writebacks +system.cpu.numCycles 8440 # number of cpu cycles simulated +system.cpu.rename.RENAME:BlockCycles 345 # Number of cycles rename is blocking +system.cpu.rename.RENAME:CommittedMaps 8102 # Number of HB maps that are committed +system.cpu.rename.RENAME:IdleCycles 9958 # Number of cycles rename is idle +system.cpu.rename.RENAME:LSQFullEvents 698 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RENAME:RenameLookups 26874 # Number of register rename lookups that rename has made +system.cpu.rename.RENAME:RenamedInsts 21097 # Number of instructions processed by rename +system.cpu.rename.RENAME:RenamedOperands 15772 # Number of destination operands rename has renamed +system.cpu.rename.RENAME:RunCycles 3566 # Number of cycles rename is running +system.cpu.rename.RENAME:SquashCycles 1395 # Number of cycles rename is squashing +system.cpu.rename.RENAME:UnblockCycles 766 # Number of cycles rename is unblocking +system.cpu.rename.RENAME:UndoneMaps 7670 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:serializeStallCycles 572 # count of cycles rename stalled for serializing inst +system.cpu.rename.RENAME:serializingInsts 48 # count of serializing insts renamed +system.cpu.rename.RENAME:skidInsts 1906 # count of insts added to the skid buffer +system.cpu.rename.RENAME:tempSerializingInsts 38 # count of temporary serializing insts renamed +system.cpu.workload0.PROG:num_syscalls 17 # Number of system calls +system.cpu.workload1.PROG:num_syscalls 17 # Number of system calls + +---------- End Simulation Statistics ---------- diff --git a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stderr b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stderr new file mode 100644 index 000000000..48d711163 --- /dev/null +++ b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stderr @@ -0,0 +1,22 @@ +warn: Entering event queue @ 0. Starting simulation... +warn: cycle 0: fault (page_table_fault) detected @ PC 0x000000 +warn: Increasing stack 0x11ff92000:0x11ff9b000 to 0x11ff90000:0x11ff9b000 because of access to 0x11ff91ff0 +warn: Increasing stack 0x11ff92000:0x11ff9b000 to 0x11ff90000:0x11ff9b000 because of access to 0x11ff91ff0 +warn: Default fetch doesn't update it's state from a functional call. +warn: Default fetch doesn't update it's state from a functional call. +warn: Default fetch doesn't update it's state from a functional call. +warn: Default fetch doesn't update it's state from a functional call. +warn: Default fetch doesn't update it's state from a functional call. +warn: Default fetch doesn't update it's state from a functional call. +warn: Default fetch doesn't update it's state from a functional call. +warn: Default fetch doesn't update it's state from a functional call. +warn: Default fetch doesn't update it's state from a functional call. +warn: Default fetch doesn't update it's state from a functional call. +warn: Default fetch doesn't update it's state from a functional call. +warn: Default fetch doesn't update it's state from a functional call. +warn: Default fetch doesn't update it's state from a functional call. +warn: Default fetch doesn't update it's state from a functional call. +warn: Default fetch doesn't update it's state from a functional call. +warn: Default fetch doesn't update it's state from a functional call. +warn: Default fetch doesn't update it's state from a functional call. +warn: Default fetch doesn't update it's state from a functional call. diff --git a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stdout b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stdout new file mode 100644 index 000000000..2b27a0049 --- /dev/null +++ b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stdout @@ -0,0 +1,14 @@ +Hello world! +Hello world! +M5 Simulator System + +Copyright (c) 2001-2006 +The Regents of The University of Michigan +All Rights Reserved + + +M5 compiled Oct 10 2006 01:56:36 +M5 started Tue Oct 10 01:57:16 2006 +M5 executing on zizzer.eecs.umich.edu +command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/quick/01.hello-2T-smt/alpha/linux/o3-timing tests/run.py quick/01.hello-2T-smt/alpha/linux/o3-timing +Exiting @ tick 8439 because target called exit() |