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Diffstat (limited to 'tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing')
-rwxr-xr-xtests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/simout6
-rw-r--r--tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt11
2 files changed, 9 insertions, 8 deletions
diff --git a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/simout b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/simout
index 3dc1278fb..1d43d276a 100755
--- a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/simout
+++ b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/simout
@@ -5,9 +5,9 @@ The Regents of The University of Michigan
All Rights Reserved
-M5 compiled Nov 15 2010 08:52:32
-M5 revision f440cdaf1c2d+ 7743+ default tip
-M5 started Nov 15 2010 13:43:59
+M5 compiled Jan 17 2011 16:24:53
+M5 revision f72d94f8c275 7839 default qtip tip outgoing.patch qbase
+M5 started Jan 17 2011 16:24:57
M5 executing on zizzer
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/01.hello-2T-smt/alpha/linux/o3-timing -re tests/run.py build/ALPHA_SE/tests/fast/quick/01.hello-2T-smt/alpha/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
diff --git a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt
index 91de8ff11..561bc8cb1 100644
--- a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt
+++ b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt
@@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
-host_inst_rate 115372 # Simulator instruction rate (inst/s)
-host_mem_usage 204236 # Number of bytes of host memory used
-host_seconds 0.11 # Real time elapsed on the host
-host_tick_rate 127463354 # Simulator tick rate (ticks/s)
+host_inst_rate 10660 # Simulator instruction rate (inst/s)
+host_mem_usage 204092 # Number of bytes of host memory used
+host_seconds 1.20 # Real time elapsed on the host
+host_tick_rate 11797749 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 12773 # Number of instructions simulated
sim_seconds 0.000014 # Number of seconds simulated
@@ -213,9 +213,10 @@ system.cpu.dtb.write_hits 2080 # DT
system.cpu.dtb.write_misses 54 # DTB write misses
system.cpu.fetch.Branches 5341 # Number of branches that fetch encountered
system.cpu.fetch.CacheLines 3993 # Number of cache lines fetched
-system.cpu.fetch.Cycles 9162 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.Cycles 5113 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.IcacheSquashes 611 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.Insts 29881 # Number of instructions fetch has processed
+system.cpu.fetch.MiscStallCycles 56 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.SquashCycles 1641 # Number of cycles fetch has spent squashing
system.cpu.fetch.branchRate 0.188868 # Number of branch fetches per cycle
system.cpu.fetch.icacheStallCycles 3993 # Number of cycles fetch is stalled on an Icache miss