diff options
Diffstat (limited to 'tests/quick/01.hello-2T-smt/ref/alpha/linux')
3 files changed, 225 insertions, 21 deletions
diff --git a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini index 808784ec1..eef6bf91e 100644 --- a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini +++ b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini @@ -136,8 +136,8 @@ size=64 [system.cpu.fuPool] type=FUPool -children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 -FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 +children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 +FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8 [system.cpu.fuPool.FUList0] type=FUDesc @@ -231,41 +231,167 @@ opLat=1 [system.cpu.fuPool.FUList5] type=FUDesc +children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 +count=4 +opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19 + +[system.cpu.fuPool.FUList5.opList00] +type=OpDesc +issueLat=1 +opClass=SimdAdd +opLat=1 + +[system.cpu.fuPool.FUList5.opList01] +type=OpDesc +issueLat=1 +opClass=SimdAddAcc +opLat=1 + +[system.cpu.fuPool.FUList5.opList02] +type=OpDesc +issueLat=1 +opClass=SimdAlu +opLat=1 + +[system.cpu.fuPool.FUList5.opList03] +type=OpDesc +issueLat=1 +opClass=SimdCmp +opLat=1 + +[system.cpu.fuPool.FUList5.opList04] +type=OpDesc +issueLat=1 +opClass=SimdCvt +opLat=1 + +[system.cpu.fuPool.FUList5.opList05] +type=OpDesc +issueLat=1 +opClass=SimdMisc +opLat=1 + +[system.cpu.fuPool.FUList5.opList06] +type=OpDesc +issueLat=1 +opClass=SimdMult +opLat=1 + +[system.cpu.fuPool.FUList5.opList07] +type=OpDesc +issueLat=1 +opClass=SimdMultAcc +opLat=1 + +[system.cpu.fuPool.FUList5.opList08] +type=OpDesc +issueLat=1 +opClass=SimdShift +opLat=1 + +[system.cpu.fuPool.FUList5.opList09] +type=OpDesc +issueLat=1 +opClass=SimdShiftAcc +opLat=1 + +[system.cpu.fuPool.FUList5.opList10] +type=OpDesc +issueLat=1 +opClass=SimdSqrt +opLat=1 + +[system.cpu.fuPool.FUList5.opList11] +type=OpDesc +issueLat=1 +opClass=SimdFloatAdd +opLat=1 + +[system.cpu.fuPool.FUList5.opList12] +type=OpDesc +issueLat=1 +opClass=SimdFloatAlu +opLat=1 + +[system.cpu.fuPool.FUList5.opList13] +type=OpDesc +issueLat=1 +opClass=SimdFloatCmp +opLat=1 + +[system.cpu.fuPool.FUList5.opList14] +type=OpDesc +issueLat=1 +opClass=SimdFloatCvt +opLat=1 + +[system.cpu.fuPool.FUList5.opList15] +type=OpDesc +issueLat=1 +opClass=SimdFloatDiv +opLat=1 + +[system.cpu.fuPool.FUList5.opList16] +type=OpDesc +issueLat=1 +opClass=SimdFloatMisc +opLat=1 + +[system.cpu.fuPool.FUList5.opList17] +type=OpDesc +issueLat=1 +opClass=SimdFloatMult +opLat=1 + +[system.cpu.fuPool.FUList5.opList18] +type=OpDesc +issueLat=1 +opClass=SimdFloatMultAcc +opLat=1 + +[system.cpu.fuPool.FUList5.opList19] +type=OpDesc +issueLat=1 +opClass=SimdFloatSqrt +opLat=1 + +[system.cpu.fuPool.FUList6] +type=FUDesc children=opList count=0 -opList=system.cpu.fuPool.FUList5.opList +opList=system.cpu.fuPool.FUList6.opList -[system.cpu.fuPool.FUList5.opList] +[system.cpu.fuPool.FUList6.opList] type=OpDesc issueLat=1 opClass=MemWrite opLat=1 -[system.cpu.fuPool.FUList6] +[system.cpu.fuPool.FUList7] type=FUDesc children=opList0 opList1 count=4 -opList=system.cpu.fuPool.FUList6.opList0 system.cpu.fuPool.FUList6.opList1 +opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 -[system.cpu.fuPool.FUList6.opList0] +[system.cpu.fuPool.FUList7.opList0] type=OpDesc issueLat=1 opClass=MemRead opLat=1 -[system.cpu.fuPool.FUList6.opList1] +[system.cpu.fuPool.FUList7.opList1] type=OpDesc issueLat=1 opClass=MemWrite opLat=1 -[system.cpu.fuPool.FUList7] +[system.cpu.fuPool.FUList8] type=FUDesc children=opList count=1 -opList=system.cpu.fuPool.FUList7.opList +opList=system.cpu.fuPool.FUList8.opList -[system.cpu.fuPool.FUList7.opList] +[system.cpu.fuPool.FUList8.opList] type=OpDesc issueLat=3 opClass=IprAccess diff --git a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/simout b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/simout index 8e80e0787..3dc1278fb 100755 --- a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/simout +++ b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/simout @@ -1,5 +1,3 @@ -Redirecting stdout to build/ALPHA_SE/tests/opt/quick/01.hello-2T-smt/alpha/linux/o3-timing/simout -Redirecting stderr to build/ALPHA_SE/tests/opt/quick/01.hello-2T-smt/alpha/linux/o3-timing/simerr M5 Simulator System Copyright (c) 2001-2008 @@ -7,11 +5,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Aug 26 2010 11:51:59 -M5 revision 85cafc6ccb42 7662 default qtip tip sc-fail-fix -M5 started Aug 26 2010 12:11:50 +M5 compiled Nov 15 2010 08:52:32 +M5 revision f440cdaf1c2d+ 7743+ default tip +M5 started Nov 15 2010 13:43:59 M5 executing on zizzer -command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/quick/01.hello-2T-smt/alpha/linux/o3-timing -re tests/run.py build/ALPHA_SE/tests/opt/quick/01.hello-2T-smt/alpha/linux/o3-timing +command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/01.hello-2T-smt/alpha/linux/o3-timing -re tests/run.py build/ALPHA_SE/tests/fast/quick/01.hello-2T-smt/alpha/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. diff --git a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt index f38e46afc..91de8ff11 100644 --- a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt +++ b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 53800 # Simulator instruction rate (inst/s) -host_mem_usage 205552 # Number of bytes of host memory used -host_seconds 0.24 # Real time elapsed on the host -host_tick_rate 59488297 # Simulator tick rate (ticks/s) +host_inst_rate 115372 # Simulator instruction rate (inst/s) +host_mem_usage 204236 # Number of bytes of host memory used +host_seconds 0.11 # Real time elapsed on the host +host_tick_rate 127463354 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 12773 # Number of instructions simulated sim_seconds 0.000014 # Number of seconds simulated @@ -436,6 +436,26 @@ system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 67.11% # Ty system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 67.11% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 67.11% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 67.11% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdAdd 0 0.00% 67.11% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 67.11% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 67.11% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 67.11% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 67.11% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 67.11% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 67.11% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 67.11% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 67.11% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 67.11% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 67.11% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd 0 0.00% 67.11% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 67.11% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp 0 0.00% 67.11% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt 0 0.00% 67.11% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv 0 0.00% 67.11% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc 0 0.00% 67.11% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 67.11% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc 0 0.00% 67.11% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 67.11% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::MemRead 2121 21.37% 88.48% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::MemWrite 1143 11.52% 100.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued @@ -451,6 +471,26 @@ system.cpu.iq.ISSUE:FU_type_1::FloatCvt 0 0.00% 67.67% # Ty system.cpu.iq.ISSUE:FU_type_1::FloatMult 0 0.00% 67.67% # Type of FU issued system.cpu.iq.ISSUE:FU_type_1::FloatDiv 0 0.00% 67.67% # Type of FU issued system.cpu.iq.ISSUE:FU_type_1::FloatSqrt 0 0.00% 67.67% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_1::SimdAdd 0 0.00% 67.67% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_1::SimdAddAcc 0 0.00% 67.67% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_1::SimdAlu 0 0.00% 67.67% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_1::SimdCmp 0 0.00% 67.67% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_1::SimdCvt 0 0.00% 67.67% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_1::SimdMisc 0 0.00% 67.67% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_1::SimdMult 0 0.00% 67.67% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_1::SimdMultAcc 0 0.00% 67.67% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_1::SimdShift 0 0.00% 67.67% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_1::SimdShiftAcc 0 0.00% 67.67% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_1::SimdSqrt 0 0.00% 67.67% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_1::SimdFloatAdd 0 0.00% 67.67% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_1::SimdFloatAlu 0 0.00% 67.67% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_1::SimdFloatCmp 0 0.00% 67.67% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_1::SimdFloatCvt 0 0.00% 67.67% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_1::SimdFloatDiv 0 0.00% 67.67% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_1::SimdFloatMisc 0 0.00% 67.67% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_1::SimdFloatMult 0 0.00% 67.67% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_1::SimdFloatMultAcc 0 0.00% 67.67% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_1::SimdFloatSqrt 0 0.00% 67.67% # Type of FU issued system.cpu.iq.ISSUE:FU_type_1::MemRead 2103 21.07% 88.75% # Type of FU issued system.cpu.iq.ISSUE:FU_type_1::MemWrite 1123 11.25% 100.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_1::IprAccess 0 0.00% 100.00% # Type of FU issued @@ -466,6 +506,26 @@ system.cpu.iq.ISSUE:FU_type::FloatCvt 0 0.00% 67.39% # Ty system.cpu.iq.ISSUE:FU_type::FloatMult 0 0.00% 67.39% # Type of FU issued system.cpu.iq.ISSUE:FU_type::FloatDiv 0 0.00% 67.39% # Type of FU issued system.cpu.iq.ISSUE:FU_type::FloatSqrt 0 0.00% 67.39% # Type of FU issued +system.cpu.iq.ISSUE:FU_type::SimdAdd 0 0.00% 67.39% # Type of FU issued +system.cpu.iq.ISSUE:FU_type::SimdAddAcc 0 0.00% 67.39% # Type of FU issued +system.cpu.iq.ISSUE:FU_type::SimdAlu 0 0.00% 67.39% # Type of FU issued +system.cpu.iq.ISSUE:FU_type::SimdCmp 0 0.00% 67.39% # Type of FU issued +system.cpu.iq.ISSUE:FU_type::SimdCvt 0 0.00% 67.39% # Type of FU issued +system.cpu.iq.ISSUE:FU_type::SimdMisc 0 0.00% 67.39% # Type of FU issued +system.cpu.iq.ISSUE:FU_type::SimdMult 0 0.00% 67.39% # Type of FU issued +system.cpu.iq.ISSUE:FU_type::SimdMultAcc 0 0.00% 67.39% # Type of FU issued +system.cpu.iq.ISSUE:FU_type::SimdShift 0 0.00% 67.39% # Type of FU issued +system.cpu.iq.ISSUE:FU_type::SimdShiftAcc 0 0.00% 67.39% # Type of FU issued +system.cpu.iq.ISSUE:FU_type::SimdSqrt 0 0.00% 67.39% # Type of FU issued +system.cpu.iq.ISSUE:FU_type::SimdFloatAdd 0 0.00% 67.39% # Type of FU issued +system.cpu.iq.ISSUE:FU_type::SimdFloatAlu 0 0.00% 67.39% # Type of FU issued +system.cpu.iq.ISSUE:FU_type::SimdFloatCmp 0 0.00% 67.39% # Type of FU issued +system.cpu.iq.ISSUE:FU_type::SimdFloatCvt 0 0.00% 67.39% # Type of FU issued +system.cpu.iq.ISSUE:FU_type::SimdFloatDiv 0 0.00% 67.39% # Type of FU issued +system.cpu.iq.ISSUE:FU_type::SimdFloatMisc 0 0.00% 67.39% # Type of FU issued +system.cpu.iq.ISSUE:FU_type::SimdFloatMult 0 0.00% 67.39% # Type of FU issued +system.cpu.iq.ISSUE:FU_type::SimdFloatMultAcc 0 0.00% 67.39% # Type of FU issued +system.cpu.iq.ISSUE:FU_type::SimdFloatSqrt 0 0.00% 67.39% # Type of FU issued system.cpu.iq.ISSUE:FU_type::MemRead 4224 21.22% 88.61% # Type of FU issued system.cpu.iq.ISSUE:FU_type::MemWrite 2266 11.39% 100.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type::IprAccess 0 0.00% 100.00% # Type of FU issued @@ -487,6 +547,26 @@ system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 9.70% # at system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 9.70% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 9.70% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 9.70% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdAdd 0 0.00% 9.70% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 9.70% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdAlu 0 0.00% 9.70% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdCmp 0 0.00% 9.70% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdCvt 0 0.00% 9.70% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdMisc 0 0.00% 9.70% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdMult 0 0.00% 9.70% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 9.70% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdShift 0 0.00% 9.70% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 9.70% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 9.70% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 9.70% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 9.70% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 9.70% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 9.70% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 9.70% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 9.70% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 9.70% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 9.70% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 9.70% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::MemRead 89 53.94% 63.64% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::MemWrite 60 36.36% 100.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available |