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-rw-r--r--tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini4
-rwxr-xr-xtests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/simout10
-rw-r--r--tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt24
3 files changed, 19 insertions, 19 deletions
diff --git a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini
index fa7d3cfec..f89bcb443 100644
--- a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini
+++ b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini
@@ -361,7 +361,7 @@ egid=100
env=
errout=cerr
euid=100
-executable=/dist/m5/regression/test-progs/hello/bin/alpha/linux/hello
+executable=tests/test-progs/hello/bin/alpha/linux/hello
gid=100
input=cin
max_stack_size=67108864
@@ -380,7 +380,7 @@ egid=100
env=
errout=cerr
euid=100
-executable=/dist/m5/regression/test-progs/hello/bin/alpha/linux/hello
+executable=tests/test-progs/hello/bin/alpha/linux/hello
gid=100
input=cin
max_stack_size=67108864
diff --git a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/simout b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/simout
index 46bfe60b8..187715811 100755
--- a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/simout
+++ b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/simout
@@ -5,11 +5,11 @@ The Regents of The University of Michigan
All Rights Reserved
-M5 compiled Apr 8 2009 12:30:02
-M5 revision 233a4a1a6110 6024 default qtip tip test_unifytlb.diff
-M5 started Apr 8 2009 12:44:23
-M5 executing on maize
-command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/01.hello-2T-smt/alpha/linux/o3-timing -re tests/run.py build/ALPHA_SE/tests/fast/quick/01.hello-2T-smt/alpha/linux/o3-timing
+M5 compiled Apr 14 2009 16:03:56
+M5 revision 5716400b2110+ 6033+ default qtip tip new-thread-status-stats-update
+M5 started Apr 14 2009 16:03:57
+M5 executing on phenom
+command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/quick/01.hello-2T-smt/alpha/linux/o3-timing -re tests/run.py build/ALPHA_SE/tests/opt/quick/01.hello-2T-smt/alpha/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
diff --git a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt
index ae5c73ad7..d738dd02e 100644
--- a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt
+++ b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt
@@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
-host_inst_rate 98882 # Simulator instruction rate (inst/s)
-host_mem_usage 203072 # Number of bytes of host memory used
-host_seconds 0.13 # Real time elapsed on the host
-host_tick_rate 110106309 # Simulator tick rate (ticks/s)
+host_inst_rate 12362 # Simulator instruction rate (inst/s)
+host_mem_usage 204880 # Number of bytes of host memory used
+host_seconds 1.03 # Real time elapsed on the host
+host_tick_rate 13784522 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 12773 # Number of instructions simulated
sim_seconds 0.000014 # Number of seconds simulated
@@ -23,10 +23,10 @@ system.cpu.commit.COM:bw_lim_events 122 # nu
system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
system.cpu.commit.COM:bw_limited_0 0 # number of insts not committed due to BW limits
system.cpu.commit.COM:bw_limited_1 0 # number of insts not committed due to BW limits
-system.cpu.commit.COM:committed_per_cycle::samples 22837 # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::samples 22838 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::0-1 16880 73.92% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::0-1 16881 73.92% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::1-2 3016 13.21% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::2-3 1386 6.07% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::3-4 576 2.52% # Number of insts commited each cycle
@@ -36,10 +36,10 @@ system.cpu.commit.COM:committed_per_cycle::6-7 170 0.74%
system.cpu.commit.COM:committed_per_cycle::7-8 93 0.41% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::8 122 0.53% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::total 22837 # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::total 22838 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::mean 0.560800 # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::stdev 1.272250 # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::mean 0.560776 # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::stdev 1.272228 # Number of insts commited each cycle
system.cpu.commit.COM:count 12807 # Number of instructions committed
system.cpu.commit.COM:count_0 6403 # Number of instructions committed
system.cpu.commit.COM:count_1 6404 # Number of instructions committed
@@ -202,7 +202,7 @@ system.cpu.dcache.warmup_cycle 0 # Cy
system.cpu.dcache.writebacks 0 # number of writebacks
system.cpu.dcache.writebacks_0 0 # number of writebacks
system.cpu.dcache.writebacks_1 0 # number of writebacks
-system.cpu.decode.DECODE:BlockedCycles 5062 # Number of cycles decode is blocked
+system.cpu.decode.DECODE:BlockedCycles 5063 # Number of cycles decode is blocked
system.cpu.decode.DECODE:BranchMispred 441 # Number of times decode detected a branch misprediction
system.cpu.decode.DECODE:BranchResolved 602 # Number of times decode resolved a branch
system.cpu.decode.DECODE:DecodedInsts 27492 # Number of instructions handled by decode
@@ -232,7 +232,7 @@ system.cpu.fetch.CacheLines 4113 # Nu
system.cpu.fetch.Cycles 9444 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.IcacheSquashes 613 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.Insts 30949 # Number of instructions fetch has processed
-system.cpu.fetch.SquashCycles 1714 # Number of cycles fetch has spent squashing
+system.cpu.fetch.SquashCycles 1712 # Number of cycles fetch has spent squashing
system.cpu.fetch.branchRate 0.194639 # Number of branch fetches per cycle
system.cpu.fetch.icacheStallCycles 4113 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.predictedBranches 1597 # Number of branches that fetch has predicted taken
@@ -737,7 +737,7 @@ system.cpu.rename.RENAME:RunCycles 4546 # Nu
system.cpu.rename.RENAME:SquashCycles 2128 # Number of cycles rename is squashing
system.cpu.rename.RENAME:UnblockCycles 1422 # Number of cycles rename is unblocking
system.cpu.rename.RENAME:UndoneMaps 10372 # Number of HB maps that are undone due to squashing
-system.cpu.rename.RENAME:serializeStallCycles 849 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RENAME:serializeStallCycles 850 # count of cycles rename stalled for serializing inst
system.cpu.rename.RENAME:serializingInsts 48 # count of serializing insts renamed
system.cpu.rename.RENAME:skidInsts 3399 # count of insts added to the skid buffer
system.cpu.rename.RENAME:tempSerializingInsts 36 # count of temporary serializing insts renamed