diff options
Diffstat (limited to 'tests/quick/02.insttest/ref/sparc/linux/o3-timing/stats.txt')
| -rw-r--r-- | tests/quick/02.insttest/ref/sparc/linux/o3-timing/stats.txt | 14 |
1 files changed, 10 insertions, 4 deletions
diff --git a/tests/quick/02.insttest/ref/sparc/linux/o3-timing/stats.txt b/tests/quick/02.insttest/ref/sparc/linux/o3-timing/stats.txt index 4b0bc6800..d92dfc078 100644 --- a/tests/quick/02.insttest/ref/sparc/linux/o3-timing/stats.txt +++ b/tests/quick/02.insttest/ref/sparc/linux/o3-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1945 # Simulator instruction rate (inst/s) -host_mem_usage 190344 # Number of bytes of host memory used -host_seconds 7.43 # Real time elapsed on the host -host_tick_rate 3735278 # Simulator tick rate (ticks/s) +host_inst_rate 72869 # Simulator instruction rate (inst/s) +host_mem_usage 190800 # Number of bytes of host memory used +host_seconds 0.20 # Real time elapsed on the host +host_tick_rate 139786869 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 14449 # Number of instructions simulated sim_seconds 0.000028 # Number of seconds simulated @@ -95,6 +95,8 @@ system.cpu.dcache.demand_mshr_misses 167 # nu system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.occ_%::0 0.026530 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::0 108.665251 # Average occupied blocks per context system.cpu.dcache.overall_accesses 5286 # number of overall (read+write) accesses system.cpu.dcache.overall_avg_miss_latency 32057.347670 # average overall miss latency system.cpu.dcache.overall_avg_mshr_miss_latency 35607.784431 # average overall mshr miss latency @@ -182,6 +184,8 @@ system.cpu.icache.demand_mshr_misses 359 # nu system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.icache.occ_%::0 0.110760 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::0 226.836007 # Average occupied blocks per context system.cpu.icache.overall_accesses 7356 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency 33620.560748 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 34869.080780 # average overall mshr miss latency @@ -354,6 +358,8 @@ system.cpu.l2cache.demand_mshr_misses 503 # nu system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.l2cache.occ_%::0 0.007680 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::0 251.642612 # Average occupied blocks per context system.cpu.l2cache.overall_accesses 507 # number of overall (read+write) accesses system.cpu.l2cache.overall_avg_miss_latency 34252.485089 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 31057.654076 # average overall mshr miss latency |