diff options
Diffstat (limited to 'tests/quick/02.insttest/ref/sparc/linux/simple-timing/stats.txt')
| -rw-r--r-- | tests/quick/02.insttest/ref/sparc/linux/simple-timing/stats.txt | 14 |
1 files changed, 10 insertions, 4 deletions
diff --git a/tests/quick/02.insttest/ref/sparc/linux/simple-timing/stats.txt b/tests/quick/02.insttest/ref/sparc/linux/simple-timing/stats.txt index 5c475dff1..07c8914c3 100644 --- a/tests/quick/02.insttest/ref/sparc/linux/simple-timing/stats.txt +++ b/tests/quick/02.insttest/ref/sparc/linux/simple-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 286976 # Simulator instruction rate (inst/s) -host_mem_usage 202788 # Number of bytes of host memory used -host_seconds 0.05 # Real time elapsed on the host -host_tick_rate 804151064 # Simulator tick rate (ticks/s) +host_inst_rate 227392 # Simulator instruction rate (inst/s) +host_mem_usage 190044 # Number of bytes of host memory used +host_seconds 0.07 # Real time elapsed on the host +host_tick_rate 637540839 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 15175 # Number of instructions simulated sim_seconds 0.000043 # Number of seconds simulated @@ -52,6 +52,8 @@ system.cpu.dcache.demand_mshr_misses 155 # nu system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.occ_%::0 0.023864 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::0 97.747327 # Average occupied blocks per context system.cpu.dcache.overall_accesses 3668 # number of overall (read+write) accesses system.cpu.dcache.overall_avg_miss_latency 56000 # average overall miss latency system.cpu.dcache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency @@ -105,6 +107,8 @@ system.cpu.icache.demand_mshr_misses 280 # nu system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.icache.occ_%::0 0.074743 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::0 153.073222 # Average occupied blocks per context system.cpu.icache.overall_accesses 15221 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency 55700 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 52700 # average overall mshr miss latency @@ -177,6 +181,8 @@ system.cpu.l2cache.demand_mshr_misses 416 # nu system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.l2cache.occ_%::0 0.005323 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::0 174.433606 # Average occupied blocks per context system.cpu.l2cache.overall_accesses 418 # number of overall (read+write) accesses system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency |