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-rw-r--r--tests/quick/02.insttest/ref/sparc/linux/o3-timing/config.ini2
-rwxr-xr-xtests/quick/02.insttest/ref/sparc/linux/o3-timing/simout10
-rw-r--r--tests/quick/02.insttest/ref/sparc/linux/o3-timing/stats.txt10
3 files changed, 11 insertions, 11 deletions
diff --git a/tests/quick/02.insttest/ref/sparc/linux/o3-timing/config.ini b/tests/quick/02.insttest/ref/sparc/linux/o3-timing/config.ini
index cd894f5bd..95ee672cf 100644
--- a/tests/quick/02.insttest/ref/sparc/linux/o3-timing/config.ini
+++ b/tests/quick/02.insttest/ref/sparc/linux/o3-timing/config.ini
@@ -361,7 +361,7 @@ egid=100
env=
errout=cerr
euid=100
-executable=/dist/m5/regression/test-progs/insttest/bin/sparc/linux/insttest
+executable=tests/test-progs/insttest/bin/sparc/linux/insttest
gid=100
input=cin
max_stack_size=67108864
diff --git a/tests/quick/02.insttest/ref/sparc/linux/o3-timing/simout b/tests/quick/02.insttest/ref/sparc/linux/o3-timing/simout
index 642546f37..974c1f458 100755
--- a/tests/quick/02.insttest/ref/sparc/linux/o3-timing/simout
+++ b/tests/quick/02.insttest/ref/sparc/linux/o3-timing/simout
@@ -5,11 +5,11 @@ The Regents of The University of Michigan
All Rights Reserved
-M5 compiled Apr 8 2009 12:30:02
-M5 revision 233a4a1a6110 6024 default qtip tip test_unifytlb.diff
-M5 started Apr 8 2009 12:32:54
-M5 executing on maize
-command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/02.insttest/sparc/linux/o3-timing -re tests/run.py build/SPARC_SE/tests/fast/quick/02.insttest/sparc/linux/o3-timing
+M5 compiled Apr 14 2009 16:03:50
+M5 revision 5716400b2110+ 6033+ default qtip tip new-thread-status-stats-update
+M5 started Apr 14 2009 16:03:52
+M5 executing on phenom
+command line: build/SPARC_SE/m5.opt -d build/SPARC_SE/tests/opt/quick/02.insttest/sparc/linux/o3-timing -re tests/run.py build/SPARC_SE/tests/opt/quick/02.insttest/sparc/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
Begining test of difficult SPARC instructions...
diff --git a/tests/quick/02.insttest/ref/sparc/linux/o3-timing/stats.txt b/tests/quick/02.insttest/ref/sparc/linux/o3-timing/stats.txt
index 77ce05481..3faf1f835 100644
--- a/tests/quick/02.insttest/ref/sparc/linux/o3-timing/stats.txt
+++ b/tests/quick/02.insttest/ref/sparc/linux/o3-timing/stats.txt
@@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
-host_inst_rate 71088 # Simulator instruction rate (inst/s)
-host_mem_usage 203480 # Number of bytes of host memory used
-host_seconds 0.20 # Real time elapsed on the host
-host_tick_rate 136384184 # Simulator tick rate (ticks/s)
+host_inst_rate 9495 # Simulator instruction rate (inst/s)
+host_mem_usage 208836 # Number of bytes of host memory used
+host_seconds 1.52 # Real time elapsed on the host
+host_tick_rate 18237542 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 14449 # Number of instructions simulated
sim_seconds 0.000028 # Number of seconds simulated
@@ -127,7 +127,7 @@ system.cpu.fetch.CacheLines 7356 # Nu
system.cpu.fetch.Cycles 24020 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.IcacheSquashes 845 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.Insts 58247 # Number of instructions fetch has processed
-system.cpu.fetch.SquashCycles 3019 # Number of cycles fetch has spent squashing
+system.cpu.fetch.SquashCycles 3018 # Number of cycles fetch has spent squashing
system.cpu.fetch.branchRate 0.205588 # Number of branch fetches per cycle
system.cpu.fetch.icacheStallCycles 7356 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.predictedBranches 4398 # Number of branches that fetch has predicted taken