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-rw-r--r--tests/quick/02.insttest/ref/sparc/linux/o3-timing/config.ini11
-rw-r--r--tests/quick/02.insttest/ref/sparc/linux/o3-timing/config.out11
-rw-r--r--tests/quick/02.insttest/ref/sparc/linux/o3-timing/m5stats.txt469
-rw-r--r--tests/quick/02.insttest/ref/sparc/linux/o3-timing/stdout8
-rw-r--r--tests/quick/02.insttest/ref/sparc/linux/simple-atomic/config.ini1
-rw-r--r--tests/quick/02.insttest/ref/sparc/linux/simple-atomic/config.out1
-rw-r--r--tests/quick/02.insttest/ref/sparc/linux/simple-atomic/m5stats.txt8
-rw-r--r--tests/quick/02.insttest/ref/sparc/linux/simple-atomic/stdout6
-rw-r--r--tests/quick/02.insttest/ref/sparc/linux/simple-timing/config.ini11
-rw-r--r--tests/quick/02.insttest/ref/sparc/linux/simple-timing/config.out11
-rw-r--r--tests/quick/02.insttest/ref/sparc/linux/simple-timing/m5stats.txt100
-rw-r--r--tests/quick/02.insttest/ref/sparc/linux/simple-timing/stdout8
12 files changed, 322 insertions, 323 deletions
diff --git a/tests/quick/02.insttest/ref/sparc/linux/o3-timing/config.ini b/tests/quick/02.insttest/ref/sparc/linux/o3-timing/config.ini
index 1f1e7a355..61102139c 100644
--- a/tests/quick/02.insttest/ref/sparc/linux/o3-timing/config.ini
+++ b/tests/quick/02.insttest/ref/sparc/linux/o3-timing/config.ini
@@ -91,8 +91,7 @@ block_size=64
compressed_bus=false
compression_latency=0
hash_delay=1
-hit_latency=1
-latency=1
+latency=1000
lifo=false
max_miss_count=0
mshrs=10
@@ -267,8 +266,7 @@ block_size=64
compressed_bus=false
compression_latency=0
hash_delay=1
-hit_latency=1
-latency=1
+latency=1000
lifo=false
max_miss_count=0
mshrs=10
@@ -306,8 +304,7 @@ block_size=64
compressed_bus=false
compression_latency=0
hash_delay=1
-hit_latency=1
-latency=1
+latency=1000
lifo=false
max_miss_count=0
mshrs=10
@@ -339,6 +336,7 @@ mem_side=system.membus.port[1]
[system.cpu.toL2Bus]
type=Bus
+block_size=64
bus_id=0
clock=1000
responder_set=false
@@ -363,6 +361,7 @@ uid=100
[system.membus]
type=Bus
+block_size=64
bus_id=0
clock=1000
responder_set=false
diff --git a/tests/quick/02.insttest/ref/sparc/linux/o3-timing/config.out b/tests/quick/02.insttest/ref/sparc/linux/o3-timing/config.out
index ac1dcb9ba..70564f749 100644
--- a/tests/quick/02.insttest/ref/sparc/linux/o3-timing/config.out
+++ b/tests/quick/02.insttest/ref/sparc/linux/o3-timing/config.out
@@ -20,6 +20,7 @@ bus_id=0
clock=1000
width=64
responder_set=false
+block_size=64
[system.cpu.workload]
type=LiveProcess
@@ -249,7 +250,7 @@ type=BaseCache
size=131072
assoc=2
block_size=64
-latency=1
+latency=1000
mshrs=10
tgts_per_mshr=20
write_buffers=8
@@ -280,14 +281,13 @@ prefetch_policy=none
prefetch_cache_check_push=true
prefetch_use_cpu_id=true
prefetch_data_accesses_only=false
-hit_latency=1
[system.cpu.dcache]
type=BaseCache
size=262144
assoc=2
block_size=64
-latency=1
+latency=1000
mshrs=10
tgts_per_mshr=20
write_buffers=8
@@ -318,14 +318,13 @@ prefetch_policy=none
prefetch_cache_check_push=true
prefetch_use_cpu_id=true
prefetch_data_accesses_only=false
-hit_latency=1
[system.cpu.l2cache]
type=BaseCache
size=2097152
assoc=2
block_size=64
-latency=1
+latency=1000
mshrs=10
tgts_per_mshr=5
write_buffers=8
@@ -356,7 +355,6 @@ prefetch_policy=none
prefetch_cache_check_push=true
prefetch_use_cpu_id=true
prefetch_data_accesses_only=false
-hit_latency=1
[system.cpu.toL2Bus]
type=Bus
@@ -364,4 +362,5 @@ bus_id=0
clock=1000
width=64
responder_set=false
+block_size=64
diff --git a/tests/quick/02.insttest/ref/sparc/linux/o3-timing/m5stats.txt b/tests/quick/02.insttest/ref/sparc/linux/o3-timing/m5stats.txt
index 8359db0f2..7859d5c2b 100644
--- a/tests/quick/02.insttest/ref/sparc/linux/o3-timing/m5stats.txt
+++ b/tests/quick/02.insttest/ref/sparc/linux/o3-timing/m5stats.txt
@@ -1,40 +1,40 @@
---------- Begin Simulation Statistics ----------
global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-global.BPredUnit.BTBHits 3154 # Number of BTB hits
-global.BPredUnit.BTBLookups 9574 # Number of BTB lookups
+global.BPredUnit.BTBHits 2726 # Number of BTB hits
+global.BPredUnit.BTBLookups 7230 # Number of BTB lookups
global.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions.
-global.BPredUnit.condIncorrect 2047 # Number of conditional branches incorrect
-global.BPredUnit.condPredicted 10459 # Number of conditional branches predicted
-global.BPredUnit.lookups 10459 # Number of BP lookups
+global.BPredUnit.condIncorrect 2062 # Number of conditional branches incorrect
+global.BPredUnit.condPredicted 7954 # Number of conditional branches predicted
+global.BPredUnit.lookups 7954 # Number of BP lookups
global.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target.
-host_inst_rate 26468 # Simulator instruction rate (inst/s)
-host_mem_usage 154944 # Number of bytes of host memory used
-host_seconds 0.41 # Real time elapsed on the host
-host_tick_rate 32157366 # Simulator tick rate (ticks/s)
-memdepunit.memDep.conflictingLoads 14 # Number of conflicting loads.
+host_inst_rate 37089 # Simulator instruction rate (inst/s)
+host_mem_usage 154932 # Number of bytes of host memory used
+host_seconds 0.30 # Real time elapsed on the host
+host_tick_rate 53780846 # Simulator tick rate (ticks/s)
+memdepunit.memDep.conflictingLoads 10 # Number of conflicting loads.
memdepunit.memDep.conflictingStores 0 # Number of conflicting stores.
-memdepunit.memDep.insertedLoads 3573 # Number of loads inserted to the mem dependence unit.
-memdepunit.memDep.insertedStores 3440 # Number of stores inserted to the mem dependence unit.
+memdepunit.memDep.insertedLoads 3198 # Number of loads inserted to the mem dependence unit.
+memdepunit.memDep.insertedStores 2970 # Number of stores inserted to the mem dependence unit.
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 10976 # Number of instructions simulated
-sim_seconds 0.000013 # Number of seconds simulated
-sim_ticks 13345500 # Number of ticks simulated
+sim_seconds 0.000016 # Number of seconds simulated
+sim_ticks 15931500 # Number of ticks simulated
system.cpu.commit.COM:branches 2152 # Number of branches committed
-system.cpu.commit.COM:bw_lim_events 164 # number cycles where commit BW limit reached
+system.cpu.commit.COM:bw_lim_events 146 # number cycles where commit BW limit reached
system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle.samples 23147
+system.cpu.commit.COM:committed_per_cycle.samples 28801
system.cpu.commit.COM:committed_per_cycle.min_value 0
- 0 17950 7754.78%
- 1 2912 1258.05%
- 2 993 429.00%
- 3 424 183.18%
- 4 287 123.99%
- 5 235 101.53%
- 6 103 44.50%
- 7 79 34.13%
- 8 164 70.85%
+ 0 23411 8128.54%
+ 1 2862 993.72%
+ 2 1174 407.62%
+ 3 608 211.10%
+ 4 359 124.65%
+ 5 123 42.71%
+ 6 103 35.76%
+ 7 15 5.21%
+ 8 146 50.69%
system.cpu.commit.COM:committed_per_cycle.max_value 8
system.cpu.commit.COM:committed_per_cycle.end_dist
@@ -43,72 +43,72 @@ system.cpu.commit.COM:loads 1462 # Nu
system.cpu.commit.COM:membars 0 # Number of memory barriers committed
system.cpu.commit.COM:refs 2760 # Number of memory references committed
system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed
-system.cpu.commit.branchMispredicts 2047 # The number of times a branch was mispredicted
+system.cpu.commit.branchMispredicts 2062 # The number of times a branch was mispredicted
system.cpu.commit.commitCommittedInsts 10976 # The number of committed instructions
system.cpu.commit.commitNonSpecStalls 327 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.commitSquashedInsts 18321 # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts 14297 # The number of squashed insts skipped by commit
system.cpu.committedInsts 10976 # Number of Instructions Simulated
system.cpu.committedInsts_total 10976 # Number of Instructions Simulated
-system.cpu.cpi 2.431851 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 2.431851 # CPI: Total CPI of All Threads
-system.cpu.dcache.ReadReq_accesses 2813 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency 4311.764706 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 3546.153846 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_hits 2728 # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency 366500 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_rate 0.030217 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_misses 85 # number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_hits 20 # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_miss_latency 230500 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate 0.023107 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_misses 65 # number of ReadReq MSHR misses
+system.cpu.cpi 2.903061 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 2.903061 # CPI: Total CPI of All Threads
+system.cpu.dcache.ReadReq_accesses 2743 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_avg_miss_latency 5392.857143 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 4696.969697 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_hits 2659 # number of ReadReq hits
+system.cpu.dcache.ReadReq_miss_latency 453000 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_rate 0.030623 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_misses 84 # number of ReadReq misses
+system.cpu.dcache.ReadReq_mshr_hits 18 # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_miss_latency 310000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate 0.024061 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_misses 66 # number of ReadReq MSHR misses
system.cpu.dcache.SwapReq_accesses 6 # number of SwapReq accesses(hits+misses)
system.cpu.dcache.SwapReq_hits 6 # number of SwapReq hits
system.cpu.dcache.WriteReq_accesses 1292 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency 4645.408163 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 3470.930233 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_hits 1096 # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency 910500 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_rate 0.151703 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses 196 # number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_hits 110 # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_miss_latency 298500 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_avg_miss_latency 5505 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 4802.325581 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_hits 1092 # number of WriteReq hits
+system.cpu.dcache.WriteReq_miss_latency 1101000 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_rate 0.154799 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_misses 200 # number of WriteReq misses
+system.cpu.dcache.WriteReq_mshr_hits 114 # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_miss_latency 413000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_rate 0.066563 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_misses 86 # number of WriteReq MSHR misses
system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
-system.cpu.dcache.avg_refs 25.364238 # Average number of references to valid blocks.
+system.cpu.dcache.avg_refs 24.717105 # Average number of references to valid blocks.
system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.demand_accesses 4105 # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency 4544.483986 # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 3503.311258 # average overall mshr miss latency
-system.cpu.dcache.demand_hits 3824 # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency 1277000 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_rate 0.068453 # miss rate for demand accesses
-system.cpu.dcache.demand_misses 281 # number of demand (read+write) misses
-system.cpu.dcache.demand_mshr_hits 130 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency 529000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_rate 0.036784 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_misses 151 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_accesses 4035 # number of demand (read+write) accesses
+system.cpu.dcache.demand_avg_miss_latency 5471.830986 # average overall miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 4756.578947 # average overall mshr miss latency
+system.cpu.dcache.demand_hits 3751 # number of demand (read+write) hits
+system.cpu.dcache.demand_miss_latency 1554000 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_rate 0.070384 # miss rate for demand accesses
+system.cpu.dcache.demand_misses 284 # number of demand (read+write) misses
+system.cpu.dcache.demand_mshr_hits 132 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_miss_latency 723000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_rate 0.037670 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_misses 152 # number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.overall_accesses 4105 # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency 4544.483986 # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 3503.311258 # average overall mshr miss latency
+system.cpu.dcache.overall_accesses 4035 # number of overall (read+write) accesses
+system.cpu.dcache.overall_avg_miss_latency 5471.830986 # average overall miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 4756.578947 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits 3824 # number of overall hits
-system.cpu.dcache.overall_miss_latency 1277000 # number of overall miss cycles
-system.cpu.dcache.overall_miss_rate 0.068453 # miss rate for overall accesses
-system.cpu.dcache.overall_misses 281 # number of overall misses
-system.cpu.dcache.overall_mshr_hits 130 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency 529000 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_rate 0.036784 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_misses 151 # number of overall MSHR misses
+system.cpu.dcache.overall_hits 3751 # number of overall hits
+system.cpu.dcache.overall_miss_latency 1554000 # number of overall miss cycles
+system.cpu.dcache.overall_miss_rate 0.070384 # miss rate for overall accesses
+system.cpu.dcache.overall_misses 284 # number of overall misses
+system.cpu.dcache.overall_mshr_hits 132 # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_miss_latency 723000 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_rate 0.037670 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_misses 152 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
@@ -121,88 +121,88 @@ system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0
system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
system.cpu.dcache.replacements 0 # number of replacements
-system.cpu.dcache.sampled_refs 151 # Sample count of references to valid blocks.
+system.cpu.dcache.sampled_refs 152 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse 112.362185 # Cycle average of tags in use
-system.cpu.dcache.total_refs 3830 # Total number of references to valid blocks.
+system.cpu.dcache.tagsinuse 113.439038 # Cycle average of tags in use
+system.cpu.dcache.total_refs 3757 # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 0 # number of writebacks
-system.cpu.decode.DECODE:BlockedCycles 4942 # Number of cycles decode is blocked
-system.cpu.decode.DECODE:DecodedInsts 48420 # Number of instructions handled by decode
-system.cpu.decode.DECODE:IdleCycles 8618 # Number of cycles decode is idle
-system.cpu.decode.DECODE:RunCycles 9347 # Number of cycles decode is running
-system.cpu.decode.DECODE:SquashCycles 3545 # Number of cycles decode is squashing
-system.cpu.decode.DECODE:UnblockCycles 240 # Number of cycles decode is unblocking
-system.cpu.fetch.Branches 10459 # Number of branches that fetch encountered
-system.cpu.fetch.CacheLines 5440 # Number of cache lines fetched
-system.cpu.fetch.Cycles 16262 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.IcacheSquashes 216 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.Insts 55152 # Number of instructions fetch has processed
-system.cpu.fetch.SquashCycles 2110 # Number of cycles fetch has spent squashing
-system.cpu.fetch.branchRate 0.391840 # Number of branch fetches per cycle
-system.cpu.fetch.icacheStallCycles 5440 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.predictedBranches 3154 # Number of branches that fetch has predicted taken
-system.cpu.fetch.rate 2.066237 # Number of inst fetches per cycle
+system.cpu.decode.DECODE:BlockedCycles 4602 # Number of cycles decode is blocked
+system.cpu.decode.DECODE:DecodedInsts 38937 # Number of instructions handled by decode
+system.cpu.decode.DECODE:IdleCycles 16098 # Number of cycles decode is idle
+system.cpu.decode.DECODE:RunCycles 7883 # Number of cycles decode is running
+system.cpu.decode.DECODE:SquashCycles 3063 # Number of cycles decode is squashing
+system.cpu.decode.DECODE:UnblockCycles 218 # Number of cycles decode is unblocking
+system.cpu.fetch.Branches 7954 # Number of branches that fetch encountered
+system.cpu.fetch.CacheLines 4933 # Number of cache lines fetched
+system.cpu.fetch.Cycles 14166 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.IcacheSquashes 565 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.Insts 44421 # Number of instructions fetch has processed
+system.cpu.fetch.SquashCycles 2121 # Number of cycles fetch has spent squashing
+system.cpu.fetch.branchRate 0.249623 # Number of branch fetches per cycle
+system.cpu.fetch.icacheStallCycles 4933 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.predictedBranches 2726 # Number of branches that fetch has predicted taken
+system.cpu.fetch.rate 1.394081 # Number of inst fetches per cycle
system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist.samples 26692
+system.cpu.fetch.rateDist.samples 31864
system.cpu.fetch.rateDist.min_value 0
- 0 15871 5945.98%
- 1 2250 842.95%
- 2 637 238.65%
- 3 971 363.78%
- 4 550 206.05%
- 5 848 317.70%
- 6 962 360.41%
- 7 321 120.26%
- 8 4282 1604.23%
+ 0 22632 7102.69%
+ 1 2187 686.35%
+ 2 562 176.37%
+ 3 869 272.72%
+ 4 521 163.51%
+ 5 770 241.65%
+ 6 886 278.06%
+ 7 243 76.26%
+ 8 3194 1002.39%
system.cpu.fetch.rateDist.max_value 8
system.cpu.fetch.rateDist.end_dist
-system.cpu.icache.ReadReq_accesses 5440 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_avg_miss_latency 3939.473684 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 2944.591029 # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_hits 5060 # number of ReadReq hits
-system.cpu.icache.ReadReq_miss_latency 1497000 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_rate 0.069853 # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_misses 380 # number of ReadReq misses
-system.cpu.icache.ReadReq_mshr_hits 1 # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_miss_latency 1116000 # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate 0.069669 # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_misses 379 # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_accesses 4933 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_avg_miss_latency 5310.666667 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 4396.174863 # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_hits 4558 # number of ReadReq hits
+system.cpu.icache.ReadReq_miss_latency 1991500 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_rate 0.076019 # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_misses 375 # number of ReadReq misses
+system.cpu.icache.ReadReq_mshr_hits 9 # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_miss_latency 1609000 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate 0.074194 # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_misses 366 # number of ReadReq MSHR misses
system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
-system.cpu.icache.avg_refs 13.350923 # Average number of references to valid blocks.
+system.cpu.icache.avg_refs 12.453552 # Average number of references to valid blocks.
system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.demand_accesses 5440 # number of demand (read+write) accesses
-system.cpu.icache.demand_avg_miss_latency 3939.473684 # average overall miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 2944.591029 # average overall mshr miss latency
-system.cpu.icache.demand_hits 5060 # number of demand (read+write) hits
-system.cpu.icache.demand_miss_latency 1497000 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_rate 0.069853 # miss rate for demand accesses
-system.cpu.icache.demand_misses 380 # number of demand (read+write) misses
-system.cpu.icache.demand_mshr_hits 1 # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_miss_latency 1116000 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_rate 0.069669 # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_misses 379 # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_accesses 4933 # number of demand (read+write) accesses
+system.cpu.icache.demand_avg_miss_latency 5310.666667 # average overall miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 4396.174863 # average overall mshr miss latency
+system.cpu.icache.demand_hits 4558 # number of demand (read+write) hits
+system.cpu.icache.demand_miss_latency 1991500 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_rate 0.076019 # miss rate for demand accesses
+system.cpu.icache.demand_misses 375 # number of demand (read+write) misses
+system.cpu.icache.demand_mshr_hits 9 # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_miss_latency 1609000 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_rate 0.074194 # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_misses 366 # number of demand (read+write) MSHR misses
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.icache.overall_accesses 5440 # number of overall (read+write) accesses
-system.cpu.icache.overall_avg_miss_latency 3939.473684 # average overall miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 2944.591029 # average overall mshr miss latency
+system.cpu.icache.overall_accesses 4933 # number of overall (read+write) accesses
+system.cpu.icache.overall_avg_miss_latency 5310.666667 # average overall miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 4396.174863 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
-system.cpu.icache.overall_hits 5060 # number of overall hits
-system.cpu.icache.overall_miss_latency 1497000 # number of overall miss cycles
-system.cpu.icache.overall_miss_rate 0.069853 # miss rate for overall accesses
-system.cpu.icache.overall_misses 380 # number of overall misses
-system.cpu.icache.overall_mshr_hits 1 # number of overall MSHR hits
-system.cpu.icache.overall_mshr_miss_latency 1116000 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_rate 0.069669 # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_misses 379 # number of overall MSHR misses
+system.cpu.icache.overall_hits 4558 # number of overall hits
+system.cpu.icache.overall_miss_latency 1991500 # number of overall miss cycles
+system.cpu.icache.overall_miss_rate 0.076019 # miss rate for overall accesses
+system.cpu.icache.overall_misses 375 # number of overall misses
+system.cpu.icache.overall_mshr_hits 9 # number of overall MSHR hits
+system.cpu.icache.overall_mshr_miss_latency 1609000 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_rate 0.074194 # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_misses 366 # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
@@ -215,60 +215,61 @@ system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0
system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
system.cpu.icache.replacements 1 # number of replacements
-system.cpu.icache.sampled_refs 379 # Sample count of references to valid blocks.
+system.cpu.icache.sampled_refs 366 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse 242.916499 # Cycle average of tags in use
-system.cpu.icache.total_refs 5060 # Total number of references to valid blocks.
+system.cpu.icache.tagsinuse 233.760012 # Cycle average of tags in use
+system.cpu.icache.total_refs 4558 # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks
-system.cpu.iew.EXEC:branches 3713 # Number of branches executed
+system.cpu.idleCycles 499 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.iew.EXEC:branches 3548 # Number of branches executed
system.cpu.iew.EXEC:nop 0 # number of nop insts executed
-system.cpu.iew.EXEC:rate 0.830061 # Inst execution rate
-system.cpu.iew.EXEC:refs 5553 # number of memory reference insts executed
-system.cpu.iew.EXEC:stores 2589 # Number of stores executed
+system.cpu.iew.EXEC:rate 0.670318 # Inst execution rate
+system.cpu.iew.EXEC:refs 5385 # number of memory reference insts executed
+system.cpu.iew.EXEC:stores 2502 # Number of stores executed
system.cpu.iew.EXEC:swp 0 # number of swp insts executed
-system.cpu.iew.WB:consumers 10966 # num instructions consuming a value
-system.cpu.iew.WB:count 21367 # cumulative count of insts written-back
-system.cpu.iew.WB:fanout 0.799836 # average fanout of values written-back
+system.cpu.iew.WB:consumers 10159 # num instructions consuming a value
+system.cpu.iew.WB:count 20199 # cumulative count of insts written-back
+system.cpu.iew.WB:fanout 0.790629 # average fanout of values written-back
system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.iew.WB:producers 8771 # num instructions producing a value
-system.cpu.iew.WB:rate 0.800502 # insts written-back per cycle
-system.cpu.iew.WB:sent 21712 # cumulative count of insts sent to commit
-system.cpu.iew.branchMispredicts 2654 # Number of branch mispredicts detected at execute
+system.cpu.iew.WB:producers 8032 # num instructions producing a value
+system.cpu.iew.WB:rate 0.633913 # insts written-back per cycle
+system.cpu.iew.WB:sent 20448 # cumulative count of insts sent to commit
+system.cpu.iew.branchMispredicts 2568 # Number of branch mispredicts detected at execute
system.cpu.iew.iewBlockCycles 0 # Number of cycles IEW is blocking
-system.cpu.iew.iewDispLoadInsts 3573 # Number of dispatched load instructions
-system.cpu.iew.iewDispNonSpecInsts 630 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewDispSquashedInsts 1509 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispStoreInsts 3440 # Number of dispatched store instructions
-system.cpu.iew.iewDispatchedInsts 29298 # Number of instructions dispatched to IQ
-system.cpu.iew.iewExecLoadInsts 2964 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 3437 # Number of squashed instructions skipped in execute
-system.cpu.iew.iewExecutedInsts 22156 # Number of executed instructions
+system.cpu.iew.iewDispLoadInsts 3198 # Number of dispatched load instructions
+system.cpu.iew.iewDispNonSpecInsts 610 # Number of dispatched non-speculative instructions
+system.cpu.iew.iewDispSquashedInsts 2750 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispStoreInsts 2970 # Number of dispatched store instructions
+system.cpu.iew.iewDispatchedInsts 25274 # Number of instructions dispatched to IQ
+system.cpu.iew.iewExecLoadInsts 2883 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 1463 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewExecutedInsts 21359 # Number of executed instructions
system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.iewSquashCycles 3545 # Number of cycles IEW is squashing
+system.cpu.iew.iewSquashCycles 3063 # Number of cycles IEW is squashing
system.cpu.iew.iewUnblockCycles 0 # Number of cycles IEW is unblocking
system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
-system.cpu.iew.lsq.thread.0.forwLoads 52 # Number of loads that had data forwarded from stores
-system.cpu.iew.lsq.thread.0.ignoredResponses 6 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread.0.forwLoads 48 # Number of loads that had data forwarded from stores
+system.cpu.iew.lsq.thread.0.ignoredResponses 8 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
-system.cpu.iew.lsq.thread.0.memOrderViolation 75 # Number of memory ordering violations
-system.cpu.iew.lsq.thread.0.rescheduledLoads 1 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread.0.squashedLoads 2111 # Number of loads squashed
-system.cpu.iew.lsq.thread.0.squashedStores 2142 # Number of stores squashed
-system.cpu.iew.memOrderViolationEvents 75 # Number of memory order violations
-system.cpu.iew.predictedNotTakenIncorrect 1030 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.predictedTakenIncorrect 1624 # Number of branches that were predicted taken incorrectly
-system.cpu.ipc 0.411209 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 0.411209 # IPC: Total IPC of All Threads
-system.cpu.iq.ISSUE:FU_type_0 25593 # Type of FU issued
+system.cpu.iew.lsq.thread.0.memOrderViolation 52 # Number of memory ordering violations
+system.cpu.iew.lsq.thread.0.rescheduledLoads 0 # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread.0.squashedLoads 1736 # Number of loads squashed
+system.cpu.iew.lsq.thread.0.squashedStores 1672 # Number of stores squashed
+system.cpu.iew.memOrderViolationEvents 52 # Number of memory order violations
+system.cpu.iew.predictedNotTakenIncorrect 958 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.predictedTakenIncorrect 1610 # Number of branches that were predicted taken incorrectly
+system.cpu.ipc 0.344464 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 0.344464 # IPC: Total IPC of All Threads
+system.cpu.iq.ISSUE:FU_type_0 22822 # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0.start_dist
- (null) 1919 7.50% # Type of FU issued
- IntAlu 17231 67.33% # Type of FU issued
+ (null) 1826 8.00% # Type of FU issued
+ IntAlu 15247 66.81% # Type of FU issued
IntMult 0 0.00% # Type of FU issued
IntDiv 0 0.00% # Type of FU issued
FloatAdd 0 0.00% # Type of FU issued
@@ -277,16 +278,16 @@ system.cpu.iq.ISSUE:FU_type_0.start_dist
FloatMult 0 0.00% # Type of FU issued
FloatDiv 0 0.00% # Type of FU issued
FloatSqrt 0 0.00% # Type of FU issued
- MemRead 3429 13.40% # Type of FU issued
- MemWrite 3014 11.78% # Type of FU issued
+ MemRead 3042 13.33% # Type of FU issued
+ MemWrite 2707 11.86% # Type of FU issued
IprAccess 0 0.00% # Type of FU issued
InstPrefetch 0 0.00% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0.end_dist
-system.cpu.iq.ISSUE:fu_busy_cnt 238 # FU busy when requested
-system.cpu.iq.ISSUE:fu_busy_rate 0.009299 # FU busy rate (busy events/executed inst)
+system.cpu.iq.ISSUE:fu_busy_cnt 190 # FU busy when requested
+system.cpu.iq.ISSUE:fu_busy_rate 0.008325 # FU busy rate (busy events/executed inst)
system.cpu.iq.ISSUE:fu_full.start_dist
(null) 0 0.00% # attempts to use FU when none available
- IntAlu 99 41.60% # attempts to use FU when none available
+ IntAlu 50 26.32% # attempts to use FU when none available
IntMult 0 0.00% # attempts to use FU when none available
IntDiv 0 0.00% # attempts to use FU when none available
FloatAdd 0 0.00% # attempts to use FU when none available
@@ -295,43 +296,43 @@ system.cpu.iq.ISSUE:fu_full.start_dist
FloatMult 0 0.00% # attempts to use FU when none available
FloatDiv 0 0.00% # attempts to use FU when none available
FloatSqrt 0 0.00% # attempts to use FU when none available
- MemRead 22 9.24% # attempts to use FU when none available
- MemWrite 117 49.16% # attempts to use FU when none available
+ MemRead 25 13.16% # attempts to use FU when none available
+ MemWrite 115 60.53% # attempts to use FU when none available
IprAccess 0 0.00% # attempts to use FU when none available
InstPrefetch 0 0.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full.end_dist
system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle.samples 26692
+system.cpu.iq.ISSUE:issued_per_cycle.samples 31864
system.cpu.iq.ISSUE:issued_per_cycle.min_value 0
- 0 17644 6610.22%
- 1 3262 1222.09%
- 2 1371 513.64%
- 3 1071 401.24%
- 4 1568 587.44%
- 5 925 346.55%
- 6 579 216.92%
- 7 171 64.06%
- 8 101 37.84%
+ 0 22879 7180.20%
+ 1 3824 1200.10%
+ 2 1304 409.24%
+ 3 1251 392.61%
+ 4 1252 392.92%
+ 5 751 235.69%
+ 6 414 129.93%
+ 7 122 38.29%
+ 8 67 21.03%
system.cpu.iq.ISSUE:issued_per_cycle.max_value 8
system.cpu.iq.ISSUE:issued_per_cycle.end_dist
-system.cpu.iq.ISSUE:rate 0.958827 # Inst issue rate
-system.cpu.iq.iqInstsAdded 28668 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqInstsIssued 25593 # Number of instructions issued
-system.cpu.iq.iqNonSpecInstsAdded 630 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqSquashedInstsExamined 15737 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedInstsIssued 133 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedNonSpecRemoved 303 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.iqSquashedOperandsExamined 7975 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.l2cache.ReadReq_accesses 526 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_avg_miss_latency 3018.060837 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1812.857414 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_miss_latency 1587500 # number of ReadReq miss cycles
+system.cpu.iq.ISSUE:rate 0.716231 # Inst issue rate
+system.cpu.iq.iqInstsAdded 24664 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqInstsIssued 22822 # Number of instructions issued
+system.cpu.iq.iqNonSpecInstsAdded 610 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqSquashedInstsExamined 11119 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedInstsIssued 83 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedNonSpecRemoved 283 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.iqSquashedOperandsExamined 5685 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.l2cache.ReadReq_accesses 514 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_avg_miss_latency 4458.171206 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2373.540856 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_miss_latency 2291500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_rate 1 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_misses 526 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency 953563 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_misses 514 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency 1220000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate 1 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_misses 526 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses 514 # number of ReadReq MSHR misses
system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
system.cpu.l2cache.avg_refs 0 # Average number of references to valid blocks.
@@ -340,32 +341,32 @@ system.cpu.l2cache.blocked_no_targets 0 # nu
system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
-system.cpu.l2cache.demand_accesses 526 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_avg_miss_latency 3018.060837 # average overall miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency 1812.857414 # average overall mshr miss latency
+system.cpu.l2cache.demand_accesses 514 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_avg_miss_latency 4458.171206 # average overall miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency 2373.540856 # average overall mshr miss latency
system.cpu.l2cache.demand_hits 0 # number of demand (read+write) hits
-system.cpu.l2cache.demand_miss_latency 1587500 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency 2291500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_rate 1 # miss rate for demand accesses
-system.cpu.l2cache.demand_misses 526 # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses 514 # number of demand (read+write) misses
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_miss_latency 953563 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency 1220000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_rate 1 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_misses 526 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses 514 # number of demand (read+write) MSHR misses
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.l2cache.overall_accesses 526 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_avg_miss_latency 3018.060837 # average overall miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency 1812.857414 # average overall mshr miss latency
+system.cpu.l2cache.overall_accesses 514 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_avg_miss_latency 4458.171206 # average overall miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency 2373.540856 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.cpu.l2cache.overall_hits 0 # number of overall hits
-system.cpu.l2cache.overall_miss_latency 1587500 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency 2291500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_rate 1 # miss rate for overall accesses
-system.cpu.l2cache.overall_misses 526 # number of overall misses
+system.cpu.l2cache.overall_misses 514 # number of overall misses
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_miss_latency 953563 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency 1220000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_rate 1 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_misses 526 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses 514 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
@@ -378,28 +379,28 @@ system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0
system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
system.cpu.l2cache.replacements 0 # number of replacements
-system.cpu.l2cache.sampled_refs 526 # Sample count of references to valid blocks.
+system.cpu.l2cache.sampled_refs 514 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse 353.661697 # Cycle average of tags in use
+system.cpu.l2cache.tagsinuse 345.564898 # Cycle average of tags in use
system.cpu.l2cache.total_refs 0 # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.writebacks 0 # number of writebacks
-system.cpu.numCycles 26692 # number of cpu cycles simulated
+system.cpu.numCycles 31864 # number of cpu cycles simulated
system.cpu.rename.RENAME:CommittedMaps 9868 # Number of HB maps that are committed
-system.cpu.rename.RENAME:IdleCycles 8631 # Number of cycles rename is idle
-system.cpu.rename.RENAME:LSQFullEvents 1 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RENAME:RenameLookups 59097 # Number of register rename lookups that rename has made
-system.cpu.rename.RENAME:RenamedInsts 39751 # Number of instructions processed by rename
-system.cpu.rename.RENAME:RenamedOperands 31999 # Number of destination operands rename has renamed
-system.cpu.rename.RENAME:RunCycles 9086 # Number of cycles rename is running
-system.cpu.rename.RENAME:SquashCycles 3545 # Number of cycles rename is squashing
-system.cpu.rename.RENAME:SquashedInsts 8167 # Number of squashed instructions processed by rename
-system.cpu.rename.RENAME:UnblockCycles 716 # Number of cycles rename is unblocking
-system.cpu.rename.RENAME:UndoneMaps 22131 # Number of HB maps that are undone due to squashing
-system.cpu.rename.RENAME:serializeStallCycles 4224 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RENAME:serializingInsts 665 # count of serializing insts renamed
-system.cpu.rename.RENAME:skidInsts 4954 # count of insts added to the skid buffer
-system.cpu.rename.RENAME:tempSerializingInsts 658 # count of temporary serializing insts renamed
+system.cpu.rename.RENAME:IdleCycles 16082 # Number of cycles rename is idle
+system.cpu.rename.RENAME:RenameLookups 44650 # Number of register rename lookups that rename has made
+system.cpu.rename.RENAME:RenamedInsts 29655 # Number of instructions processed by rename
+system.cpu.rename.RENAME:RenamedOperands 24195 # Number of destination operands rename has renamed
+system.cpu.rename.RENAME:RunCycles 7618 # Number of cycles rename is running
+system.cpu.rename.RENAME:SquashCycles 3063 # Number of cycles rename is squashing
+system.cpu.rename.RENAME:SquashedInsts 8815 # Number of squashed instructions processed by rename
+system.cpu.rename.RENAME:UnblockCycles 684 # Number of cycles rename is unblocking
+system.cpu.rename.RENAME:UndoneMaps 14327 # Number of HB maps that are undone due to squashing
+system.cpu.rename.RENAME:serializeStallCycles 3915 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RENAME:serializingInsts 631 # count of serializing insts renamed
+system.cpu.rename.RENAME:skidInsts 4702 # count of insts added to the skid buffer
+system.cpu.rename.RENAME:tempSerializingInsts 623 # count of temporary serializing insts renamed
+system.cpu.timesIdled 1 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.workload.PROG:num_syscalls 8 # Number of system calls
---------- End Simulation Statistics ----------
diff --git a/tests/quick/02.insttest/ref/sparc/linux/o3-timing/stdout b/tests/quick/02.insttest/ref/sparc/linux/o3-timing/stdout
index 0bb67880e..0b6e54449 100644
--- a/tests/quick/02.insttest/ref/sparc/linux/o3-timing/stdout
+++ b/tests/quick/02.insttest/ref/sparc/linux/o3-timing/stdout
@@ -16,9 +16,9 @@ The Regents of The University of Michigan
All Rights Reserved
-M5 compiled Apr 22 2007 20:15:56
-M5 started Sun Apr 22 20:26:05 2007
-M5 executing on zamp.eecs.umich.edu
+M5 compiled May 15 2007 13:02:31
+M5 started Tue May 15 17:00:06 2007
+M5 executing on zizzer.eecs.umich.edu
command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/02.insttest/sparc/linux/o3-timing tests/run.py quick/02.insttest/sparc/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
-Exiting @ tick 13345500 because target called exit()
+Exiting @ tick 15931500 because target called exit()
diff --git a/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/config.ini b/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/config.ini
index 7e9c12db2..5493b952f 100644
--- a/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/config.ini
+++ b/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/config.ini
@@ -48,6 +48,7 @@ uid=100
[system.membus]
type=Bus
+block_size=64
bus_id=0
clock=1000
responder_set=false
diff --git a/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/config.out b/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/config.out
index 29915233b..c1a77ba0d 100644
--- a/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/config.out
+++ b/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/config.out
@@ -20,6 +20,7 @@ bus_id=0
clock=1000
width=64
responder_set=false
+block_size=64
[system.cpu.workload]
type=LiveProcess
diff --git a/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/m5stats.txt b/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/m5stats.txt
index 22ea72ebd..468b3f0a1 100644
--- a/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/m5stats.txt
+++ b/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/m5stats.txt
@@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
-host_inst_rate 430012 # Simulator instruction rate (inst/s)
-host_mem_usage 149064 # Number of bytes of host memory used
-host_seconds 0.03 # Real time elapsed on the host
-host_tick_rate 207711772 # Simulator tick rate (ticks/s)
+host_inst_rate 563720 # Simulator instruction rate (inst/s)
+host_mem_usage 149048 # Number of bytes of host memory used
+host_seconds 0.02 # Real time elapsed on the host
+host_tick_rate 276035132 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 11001 # Number of instructions simulated
sim_seconds 0.000005 # Number of seconds simulated
diff --git a/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/stdout b/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/stdout
index 66bfb4931..01c59e833 100644
--- a/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/stdout
+++ b/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/stdout
@@ -16,9 +16,9 @@ The Regents of The University of Michigan
All Rights Reserved
-M5 compiled Apr 22 2007 20:15:56
-M5 started Sun Apr 22 20:26:06 2007
-M5 executing on zamp.eecs.umich.edu
+M5 compiled May 15 2007 13:02:31
+M5 started Tue May 15 17:00:07 2007
+M5 executing on zizzer.eecs.umich.edu
command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/02.insttest/sparc/linux/simple-atomic tests/run.py quick/02.insttest/sparc/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second
Exiting @ tick 5500000 because target called exit()
diff --git a/tests/quick/02.insttest/ref/sparc/linux/simple-timing/config.ini b/tests/quick/02.insttest/ref/sparc/linux/simple-timing/config.ini
index 394f564a5..2e2789f26 100644
--- a/tests/quick/02.insttest/ref/sparc/linux/simple-timing/config.ini
+++ b/tests/quick/02.insttest/ref/sparc/linux/simple-timing/config.ini
@@ -36,8 +36,7 @@ block_size=64
compressed_bus=false
compression_latency=0
hash_delay=1
-hit_latency=1
-latency=1
+latency=1000
lifo=false
max_miss_count=0
mshrs=10
@@ -75,8 +74,7 @@ block_size=64
compressed_bus=false
compression_latency=0
hash_delay=1
-hit_latency=1
-latency=1
+latency=1000
lifo=false
max_miss_count=0
mshrs=10
@@ -114,8 +112,7 @@ block_size=64
compressed_bus=false
compression_latency=0
hash_delay=1
-hit_latency=1
-latency=1
+latency=10000
lifo=false
max_miss_count=0
mshrs=10
@@ -147,6 +144,7 @@ mem_side=system.membus.port[1]
[system.cpu.toL2Bus]
type=Bus
+block_size=64
bus_id=0
clock=1000
responder_set=false
@@ -171,6 +169,7 @@ uid=100
[system.membus]
type=Bus
+block_size=64
bus_id=0
clock=1000
responder_set=false
diff --git a/tests/quick/02.insttest/ref/sparc/linux/simple-timing/config.out b/tests/quick/02.insttest/ref/sparc/linux/simple-timing/config.out
index 9d999c4c3..df1a9c852 100644
--- a/tests/quick/02.insttest/ref/sparc/linux/simple-timing/config.out
+++ b/tests/quick/02.insttest/ref/sparc/linux/simple-timing/config.out
@@ -20,6 +20,7 @@ bus_id=0
clock=1000
width=64
responder_set=false
+block_size=64
[system.cpu.workload]
type=LiveProcess
@@ -61,13 +62,14 @@ bus_id=0
clock=1000
width=64
responder_set=false
+block_size=64
[system.cpu.icache]
type=BaseCache
size=131072
assoc=2
block_size=64
-latency=1
+latency=1000
mshrs=10
tgts_per_mshr=5
write_buffers=8
@@ -98,14 +100,13 @@ prefetch_policy=none
prefetch_cache_check_push=true
prefetch_use_cpu_id=true
prefetch_data_accesses_only=false
-hit_latency=1
[system.cpu.dcache]
type=BaseCache
size=262144
assoc=2
block_size=64
-latency=1
+latency=1000
mshrs=10
tgts_per_mshr=5
write_buffers=8
@@ -136,14 +137,13 @@ prefetch_policy=none
prefetch_cache_check_push=true
prefetch_use_cpu_id=true
prefetch_data_accesses_only=false
-hit_latency=1
[system.cpu.l2cache]
type=BaseCache
size=2097152
assoc=2
block_size=64
-latency=1
+latency=10000
mshrs=10
tgts_per_mshr=5
write_buffers=8
@@ -174,5 +174,4 @@ prefetch_policy=none
prefetch_cache_check_push=true
prefetch_use_cpu_id=true
prefetch_data_accesses_only=false
-hit_latency=1
diff --git a/tests/quick/02.insttest/ref/sparc/linux/simple-timing/m5stats.txt b/tests/quick/02.insttest/ref/sparc/linux/simple-timing/m5stats.txt
index aef9433e6..33502bf5c 100644
--- a/tests/quick/02.insttest/ref/sparc/linux/simple-timing/m5stats.txt
+++ b/tests/quick/02.insttest/ref/sparc/linux/simple-timing/m5stats.txt
@@ -1,33 +1,33 @@
---------- Begin Simulation Statistics ----------
-host_inst_rate 285170 # Simulator instruction rate (inst/s)
-host_mem_usage 154424 # Number of bytes of host memory used
-host_seconds 0.04 # Real time elapsed on the host
-host_tick_rate 211576923 # Simulator tick rate (ticks/s)
+host_inst_rate 346412 # Simulator instruction rate (inst/s)
+host_mem_usage 154396 # Number of bytes of host memory used
+host_seconds 0.03 # Real time elapsed on the host
+host_tick_rate 598818775 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 11001 # Number of instructions simulated
-sim_seconds 0.000008 # Number of seconds simulated
-sim_ticks 8251500 # Number of ticks simulated
+sim_seconds 0.000019 # Number of seconds simulated
+sim_ticks 19264000 # Number of ticks simulated
system.cpu.dcache.ReadReq_accesses 1462 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency 3712.962963 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2712.962963 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency 14000 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 13000 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_hits 1408 # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency 200500 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency 756000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_rate 0.036936 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_misses 54 # number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_miss_latency 146500 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency 702000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate 0.036936 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_misses 54 # number of ReadReq MSHR misses
system.cpu.dcache.SwapReq_accesses 6 # number of SwapReq accesses(hits+misses)
system.cpu.dcache.SwapReq_hits 6 # number of SwapReq hits
system.cpu.dcache.WriteReq_accesses 1292 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency 3676.136364 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 2676.136364 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency 14000 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 13000 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_hits 1204 # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency 323500 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency 1232000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_rate 0.068111 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_misses 88 # number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_miss_latency 235500 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency 1144000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_rate 0.068111 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_misses 88 # number of WriteReq MSHR misses
system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
@@ -39,29 +39,29 @@ system.cpu.dcache.blocked_cycles_no_mshrs 0 # n
system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.demand_accesses 2754 # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency 3690.140845 # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 2690.140845 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_miss_latency 14000 # average overall miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 13000 # average overall mshr miss latency
system.cpu.dcache.demand_hits 2612 # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency 524000 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency 1988000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_rate 0.051561 # miss rate for demand accesses
system.cpu.dcache.demand_misses 142 # number of demand (read+write) misses
system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency 382000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency 1846000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_rate 0.051561 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_misses 142 # number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.overall_accesses 2754 # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency 3690.140845 # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 2690.140845 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_miss_latency 14000 # average overall miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 13000 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.cpu.dcache.overall_hits 2612 # number of overall hits
-system.cpu.dcache.overall_miss_latency 524000 # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency 1988000 # number of overall miss cycles
system.cpu.dcache.overall_miss_rate 0.051561 # miss rate for overall accesses
system.cpu.dcache.overall_misses 142 # number of overall misses
system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency 382000 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency 1846000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_rate 0.051561 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_misses 142 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
@@ -78,18 +78,18 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0
system.cpu.dcache.replacements 0 # number of replacements
system.cpu.dcache.sampled_refs 142 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse 106.692969 # Cycle average of tags in use
+system.cpu.dcache.tagsinuse 103.809387 # Cycle average of tags in use
system.cpu.dcache.total_refs 2618 # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 0 # number of writebacks
system.cpu.icache.ReadReq_accesses 11002 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_avg_miss_latency 3743.816254 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 2743.816254 # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_miss_latency 13922.261484 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 12922.261484 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_hits 10719 # number of ReadReq hits
-system.cpu.icache.ReadReq_miss_latency 1059500 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency 3940000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_rate 0.025723 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_misses 283 # number of ReadReq misses
-system.cpu.icache.ReadReq_mshr_miss_latency 776500 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency 3657000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate 0.025723 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_misses 283 # number of ReadReq MSHR misses
system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
@@ -101,29 +101,29 @@ system.cpu.icache.blocked_cycles_no_mshrs 0 # n
system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.demand_accesses 11002 # number of demand (read+write) accesses
-system.cpu.icache.demand_avg_miss_latency 3743.816254 # average overall miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 2743.816254 # average overall mshr miss latency
+system.cpu.icache.demand_avg_miss_latency 13922.261484 # average overall miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 12922.261484 # average overall mshr miss latency
system.cpu.icache.demand_hits 10719 # number of demand (read+write) hits
-system.cpu.icache.demand_miss_latency 1059500 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency 3940000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_rate 0.025723 # miss rate for demand accesses
system.cpu.icache.demand_misses 283 # number of demand (read+write) misses
system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_miss_latency 776500 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency 3657000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_rate 0.025723 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_misses 283 # number of demand (read+write) MSHR misses
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.icache.overall_accesses 11002 # number of overall (read+write) accesses
-system.cpu.icache.overall_avg_miss_latency 3743.816254 # average overall miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 2743.816254 # average overall mshr miss latency
+system.cpu.icache.overall_avg_miss_latency 13922.261484 # average overall miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 12922.261484 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.cpu.icache.overall_hits 10719 # number of overall hits
-system.cpu.icache.overall_miss_latency 1059500 # number of overall miss cycles
+system.cpu.icache.overall_miss_latency 3940000 # number of overall miss cycles
system.cpu.icache.overall_miss_rate 0.025723 # miss rate for overall accesses
system.cpu.icache.overall_misses 283 # number of overall misses
system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.icache.overall_mshr_miss_latency 776500 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency 3657000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_rate 0.025723 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_misses 283 # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
@@ -140,18 +140,18 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0
system.cpu.icache.replacements 0 # number of replacements
system.cpu.icache.sampled_refs 283 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse 170.449932 # Cycle average of tags in use
+system.cpu.icache.tagsinuse 163.879834 # Cycle average of tags in use
system.cpu.icache.total_refs 10719 # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks
system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.l2cache.ReadReq_accesses 423 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_avg_miss_latency 2730.496454 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1729.496454 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_miss_latency 1155000 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_avg_miss_latency 13000 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 11000 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_miss_latency 5499000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_rate 1 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_misses 423 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency 731577 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency 4653000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate 1 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_misses 423 # number of ReadReq MSHR misses
system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
@@ -163,29 +163,29 @@ system.cpu.l2cache.blocked_cycles_no_mshrs 0 #
system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.demand_accesses 423 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_avg_miss_latency 2730.496454 # average overall miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency 1729.496454 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_miss_latency 13000 # average overall miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency 11000 # average overall mshr miss latency
system.cpu.l2cache.demand_hits 0 # number of demand (read+write) hits
-system.cpu.l2cache.demand_miss_latency 1155000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency 5499000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_rate 1 # miss rate for demand accesses
system.cpu.l2cache.demand_misses 423 # number of demand (read+write) misses
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_miss_latency 731577 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency 4653000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_rate 1 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_misses 423 # number of demand (read+write) MSHR misses
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.overall_accesses 423 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_avg_miss_latency 2730.496454 # average overall miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency 1729.496454 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_miss_latency 13000 # average overall miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency 11000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.cpu.l2cache.overall_hits 0 # number of overall hits
-system.cpu.l2cache.overall_miss_latency 1155000 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency 5499000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_rate 1 # miss rate for overall accesses
system.cpu.l2cache.overall_misses 423 # number of overall misses
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_miss_latency 731577 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency 4653000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_rate 1 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_misses 423 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
@@ -202,12 +202,12 @@ system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0
system.cpu.l2cache.replacements 0 # number of replacements
system.cpu.l2cache.sampled_refs 423 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse 276.385948 # Cycle average of tags in use
+system.cpu.l2cache.tagsinuse 266.922506 # Cycle average of tags in use
system.cpu.l2cache.total_refs 0 # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.writebacks 0 # number of writebacks
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
-system.cpu.numCycles 8251500 # number of cpu cycles simulated
+system.cpu.numCycles 19264000 # number of cpu cycles simulated
system.cpu.num_insts 11001 # Number of instructions executed
system.cpu.num_refs 2760 # Number of memory references
system.cpu.workload.PROG:num_syscalls 8 # Number of system calls
diff --git a/tests/quick/02.insttest/ref/sparc/linux/simple-timing/stdout b/tests/quick/02.insttest/ref/sparc/linux/simple-timing/stdout
index dd4d8d282..c2d31ed8f 100644
--- a/tests/quick/02.insttest/ref/sparc/linux/simple-timing/stdout
+++ b/tests/quick/02.insttest/ref/sparc/linux/simple-timing/stdout
@@ -16,9 +16,9 @@ The Regents of The University of Michigan
All Rights Reserved
-M5 compiled Apr 22 2007 20:15:56
-M5 started Sun Apr 22 20:26:07 2007
-M5 executing on zamp.eecs.umich.edu
+M5 compiled May 15 2007 13:02:31
+M5 started Tue May 15 17:00:07 2007
+M5 executing on zizzer.eecs.umich.edu
command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/02.insttest/sparc/linux/simple-timing tests/run.py quick/02.insttest/sparc/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
-Exiting @ tick 8251500 because target called exit()
+Exiting @ tick 19264000 because target called exit()