1 files changed, 16 insertions, 52 deletions
diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini
index 2d3b1a754..d3a9862e8 100644
--- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini
+++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini
@@ -35,7 +35,7 @@ side_b=system.membus.port[0]
 
 [system.cpu0]
 type=AtomicSimpleCPU
-children=dcache dtb icache itb
+children=dcache dtb icache itb tracer
 clock=500
 cpu_id=0
 defer_registration=false
@@ -55,18 +55,16 @@ profile=0
 progress_interval=0
 simulate_stalls=false
 system=system
+tracer=system.cpu0.tracer
 width=1
 dcache_port=system.cpu0.dcache.cpu_side
 icache_port=system.cpu0.icache.cpu_side
 
 [system.cpu0.dcache]
 type=BaseCache
-children=protocol
-adaptive_compression=false
+addr_range=0:18446744073709551615
 assoc=4
 block_size=64
-compressed_bus=false
-compression_latency=0
 hash_delay=1
 latency=1000
 lifo=false
@@ -84,12 +82,10 @@ prefetch_serial_squash=false
 prefetch_use_cpu_id=true
 prefetcher_size=100
 prioritizeRequests=false
-protocol=system.cpu0.dcache.protocol
 repl=Null
 size=32768
 split=false
 split_size=0
-store_compressed=false
 subblock_size=0
 tgts_per_mshr=8
 trace_addr=0
@@ -98,23 +94,15 @@ write_buffers=8
 cpu_side=system.cpu0.dcache_port
 mem_side=system.toL2Bus.port[2]
 
-[system.cpu0.dcache.protocol]
-type=CoherenceProtocol
-do_upgrades=true
-protocol=moesi
-
 [system.cpu0.dtb]
 type=AlphaDTB
 size=64
 
 [system.cpu0.icache]
 type=BaseCache
-children=protocol
-adaptive_compression=false
+addr_range=0:18446744073709551615
 assoc=1
 block_size=64
-compressed_bus=false
-compression_latency=0
 hash_delay=1
 latency=1000
 lifo=false
@@ -132,12 +120,10 @@ prefetch_serial_squash=false
 prefetch_use_cpu_id=true
 prefetcher_size=100
 prioritizeRequests=false
-protocol=system.cpu0.icache.protocol
 repl=Null
 size=32768
 split=false
 split_size=0
-store_compressed=false
 subblock_size=0
 tgts_per_mshr=8
 trace_addr=0
@@ -146,18 +132,16 @@ write_buffers=8
 cpu_side=system.cpu0.icache_port
 mem_side=system.toL2Bus.port[1]
 
-[system.cpu0.icache.protocol]
-type=CoherenceProtocol
-do_upgrades=true
-protocol=moesi
-
 [system.cpu0.itb]
 type=AlphaITB
 size=48
 
+[system.cpu0.tracer]
+type=ExeTracer
+
 [system.cpu1]
 type=AtomicSimpleCPU
-children=dcache dtb icache itb
+children=dcache dtb icache itb tracer
 clock=500
 cpu_id=1
 defer_registration=false
@@ -177,18 +161,16 @@ profile=0
 progress_interval=0
 simulate_stalls=false
 system=system
+tracer=system.cpu1.tracer
 width=1
 dcache_port=system.cpu1.dcache.cpu_side
 icache_port=system.cpu1.icache.cpu_side
 
 [system.cpu1.dcache]
 type=BaseCache
-children=protocol
-adaptive_compression=false
+addr_range=0:18446744073709551615
 assoc=4
 block_size=64
-compressed_bus=false
-compression_latency=0
 hash_delay=1
 latency=1000
 lifo=false
@@ -206,12 +188,10 @@ prefetch_serial_squash=false
 prefetch_use_cpu_id=true
 prefetcher_size=100
 prioritizeRequests=false
-protocol=system.cpu1.dcache.protocol
 repl=Null
 size=32768
 split=false
 split_size=0
-store_compressed=false
 subblock_size=0
 tgts_per_mshr=8
 trace_addr=0
@@ -220,23 +200,15 @@ write_buffers=8
 cpu_side=system.cpu1.dcache_port
 mem_side=system.toL2Bus.port[4]
 
-[system.cpu1.dcache.protocol]
-type=CoherenceProtocol
-do_upgrades=true
-protocol=moesi
-
 [system.cpu1.dtb]
 type=AlphaDTB
 size=64
 
 [system.cpu1.icache]
 type=BaseCache
-children=protocol
-adaptive_compression=false
+addr_range=0:18446744073709551615
 assoc=1
 block_size=64
-compressed_bus=false
-compression_latency=0
 hash_delay=1
 latency=1000
 lifo=false
@@ -254,12 +226,10 @@ prefetch_serial_squash=false
 prefetch_use_cpu_id=true
 prefetcher_size=100
 prioritizeRequests=false
-protocol=system.cpu1.icache.protocol
 repl=Null
 size=32768
 split=false
 split_size=0
-store_compressed=false
 subblock_size=0
 tgts_per_mshr=8
 trace_addr=0
@@ -268,15 +238,13 @@ write_buffers=8
 cpu_side=system.cpu1.icache_port
 mem_side=system.toL2Bus.port[3]
 
-[system.cpu1.icache.protocol]
-type=CoherenceProtocol
-do_upgrades=true
-protocol=moesi
-
 [system.cpu1.itb]
 type=AlphaITB
 size=48
 
+[system.cpu1.tracer]
+type=ExeTracer
+
 [system.disk0]
 type=IdeDisk
 children=image
@@ -331,11 +299,9 @@ port=system.bridge.side_a system.tsunami.cchip.pio system.tsunami.pchip.pio syst
 
 [system.l2c]
 type=BaseCache
-adaptive_compression=false
+addr_range=0:18446744073709551615
 assoc=8
 block_size=64
-compressed_bus=false
-compression_latency=0
 hash_delay=1
 latency=10000
 lifo=false
@@ -353,12 +319,10 @@ prefetch_serial_squash=false
 prefetch_use_cpu_id=true
 prefetcher_size=100
 prioritizeRequests=false
-protocol=Null
 repl=Null
 size=4194304
 split=false
 split_size=0
-store_compressed=false
 subblock_size=0
 tgts_per_mshr=16
 trace_addr=0
@@ -922,7 +886,7 @@ pio_addr=8804615847936
 pio_latency=1000
 platform=system.tsunami
 system=system
-time=2009 1 1 0 0 0 3 1
+time=Thu Jan  1 00:00:00 2009
 tsunami=system.tsunami
 year_is_bcd=false
 pio=system.iobus.port[23]