diff options
Diffstat (limited to 'tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/m5stats.txt')
| -rw-r--r-- | tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/m5stats.txt | 184 |
1 files changed, 72 insertions, 112 deletions
diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/m5stats.txt b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/m5stats.txt index 722437701..cc91e4c90 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/m5stats.txt +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/m5stats.txt @@ -1,35 +1,44 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1403977 # Simulator instruction rate (inst/s) -host_seconds 42.74 # Real time elapsed on the host -host_tick_rate 42777462102 # Simulator tick rate (ticks/s) +host_inst_rate 1294756 # Simulator instruction rate (inst/s) +host_mem_usage 255900 # Number of bytes of host memory used +host_seconds 46.35 # Real time elapsed on the host +host_tick_rate 39449403667 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 60007317 # Number of instructions simulated sim_seconds 1.828355 # Number of seconds simulated -sim_ticks 1828355486000 # Number of ticks simulated -system.cpu.dcache.ReadReq_accesses 9723333 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_hits 7984498 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_rate 0.178831 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 1738835 # number of ReadReq misses -system.cpu.dcache.WriteReq_accesses 6349447 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_hits 6045093 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_rate 0.047934 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 304354 # number of WriteReq misses +sim_ticks 1828355476000 # Number of ticks simulated +system.cpu.dcache.LoadLockedReq_accesses 200279 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_hits 183119 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_miss_rate 0.085680 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_misses 17160 # number of LoadLockedReq misses +system.cpu.dcache.ReadReq_accesses 9523054 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_hits 7801377 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_rate 0.180790 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 1721677 # number of ReadReq misses +system.cpu.dcache.StoreCondReq_accesses 199258 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_hits 169392 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_miss_rate 0.149886 # miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_misses 29866 # number of StoreCondReq misses +system.cpu.dcache.WriteReq_accesses 6150189 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_hits 5750772 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_rate 0.064944 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 399417 # number of WriteReq misses system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 6.866566 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 6.866558 # Average number of references to valid blocks. system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 16072780 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses 15673243 # number of demand (read+write) accesses system.cpu.dcache.demand_avg_miss_latency 0 # average overall miss latency system.cpu.dcache.demand_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency -system.cpu.dcache.demand_hits 14029591 # number of demand (read+write) hits +system.cpu.dcache.demand_hits 13552149 # number of demand (read+write) hits system.cpu.dcache.demand_miss_latency 0 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.127121 # miss rate for demand accesses -system.cpu.dcache.demand_misses 2043189 # number of demand (read+write) misses +system.cpu.dcache.demand_miss_rate 0.135332 # miss rate for demand accesses +system.cpu.dcache.demand_misses 2121094 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.cpu.dcache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses @@ -37,14 +46,14 @@ system.cpu.dcache.demand_mshr_misses 0 # nu system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.overall_accesses 16072780 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses 15673243 # number of overall (read+write) accesses system.cpu.dcache.overall_avg_miss_latency 0 # average overall miss latency system.cpu.dcache.overall_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 14029591 # number of overall hits +system.cpu.dcache.overall_hits 13552149 # number of overall hits system.cpu.dcache.overall_miss_latency 0 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.127121 # miss rate for overall accesses -system.cpu.dcache.overall_misses 2043189 # number of overall misses +system.cpu.dcache.overall_miss_rate 0.135332 # miss rate for overall accesses +system.cpu.dcache.overall_misses 2121094 # number of overall misses system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits system.cpu.dcache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses @@ -60,39 +69,13 @@ system.cpu.dcache.prefetcher.num_hwpf_issued 0 system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.dcache.protocol.hwpf_invalid 0 # hard prefetch misses to invalid blocks -system.cpu.dcache.protocol.read_invalid 1738835 # read misses to invalid blocks -system.cpu.dcache.protocol.snoop_inv_exclusive 0 # Invalidate snoops on exclusive blocks -system.cpu.dcache.protocol.snoop_inv_invalid 0 # Invalidate snoops on invalid blocks -system.cpu.dcache.protocol.snoop_inv_modified 1 # Invalidate snoops on modified blocks -system.cpu.dcache.protocol.snoop_inv_owned 0 # Invalidate snoops on owned blocks -system.cpu.dcache.protocol.snoop_inv_shared 0 # Invalidate snoops on shared blocks -system.cpu.dcache.protocol.snoop_read_exclusive 10 # read snoops on exclusive blocks -system.cpu.dcache.protocol.snoop_read_modified 15 # read snoops on modified blocks -system.cpu.dcache.protocol.snoop_read_owned 2 # read snoops on owned blocks -system.cpu.dcache.protocol.snoop_read_shared 124 # read snoops on shared blocks -system.cpu.dcache.protocol.snoop_readex_exclusive 0 # readEx snoops on exclusive blocks -system.cpu.dcache.protocol.snoop_readex_modified 0 # readEx snoops on modified blocks -system.cpu.dcache.protocol.snoop_readex_owned 0 # readEx snoops on owned blocks -system.cpu.dcache.protocol.snoop_readex_shared 0 # readEx snoops on shared blocks -system.cpu.dcache.protocol.snoop_upgrade_owned 0 # upgrade snoops on owned blocks -system.cpu.dcache.protocol.snoop_upgrade_shared 0 # upgradee snoops on shared blocks -system.cpu.dcache.protocol.snoop_writeinv_exclusive 0 # WriteInvalidate snoops on exclusive blocks -system.cpu.dcache.protocol.snoop_writeinv_invalid 0 # WriteInvalidate snoops on invalid blocks -system.cpu.dcache.protocol.snoop_writeinv_modified 0 # WriteInvalidate snoops on modified blocks -system.cpu.dcache.protocol.snoop_writeinv_owned 0 # WriteInvalidate snoops on owned blocks -system.cpu.dcache.protocol.snoop_writeinv_shared 0 # WriteInvalidate snoops on shared blocks -system.cpu.dcache.protocol.swpf_invalid 0 # soft prefetch misses to invalid blocks -system.cpu.dcache.protocol.write_invalid 304342 # write misses to invalid blocks -system.cpu.dcache.protocol.write_owned 8 # write misses to owned blocks -system.cpu.dcache.protocol.write_shared 4 # write misses to shared blocks -system.cpu.dcache.replacements 2042664 # number of replacements -system.cpu.dcache.sampled_refs 2043176 # Sample count of references to valid blocks. +system.cpu.dcache.replacements 2042666 # number of replacements +system.cpu.dcache.sampled_refs 2043178 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.dcache.tagsinuse 511.997801 # Cycle average of tags in use -system.cpu.dcache.total_refs 14029603 # Total number of references to valid blocks. +system.cpu.dcache.total_refs 14029601 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 10840000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 0 # number of writebacks +system.cpu.dcache.writebacks 428885 # number of writebacks system.cpu.dtb.accesses 1020787 # DTB accesses system.cpu.dtb.acv 367 # DTB access violations system.cpu.dtb.hits 16053818 # DTB hits @@ -106,12 +89,12 @@ system.cpu.dtb.write_acv 157 # DT system.cpu.dtb.write_hits 6349968 # DTB write hits system.cpu.dtb.write_misses 1142 # DTB write misses system.cpu.icache.ReadReq_accesses 60007317 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_hits 59087263 # number of ReadReq hits +system.cpu.icache.ReadReq_hits 59087260 # number of ReadReq hits system.cpu.icache.ReadReq_miss_rate 0.015332 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 920054 # number of ReadReq misses +system.cpu.icache.ReadReq_misses 920057 # number of ReadReq misses system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.icache.avg_refs 64.229545 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 64.229332 # Average number of references to valid blocks. system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked @@ -120,10 +103,10 @@ system.cpu.icache.cache_copies 0 # nu system.cpu.icache.demand_accesses 60007317 # number of demand (read+write) accesses system.cpu.icache.demand_avg_miss_latency 0 # average overall miss latency system.cpu.icache.demand_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency -system.cpu.icache.demand_hits 59087263 # number of demand (read+write) hits +system.cpu.icache.demand_hits 59087260 # number of demand (read+write) hits system.cpu.icache.demand_miss_latency 0 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_rate 0.015332 # miss rate for demand accesses -system.cpu.icache.demand_misses 920054 # number of demand (read+write) misses +system.cpu.icache.demand_misses 920057 # number of demand (read+write) misses system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.cpu.icache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses @@ -135,10 +118,10 @@ system.cpu.icache.overall_accesses 60007317 # nu system.cpu.icache.overall_avg_miss_latency 0 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 59087263 # number of overall hits +system.cpu.icache.overall_hits 59087260 # number of overall hits system.cpu.icache.overall_miss_latency 0 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.015332 # miss rate for overall accesses -system.cpu.icache.overall_misses 920054 # number of overall misses +system.cpu.icache.overall_misses 920057 # number of overall misses system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits system.cpu.icache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses @@ -154,37 +137,11 @@ system.cpu.icache.prefetcher.num_hwpf_issued 0 system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.icache.protocol.hwpf_invalid 0 # hard prefetch misses to invalid blocks -system.cpu.icache.protocol.read_invalid 920054 # read misses to invalid blocks -system.cpu.icache.protocol.snoop_inv_exclusive 0 # Invalidate snoops on exclusive blocks -system.cpu.icache.protocol.snoop_inv_invalid 0 # Invalidate snoops on invalid blocks -system.cpu.icache.protocol.snoop_inv_modified 0 # Invalidate snoops on modified blocks -system.cpu.icache.protocol.snoop_inv_owned 0 # Invalidate snoops on owned blocks -system.cpu.icache.protocol.snoop_inv_shared 0 # Invalidate snoops on shared blocks -system.cpu.icache.protocol.snoop_read_exclusive 643 # read snoops on exclusive blocks -system.cpu.icache.protocol.snoop_read_modified 0 # read snoops on modified blocks -system.cpu.icache.protocol.snoop_read_owned 0 # read snoops on owned blocks -system.cpu.icache.protocol.snoop_read_shared 1039 # read snoops on shared blocks -system.cpu.icache.protocol.snoop_readex_exclusive 105 # readEx snoops on exclusive blocks -system.cpu.icache.protocol.snoop_readex_modified 0 # readEx snoops on modified blocks -system.cpu.icache.protocol.snoop_readex_owned 0 # readEx snoops on owned blocks -system.cpu.icache.protocol.snoop_readex_shared 1 # readEx snoops on shared blocks -system.cpu.icache.protocol.snoop_upgrade_owned 0 # upgrade snoops on owned blocks -system.cpu.icache.protocol.snoop_upgrade_shared 9 # upgradee snoops on shared blocks -system.cpu.icache.protocol.snoop_writeinv_exclusive 0 # WriteInvalidate snoops on exclusive blocks -system.cpu.icache.protocol.snoop_writeinv_invalid 0 # WriteInvalidate snoops on invalid blocks -system.cpu.icache.protocol.snoop_writeinv_modified 0 # WriteInvalidate snoops on modified blocks -system.cpu.icache.protocol.snoop_writeinv_owned 0 # WriteInvalidate snoops on owned blocks -system.cpu.icache.protocol.snoop_writeinv_shared 0 # WriteInvalidate snoops on shared blocks -system.cpu.icache.protocol.swpf_invalid 0 # soft prefetch misses to invalid blocks -system.cpu.icache.protocol.write_invalid 0 # write misses to invalid blocks -system.cpu.icache.protocol.write_owned 0 # write misses to owned blocks -system.cpu.icache.protocol.write_shared 0 # write misses to shared blocks -system.cpu.icache.replacements 919427 # number of replacements -system.cpu.icache.sampled_refs 919939 # Sample count of references to valid blocks. +system.cpu.icache.replacements 919430 # number of replacements +system.cpu.icache.sampled_refs 919942 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.icache.tagsinuse 511.214820 # Cycle average of tags in use -system.cpu.icache.total_refs 59087263 # Total number of references to valid blocks. +system.cpu.icache.total_refs 59087260 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 9686972500 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks system.cpu.idle_fraction 0.983588 # Percentage of idle cycles @@ -222,8 +179,8 @@ system.cpu.kern.ipl_good_0 73448 49.29% 49.29% # nu system.cpu.kern.ipl_good_21 243 0.16% 49.46% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good_22 1865 1.25% 50.71% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good_31 73448 49.29% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_ticks 1828355278500 # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks_0 1811087547500 99.06% 99.06% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks 1828355268500 # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks_0 1811087537500 99.06% 99.06% # number of cycles we spent at this ipl system.cpu.kern.ipl_ticks_21 20110000 0.00% 99.06% # number of cycles we spent at this ipl system.cpu.kern.ipl_ticks_22 80195000 0.00% 99.06% # number of cycles we spent at this ipl system.cpu.kern.ipl_ticks_31 17167426000 0.94% 100.00% # number of cycles we spent at this ipl @@ -243,7 +200,7 @@ system.cpu.kern.mode_switch_good_user 1 # fr system.cpu.kern.mode_switch_good_idle 0.081545 # fraction of useful protection mode switches system.cpu.kern.mode_ticks_kernel 26834026500 1.47% 1.47% # number of ticks spent at the given mode system.cpu.kern.mode_ticks_user 1465069000 0.08% 1.55% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks_idle 1800056182000 98.45% 100.00% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks_idle 1800056172000 98.45% 100.00% # number of ticks spent at the given mode system.cpu.kern.swap_context 4178 # number of times the context was actually changed system.cpu.kern.syscall 326 # number of syscalls executed system.cpu.kern.syscall_2 8 2.45% 2.45% # number of syscalls executed @@ -293,30 +250,33 @@ system.disk2.dma_write_bytes 8192 # Nu system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. system.disk2.dma_write_txs 1 # Number of DMA write transactions. system.l2c.ReadExReq_accesses 304342 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_hits 187346 # number of ReadExReq hits -system.l2c.ReadExReq_miss_rate 0.384423 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_misses 116996 # number of ReadExReq misses -system.l2c.ReadReq_accesses 2658872 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_hits 1717828 # number of ReadReq hits -system.l2c.ReadReq_miss_rate 0.353926 # miss rate for ReadReq accesses -system.l2c.ReadReq_misses 941044 # number of ReadReq misses +system.l2c.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_misses 304342 # number of ReadExReq misses +system.l2c.ReadReq_accesses 2658877 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_hits 1558398 # number of ReadReq hits +system.l2c.ReadReq_miss_rate 0.413889 # miss rate for ReadReq accesses +system.l2c.ReadReq_misses 1100479 # number of ReadReq misses +system.l2c.UpgradeReq_accesses 124941 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_misses 124941 # number of UpgradeReq misses system.l2c.Writeback_accesses 428885 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_hits 428885 # number of Writeback hits +system.l2c.Writeback_miss_rate 1 # miss rate for Writeback accesses +system.l2c.Writeback_misses 428885 # number of Writeback misses system.l2c.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.l2c.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.l2c.avg_refs 2.205901 # Average number of references to valid blocks. +system.l2c.avg_refs 1.644070 # Average number of references to valid blocks. system.l2c.blocked_no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_no_targets 0 # number of cycles access was blocked system.l2c.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles_no_targets 0 # number of cycles access was blocked system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.demand_accesses 2658872 # number of demand (read+write) accesses +system.l2c.demand_accesses 2963219 # number of demand (read+write) accesses system.l2c.demand_avg_miss_latency 0 # average overall miss latency system.l2c.demand_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency -system.l2c.demand_hits 1717828 # number of demand (read+write) hits +system.l2c.demand_hits 1558398 # number of demand (read+write) hits system.l2c.demand_miss_latency 0 # number of demand (read+write) miss cycles -system.l2c.demand_miss_rate 0.353926 # miss rate for demand accesses -system.l2c.demand_misses 941044 # number of demand (read+write) misses +system.l2c.demand_miss_rate 0.474086 # miss rate for demand accesses +system.l2c.demand_misses 1404821 # number of demand (read+write) misses system.l2c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.l2c.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles system.l2c.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses @@ -324,14 +284,14 @@ system.l2c.demand_mshr_misses 0 # nu system.l2c.fast_writes 0 # number of fast writes performed system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.overall_accesses 3087757 # number of overall (read+write) accesses +system.l2c.overall_accesses 2963219 # number of overall (read+write) accesses system.l2c.overall_avg_miss_latency 0 # average overall miss latency system.l2c.overall_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency system.l2c.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.l2c.overall_hits 2146713 # number of overall hits +system.l2c.overall_hits 1558398 # number of overall hits system.l2c.overall_miss_latency 0 # number of overall miss cycles -system.l2c.overall_miss_rate 0.304766 # miss rate for overall accesses -system.l2c.overall_misses 941044 # number of overall misses +system.l2c.overall_miss_rate 0.474086 # miss rate for overall accesses +system.l2c.overall_misses 1404821 # number of overall misses system.l2c.overall_mshr_hits 0 # number of overall MSHR hits system.l2c.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles system.l2c.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses @@ -347,12 +307,12 @@ system.l2c.prefetcher.num_hwpf_issued 0 # nu system.l2c.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.l2c.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.l2c.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.l2c.replacements 992432 # number of replacements -system.l2c.sampled_refs 1057820 # Sample count of references to valid blocks. +system.l2c.replacements 947436 # number of replacements +system.l2c.sampled_refs 965232 # Sample count of references to valid blocks. system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.l2c.tagsinuse 65517.661064 # Cycle average of tags in use -system.l2c.total_refs 2333446 # Total number of references to valid blocks. -system.l2c.warmup_cycle 614754000 # Cycle when the warmup percentage was hit. +system.l2c.tagsinuse 15309.548937 # Cycle average of tags in use +system.l2c.total_refs 1586909 # Total number of references to valid blocks. +system.l2c.warmup_cycle 789998500 # Cycle when the warmup percentage was hit. system.l2c.writebacks 0 # number of writebacks system.tsunami.ethernet.coalescedRxDesc <err: div-0> # average number of RxDesc's coalesced into each post system.tsunami.ethernet.coalescedRxIdle <err: div-0> # average number of RxIdle's coalesced into each post |