diff options
Diffstat (limited to 'tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic')
3 files changed, 26 insertions, 19 deletions
diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini index 5eca545be..372087060 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini @@ -8,11 +8,11 @@ type=LinuxAlphaSystem children=bridge cpu disk0 disk2 intrctrl iobus iocache l2c membus physmem simple_disk terminal toL2Bus tsunami boot_cpu_frequency=500 boot_osflags=root=/dev/hda1 console=ttyS0 -console=/proj/aatl_perfmod_arch/m5_system_files/m5_system_2.0b3/binaries/console +console=/home/stever/m5/m5_system_2.0b3/binaries/console init_param=0 -kernel=/proj/aatl_perfmod_arch/m5_system_files/m5_system_2.0b3/binaries/vmlinux +kernel=/home/stever/m5/m5_system_2.0b3/binaries/vmlinux mem_mode=atomic -pal=/proj/aatl_perfmod_arch/m5_system_files/m5_system_2.0b3/binaries/ts_osfpal +pal=/home/stever/m5/m5_system_2.0b3/binaries/ts_osfpal physmem=system.physmem readfile=tests/halt.sh symbolfile= @@ -157,7 +157,7 @@ table_size=65536 [system.disk0.image.child] type=RawDiskImage -image_file=/proj/aatl_perfmod_arch/m5_system_files/m5_system_2.0b3/disks/linux-latest.img +image_file=/home/stever/m5/m5_system_2.0b3/disks/linux-latest.img read_only=true [system.disk2] @@ -177,7 +177,7 @@ table_size=65536 [system.disk2.image.child] type=RawDiskImage -image_file=/proj/aatl_perfmod_arch/m5_system_files/m5_system_2.0b3/disks/linux-bigswap2.img +image_file=/home/stever/m5/m5_system_2.0b3/disks/linux-bigswap2.img read_only=true [system.intrctrl] @@ -303,7 +303,7 @@ system=system [system.simple_disk.disk] type=RawDiskImage -image_file=/proj/aatl_perfmod_arch/m5_system_files/m5_system_2.0b3/disks/linux-latest.img +image_file=/home/stever/m5/m5_system_2.0b3/disks/linux-latest.img read_only=true [system.terminal] diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/simout b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/simout index a264b4253..af78d2d19 100755 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/simout +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/simout @@ -1,3 +1,5 @@ +Redirecting stdout to build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic/simout +Redirecting stderr to build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic/simerr M5 Simulator System Copyright (c) 2001-2008 @@ -5,12 +7,12 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 24 2010 23:13:04 -M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip -M5 started Feb 24 2010 23:13:11 -M5 executing on SC2B0619 +M5 compiled Jun 16 2010 10:39:13 +M5 revision b85fd4ba5453 7466 default qtip tip llsc-fix-stats +M5 started Jun 16 2010 10:39:16 +M5 executing on phenom command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic -re tests/run.py build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic Global frequency set at 1000000000000 ticks per second -info: kernel located at: /proj/aatl_perfmod_arch/m5_system_files/m5_system_2.0b3/binaries/vmlinux +info: kernel located at: /home/stever/m5/m5_system_2.0b3/binaries/vmlinux info: Entering event queue @ 0. Starting simulation... Exiting @ tick 1829332258000 because m5_exit instruction encountered diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt index 8a27a93dd..7a54ae203 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 2156504 # Simulator instruction rate (inst/s) -host_mem_usage 277176 # Number of bytes of host memory used -host_seconds 27.84 # Real time elapsed on the host -host_tick_rate 65706739181 # Simulator tick rate (ticks/s) +host_inst_rate 3274924 # Simulator instruction rate (inst/s) +host_mem_usage 275440 # Number of bytes of host memory used +host_seconds 18.33 # Real time elapsed on the host +host_tick_rate 99783911231 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 60038305 # Number of instructions simulated sim_seconds 1.829332 # Number of seconds simulated @@ -405,11 +405,16 @@ system.l2c.ReadReq_hits::total 1696652 # nu system.l2c.ReadReq_miss_rate::0 0.361938 # miss rate for ReadReq accesses system.l2c.ReadReq_misses::0 962419 # number of ReadReq misses system.l2c.ReadReq_misses::total 962419 # number of ReadReq misses -system.l2c.UpgradeReq_accesses::0 124945 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 124945 # number of UpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::0 29867 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::total 29867 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_miss_rate::0 1 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_misses::0 29867 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::total 29867 # number of SCUpgradeReq misses +system.l2c.UpgradeReq_accesses::0 95078 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 95078 # number of UpgradeReq accesses(hits+misses) system.l2c.UpgradeReq_miss_rate::0 1 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_misses::0 124945 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 124945 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::0 95078 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 95078 # number of UpgradeReq misses system.l2c.Writeback_accesses::0 428893 # number of Writeback accesses(hits+misses) system.l2c.Writeback_accesses::total 428893 # number of Writeback accesses(hits+misses) system.l2c.Writeback_hits::0 428893 # number of Writeback hits |