diff options
Diffstat (limited to 'tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual')
4 files changed, 65 insertions, 20 deletions
diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini index ef977d929..41a7379e1 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini @@ -1,24 +1,33 @@ [root] type=Root children=system -dummy=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 [system] type=LinuxAlphaSystem children=bridge cpu0 cpu1 disk0 disk2 intrctrl iobus iocache l2c membus physmem simple_disk terminal toL2Bus tsunami boot_cpu_frequency=500 boot_osflags=root=/dev/hda1 console=ttyS0 -console=/chips/pd/randd/dist/binaries/console +console=/dist/m5/system/binaries/console init_param=0 -kernel=/chips/pd/randd/dist/binaries/vmlinux +kernel=/dist/m5/system/binaries/vmlinux load_addr_mask=1099511627775 mem_mode=timing -pal=/chips/pd/randd/dist/binaries/ts_osfpal +pal=/dist/m5/system/binaries/ts_osfpal physmem=system.physmem readfile=tests/halt.sh symbolfile= system_rev=1024 system_type=34 +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 [system.bridge] type=Bridge @@ -259,7 +268,7 @@ table_size=65536 [system.disk0.image.child] type=RawDiskImage -image_file=/chips/pd/randd/dist/disks/linux-latest.img +image_file=/dist/m5/system/disks/linux-latest.img read_only=true [system.disk2] @@ -279,7 +288,7 @@ table_size=65536 [system.disk2.image.child] type=RawDiskImage -image_file=/chips/pd/randd/dist/disks/linux-bigswap2.img +image_file=/dist/m5/system/disks/linux-bigswap2.img read_only=true [system.intrctrl] @@ -405,7 +414,7 @@ system=system [system.simple_disk.disk] type=RawDiskImage -image_file=/chips/pd/randd/dist/disks/linux-latest.img +image_file=/dist/m5/system/disks/linux-latest.img read_only=true [system.terminal] @@ -876,7 +885,9 @@ SubsystemID=0 SubsystemVendorID=0 VendorID=32902 config_latency=20000 +ctrl_offset=0 disks=system.disk0 system.disk2 +io_shift=0 max_backoff_delay=10000000 min_backoff_delay=4000 pci_bus=0 diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simerr b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simerr index 83c71fc5c..0372a3b05 100755 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simerr +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simerr @@ -2,4 +2,8 @@ warn: Sockets disabled, not accepting terminal connections For more information see: http://www.m5sim.org/warn/8742226b warn: Sockets disabled, not accepting gdb connections For more information see: http://www.m5sim.org/warn/d946bea6 +warn: Prefetch instrutions is Alpha do not do anything +For more information see: http://www.m5sim.org/warn/3e0eccba +warn: Prefetch instrutions is Alpha do not do anything +For more information see: http://www.m5sim.org/warn/3e0eccba hack: be nice to actually delete the event here diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simout b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simout index 8585e8d27..8f8e92a25 100755 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simout +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simout @@ -1,5 +1,3 @@ -Redirecting stdout to build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-timing-dual/simout -Redirecting stderr to build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-timing-dual/simerr M5 Simulator System Copyright (c) 2001-2008 @@ -7,13 +5,13 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Nov 2 2010 23:00:12 -M5 revision 0af3760102ec+ 7713+ default qtip ext/alpha_prefetch.patch tip -M5 started Nov 2 2010 23:10:42 -M5 executing on aus-bc2-b15 +M5 compiled Feb 7 2011 01:46:17 +M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip +M5 started Feb 7 2011 01:46:32 +M5 executing on burrito command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-timing-dual -re tests/run.py build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-timing-dual Global frequency set at 1000000000000 ticks per second -info: kernel located at: /chips/pd/randd/dist/binaries/vmlinux +info: kernel located at: /dist/m5/system/binaries/vmlinux info: Entering event queue @ 0. Starting simulation... info: Launching CPU 1 @ 562628000 Exiting @ tick 1958647095000 because m5_exit instruction encountered diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt index 0517b4d72..6e0648c43 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1781653 # Simulator instruction rate (inst/s) -host_mem_usage 323564 # Number of bytes of host memory used -host_seconds 33.32 # Real time elapsed on the host -host_tick_rate 58791386546 # Simulator tick rate (ticks/s) +host_inst_rate 901052 # Simulator instruction rate (inst/s) +host_mem_usage 309020 # Number of bytes of host memory used +host_seconds 65.87 # Real time elapsed on the host +host_tick_rate 29733229075 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 59355643 # Number of instructions simulated sim_seconds 1.958647 # Number of seconds simulated @@ -360,8 +360,24 @@ system.cpu0.kern.syscall::147 2 0.90% 100.00% # nu system.cpu0.kern.syscall::total 222 # number of syscalls executed system.cpu0.not_idle_fraction 0.060263 # Percentage of non-idle cycles system.cpu0.numCycles 3916023774 # number of cpu cycles simulated +system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu0.num_busy_cycles 235989726.444158 # Number of busy cycles +system.cpu0.num_conditional_control_insts 6237040 # number of instructions that are conditional controls +system.cpu0.num_fp_alu_accesses 293967 # Number of float alu accesses +system.cpu0.num_fp_insts 293967 # number of float instructions +system.cpu0.num_fp_register_reads 143353 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 146452 # number of times the floating registers were written +system.cpu0.num_func_calls 1426863 # number of times a function call or return occured +system.cpu0.num_idle_cycles 3680034047.555842 # Number of idle cycles system.cpu0.num_insts 54072652 # Number of instructions executed -system.cpu0.num_refs 14724357 # Number of memory references +system.cpu0.num_int_alu_accesses 50043234 # Number of integer alu accesses +system.cpu0.num_int_insts 50043234 # number of integer instructions +system.cpu0.num_int_register_reads 68528072 # number of times the integer registers were read +system.cpu0.num_int_register_writes 37080372 # number of times the integer registers were written +system.cpu0.num_load_insts 8664914 # Number of load instructions +system.cpu0.num_mem_refs 14724357 # number of memory refs +system.cpu0.num_store_insts 6059443 # Number of store instructions system.cpu1.dcache.LoadLockedReq_accesses::0 12766 # number of LoadLockedReq accesses(hits+misses) system.cpu1.dcache.LoadLockedReq_accesses::total 12766 # number of LoadLockedReq accesses(hits+misses) system.cpu1.dcache.LoadLockedReq_avg_miss_latency::0 13318.737271 # average LoadLockedReq miss latency @@ -691,8 +707,24 @@ system.cpu1.kern.syscall::132 3 2.88% 100.00% # nu system.cpu1.kern.syscall::total 104 # number of syscalls executed system.cpu1.not_idle_fraction 0.004865 # Percentage of non-idle cycles system.cpu1.numCycles 3917294190 # number of cpu cycles simulated +system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu1.num_busy_cycles 19057169.001990 # Number of busy cycles +system.cpu1.num_conditional_control_insts 510974 # number of instructions that are conditional controls +system.cpu1.num_fp_alu_accesses 34031 # Number of float alu accesses +system.cpu1.num_fp_insts 34031 # number of float instructions +system.cpu1.num_fp_register_reads 22062 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 21862 # number of times the floating registers were written +system.cpu1.num_func_calls 158031 # number of times a function call or return occured +system.cpu1.num_idle_cycles 3898237020.998010 # Number of idle cycles system.cpu1.num_insts 5282991 # Number of instructions executed -system.cpu1.num_refs 1710778 # Number of memory references +system.cpu1.num_int_alu_accesses 4948310 # Number of integer alu accesses +system.cpu1.num_int_insts 4948310 # number of integer instructions +system.cpu1.num_int_register_reads 6886066 # number of times the integer registers were read +system.cpu1.num_int_register_writes 3732878 # number of times the integer registers were written +system.cpu1.num_load_insts 1056124 # Number of load instructions +system.cpu1.num_mem_refs 1710778 # number of memory refs +system.cpu1.num_store_insts 654654 # Number of store instructions system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). |