diff options
Diffstat (limited to 'tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt')
| -rw-r--r-- | tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt | 580 |
1 files changed, 291 insertions, 289 deletions
diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt index f93fce19a..3b140faa7 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt @@ -1,157 +1,157 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1511189 # Simulator instruction rate (inst/s) -host_mem_usage 272256 # Number of bytes of host memory used -host_seconds 37.19 # Real time elapsed on the host -host_tick_rate 51895589412 # Simulator tick rate (ticks/s) +host_inst_rate 1563603 # Simulator instruction rate (inst/s) +host_mem_usage 288804 # Number of bytes of host memory used +host_seconds 35.93 # Real time elapsed on the host +host_tick_rate 53658174093 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 56205703 # Number of instructions simulated -sim_seconds 1.930165 # Number of seconds simulated -sim_ticks 1930164593000 # Number of ticks simulated -system.cpu.dcache.LoadLockedReq_accesses::0 200404 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 200404 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_avg_miss_latency::0 14361.546017 # average LoadLockedReq miss latency +sim_insts 56180319 # Number of instructions simulated +sim_seconds 1.927952 # Number of seconds simulated +sim_ticks 1927951878000 # Number of ticks simulated +system.cpu.dcache.LoadLockedReq_accesses::0 200373 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 200373 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_avg_miss_latency::0 14335.708080 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::1 inf # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::total inf # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency 11361.546017 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_hits::0 183095 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 183095 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_miss_latency 248584000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_rate::0 0.086371 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_misses::0 17309 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 17309 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_mshr_miss_latency 196657000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::0 0.086371 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency 11335.708080 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_hits::0 183108 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 183108 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_miss_latency 247506000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_rate::0 0.086164 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_misses::0 17265 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 17265 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_mshr_miss_latency 195711000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::0 0.086164 # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_mshr_miss_rate::1 inf # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total inf # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_misses 17309 # number of LoadLockedReq MSHR misses -system.cpu.dcache.ReadReq_accesses::0 8888653 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 8888653 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency::0 25452.354477 # average ReadReq miss latency +system.cpu.dcache.LoadLockedReq_mshr_misses 17265 # number of LoadLockedReq MSHR misses +system.cpu.dcache.ReadReq_accesses::0 8883579 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 8883579 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency::0 25418.459915 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 22452.311493 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 22418.417380 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.cpu.dcache.ReadReq_hits::0 7818479 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 7818479 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 27238448000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate::0 0.120398 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses::0 1070174 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1070174 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_miss_latency 24027880000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::0 0.120398 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_hits::0 7813872 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 7813872 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 27190304500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate::0 0.120414 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses::0 1069707 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1069707 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_miss_latency 23981138000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::0 0.120414 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 1070174 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses 1069707 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_uncacheable_latency 862763000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.StoreCondReq_accesses::0 199383 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 199383 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_avg_miss_latency::0 56004.366085 # average StoreCondReq miss latency +system.cpu.dcache.StoreCondReq_accesses::0 199352 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 199352 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_avg_miss_latency::0 56004.626718 # average StoreCondReq miss latency system.cpu.dcache.StoreCondReq_avg_miss_latency::1 inf # average StoreCondReq miss latency system.cpu.dcache.StoreCondReq_avg_miss_latency::total inf # average StoreCondReq miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency 53004.366085 # average StoreCondReq mshr miss latency -system.cpu.dcache.StoreCondReq_hits::0 169379 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 169379 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_miss_latency 1680355000 # number of StoreCondReq miss cycles -system.cpu.dcache.StoreCondReq_miss_rate::0 0.150484 # miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_misses::0 30004 # number of StoreCondReq misses -system.cpu.dcache.StoreCondReq_misses::total 30004 # number of StoreCondReq misses -system.cpu.dcache.StoreCondReq_mshr_miss_latency 1590343000 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_rate::0 0.150484 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency 53004.626718 # average StoreCondReq mshr miss latency +system.cpu.dcache.StoreCondReq_hits::0 177090 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 177090 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_miss_latency 1246775000 # number of StoreCondReq miss cycles +system.cpu.dcache.StoreCondReq_miss_rate::0 0.111672 # miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_misses::0 22262 # number of StoreCondReq misses +system.cpu.dcache.StoreCondReq_misses::total 22262 # number of StoreCondReq misses +system.cpu.dcache.StoreCondReq_mshr_miss_latency 1179989000 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_rate::0 0.111672 # mshr miss rate for StoreCondReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::1 inf # mshr miss rate for StoreCondReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::total inf # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_mshr_misses 30004 # number of StoreCondReq MSHR misses -system.cpu.dcache.WriteReq_accesses::0 6160337 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 6160337 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency::0 56004.022652 # average WriteReq miss latency +system.cpu.dcache.StoreCondReq_mshr_misses 22262 # number of StoreCondReq MSHR misses +system.cpu.dcache.WriteReq_accesses::0 6156793 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 6156793 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_avg_miss_latency::0 55757.232436 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::1 inf # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53004.022652 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 52757.232436 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency -system.cpu.dcache.WriteReq_hits::0 5759482 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 5759482 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 22449492500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate::0 0.065070 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses::0 400855 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 400855 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_miss_latency 21246927500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate::0 0.065070 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_hits::0 5786171 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 5786171 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 20664857000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate::0 0.060197 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses::0 370622 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 370622 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_miss_latency 19552991000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate::0 0.060197 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::1 inf # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 400855 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_uncacheable_latency 1201243500 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_misses 370622 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_uncacheable_latency 1200971000 # number of WriteReq MSHR uncacheable cycles system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 10.097318 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 10.097149 # Average number of references to valid blocks. system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses::0 15048990 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::0 15040372 # number of demand (read+write) accesses system.cpu.dcache.demand_accesses::1 0 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 15048990 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency::0 33777.675695 # average overall miss latency +system.cpu.dcache.demand_accesses::total 15040372 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency::0 33225.160016 # average overall miss latency system.cpu.dcache.demand_avg_miss_latency::1 inf # average overall miss latency system.cpu.dcache.demand_avg_miss_latency::total inf # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 30777.644424 # average overall mshr miss latency -system.cpu.dcache.demand_hits::0 13577961 # number of demand (read+write) hits +system.cpu.dcache.demand_avg_mshr_miss_latency 30225.128426 # average overall mshr miss latency +system.cpu.dcache.demand_hits::0 13600043 # number of demand (read+write) hits system.cpu.dcache.demand_hits::1 0 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 13577961 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 49687940500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate::0 0.097749 # miss rate for demand accesses +system.cpu.dcache.demand_hits::total 13600043 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 47855161500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate::0 0.095764 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu.dcache.demand_misses::0 1471029 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::0 1440329 # number of demand (read+write) misses system.cpu.dcache.demand_misses::1 0 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1471029 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1440329 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 45274807500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate::0 0.097749 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_latency 43534129000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate::0 0.095764 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 1471029 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses 1440329 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.occ_%::0 0.999969 # Average percentage of cache occupancy -system.cpu.dcache.occ_blocks::0 511.984142 # Average occupied blocks per context -system.cpu.dcache.overall_accesses::0 15048990 # number of overall (read+write) accesses +system.cpu.dcache.occ_blocks::0 511.984152 # Average occupied blocks per context +system.cpu.dcache.overall_accesses::0 15040372 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::1 0 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 15048990 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency::0 33777.675695 # average overall miss latency +system.cpu.dcache.overall_accesses::total 15040372 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency::0 33225.160016 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::1 inf # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::total inf # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 30777.644424 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 30225.128426 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits::0 13577961 # number of overall hits +system.cpu.dcache.overall_hits::0 13600043 # number of overall hits system.cpu.dcache.overall_hits::1 0 # number of overall hits -system.cpu.dcache.overall_hits::total 13577961 # number of overall hits -system.cpu.dcache.overall_miss_latency 49687940500 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate::0 0.097749 # miss rate for overall accesses +system.cpu.dcache.overall_hits::total 13600043 # number of overall hits +system.cpu.dcache.overall_miss_latency 47855161500 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate::0 0.095764 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu.dcache.overall_misses::0 1471029 # number of overall misses +system.cpu.dcache.overall_misses::0 1440329 # number of overall misses system.cpu.dcache.overall_misses::1 0 # number of overall misses -system.cpu.dcache.overall_misses::total 1471029 # number of overall misses +system.cpu.dcache.overall_misses::total 1440329 # number of overall misses system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 45274807500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate::0 0.097749 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_latency 43534129000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate::0 0.095764 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 1471029 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_uncacheable_latency 2064006500 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_misses 1440329 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_uncacheable_latency 2063734000 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.replacements 1391606 # number of replacements -system.cpu.dcache.sampled_refs 1392118 # Sample count of references to valid blocks. +system.cpu.dcache.replacements 1390845 # number of replacements +system.cpu.dcache.sampled_refs 1391357 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 511.984142 # Cycle average of tags in use -system.cpu.dcache.total_refs 14056658 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 84139000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 430459 # number of writebacks +system.cpu.dcache.tagsinuse 511.984152 # Cycle average of tags in use +system.cpu.dcache.total_refs 14048739 # Total number of references to valid blocks. +system.cpu.dcache.warmup_cycle 84029000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.writebacks 452168 # number of writebacks system.cpu.dtb.data_accesses 1020784 # DTB accesses system.cpu.dtb.data_acv 367 # DTB access violations -system.cpu.dtb.data_hits 15429793 # DTB hits +system.cpu.dtb.data_hits 15421062 # DTB hits system.cpu.dtb.data_misses 11466 # DTB misses system.cpu.dtb.fetch_accesses 0 # ITB accesses system.cpu.dtb.fetch_acv 0 # ITB acv @@ -159,106 +159,106 @@ system.cpu.dtb.fetch_hits 0 # IT system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.read_accesses 728853 # DTB read accesses system.cpu.dtb.read_acv 210 # DTB read access violations -system.cpu.dtb.read_hits 9069700 # DTB read hits +system.cpu.dtb.read_hits 9064565 # DTB read hits system.cpu.dtb.read_misses 10324 # DTB read misses system.cpu.dtb.write_accesses 291931 # DTB write accesses system.cpu.dtb.write_acv 157 # DTB write access violations -system.cpu.dtb.write_hits 6360093 # DTB write hits +system.cpu.dtb.write_hits 6356497 # DTB write hits system.cpu.dtb.write_misses 1142 # DTB write misses -system.cpu.icache.ReadReq_accesses::0 56217537 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 56217537 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency::0 14711.221983 # average ReadReq miss latency +system.cpu.icache.ReadReq_accesses::0 56192153 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 56192153 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency::0 14699.293599 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency system.cpu.icache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 11710.491665 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits::0 55286436 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 55286436 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 13697633500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate::0 0.016562 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses::0 931101 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 931101 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_miss_latency 10903650500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::0 0.016562 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency 11698.559265 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits::0 55261378 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 55261378 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 13681735000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate::0 0.016564 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses::0 930775 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 930775 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_miss_latency 10888726500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::0 0.016564 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 931101 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses 930775 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.icache.avg_refs 59.387754 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 59.381568 # Average number of references to valid blocks. system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses::0 56217537 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::0 56192153 # number of demand (read+write) accesses system.cpu.icache.demand_accesses::1 0 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 56217537 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency::0 14711.221983 # average overall miss latency +system.cpu.icache.demand_accesses::total 56192153 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency::0 14699.293599 # average overall miss latency system.cpu.icache.demand_avg_miss_latency::1 inf # average overall miss latency system.cpu.icache.demand_avg_miss_latency::total inf # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 11710.491665 # average overall mshr miss latency -system.cpu.icache.demand_hits::0 55286436 # number of demand (read+write) hits +system.cpu.icache.demand_avg_mshr_miss_latency 11698.559265 # average overall mshr miss latency +system.cpu.icache.demand_hits::0 55261378 # number of demand (read+write) hits system.cpu.icache.demand_hits::1 0 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 55286436 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 13697633500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate::0 0.016562 # miss rate for demand accesses +system.cpu.icache.demand_hits::total 55261378 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 13681735000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate::0 0.016564 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::1 no_value # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu.icache.demand_misses::0 931101 # number of demand (read+write) misses +system.cpu.icache.demand_misses::0 930775 # number of demand (read+write) misses system.cpu.icache.demand_misses::1 0 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 931101 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 930775 # number of demand (read+write) misses system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 10903650500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate::0 0.016562 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_latency 10888726500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate::0 0.016564 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 931101 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses 930775 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_%::0 0.993281 # Average percentage of cache occupancy -system.cpu.icache.occ_blocks::0 508.559728 # Average occupied blocks per context -system.cpu.icache.overall_accesses::0 56217537 # number of overall (read+write) accesses +system.cpu.icache.occ_%::0 0.993310 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::0 508.574724 # Average occupied blocks per context +system.cpu.icache.overall_accesses::0 56192153 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::1 0 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 56217537 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency::0 14711.221983 # average overall miss latency +system.cpu.icache.overall_accesses::total 56192153 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency::0 14699.293599 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::1 inf # average overall miss latency system.cpu.icache.overall_avg_miss_latency::total inf # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 11710.491665 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 11698.559265 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.overall_hits::0 55286436 # number of overall hits +system.cpu.icache.overall_hits::0 55261378 # number of overall hits system.cpu.icache.overall_hits::1 0 # number of overall hits -system.cpu.icache.overall_hits::total 55286436 # number of overall hits -system.cpu.icache.overall_miss_latency 13697633500 # number of overall miss cycles -system.cpu.icache.overall_miss_rate::0 0.016562 # miss rate for overall accesses +system.cpu.icache.overall_hits::total 55261378 # number of overall hits +system.cpu.icache.overall_miss_latency 13681735000 # number of overall miss cycles +system.cpu.icache.overall_miss_rate::0 0.016564 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::1 no_value # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu.icache.overall_misses::0 931101 # number of overall misses +system.cpu.icache.overall_misses::0 930775 # number of overall misses system.cpu.icache.overall_misses::1 0 # number of overall misses -system.cpu.icache.overall_misses::total 931101 # number of overall misses +system.cpu.icache.overall_misses::total 930775 # number of overall misses system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 10903650500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate::0 0.016562 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_latency 10888726500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate::0 0.016564 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 931101 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses 930775 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.replacements 930429 # number of replacements -system.cpu.icache.sampled_refs 930940 # Sample count of references to valid blocks. +system.cpu.icache.replacements 930104 # number of replacements +system.cpu.icache.sampled_refs 930615 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 508.559728 # Cycle average of tags in use -system.cpu.icache.total_refs 55286436 # Total number of references to valid blocks. -system.cpu.icache.warmup_cycle 39055604000 # Cycle when the warmup percentage was hit. +system.cpu.icache.tagsinuse 508.574724 # Cycle average of tags in use +system.cpu.icache.total_refs 55261378 # Total number of references to valid blocks. +system.cpu.icache.warmup_cycle 38310365000 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idle_fraction 0.929209 # Percentage of idle cycles +system.cpu.idle_fraction 0.930310 # Percentage of idle cycles system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_hits 0 # DTB hits system.cpu.itb.data_misses 0 # DTB misses -system.cpu.itb.fetch_accesses 4982987 # ITB accesses +system.cpu.itb.fetch_accesses 4982567 # ITB accesses system.cpu.itb.fetch_acv 184 # ITB acv -system.cpu.itb.fetch_hits 4977977 # ITB hits +system.cpu.itb.fetch_hits 4977557 # ITB hits system.cpu.itb.fetch_misses 5010 # ITB misses system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.read_acv 0 # DTB read access violations @@ -272,55 +272,55 @@ system.cpu.kern.callpal::cserve 1 0.00% 0.00% # nu system.cpu.kern.callpal::wrmces 1 0.00% 0.00% # number of callpals executed system.cpu.kern.callpal::wrfen 1 0.00% 0.00% # number of callpals executed system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # number of callpals executed -system.cpu.kern.callpal::swpctx 4171 2.16% 2.16% # number of callpals executed +system.cpu.kern.callpal::swpctx 4177 2.16% 2.16% # number of callpals executed system.cpu.kern.callpal::tbi 54 0.03% 2.19% # number of callpals executed -system.cpu.kern.callpal::wrent 7 0.00% 2.19% # number of callpals executed -system.cpu.kern.callpal::swpipl 176257 91.22% 93.41% # number of callpals executed -system.cpu.kern.callpal::rdps 6844 3.54% 96.95% # number of callpals executed +system.cpu.kern.callpal::wrent 7 0.00% 2.20% # number of callpals executed +system.cpu.kern.callpal::swpipl 176202 91.22% 93.41% # number of callpals executed +system.cpu.kern.callpal::rdps 6843 3.54% 96.95% # number of callpals executed system.cpu.kern.callpal::wrkgp 1 0.00% 96.96% # number of callpals executed system.cpu.kern.callpal::wrusp 7 0.00% 96.96% # number of callpals executed system.cpu.kern.callpal::rdusp 9 0.00% 96.96% # number of callpals executed system.cpu.kern.callpal::whami 2 0.00% 96.96% # number of callpals executed -system.cpu.kern.callpal::rti 5169 2.68% 99.64% # number of callpals executed +system.cpu.kern.callpal::rti 5167 2.67% 99.64% # number of callpals executed system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed -system.cpu.kern.callpal::total 193221 # number of callpals executed +system.cpu.kern.callpal::total 193169 # number of callpals executed system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.hwrei 212325 # number of hwrei instructions executed -system.cpu.kern.inst.quiesce 6374 # number of quiesce instructions executed -system.cpu.kern.ipl_count::0 75001 40.87% 40.87% # number of times we switched to this ipl +system.cpu.kern.inst.hwrei 212271 # number of hwrei instructions executed +system.cpu.kern.inst.quiesce 6373 # number of quiesce instructions executed +system.cpu.kern.ipl_count::0 74979 40.87% 40.87% # number of times we switched to this ipl system.cpu.kern.ipl_count::21 131 0.07% 40.94% # number of times we switched to this ipl -system.cpu.kern.ipl_count::22 1944 1.06% 42.00% # number of times we switched to this ipl -system.cpu.kern.ipl_count::31 106426 58.00% 100.00% # number of times we switched to this ipl -system.cpu.kern.ipl_count::total 183502 # number of times we switched to this ipl -system.cpu.kern.ipl_good::0 73634 49.31% 49.31% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_count::22 1942 1.06% 42.00% # number of times we switched to this ipl +system.cpu.kern.ipl_count::31 106391 58.00% 100.00% # number of times we switched to this ipl +system.cpu.kern.ipl_count::total 183443 # number of times we switched to this ipl +system.cpu.kern.ipl_good::0 73612 49.31% 49.31% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good::21 131 0.09% 49.39% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::22 1944 1.30% 50.69% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::31 73634 49.31% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::total 149343 # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_ticks::0 1866810523000 96.72% 96.72% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::21 96331500 0.00% 96.72% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::22 565310500 0.03% 96.75% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::31 62691670000 3.25% 100.00% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::total 1930163835000 # number of cycles we spent at this ipl -system.cpu.kern.ipl_used::0 0.981774 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_good::22 1942 1.30% 50.69% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::31 73612 49.31% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::total 149297 # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_ticks::0 1865248449500 96.75% 96.75% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::21 84324500 0.00% 96.75% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::22 564095000 0.03% 96.78% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::31 62054251000 3.22% 100.00% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::total 1927951120000 # number of cycles we spent at this ipl +system.cpu.kern.ipl_used::0 0.981768 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::31 0.691880 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.mode_good::kernel 1911 +system.cpu.kern.ipl_used::31 0.691901 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.mode_good::kernel 1914 system.cpu.kern.mode_good::user 1744 -system.cpu.kern.mode_good::idle 167 -system.cpu.kern.mode_switch::kernel 5917 # number of protection mode switches +system.cpu.kern.mode_good::idle 170 +system.cpu.kern.mode_switch::kernel 5914 # number of protection mode switches system.cpu.kern.mode_switch::user 1744 # number of protection mode switches -system.cpu.kern.mode_switch::idle 2089 # number of protection mode switches -system.cpu.kern.mode_switch_good::kernel 0.322968 # fraction of useful protection mode switches +system.cpu.kern.mode_switch::idle 2096 # number of protection mode switches +system.cpu.kern.mode_switch_good::kernel 0.323639 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::idle 0.079943 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::total 1.402910 # fraction of useful protection mode switches -system.cpu.kern.mode_ticks::kernel 48447088000 2.51% 2.51% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::user 5539986000 0.29% 2.80% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::idle 1876176759000 97.20% 100.00% # number of ticks spent at the given mode -system.cpu.kern.swap_context 4172 # number of times the context was actually changed +system.cpu.kern.mode_switch_good::idle 0.081107 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good::total 1.404746 # fraction of useful protection mode switches +system.cpu.kern.mode_ticks::kernel 47869140000 2.48% 2.48% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::user 5515150000 0.29% 2.77% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::idle 1874566828000 97.23% 100.00% # number of ticks spent at the given mode +system.cpu.kern.swap_context 4178 # number of times the context was actually changed system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed @@ -352,10 +352,10 @@ system.cpu.kern.syscall::132 4 1.23% 98.77% # nu system.cpu.kern.syscall::144 2 0.61% 99.39% # number of syscalls executed system.cpu.kern.syscall::147 2 0.61% 100.00% # number of syscalls executed system.cpu.kern.syscall::total 326 # number of syscalls executed -system.cpu.not_idle_fraction 0.070791 # Percentage of non-idle cycles -system.cpu.numCycles 3860329186 # number of cpu cycles simulated -system.cpu.num_insts 56205703 # Number of instructions executed -system.cpu.num_refs 15677891 # Number of memory references +system.cpu.not_idle_fraction 0.069690 # Percentage of non-idle cycles +system.cpu.numCycles 3855903756 # number of cpu cycles simulated +system.cpu.num_insts 56180319 # Number of instructions executed +system.cpu.num_refs 15669216 # Number of memory references system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). @@ -386,37 +386,37 @@ system.iocache.ReadReq_mshr_misses 173 # nu system.iocache.WriteReq_accesses::1 41552 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 41552 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_avg_miss_latency::0 inf # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::1 137876.559636 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::1 137846.765643 # average WriteReq miss latency system.iocache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency -system.iocache.WriteReq_avg_mshr_miss_latency 85873.072921 # average WriteReq mshr miss latency -system.iocache.WriteReq_miss_latency 5729046806 # number of WriteReq miss cycles +system.iocache.WriteReq_avg_mshr_miss_latency 85843.300347 # average WriteReq mshr miss latency +system.iocache.WriteReq_miss_latency 5727808806 # number of WriteReq miss cycles system.iocache.WriteReq_miss_rate::1 1 # miss rate for WriteReq accesses system.iocache.WriteReq_misses::1 41552 # number of WriteReq misses system.iocache.WriteReq_misses::total 41552 # number of WriteReq misses -system.iocache.WriteReq_mshr_miss_latency 3568197926 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency 3566960816 # number of WriteReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_rate::0 inf # mshr miss rate for WriteReq accesses system.iocache.WriteReq_mshr_miss_rate::1 1 # mshr miss rate for WriteReq accesses system.iocache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses system.iocache.WriteReq_mshr_misses 41552 # number of WriteReq MSHR misses -system.iocache.avg_blocked_cycles::no_mshrs 6163.674943 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 6165.192131 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.iocache.avg_refs 0 # Average number of references to valid blocks. system.iocache.blocked::no_mshrs 10472 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.blocked_cycles::no_mshrs 64546004 # number of cycles access was blocked +system.iocache.blocked_cycles::no_mshrs 64561892 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.iocache.cache_copies 0 # number of cache copies performed system.iocache.demand_accesses::0 0 # number of demand (read+write) accesses system.iocache.demand_accesses::1 41725 # number of demand (read+write) accesses system.iocache.demand_accesses::total 41725 # number of demand (read+write) accesses system.iocache.demand_avg_miss_latency::0 inf # average overall miss latency -system.iocache.demand_avg_miss_latency::1 137782.763427 # average overall miss latency +system.iocache.demand_avg_miss_latency::1 137753.092966 # average overall miss latency system.iocache.demand_avg_miss_latency::total inf # average overall miss latency -system.iocache.demand_avg_mshr_miss_latency 85779.291168 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency 85749.642037 # average overall mshr miss latency system.iocache.demand_hits::0 0 # number of demand (read+write) hits system.iocache.demand_hits::1 0 # number of demand (read+write) hits system.iocache.demand_hits::total 0 # number of demand (read+write) hits -system.iocache.demand_miss_latency 5748985804 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency 5747747804 # number of demand (read+write) miss cycles system.iocache.demand_miss_rate::0 no_value # miss rate for demand accesses system.iocache.demand_miss_rate::1 1 # miss rate for demand accesses system.iocache.demand_miss_rate::total no_value # miss rate for demand accesses @@ -424,7 +424,7 @@ system.iocache.demand_misses::0 0 # nu system.iocache.demand_misses::1 41725 # number of demand (read+write) misses system.iocache.demand_misses::total 41725 # number of demand (read+write) misses system.iocache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.iocache.demand_mshr_miss_latency 3579140924 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency 3577903814 # number of demand (read+write) MSHR miss cycles system.iocache.demand_mshr_miss_rate::0 inf # mshr miss rate for demand accesses system.iocache.demand_mshr_miss_rate::1 1 # mshr miss rate for demand accesses system.iocache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses @@ -432,20 +432,20 @@ system.iocache.demand_mshr_misses 41725 # nu system.iocache.fast_writes 0 # number of fast writes performed system.iocache.mshr_cap_events 0 # number of times MSHR cap was activated system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.iocache.occ_%::1 0.084587 # Average percentage of cache occupancy -system.iocache.occ_blocks::1 1.353399 # Average occupied blocks per context +system.iocache.occ_%::1 0.084569 # Average percentage of cache occupancy +system.iocache.occ_blocks::1 1.353112 # Average occupied blocks per context system.iocache.overall_accesses::0 0 # number of overall (read+write) accesses system.iocache.overall_accesses::1 41725 # number of overall (read+write) accesses system.iocache.overall_accesses::total 41725 # number of overall (read+write) accesses system.iocache.overall_avg_miss_latency::0 inf # average overall miss latency -system.iocache.overall_avg_miss_latency::1 137782.763427 # average overall miss latency +system.iocache.overall_avg_miss_latency::1 137753.092966 # average overall miss latency system.iocache.overall_avg_miss_latency::total inf # average overall miss latency -system.iocache.overall_avg_mshr_miss_latency 85779.291168 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency 85749.642037 # average overall mshr miss latency system.iocache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.iocache.overall_hits::0 0 # number of overall hits system.iocache.overall_hits::1 0 # number of overall hits system.iocache.overall_hits::total 0 # number of overall hits -system.iocache.overall_miss_latency 5748985804 # number of overall miss cycles +system.iocache.overall_miss_latency 5747747804 # number of overall miss cycles system.iocache.overall_miss_rate::0 no_value # miss rate for overall accesses system.iocache.overall_miss_rate::1 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total no_value # miss rate for overall accesses @@ -453,7 +453,7 @@ system.iocache.overall_misses::0 0 # nu system.iocache.overall_misses::1 41725 # number of overall misses system.iocache.overall_misses::total 41725 # number of overall misses system.iocache.overall_mshr_hits 0 # number of overall MSHR hits -system.iocache.overall_mshr_miss_latency 3579140924 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency 3577903814 # number of overall MSHR miss cycles system.iocache.overall_mshr_miss_rate::0 inf # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::1 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses @@ -463,151 +463,153 @@ system.iocache.overall_mshr_uncacheable_misses 0 system.iocache.replacements 41685 # number of replacements system.iocache.sampled_refs 41701 # Sample count of references to valid blocks. system.iocache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.iocache.tagsinuse 1.353399 # Cycle average of tags in use +system.iocache.tagsinuse 1.353112 # Cycle average of tags in use system.iocache.total_refs 0 # Total number of references to valid blocks. -system.iocache.warmup_cycle 1762299470000 # Cycle when the warmup percentage was hit. +system.iocache.warmup_cycle 1760339542000 # Cycle when the warmup percentage was hit. system.iocache.writebacks 41512 # number of writebacks -system.l2c.ReadExReq_accesses::0 304636 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 304636 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_avg_miss_latency::0 52003.289171 # average ReadExReq miss latency +system.l2c.ReadExReq_accesses::0 304386 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 304386 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_avg_miss_latency::0 52003.580327 # average ReadExReq miss latency system.l2c.ReadExReq_avg_miss_latency::1 inf # average ReadExReq miss latency system.l2c.ReadExReq_avg_miss_latency::total inf # average ReadExReq miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency 40003.289171 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_miss_latency 15842074000 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_rate::0 1 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_misses::0 304636 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 304636 # number of ReadExReq misses -system.l2c.ReadExReq_mshr_miss_latency 12186442000 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_rate::0 1 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_avg_mshr_miss_latency 40003.580327 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_hits::0 2179 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 2179 # number of ReadExReq hits +system.l2c.ReadExReq_miss_latency 15715846000 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_rate::0 0.992841 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_misses::0 302207 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 302207 # number of ReadExReq misses +system.l2c.ReadExReq_mshr_miss_latency 12089362000 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_rate::0 0.992841 # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::1 inf # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::total inf # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_misses 304636 # number of ReadExReq MSHR misses -system.l2c.ReadReq_accesses::0 2018564 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 2018564 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_avg_miss_latency::0 52016.377161 # average ReadReq miss latency +system.l2c.ReadExReq_mshr_misses 302207 # number of ReadExReq MSHR misses +system.l2c.ReadReq_accesses::0 2017728 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 2017728 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_avg_miss_latency::0 52016.477812 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.l2c.ReadReq_avg_mshr_miss_latency 40016.359280 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency 40016.459857 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_hits::0 1710971 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1710971 # number of ReadReq hits -system.l2c.ReadReq_miss_latency 15999873500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_rate::0 0.152382 # miss rate for ReadReq accesses -system.l2c.ReadReq_misses::0 307593 # number of ReadReq misses -system.l2c.ReadReq_misses::total 307593 # number of ReadReq misses -system.l2c.ReadReq_mshr_miss_latency 12308752000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_rate::0 0.152382 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_hits::0 1711407 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1711407 # number of ReadReq hits +system.l2c.ReadReq_miss_latency 15933739500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_rate::0 0.151815 # miss rate for ReadReq accesses +system.l2c.ReadReq_misses::0 306321 # number of ReadReq misses +system.l2c.ReadReq_misses::total 306321 # number of ReadReq misses +system.l2c.ReadReq_mshr_miss_latency 12257882000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_rate::0 0.151815 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_misses 307593 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses 306321 # number of ReadReq MSHR misses system.l2c.ReadReq_mshr_uncacheable_latency 772673000 # number of ReadReq MSHR uncacheable cycles -system.l2c.SCUpgradeReq_accesses::0 30004 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 30004 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_avg_miss_latency::0 52004.366085 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_accesses::0 22262 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::total 22262 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_avg_miss_latency::0 52004.626718 # average SCUpgradeReq miss latency system.l2c.SCUpgradeReq_avg_miss_latency::1 inf # average SCUpgradeReq miss latency system.l2c.SCUpgradeReq_avg_miss_latency::total inf # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency 40004.366085 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_miss_latency 1560339000 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_avg_mshr_miss_latency 40004.626718 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_miss_latency 1157727000 # number of SCUpgradeReq miss cycles system.l2c.SCUpgradeReq_miss_rate::0 1 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_misses::0 30004 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 30004 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_mshr_miss_latency 1200291000 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_misses::0 22262 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::total 22262 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_mshr_miss_latency 890583000 # number of SCUpgradeReq MSHR miss cycles system.l2c.SCUpgradeReq_mshr_miss_rate::0 1 # mshr miss rate for SCUpgradeReq accesses system.l2c.SCUpgradeReq_mshr_miss_rate::1 inf # mshr miss rate for SCUpgradeReq accesses system.l2c.SCUpgradeReq_mshr_miss_rate::total inf # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_misses 30004 # number of SCUpgradeReq MSHR misses -system.l2c.UpgradeReq_accesses::0 96219 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 96219 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_avg_miss_latency::0 52001.013313 # average UpgradeReq miss latency +system.l2c.SCUpgradeReq_mshr_misses 22262 # number of SCUpgradeReq MSHR misses +system.l2c.UpgradeReq_accesses::0 66236 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 66236 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_avg_miss_latency::0 52000.030195 # average UpgradeReq miss latency system.l2c.UpgradeReq_avg_miss_latency::1 inf # average UpgradeReq miss latency system.l2c.UpgradeReq_avg_miss_latency::total inf # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency 40006.391669 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_miss_latency 5003485500 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_avg_mshr_miss_latency 40007.095839 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_miss_latency 3444274000 # number of UpgradeReq miss cycles system.l2c.UpgradeReq_miss_rate::0 1 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_misses::0 96219 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 96219 # number of UpgradeReq misses -system.l2c.UpgradeReq_mshr_miss_latency 3849375000 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_misses::0 66236 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 66236 # number of UpgradeReq misses +system.l2c.UpgradeReq_mshr_miss_latency 2649910000 # number of UpgradeReq MSHR miss cycles system.l2c.UpgradeReq_mshr_miss_rate::0 1 # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::1 inf # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::total inf # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_misses 96219 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses 66236 # number of UpgradeReq MSHR misses system.l2c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_mshr_uncacheable_latency 1085299500 # number of WriteReq MSHR uncacheable cycles -system.l2c.Writeback_accesses::0 430459 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 430459 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_hits::0 430459 # number of Writeback hits -system.l2c.Writeback_hits::total 430459 # number of Writeback hits +system.l2c.WriteReq_mshr_uncacheable_latency 1085051000 # number of WriteReq MSHR uncacheable cycles +system.l2c.Writeback_accesses::0 452168 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 452168 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_hits::0 452168 # number of Writeback hits +system.l2c.Writeback_hits::total 452168 # number of Writeback hits system.l2c.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.l2c.avg_refs 4.436562 # Average number of references to valid blocks. +system.l2c.avg_refs 4.517115 # Average number of references to valid blocks. system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked::no_targets 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.demand_accesses::0 2323200 # number of demand (read+write) accesses +system.l2c.demand_accesses::0 2322114 # number of demand (read+write) accesses system.l2c.demand_accesses::1 0 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 2323200 # number of demand (read+write) accesses -system.l2c.demand_avg_miss_latency::0 52009.864773 # average overall miss latency +system.l2c.demand_accesses::total 2322114 # number of demand (read+write) accesses +system.l2c.demand_avg_miss_latency::0 52010.072667 # average overall miss latency system.l2c.demand_avg_miss_latency::1 inf # average overall miss latency system.l2c.demand_avg_miss_latency::total inf # average overall miss latency -system.l2c.demand_avg_mshr_miss_latency 40009.855789 # average overall mshr miss latency -system.l2c.demand_hits::0 1710971 # number of demand (read+write) hits +system.l2c.demand_avg_mshr_miss_latency 40010.063629 # average overall mshr miss latency +system.l2c.demand_hits::0 1713586 # number of demand (read+write) hits system.l2c.demand_hits::1 0 # number of demand (read+write) hits -system.l2c.demand_hits::total 1710971 # number of demand (read+write) hits -system.l2c.demand_miss_latency 31841947500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_rate::0 0.263528 # miss rate for demand accesses +system.l2c.demand_hits::total 1713586 # number of demand (read+write) hits +system.l2c.demand_miss_latency 31649585500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_rate::0 0.262058 # miss rate for demand accesses system.l2c.demand_miss_rate::1 no_value # miss rate for demand accesses system.l2c.demand_miss_rate::total no_value # miss rate for demand accesses -system.l2c.demand_misses::0 612229 # number of demand (read+write) misses +system.l2c.demand_misses::0 608528 # number of demand (read+write) misses system.l2c.demand_misses::1 0 # number of demand (read+write) misses -system.l2c.demand_misses::total 612229 # number of demand (read+write) misses +system.l2c.demand_misses::total 608528 # number of demand (read+write) misses system.l2c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_miss_latency 24495194000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_rate::0 0.263528 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_latency 24347244000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_rate::0 0.262058 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.l2c.demand_mshr_misses 612229 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses 608528 # number of demand (read+write) MSHR misses system.l2c.fast_writes 0 # number of fast writes performed system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.occ_%::0 0.086363 # Average percentage of cache occupancy -system.l2c.occ_%::1 0.380427 # Average percentage of cache occupancy -system.l2c.occ_blocks::0 5659.865751 # Average occupied blocks per context -system.l2c.occ_blocks::1 24931.678191 # Average occupied blocks per context -system.l2c.overall_accesses::0 2323200 # number of overall (read+write) accesses +system.l2c.occ_%::0 0.156745 # Average percentage of cache occupancy +system.l2c.occ_%::1 0.334961 # Average percentage of cache occupancy +system.l2c.occ_blocks::0 10272.459916 # Average occupied blocks per context +system.l2c.occ_blocks::1 21951.974033 # Average occupied blocks per context +system.l2c.overall_accesses::0 2322114 # number of overall (read+write) accesses system.l2c.overall_accesses::1 0 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 2323200 # number of overall (read+write) accesses -system.l2c.overall_avg_miss_latency::0 52009.864773 # average overall miss latency +system.l2c.overall_accesses::total 2322114 # number of overall (read+write) accesses +system.l2c.overall_avg_miss_latency::0 52010.072667 # average overall miss latency system.l2c.overall_avg_miss_latency::1 inf # average overall miss latency system.l2c.overall_avg_miss_latency::total inf # average overall miss latency -system.l2c.overall_avg_mshr_miss_latency 40009.855789 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency 40010.063629 # average overall mshr miss latency system.l2c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.l2c.overall_hits::0 1710971 # number of overall hits +system.l2c.overall_hits::0 1713586 # number of overall hits system.l2c.overall_hits::1 0 # number of overall hits -system.l2c.overall_hits::total 1710971 # number of overall hits -system.l2c.overall_miss_latency 31841947500 # number of overall miss cycles -system.l2c.overall_miss_rate::0 0.263528 # miss rate for overall accesses +system.l2c.overall_hits::total 1713586 # number of overall hits +system.l2c.overall_miss_latency 31649585500 # number of overall miss cycles +system.l2c.overall_miss_rate::0 0.262058 # miss rate for overall accesses system.l2c.overall_miss_rate::1 no_value # miss rate for overall accesses system.l2c.overall_miss_rate::total no_value # miss rate for overall accesses -system.l2c.overall_misses::0 612229 # number of overall misses +system.l2c.overall_misses::0 608528 # number of overall misses system.l2c.overall_misses::1 0 # number of overall misses -system.l2c.overall_misses::total 612229 # number of overall misses +system.l2c.overall_misses::total 608528 # number of overall misses system.l2c.overall_mshr_hits 0 # number of overall MSHR hits -system.l2c.overall_mshr_miss_latency 24495194000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_rate::0 0.263528 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_latency 24347244000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_rate::0 0.262058 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.l2c.overall_mshr_misses 612229 # number of overall MSHR misses -system.l2c.overall_mshr_uncacheable_latency 1857972500 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_misses 608528 # number of overall MSHR misses +system.l2c.overall_mshr_uncacheable_latency 1857724000 # number of overall MSHR uncacheable cycles system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.l2c.replacements 394928 # number of replacements -system.l2c.sampled_refs 425903 # Sample count of references to valid blocks. +system.l2c.replacements 393234 # number of replacements +system.l2c.sampled_refs 424575 # Sample count of references to valid blocks. system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.l2c.tagsinuse 30591.543942 # Cycle average of tags in use -system.l2c.total_refs 1889545 # Total number of references to valid blocks. -system.l2c.warmup_cycle 6968733000 # Cycle when the warmup percentage was hit. -system.l2c.writebacks 119060 # number of writebacks +system.l2c.tagsinuse 32224.433949 # Cycle average of tags in use +system.l2c.total_refs 1917854 # Total number of references to valid blocks. +system.l2c.warmup_cycle 6967096000 # Cycle when the warmup percentage was hit. +system.l2c.writebacks 118566 # number of writebacks system.tsunami.ethernet.coalescedRxDesc no_value # average number of RxDesc's coalesced into each post system.tsunami.ethernet.coalescedRxIdle no_value # average number of RxIdle's coalesced into each post system.tsunami.ethernet.coalescedRxOk no_value # average number of RxOk's coalesced into each post |