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-rw-r--r--tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini4
-rwxr-xr-xtests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simout10
-rw-r--r--tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt40
3 files changed, 35 insertions, 19 deletions
diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini
index 468bf0248..a7d96b196 100644
--- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini
+++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini
@@ -94,7 +94,7 @@ cpu_side=system.cpu.dcache_port
mem_side=system.toL2Bus.port[2]
[system.cpu.dtb]
-type=AlphaDTB
+type=AlphaTLB
size=64
[system.cpu.icache]
@@ -133,7 +133,7 @@ mem_side=system.toL2Bus.port[1]
type=AlphaInterrupts
[system.cpu.itb]
-type=AlphaITB
+type=AlphaTLB
size=48
[system.cpu.tracer]
diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simout b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simout
index ba86a45b9..0edc8e974 100755
--- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simout
+++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simout
@@ -5,11 +5,11 @@ The Regents of The University of Michigan
All Rights Reserved
-M5 compiled Feb 16 2009 00:15:24
-M5 revision d8c62c2eaaa6 5874 default qtip pf1 tip qbase
-M5 started Feb 16 2009 00:15:52
-M5 executing on zizzer
-command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-timing -re tests/run.py quick/10.linux-boot/alpha/linux/tsunami-simple-timing
+M5 compiled Apr 8 2009 12:30:02
+M5 revision 233a4a1a6110 6024 default qtip tip test_unifytlb.diff
+M5 started Apr 8 2009 12:30:04
+M5 executing on maize
+command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-timing -re tests/run.py build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-timing
Global frequency set at 1000000000000 ticks per second
info: kernel located at: /dist/m5/system/binaries/vmlinux
info: Entering event queue @ 0. Starting simulation...
diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt
index cbf231e85..7b42fa0e8 100644
--- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt
+++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt
@@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
-host_inst_rate 1953289 # Simulator instruction rate (inst/s)
-host_mem_usage 288556 # Number of bytes of host memory used
-host_seconds 28.78 # Real time elapsed on the host
-host_tick_rate 67077404616 # Simulator tick rate (ticks/s)
+host_inst_rate 2046881 # Simulator instruction rate (inst/s)
+host_mem_usage 290296 # Number of bytes of host memory used
+host_seconds 27.46 # Real time elapsed on the host
+host_tick_rate 70291420604 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 56205703 # Number of instructions simulated
sim_seconds 1.930165 # Number of seconds simulated
@@ -95,10 +95,14 @@ system.cpu.dcache.tagsinuse 511.984142 # Cy
system.cpu.dcache.total_refs 14056658 # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle 84139000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 430459 # number of writebacks
-system.cpu.dtb.accesses 1020784 # DTB accesses
-system.cpu.dtb.acv 367 # DTB access violations
-system.cpu.dtb.hits 15429793 # DTB hits
-system.cpu.dtb.misses 11466 # DTB misses
+system.cpu.dtb.data_accesses 1020784 # DTB accesses
+system.cpu.dtb.data_acv 367 # DTB access violations
+system.cpu.dtb.data_hits 15429793 # DTB hits
+system.cpu.dtb.data_misses 11466 # DTB misses
+system.cpu.dtb.fetch_accesses 0 # ITB accesses
+system.cpu.dtb.fetch_acv 0 # ITB acv
+system.cpu.dtb.fetch_hits 0 # ITB hits
+system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.read_accesses 728853 # DTB read accesses
system.cpu.dtb.read_acv 210 # DTB read access violations
system.cpu.dtb.read_hits 9069700 # DTB read hits
@@ -161,10 +165,22 @@ system.cpu.icache.total_refs 55286436 # To
system.cpu.icache.warmup_cycle 39055604000 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks
system.cpu.idle_fraction 0.929209 # Percentage of idle cycles
-system.cpu.itb.accesses 4982987 # ITB accesses
-system.cpu.itb.acv 184 # ITB acv
-system.cpu.itb.hits 4977977 # ITB hits
-system.cpu.itb.misses 5010 # ITB misses
+system.cpu.itb.data_accesses 0 # DTB accesses
+system.cpu.itb.data_acv 0 # DTB access violations
+system.cpu.itb.data_hits 0 # DTB hits
+system.cpu.itb.data_misses 0 # DTB misses
+system.cpu.itb.fetch_accesses 4982987 # ITB accesses
+system.cpu.itb.fetch_acv 184 # ITB acv
+system.cpu.itb.fetch_hits 4977977 # ITB hits
+system.cpu.itb.fetch_misses 5010 # ITB misses
+system.cpu.itb.read_accesses 0 # DTB read accesses
+system.cpu.itb.read_acv 0 # DTB read access violations
+system.cpu.itb.read_hits 0 # DTB read hits
+system.cpu.itb.read_misses 0 # DTB read misses
+system.cpu.itb.write_accesses 0 # DTB write accesses
+system.cpu.itb.write_acv 0 # DTB write access violations
+system.cpu.itb.write_hits 0 # DTB write hits
+system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.kern.callpal 193221 # number of callpals executed
system.cpu.kern.callpal_cserve 1 0.00% 0.00% # number of callpals executed
system.cpu.kern.callpal_wrmces 1 0.00% 0.00% # number of callpals executed