diff options
Diffstat (limited to 'tests/quick/10.linux-boot/ref/alpha')
12 files changed, 1118 insertions, 1087 deletions
diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini index 7292b0c1a..587e758aa 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini @@ -8,11 +8,12 @@ type=LinuxAlphaSystem children=bridge cpu0 cpu1 disk0 disk2 intrctrl iobus iocache l2c membus physmem simple_disk terminal toL2Bus tsunami boot_cpu_frequency=500 boot_osflags=root=/dev/hda1 console=ttyS0 -console=/home/stever/m5/m5_system_2.0b3/binaries/console +console=/dist/m5/system/binaries/console init_param=0 -kernel=/home/stever/m5/m5_system_2.0b3/binaries/vmlinux +kernel=/dist/m5/system/binaries/vmlinux +load_addr_mask=1099511627775 mem_mode=atomic -pal=/home/stever/m5/m5_system_2.0b3/binaries/ts_osfpal +pal=/dist/m5/system/binaries/ts_osfpal physmem=system.physmem readfile=tests/halt.sh symbolfile= @@ -264,7 +265,7 @@ table_size=65536 [system.disk0.image.child] type=RawDiskImage -image_file=/home/stever/m5/m5_system_2.0b3/disks/linux-latest.img +image_file=/dist/m5/system/disks/linux-latest.img read_only=true [system.disk2] @@ -284,7 +285,7 @@ table_size=65536 [system.disk2.image.child] type=RawDiskImage -image_file=/home/stever/m5/m5_system_2.0b3/disks/linux-bigswap2.img +image_file=/dist/m5/system/disks/linux-bigswap2.img read_only=true [system.intrctrl] @@ -410,7 +411,7 @@ system=system [system.simple_disk.disk] type=RawDiskImage -image_file=/home/stever/m5/m5_system_2.0b3/disks/linux-latest.img +image_file=/dist/m5/system/disks/linux-latest.img read_only=true [system.terminal] diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/simout b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/simout index 74b825924..2604d666e 100755 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/simout +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/simout @@ -1,5 +1,5 @@ -Redirecting stdout to build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual/simout -Redirecting stderr to build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual/simerr +Redirecting stdout to build/ALPHA_FS/tests/opt/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual/simout +Redirecting stderr to build/ALPHA_FS/tests/opt/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual/simerr M5 Simulator System Copyright (c) 2001-2008 @@ -7,13 +7,14 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Jun 16 2010 10:39:13 -M5 revision b85fd4ba5453 7466 default qtip tip llsc-fix-stats -M5 started Jun 16 2010 10:44:34 -M5 executing on phenom -command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual -re tests/run.py build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual +M5 compiled Aug 26 2010 12:51:14 +M5 revision 85cafc6ccb42 7662 default qtip tip sc-fail-fix +M5 started Aug 26 2010 12:51:21 +M5 executing on zizzer +command line: build/ALPHA_FS/m5.opt -d build/ALPHA_FS/tests/opt/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual -re tests/run.py build/ALPHA_FS/tests/opt/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual Global frequency set at 1000000000000 ticks per second -info: kernel located at: /home/stever/m5/m5_system_2.0b3/binaries/vmlinux +info: kernel located at: /dist/m5/system/binaries/vmlinux + 0: system.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009 info: Entering event queue @ 0. Starting simulation... info: Launching CPU 1 @ 97861500 Exiting @ tick 1870335522500 because m5_exit instruction encountered diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt index 7f610a74e..9b7657157 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 3116744 # Simulator instruction rate (inst/s) -host_mem_usage 276812 # Number of bytes of host memory used -host_seconds 20.26 # Real time elapsed on the host -host_tick_rate 92302855126 # Simulator tick rate (ticks/s) +host_inst_rate 2244323 # Simulator instruction rate (inst/s) +host_mem_usage 293120 # Number of bytes of host memory used +host_seconds 28.14 # Real time elapsed on the host +host_tick_rate 66466128576 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 63154034 # Number of instructions simulated sim_seconds 1.870336 # Number of seconds simulated @@ -24,18 +24,18 @@ system.cpu0.dcache.ReadReq_misses::0 1683563 # nu system.cpu0.dcache.ReadReq_misses::total 1683563 # number of ReadReq misses system.cpu0.dcache.StoreCondReq_accesses::0 187338 # number of StoreCondReq accesses(hits+misses) system.cpu0.dcache.StoreCondReq_accesses::total 187338 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_hits::0 159838 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 159838 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_miss_rate::0 0.146793 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_misses::0 27500 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 27500 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_hits::0 165851 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 165851 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_miss_rate::0 0.114696 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_misses::0 21487 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 21487 # number of StoreCondReq misses system.cpu0.dcache.WriteReq_accesses::0 5748261 # number of WriteReq accesses(hits+misses) system.cpu0.dcache.WriteReq_accesses::total 5748261 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_hits::0 5374453 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 5374453 # number of WriteReq hits -system.cpu0.dcache.WriteReq_miss_rate::0 0.065030 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_misses::0 373808 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 373808 # number of WriteReq misses +system.cpu0.dcache.WriteReq_hits::0 5400040 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 5400040 # number of WriteReq hits +system.cpu0.dcache.WriteReq_miss_rate::0 0.060578 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_misses::0 348221 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 348221 # number of WriteReq misses system.cpu0.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu0.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu0.dcache.avg_refs 6.629793 # Average number of references to valid blocks. @@ -51,16 +51,16 @@ system.cpu0.dcache.demand_avg_miss_latency::0 0 system.cpu0.dcache.demand_avg_miss_latency::1 no_value # average overall miss latency system.cpu0.dcache.demand_avg_miss_latency::total no_value # average overall miss latency system.cpu0.dcache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency -system.cpu0.dcache.demand_hits::0 12672559 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::0 12698146 # number of demand (read+write) hits system.cpu0.dcache.demand_hits::1 0 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 12672559 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 12698146 # number of demand (read+write) hits system.cpu0.dcache.demand_miss_latency 0 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_rate::0 0.139673 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::0 0.137936 # miss rate for demand accesses system.cpu0.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses system.cpu0.dcache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu0.dcache.demand_misses::0 2057371 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::0 2031784 # number of demand (read+write) misses system.cpu0.dcache.demand_misses::1 0 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 2057371 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 2031784 # number of demand (read+write) misses system.cpu0.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.cpu0.dcache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles system.cpu0.dcache.demand_mshr_miss_rate::0 0 # mshr miss rate for demand accesses @@ -80,16 +80,16 @@ system.cpu0.dcache.overall_avg_miss_latency::1 no_value system.cpu0.dcache.overall_avg_miss_latency::total no_value # average overall miss latency system.cpu0.dcache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu0.dcache.overall_hits::0 12672559 # number of overall hits +system.cpu0.dcache.overall_hits::0 12698146 # number of overall hits system.cpu0.dcache.overall_hits::1 0 # number of overall hits -system.cpu0.dcache.overall_hits::total 12672559 # number of overall hits +system.cpu0.dcache.overall_hits::total 12698146 # number of overall hits system.cpu0.dcache.overall_miss_latency 0 # number of overall miss cycles -system.cpu0.dcache.overall_miss_rate::0 0.139673 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::0 0.137936 # miss rate for overall accesses system.cpu0.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses system.cpu0.dcache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu0.dcache.overall_misses::0 2057371 # number of overall misses +system.cpu0.dcache.overall_misses::0 2031784 # number of overall misses system.cpu0.dcache.overall_misses::1 0 # number of overall misses -system.cpu0.dcache.overall_misses::total 2057371 # number of overall misses +system.cpu0.dcache.overall_misses::total 2031784 # number of overall misses system.cpu0.dcache.overall_mshr_hits 0 # number of overall MSHR hits system.cpu0.dcache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles system.cpu0.dcache.overall_mshr_miss_rate::0 0 # mshr miss rate for overall accesses @@ -104,7 +104,7 @@ system.cpu0.dcache.soft_prefetch_mshr_full 0 # system.cpu0.dcache.tagsinuse 504.827058 # Cycle average of tags in use system.cpu0.dcache.total_refs 13123502 # Total number of references to valid blocks. system.cpu0.dcache.warmup_cycle 10840000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.writebacks 396793 # number of writebacks +system.cpu0.dcache.writebacks 419022 # number of writebacks system.cpu0.dtb.data_accesses 698037 # DTB accesses system.cpu0.dtb.data_acv 251 # DTB access violations system.cpu0.dtb.data_hits 15091429 # DTB hits @@ -323,18 +323,18 @@ system.cpu1.dcache.ReadReq_misses::0 41650 # nu system.cpu1.dcache.ReadReq_misses::total 41650 # number of ReadReq misses system.cpu1.dcache.StoreCondReq_accesses::0 16345 # number of StoreCondReq accesses(hits+misses) system.cpu1.dcache.StoreCondReq_accesses::total 16345 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_hits::0 13438 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 13438 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_miss_rate::0 0.177853 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_misses::0 2907 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 2907 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_hits::0 13853 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 13853 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_miss_rate::0 0.152463 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_misses::0 2492 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 2492 # number of StoreCondReq misses system.cpu1.dcache.WriteReq_accesses::0 733305 # number of WriteReq accesses(hits+misses) system.cpu1.dcache.WriteReq_accesses::total 733305 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_hits::0 702803 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 702803 # number of WriteReq hits -system.cpu1.dcache.WriteReq_miss_rate::0 0.041595 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_misses::0 30502 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 30502 # number of WriteReq misses +system.cpu1.dcache.WriteReq_hits::0 703732 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 703732 # number of WriteReq hits +system.cpu1.dcache.WriteReq_miss_rate::0 0.040328 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_misses::0 29573 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 29573 # number of WriteReq misses system.cpu1.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu1.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu1.dcache.avg_refs 29.279155 # Average number of references to valid blocks. @@ -350,16 +350,16 @@ system.cpu1.dcache.demand_avg_miss_latency::0 0 system.cpu1.dcache.demand_avg_miss_latency::1 no_value # average overall miss latency system.cpu1.dcache.demand_avg_miss_latency::total no_value # average overall miss latency system.cpu1.dcache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency -system.cpu1.dcache.demand_hits::0 1812118 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::0 1813047 # number of demand (read+write) hits system.cpu1.dcache.demand_hits::1 0 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 1812118 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 1813047 # number of demand (read+write) hits system.cpu1.dcache.demand_miss_latency 0 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_rate::0 0.038292 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::0 0.037799 # miss rate for demand accesses system.cpu1.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses system.cpu1.dcache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu1.dcache.demand_misses::0 72152 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::0 71223 # number of demand (read+write) misses system.cpu1.dcache.demand_misses::1 0 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 72152 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 71223 # number of demand (read+write) misses system.cpu1.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.cpu1.dcache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles system.cpu1.dcache.demand_mshr_miss_rate::0 0 # mshr miss rate for demand accesses @@ -379,16 +379,16 @@ system.cpu1.dcache.overall_avg_miss_latency::1 no_value system.cpu1.dcache.overall_avg_miss_latency::total no_value # average overall miss latency system.cpu1.dcache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency system.cpu1.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu1.dcache.overall_hits::0 1812118 # number of overall hits +system.cpu1.dcache.overall_hits::0 1813047 # number of overall hits system.cpu1.dcache.overall_hits::1 0 # number of overall hits -system.cpu1.dcache.overall_hits::total 1812118 # number of overall hits +system.cpu1.dcache.overall_hits::total 1813047 # number of overall hits system.cpu1.dcache.overall_miss_latency 0 # number of overall miss cycles -system.cpu1.dcache.overall_miss_rate::0 0.038292 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::0 0.037799 # miss rate for overall accesses system.cpu1.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses system.cpu1.dcache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu1.dcache.overall_misses::0 72152 # number of overall misses +system.cpu1.dcache.overall_misses::0 71223 # number of overall misses system.cpu1.dcache.overall_misses::1 0 # number of overall misses -system.cpu1.dcache.overall_misses::total 72152 # number of overall misses +system.cpu1.dcache.overall_misses::total 71223 # number of overall misses system.cpu1.dcache.overall_mshr_hits 0 # number of overall MSHR hits system.cpu1.dcache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles system.cpu1.dcache.overall_mshr_miss_rate::0 0 # mshr miss rate for overall accesses @@ -403,7 +403,7 @@ system.cpu1.dcache.soft_prefetch_mshr_full 0 # system.cpu1.dcache.tagsinuse 391.951263 # Cycle average of tags in use system.cpu1.dcache.total_refs 1834544 # Total number of references to valid blocks. system.cpu1.dcache.warmup_cycle 1851267520500 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.writebacks 30848 # number of writebacks +system.cpu1.dcache.writebacks 31228 # number of writebacks system.cpu1.dtb.data_accesses 323622 # DTB accesses system.cpu1.dtb.data_acv 116 # DTB access violations system.cpu1.dtb.data_hits 1914885 # DTB hits @@ -683,72 +683,81 @@ system.iocache.writebacks 41520 # nu system.l2c.ReadExReq_accesses::0 282023 # number of ReadExReq accesses(hits+misses) system.l2c.ReadExReq_accesses::1 24224 # number of ReadExReq accesses(hits+misses) system.l2c.ReadExReq_accesses::total 306247 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_miss_rate::0 1 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::1 1 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_misses::0 282023 # number of ReadExReq misses -system.l2c.ReadExReq_misses::1 24224 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 306247 # number of ReadExReq misses -system.l2c.ReadReq_accesses::0 2581928 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::1 142339 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 2724267 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_hits::0 1623113 # number of ReadReq hits -system.l2c.ReadReq_hits::1 136618 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1759731 # number of ReadReq hits -system.l2c.ReadReq_miss_rate::0 0.371356 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::1 0.040193 # miss rate for ReadReq accesses -system.l2c.ReadReq_misses::0 958815 # number of ReadReq misses -system.l2c.ReadReq_misses::1 5721 # number of ReadReq misses -system.l2c.ReadReq_misses::total 964536 # number of ReadReq misses -system.l2c.SCUpgradeReq_accesses::0 26914 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::1 2297 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 29211 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_miss_rate::0 1 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::1 1 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_misses::0 26914 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::1 2297 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 29211 # number of SCUpgradeReq misses -system.l2c.UpgradeReq_accesses::0 90515 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::1 5281 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 95796 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_miss_rate::0 1 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::1 1 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_misses::0 90515 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::1 5281 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 95796 # number of UpgradeReq misses -system.l2c.Writeback_accesses::0 427641 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 427641 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_hits::0 427641 # number of Writeback hits -system.l2c.Writeback_hits::total 427641 # number of Writeback hits +system.l2c.ReadExReq_hits::0 1653 # number of ReadExReq hits +system.l2c.ReadExReq_hits::1 139 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 1792 # number of ReadExReq hits +system.l2c.ReadExReq_miss_rate::0 0.994139 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::1 0.994262 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_misses::0 280370 # number of ReadExReq misses +system.l2c.ReadExReq_misses::1 24085 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 304455 # number of ReadExReq misses +system.l2c.ReadReq_accesses::0 2581832 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::1 142288 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 2724120 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_hits::0 1623623 # number of ReadReq hits +system.l2c.ReadReq_hits::1 136766 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1760389 # number of ReadReq hits +system.l2c.ReadReq_miss_rate::0 0.371135 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::1 0.038809 # miss rate for ReadReq accesses +system.l2c.ReadReq_misses::0 958209 # number of ReadReq misses +system.l2c.ReadReq_misses::1 5522 # number of ReadReq misses +system.l2c.ReadReq_misses::total 963731 # number of ReadReq misses +system.l2c.SCUpgradeReq_accesses::0 20901 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::1 1879 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::total 22780 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_hits::0 3 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::1 4 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 7 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_miss_rate::0 0.999856 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::1 0.997871 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_misses::0 20898 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::1 1875 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::total 22773 # number of SCUpgradeReq misses +system.l2c.UpgradeReq_accesses::0 64914 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::1 4352 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 69266 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_hits::0 12 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::1 3 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 15 # number of UpgradeReq hits +system.l2c.UpgradeReq_miss_rate::0 0.999815 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::1 0.999311 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_misses::0 64902 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::1 4349 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 69251 # number of UpgradeReq misses +system.l2c.Writeback_accesses::0 450250 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 450250 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_hits::0 450250 # number of Writeback hits +system.l2c.Writeback_hits::total 450250 # number of Writeback hits system.l2c.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.l2c.avg_refs 1.788900 # Average number of references to valid blocks. +system.l2c.avg_refs 1.817381 # Average number of references to valid blocks. system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked::no_targets 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.demand_accesses::0 2863951 # number of demand (read+write) accesses -system.l2c.demand_accesses::1 166563 # number of demand (read+write) accesses +system.l2c.demand_accesses::0 2863855 # number of demand (read+write) accesses +system.l2c.demand_accesses::1 166512 # number of demand (read+write) accesses system.l2c.demand_accesses::2 0 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 3030514 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 3030367 # number of demand (read+write) accesses system.l2c.demand_avg_miss_latency::0 0 # average overall miss latency system.l2c.demand_avg_miss_latency::1 0 # average overall miss latency system.l2c.demand_avg_miss_latency::2 no_value # average overall miss latency system.l2c.demand_avg_miss_latency::total no_value # average overall miss latency system.l2c.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency -system.l2c.demand_hits::0 1623113 # number of demand (read+write) hits -system.l2c.demand_hits::1 136618 # number of demand (read+write) hits +system.l2c.demand_hits::0 1625276 # number of demand (read+write) hits +system.l2c.demand_hits::1 136905 # number of demand (read+write) hits system.l2c.demand_hits::2 0 # number of demand (read+write) hits -system.l2c.demand_hits::total 1759731 # number of demand (read+write) hits +system.l2c.demand_hits::total 1762181 # number of demand (read+write) hits system.l2c.demand_miss_latency 0 # number of demand (read+write) miss cycles -system.l2c.demand_miss_rate::0 0.433261 # miss rate for demand accesses -system.l2c.demand_miss_rate::1 0.179782 # miss rate for demand accesses +system.l2c.demand_miss_rate::0 0.432487 # miss rate for demand accesses +system.l2c.demand_miss_rate::1 0.177807 # miss rate for demand accesses system.l2c.demand_miss_rate::2 no_value # miss rate for demand accesses system.l2c.demand_miss_rate::total no_value # miss rate for demand accesses -system.l2c.demand_misses::0 1240838 # number of demand (read+write) misses -system.l2c.demand_misses::1 29945 # number of demand (read+write) misses +system.l2c.demand_misses::0 1238579 # number of demand (read+write) misses +system.l2c.demand_misses::1 29607 # number of demand (read+write) misses system.l2c.demand_misses::2 0 # number of demand (read+write) misses -system.l2c.demand_misses::total 1270783 # number of demand (read+write) misses +system.l2c.demand_misses::total 1268186 # number of demand (read+write) misses system.l2c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.l2c.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles system.l2c.demand_mshr_miss_rate::0 0 # mshr miss rate for demand accesses @@ -759,35 +768,35 @@ system.l2c.demand_mshr_misses 0 # nu system.l2c.fast_writes 0 # number of fast writes performed system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.occ_%::0 0.079636 # Average percentage of cache occupancy -system.l2c.occ_%::1 0.003863 # Average percentage of cache occupancy -system.l2c.occ_%::2 0.382298 # Average percentage of cache occupancy -system.l2c.occ_blocks::0 5219.016701 # Average occupied blocks per context -system.l2c.occ_blocks::1 253.146931 # Average occupied blocks per context -system.l2c.occ_blocks::2 25054.312004 # Average occupied blocks per context -system.l2c.overall_accesses::0 2863951 # number of overall (read+write) accesses -system.l2c.overall_accesses::1 166563 # number of overall (read+write) accesses +system.l2c.occ_%::0 0.144031 # Average percentage of cache occupancy +system.l2c.occ_%::1 0.004095 # Average percentage of cache occupancy +system.l2c.occ_%::2 0.343441 # Average percentage of cache occupancy +system.l2c.occ_blocks::0 9439.247714 # Average occupied blocks per context +system.l2c.occ_blocks::1 268.394267 # Average occupied blocks per context +system.l2c.occ_blocks::2 22507.731761 # Average occupied blocks per context +system.l2c.overall_accesses::0 2863855 # number of overall (read+write) accesses +system.l2c.overall_accesses::1 166512 # number of overall (read+write) accesses system.l2c.overall_accesses::2 0 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 3030514 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 3030367 # number of overall (read+write) accesses system.l2c.overall_avg_miss_latency::0 0 # average overall miss latency system.l2c.overall_avg_miss_latency::1 0 # average overall miss latency system.l2c.overall_avg_miss_latency::2 no_value # average overall miss latency system.l2c.overall_avg_miss_latency::total no_value # average overall miss latency system.l2c.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency system.l2c.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.l2c.overall_hits::0 1623113 # number of overall hits -system.l2c.overall_hits::1 136618 # number of overall hits +system.l2c.overall_hits::0 1625276 # number of overall hits +system.l2c.overall_hits::1 136905 # number of overall hits system.l2c.overall_hits::2 0 # number of overall hits -system.l2c.overall_hits::total 1759731 # number of overall hits +system.l2c.overall_hits::total 1762181 # number of overall hits system.l2c.overall_miss_latency 0 # number of overall miss cycles -system.l2c.overall_miss_rate::0 0.433261 # miss rate for overall accesses -system.l2c.overall_miss_rate::1 0.179782 # miss rate for overall accesses +system.l2c.overall_miss_rate::0 0.432487 # miss rate for overall accesses +system.l2c.overall_miss_rate::1 0.177807 # miss rate for overall accesses system.l2c.overall_miss_rate::2 no_value # miss rate for overall accesses system.l2c.overall_miss_rate::total no_value # miss rate for overall accesses -system.l2c.overall_misses::0 1240838 # number of overall misses -system.l2c.overall_misses::1 29945 # number of overall misses +system.l2c.overall_misses::0 1238579 # number of overall misses +system.l2c.overall_misses::1 29607 # number of overall misses system.l2c.overall_misses::2 0 # number of overall misses -system.l2c.overall_misses::total 1270783 # number of overall misses +system.l2c.overall_misses::total 1268186 # number of overall misses system.l2c.overall_mshr_hits 0 # number of overall MSHR hits system.l2c.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles system.l2c.overall_mshr_miss_rate::0 0 # mshr miss rate for overall accesses @@ -797,13 +806,13 @@ system.l2c.overall_mshr_miss_rate::total no_value # ms system.l2c.overall_mshr_misses 0 # number of overall MSHR misses system.l2c.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.l2c.replacements 1056803 # number of replacements -system.l2c.sampled_refs 1091452 # Sample count of references to valid blocks. +system.l2c.replacements 1055565 # number of replacements +system.l2c.sampled_refs 1090545 # Sample count of references to valid blocks. system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.l2c.tagsinuse 30526.475636 # Cycle average of tags in use -system.l2c.total_refs 1952499 # Total number of references to valid blocks. +system.l2c.tagsinuse 32215.373742 # Cycle average of tags in use +system.l2c.total_refs 1981936 # Total number of references to valid blocks. system.l2c.warmup_cycle 990121000 # Cycle when the warmup percentage was hit. -system.l2c.writebacks 123882 # number of writebacks +system.l2c.writebacks 123249 # number of writebacks system.tsunami.ethernet.coalescedRxDesc no_value # average number of RxDesc's coalesced into each post system.tsunami.ethernet.coalescedRxIdle no_value # average number of RxIdle's coalesced into each post system.tsunami.ethernet.coalescedRxOk no_value # average number of RxOk's coalesced into each post diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini index c4ecb27ec..95ba28054 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini @@ -8,11 +8,12 @@ type=LinuxAlphaSystem children=bridge cpu disk0 disk2 intrctrl iobus iocache l2c membus physmem simple_disk terminal toL2Bus tsunami boot_cpu_frequency=500 boot_osflags=root=/dev/hda1 console=ttyS0 -console=/home/stever/m5/m5_system_2.0b3/binaries/console +console=/dist/m5/system/binaries/console init_param=0 -kernel=/home/stever/m5/m5_system_2.0b3/binaries/vmlinux +kernel=/dist/m5/system/binaries/vmlinux +load_addr_mask=1099511627775 mem_mode=atomic -pal=/home/stever/m5/m5_system_2.0b3/binaries/ts_osfpal +pal=/dist/m5/system/binaries/ts_osfpal physmem=system.physmem readfile=tests/halt.sh symbolfile= @@ -157,7 +158,7 @@ table_size=65536 [system.disk0.image.child] type=RawDiskImage -image_file=/home/stever/m5/m5_system_2.0b3/disks/linux-latest.img +image_file=/dist/m5/system/disks/linux-latest.img read_only=true [system.disk2] @@ -177,7 +178,7 @@ table_size=65536 [system.disk2.image.child] type=RawDiskImage -image_file=/home/stever/m5/m5_system_2.0b3/disks/linux-bigswap2.img +image_file=/dist/m5/system/disks/linux-bigswap2.img read_only=true [system.intrctrl] @@ -303,7 +304,7 @@ system=system [system.simple_disk.disk] type=RawDiskImage -image_file=/home/stever/m5/m5_system_2.0b3/disks/linux-latest.img +image_file=/dist/m5/system/disks/linux-latest.img read_only=true [system.terminal] diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/simout b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/simout index af78d2d19..88c4f9cc3 100755 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/simout +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/simout @@ -1,5 +1,5 @@ -Redirecting stdout to build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic/simout -Redirecting stderr to build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic/simerr +Redirecting stdout to build/ALPHA_FS/tests/opt/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic/simout +Redirecting stderr to build/ALPHA_FS/tests/opt/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic/simerr M5 Simulator System Copyright (c) 2001-2008 @@ -7,12 +7,13 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Jun 16 2010 10:39:13 -M5 revision b85fd4ba5453 7466 default qtip tip llsc-fix-stats -M5 started Jun 16 2010 10:39:16 -M5 executing on phenom -command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic -re tests/run.py build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic +M5 compiled Aug 26 2010 12:51:14 +M5 revision 85cafc6ccb42 7662 default qtip tip sc-fail-fix +M5 started Aug 26 2010 12:51:50 +M5 executing on zizzer +command line: build/ALPHA_FS/m5.opt -d build/ALPHA_FS/tests/opt/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic -re tests/run.py build/ALPHA_FS/tests/opt/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic Global frequency set at 1000000000000 ticks per second -info: kernel located at: /home/stever/m5/m5_system_2.0b3/binaries/vmlinux +info: kernel located at: /dist/m5/system/binaries/vmlinux + 0: system.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009 info: Entering event queue @ 0. Starting simulation... Exiting @ tick 1829332258000 because m5_exit instruction encountered diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt index 7a54ae203..da0ed6f79 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 3274924 # Simulator instruction rate (inst/s) -host_mem_usage 275440 # Number of bytes of host memory used -host_seconds 18.33 # Real time elapsed on the host -host_tick_rate 99783911231 # Simulator tick rate (ticks/s) +host_inst_rate 2897706 # Simulator instruction rate (inst/s) +host_mem_usage 291728 # Number of bytes of host memory used +host_seconds 20.72 # Real time elapsed on the host +host_tick_rate 88290469218 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 60038305 # Number of instructions simulated sim_seconds 1.829332 # Number of seconds simulated @@ -24,18 +24,18 @@ system.cpu.dcache.ReadReq_misses::0 1721705 # nu system.cpu.dcache.ReadReq_misses::total 1721705 # number of ReadReq misses system.cpu.dcache.StoreCondReq_accesses::0 199282 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 199282 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_hits::0 169415 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 169415 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_miss_rate::0 0.149873 # miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_misses::0 29867 # number of StoreCondReq misses -system.cpu.dcache.StoreCondReq_misses::total 29867 # number of StoreCondReq misses +system.cpu.dcache.StoreCondReq_hits::0 177079 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 177079 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_miss_rate::0 0.111415 # miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_misses::0 22203 # number of StoreCondReq misses +system.cpu.dcache.StoreCondReq_misses::total 22203 # number of StoreCondReq misses system.cpu.dcache.WriteReq_accesses::0 6152574 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 6152574 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_hits::0 5753150 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 5753150 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_rate::0 0.064920 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses::0 399424 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 399424 # number of WriteReq misses +system.cpu.dcache.WriteReq_hits::0 5781102 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 5781102 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_rate::0 0.060377 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses::0 371472 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 371472 # number of WriteReq misses system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.dcache.avg_refs 6.870767 # Average number of references to valid blocks. @@ -51,16 +51,16 @@ system.cpu.dcache.demand_avg_miss_latency::0 0 system.cpu.dcache.demand_avg_miss_latency::1 no_value # average overall miss latency system.cpu.dcache.demand_avg_miss_latency::total no_value # average overall miss latency system.cpu.dcache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency -system.cpu.dcache.demand_hits::0 13560932 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::0 13588884 # number of demand (read+write) hits system.cpu.dcache.demand_hits::1 0 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 13560932 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 13588884 # number of demand (read+write) hits system.cpu.dcache.demand_miss_latency 0 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate::0 0.135258 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::0 0.133476 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu.dcache.demand_misses::0 2121129 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::0 2093177 # number of demand (read+write) misses system.cpu.dcache.demand_misses::1 0 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2121129 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2093177 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.cpu.dcache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_rate::0 0 # mshr miss rate for demand accesses @@ -80,16 +80,16 @@ system.cpu.dcache.overall_avg_miss_latency::1 no_value system.cpu.dcache.overall_avg_miss_latency::total no_value # average overall miss latency system.cpu.dcache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits::0 13560932 # number of overall hits +system.cpu.dcache.overall_hits::0 13588884 # number of overall hits system.cpu.dcache.overall_hits::1 0 # number of overall hits -system.cpu.dcache.overall_hits::total 13560932 # number of overall hits +system.cpu.dcache.overall_hits::total 13588884 # number of overall hits system.cpu.dcache.overall_miss_latency 0 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate::0 0.135258 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::0 0.133476 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu.dcache.overall_misses::0 2121129 # number of overall misses +system.cpu.dcache.overall_misses::0 2093177 # number of overall misses system.cpu.dcache.overall_misses::1 0 # number of overall misses -system.cpu.dcache.overall_misses::total 2121129 # number of overall misses +system.cpu.dcache.overall_misses::total 2093177 # number of overall misses system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits system.cpu.dcache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_rate::0 0 # mshr miss rate for overall accesses @@ -104,7 +104,7 @@ system.cpu.dcache.soft_prefetch_mshr_full 0 # n system.cpu.dcache.tagsinuse 511.997802 # Cycle average of tags in use system.cpu.dcache.total_refs 14038433 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 10840000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 428893 # number of writebacks +system.cpu.dcache.writebacks 450979 # number of writebacks system.cpu.dtb.data_accesses 1020787 # DTB accesses system.cpu.dtb.data_acv 367 # DTB access violations system.cpu.dtb.data_hits 16062925 # DTB hits @@ -395,33 +395,35 @@ system.iocache.warmup_cycle 1685780659017 # C system.iocache.writebacks 41512 # number of writebacks system.l2c.ReadExReq_accesses::0 304346 # number of ReadExReq accesses(hits+misses) system.l2c.ReadExReq_accesses::total 304346 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_miss_rate::0 1 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_misses::0 304346 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 304346 # number of ReadExReq misses +system.l2c.ReadExReq_hits::0 1965 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 1965 # number of ReadExReq hits +system.l2c.ReadExReq_miss_rate::0 0.993544 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_misses::0 302381 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 302381 # number of ReadExReq misses system.l2c.ReadReq_accesses::0 2659071 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::total 2659071 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_hits::0 1696652 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1696652 # number of ReadReq hits -system.l2c.ReadReq_miss_rate::0 0.361938 # miss rate for ReadReq accesses -system.l2c.ReadReq_misses::0 962419 # number of ReadReq misses -system.l2c.ReadReq_misses::total 962419 # number of ReadReq misses -system.l2c.SCUpgradeReq_accesses::0 29867 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 29867 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.ReadReq_hits::0 1697753 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1697753 # number of ReadReq hits +system.l2c.ReadReq_miss_rate::0 0.361524 # miss rate for ReadReq accesses +system.l2c.ReadReq_misses::0 961318 # number of ReadReq misses +system.l2c.ReadReq_misses::total 961318 # number of ReadReq misses +system.l2c.SCUpgradeReq_accesses::0 22203 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::total 22203 # number of SCUpgradeReq accesses(hits+misses) system.l2c.SCUpgradeReq_miss_rate::0 1 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_misses::0 29867 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 29867 # number of SCUpgradeReq misses -system.l2c.UpgradeReq_accesses::0 95078 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 95078 # number of UpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_misses::0 22203 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::total 22203 # number of SCUpgradeReq misses +system.l2c.UpgradeReq_accesses::0 67126 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 67126 # number of UpgradeReq accesses(hits+misses) system.l2c.UpgradeReq_miss_rate::0 1 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_misses::0 95078 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 95078 # number of UpgradeReq misses -system.l2c.Writeback_accesses::0 428893 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 428893 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_hits::0 428893 # number of Writeback hits -system.l2c.Writeback_hits::total 428893 # number of Writeback hits +system.l2c.UpgradeReq_misses::0 67126 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 67126 # number of UpgradeReq misses +system.l2c.Writeback_accesses::0 450979 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 450979 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_hits::0 450979 # number of Writeback hits +system.l2c.Writeback_hits::total 450979 # number of Writeback hits system.l2c.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.l2c.avg_refs 1.727246 # Average number of references to valid blocks. +system.l2c.avg_refs 1.759381 # Average number of references to valid blocks. system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked::no_targets 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked @@ -434,16 +436,16 @@ system.l2c.demand_avg_miss_latency::0 0 # av system.l2c.demand_avg_miss_latency::1 no_value # average overall miss latency system.l2c.demand_avg_miss_latency::total no_value # average overall miss latency system.l2c.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency -system.l2c.demand_hits::0 1696652 # number of demand (read+write) hits +system.l2c.demand_hits::0 1699718 # number of demand (read+write) hits system.l2c.demand_hits::1 0 # number of demand (read+write) hits -system.l2c.demand_hits::total 1696652 # number of demand (read+write) hits +system.l2c.demand_hits::total 1699718 # number of demand (read+write) hits system.l2c.demand_miss_latency 0 # number of demand (read+write) miss cycles -system.l2c.demand_miss_rate::0 0.427468 # miss rate for demand accesses +system.l2c.demand_miss_rate::0 0.426433 # miss rate for demand accesses system.l2c.demand_miss_rate::1 no_value # miss rate for demand accesses system.l2c.demand_miss_rate::total no_value # miss rate for demand accesses -system.l2c.demand_misses::0 1266765 # number of demand (read+write) misses +system.l2c.demand_misses::0 1263699 # number of demand (read+write) misses system.l2c.demand_misses::1 0 # number of demand (read+write) misses -system.l2c.demand_misses::total 1266765 # number of demand (read+write) misses +system.l2c.demand_misses::total 1263699 # number of demand (read+write) misses system.l2c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.l2c.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles system.l2c.demand_mshr_miss_rate::0 0 # mshr miss rate for demand accesses @@ -453,10 +455,10 @@ system.l2c.demand_mshr_misses 0 # nu system.l2c.fast_writes 0 # number of fast writes performed system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.occ_%::0 0.077203 # Average percentage of cache occupancy -system.l2c.occ_%::1 0.384049 # Average percentage of cache occupancy -system.l2c.occ_blocks::0 5059.576308 # Average occupied blocks per context -system.l2c.occ_blocks::1 25169.009297 # Average occupied blocks per context +system.l2c.occ_%::0 0.141683 # Average percentage of cache occupancy +system.l2c.occ_%::1 0.342776 # Average percentage of cache occupancy +system.l2c.occ_blocks::0 9285.312813 # Average occupied blocks per context +system.l2c.occ_blocks::1 22464.151503 # Average occupied blocks per context system.l2c.overall_accesses::0 2963417 # number of overall (read+write) accesses system.l2c.overall_accesses::1 0 # number of overall (read+write) accesses system.l2c.overall_accesses::total 2963417 # number of overall (read+write) accesses @@ -465,16 +467,16 @@ system.l2c.overall_avg_miss_latency::1 no_value # av system.l2c.overall_avg_miss_latency::total no_value # average overall miss latency system.l2c.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency system.l2c.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.l2c.overall_hits::0 1696652 # number of overall hits +system.l2c.overall_hits::0 1699718 # number of overall hits system.l2c.overall_hits::1 0 # number of overall hits -system.l2c.overall_hits::total 1696652 # number of overall hits +system.l2c.overall_hits::total 1699718 # number of overall hits system.l2c.overall_miss_latency 0 # number of overall miss cycles -system.l2c.overall_miss_rate::0 0.427468 # miss rate for overall accesses +system.l2c.overall_miss_rate::0 0.426433 # miss rate for overall accesses system.l2c.overall_miss_rate::1 no_value # miss rate for overall accesses system.l2c.overall_miss_rate::total no_value # miss rate for overall accesses -system.l2c.overall_misses::0 1266765 # number of overall misses +system.l2c.overall_misses::0 1263699 # number of overall misses system.l2c.overall_misses::1 0 # number of overall misses -system.l2c.overall_misses::total 1266765 # number of overall misses +system.l2c.overall_misses::total 1263699 # number of overall misses system.l2c.overall_mshr_hits 0 # number of overall MSHR hits system.l2c.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles system.l2c.overall_mshr_miss_rate::0 0 # mshr miss rate for overall accesses @@ -483,13 +485,13 @@ system.l2c.overall_mshr_miss_rate::total no_value # ms system.l2c.overall_mshr_misses 0 # number of overall MSHR misses system.l2c.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.l2c.replacements 1050724 # number of replacements -system.l2c.sampled_refs 1081067 # Sample count of references to valid blocks. +system.l2c.replacements 1048986 # number of replacements +system.l2c.sampled_refs 1079842 # Sample count of references to valid blocks. system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.l2c.tagsinuse 30228.585605 # Cycle average of tags in use -system.l2c.total_refs 1867269 # Total number of references to valid blocks. +system.l2c.tagsinuse 31749.464316 # Cycle average of tags in use +system.l2c.total_refs 1899854 # Total number of references to valid blocks. system.l2c.warmup_cycle 765422500 # Cycle when the warmup percentage was hit. -system.l2c.writebacks 119147 # number of writebacks +system.l2c.writebacks 118452 # number of writebacks system.tsunami.ethernet.coalescedRxDesc no_value # average number of RxDesc's coalesced into each post system.tsunami.ethernet.coalescedRxIdle no_value # average number of RxIdle's coalesced into each post system.tsunami.ethernet.coalescedRxOk no_value # average number of RxOk's coalesced into each post diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini index d4b4f018c..425a86d16 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini @@ -8,11 +8,12 @@ type=LinuxAlphaSystem children=bridge cpu0 cpu1 disk0 disk2 intrctrl iobus iocache l2c membus physmem simple_disk terminal toL2Bus tsunami boot_cpu_frequency=500 boot_osflags=root=/dev/hda1 console=ttyS0 -console=/home/stever/m5/m5_system_2.0b3/binaries/console +console=/dist/m5/system/binaries/console init_param=0 -kernel=/home/stever/m5/m5_system_2.0b3/binaries/vmlinux +kernel=/dist/m5/system/binaries/vmlinux +load_addr_mask=1099511627775 mem_mode=timing -pal=/home/stever/m5/m5_system_2.0b3/binaries/ts_osfpal +pal=/dist/m5/system/binaries/ts_osfpal physmem=system.physmem readfile=tests/halt.sh symbolfile= @@ -258,7 +259,7 @@ table_size=65536 [system.disk0.image.child] type=RawDiskImage -image_file=/home/stever/m5/m5_system_2.0b3/disks/linux-latest.img +image_file=/dist/m5/system/disks/linux-latest.img read_only=true [system.disk2] @@ -278,7 +279,7 @@ table_size=65536 [system.disk2.image.child] type=RawDiskImage -image_file=/home/stever/m5/m5_system_2.0b3/disks/linux-bigswap2.img +image_file=/dist/m5/system/disks/linux-bigswap2.img read_only=true [system.intrctrl] @@ -404,7 +405,7 @@ system=system [system.simple_disk.disk] type=RawDiskImage -image_file=/home/stever/m5/m5_system_2.0b3/disks/linux-latest.img +image_file=/dist/m5/system/disks/linux-latest.img read_only=true [system.terminal] diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simout b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simout index 24b896c4e..079f41b2d 100755 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simout +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simout @@ -1,5 +1,5 @@ -Redirecting stdout to build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-timing-dual/simout -Redirecting stderr to build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-timing-dual/simerr +Redirecting stdout to build/ALPHA_FS/tests/opt/quick/10.linux-boot/alpha/linux/tsunami-simple-timing-dual/simout +Redirecting stderr to build/ALPHA_FS/tests/opt/quick/10.linux-boot/alpha/linux/tsunami-simple-timing-dual/simerr M5 Simulator System Copyright (c) 2001-2008 @@ -7,13 +7,14 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Jun 16 2010 10:39:13 -M5 revision b85fd4ba5453 7466 default qtip tip llsc-fix-stats -M5 started Jun 16 2010 10:43:55 -M5 executing on phenom -command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-timing-dual -re tests/run.py build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-timing-dual +M5 compiled Aug 26 2010 12:51:14 +M5 revision 85cafc6ccb42 7662 default qtip tip sc-fail-fix +M5 started Aug 26 2010 12:51:18 +M5 executing on zizzer +command line: build/ALPHA_FS/m5.opt -d build/ALPHA_FS/tests/opt/quick/10.linux-boot/alpha/linux/tsunami-simple-timing-dual -re tests/run.py build/ALPHA_FS/tests/opt/quick/10.linux-boot/alpha/linux/tsunami-simple-timing-dual Global frequency set at 1000000000000 ticks per second -info: kernel located at: /home/stever/m5/m5_system_2.0b3/binaries/vmlinux +info: kernel located at: /dist/m5/system/binaries/vmlinux + 0: system.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009 info: Entering event queue @ 0. Starting simulation... -info: Launching CPU 1 @ 591544000 -Exiting @ tick 1972135461000 because m5_exit instruction encountered +info: Launching CPU 1 @ 591240000 +Exiting @ tick 1967163347000 because m5_exit instruction encountered diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt index c2f737377..eb5599859 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt @@ -1,157 +1,159 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1520606 # Simulator instruction rate (inst/s) -host_mem_usage 273632 # Number of bytes of host memory used -host_seconds 39.08 # Real time elapsed on the host -host_tick_rate 50467758461 # Simulator tick rate (ticks/s) +host_inst_rate 1510892 # Simulator instruction rate (inst/s) +host_mem_usage 289944 # Number of bytes of host memory used +host_seconds 40.42 # Real time elapsed on the host +host_tick_rate 48670449492 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 59420593 # Number of instructions simulated -sim_seconds 1.972135 # Number of seconds simulated -sim_ticks 1972135461000 # Number of ticks simulated -system.cpu0.dcache.LoadLockedReq_accesses::0 192630 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 192630 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::0 14259.465279 # average LoadLockedReq miss latency +sim_insts 61066894 # Number of instructions simulated +sim_seconds 1.967163 # Number of seconds simulated +sim_ticks 1967163347000 # Number of ticks simulated +system.cpu0.dcache.LoadLockedReq_accesses::0 150276 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 150276 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::0 11859.655689 # average LoadLockedReq miss latency system.cpu0.dcache.LoadLockedReq_avg_miss_latency::1 inf # average LoadLockedReq miss latency system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total inf # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency 11259.465279 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_hits::0 175911 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 175911 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_miss_latency 238404000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_rate::0 0.086793 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_misses::0 16719 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 16719 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency 188247000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::0 0.086793 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency 8859.655689 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_hits::0 136916 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 136916 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_miss_latency 158445000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_rate::0 0.088903 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_misses::0 13360 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 13360 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency 118365000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::0 0.088903 # mshr miss rate for LoadLockedReq accesses system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::1 inf # mshr miss rate for LoadLockedReq accesses system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total inf # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_misses 16719 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.ReadReq_accesses::0 8488393 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 8488393 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_avg_miss_latency::0 25694.266311 # average ReadReq miss latency +system.cpu0.dcache.LoadLockedReq_mshr_misses 13360 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.ReadReq_accesses::0 7279990 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 7279990 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_avg_miss_latency::0 26932.541490 # average ReadReq miss latency system.cpu0.dcache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency system.cpu0.dcache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency 22694.226839 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency 23932.489517 # average ReadReq mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_hits::0 7449690 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 7449690 # number of ReadReq hits -system.cpu0.dcache.ReadReq_miss_latency 26688711500 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_rate::0 0.122367 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_misses::0 1038703 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 1038703 # number of ReadReq misses -system.cpu0.dcache.ReadReq_mshr_miss_latency 23572561500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::0 0.122367 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_hits::0 6346809 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 6346809 # number of ReadReq hits +system.cpu0.dcache.ReadReq_miss_latency 25132936000 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_rate::0 0.128184 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_misses::0 933181 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 933181 # number of ReadReq misses +system.cpu0.dcache.ReadReq_mshr_miss_latency 22333344500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::0 0.128184 # mshr miss rate for ReadReq accesses system.cpu0.dcache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses system.cpu0.dcache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_misses 1038703 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency 883604000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.StoreCondReq_accesses::0 191666 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 191666 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_avg_miss_latency::0 55344.484086 # average StoreCondReq miss latency +system.cpu0.dcache.ReadReq_mshr_misses 933181 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency 883599000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.StoreCondReq_accesses::0 149766 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 149766 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_avg_miss_latency::0 42774.669320 # average StoreCondReq miss latency system.cpu0.dcache.StoreCondReq_avg_miss_latency::1 inf # average StoreCondReq miss latency system.cpu0.dcache.StoreCondReq_avg_miss_latency::total inf # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency 52344.484086 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_hits::0 163357 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 163357 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_miss_latency 1566747000 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_rate::0 0.147700 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_misses::0 28309 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 28309 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_mshr_miss_latency 1481820000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::0 0.147700 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency 39774.669320 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_hits::0 132680 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 132680 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_miss_latency 730848000 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_rate::0 0.114085 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_misses::0 17086 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 17086 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_mshr_miss_latency 679590000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::0 0.114085 # mshr miss rate for StoreCondReq accesses system.cpu0.dcache.StoreCondReq_mshr_miss_rate::1 inf # mshr miss rate for StoreCondReq accesses system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total inf # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_misses 28309 # number of StoreCondReq MSHR misses -system.cpu0.dcache.WriteReq_accesses::0 5847430 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 5847430 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_avg_miss_latency::0 55891.373878 # average WriteReq miss latency +system.cpu0.dcache.StoreCondReq_mshr_misses 17086 # number of StoreCondReq MSHR misses +system.cpu0.dcache.WriteReq_accesses::0 4822937 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 4822937 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_avg_miss_latency::0 54619.723929 # average WriteReq miss latency system.cpu0.dcache.WriteReq_avg_miss_latency::1 inf # average WriteReq miss latency system.cpu0.dcache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency 52891.373878 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency 51619.723929 # average WriteReq mshr miss latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_hits::0 5468175 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 5468175 # number of WriteReq hits -system.cpu0.dcache.WriteReq_miss_latency 21197083000 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_rate::0 0.064858 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_misses::0 379255 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 379255 # number of WriteReq misses -system.cpu0.dcache.WriteReq_mshr_miss_latency 20059318000 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_rate::0 0.064858 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_hits::0 4533446 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 4533446 # number of WriteReq hits +system.cpu0.dcache.WriteReq_miss_latency 15811918500 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_rate::0 0.060024 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_misses::0 289491 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 289491 # number of WriteReq misses +system.cpu0.dcache.WriteReq_mshr_miss_latency 14943445500 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_rate::0 0.060024 # mshr miss rate for WriteReq accesses system.cpu0.dcache.WriteReq_mshr_miss_rate::1 inf # mshr miss rate for WriteReq accesses system.cpu0.dcache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_misses 379255 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency 1240870000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_misses 289491 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency 1351640000 # number of WriteReq MSHR uncacheable cycles system.cpu0.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu0.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu0.dcache.avg_refs 9.990826 # Average number of references to valid blocks. +system.cpu0.dcache.avg_refs 9.594836 # Average number of references to valid blocks. system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.demand_accesses::0 14335823 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::0 12102927 # number of demand (read+write) accesses system.cpu0.dcache.demand_accesses::1 0 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 14335823 # number of demand (read+write) accesses -system.cpu0.dcache.demand_avg_miss_latency::0 33770.954076 # average overall miss latency +system.cpu0.dcache.demand_accesses::total 12102927 # number of demand (read+write) accesses +system.cpu0.dcache.demand_avg_miss_latency::0 33488.011912 # average overall miss latency system.cpu0.dcache.demand_avg_miss_latency::1 inf # average overall miss latency system.cpu0.dcache.demand_avg_miss_latency::total inf # average overall miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency 30770.925161 # average overall mshr miss latency -system.cpu0.dcache.demand_hits::0 12917865 # number of demand (read+write) hits +system.cpu0.dcache.demand_avg_mshr_miss_latency 30487.972244 # average overall mshr miss latency +system.cpu0.dcache.demand_hits::0 10880255 # number of demand (read+write) hits system.cpu0.dcache.demand_hits::1 0 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 12917865 # number of demand (read+write) hits -system.cpu0.dcache.demand_miss_latency 47885794500 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_rate::0 0.098910 # miss rate for demand accesses +system.cpu0.dcache.demand_hits::total 10880255 # number of demand (read+write) hits +system.cpu0.dcache.demand_miss_latency 40944854500 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_rate::0 0.101023 # miss rate for demand accesses system.cpu0.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses system.cpu0.dcache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu0.dcache.demand_misses::0 1417958 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::0 1222672 # number of demand (read+write) misses system.cpu0.dcache.demand_misses::1 0 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 1417958 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 1222672 # number of demand (read+write) misses system.cpu0.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_miss_latency 43631879500 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_rate::0 0.098910 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_latency 37276790000 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_rate::0 0.101023 # mshr miss rate for demand accesses system.cpu0.dcache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses system.cpu0.dcache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_misses 1417958 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses 1222672 # number of demand (read+write) MSHR misses system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.occ_%::0 0.983612 # Average percentage of cache occupancy -system.cpu0.dcache.occ_blocks::0 503.609177 # Average occupied blocks per context -system.cpu0.dcache.overall_accesses::0 14335823 # number of overall (read+write) accesses +system.cpu0.dcache.occ_%::0 0.971951 # Average percentage of cache occupancy +system.cpu0.dcache.occ_%::1 -0.001953 # Average percentage of cache occupancy +system.cpu0.dcache.occ_blocks::0 497.638883 # Average occupied blocks per context +system.cpu0.dcache.occ_blocks::1 -1.000000 # Average occupied blocks per context +system.cpu0.dcache.overall_accesses::0 12102927 # number of overall (read+write) accesses system.cpu0.dcache.overall_accesses::1 0 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 14335823 # number of overall (read+write) accesses -system.cpu0.dcache.overall_avg_miss_latency::0 33770.954076 # average overall miss latency +system.cpu0.dcache.overall_accesses::total 12102927 # number of overall (read+write) accesses +system.cpu0.dcache.overall_avg_miss_latency::0 33488.011912 # average overall miss latency system.cpu0.dcache.overall_avg_miss_latency::1 inf # average overall miss latency system.cpu0.dcache.overall_avg_miss_latency::total inf # average overall miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency 30770.925161 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency 30487.972244 # average overall mshr miss latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.cpu0.dcache.overall_hits::0 12917865 # number of overall hits +system.cpu0.dcache.overall_hits::0 10880255 # number of overall hits system.cpu0.dcache.overall_hits::1 0 # number of overall hits -system.cpu0.dcache.overall_hits::total 12917865 # number of overall hits -system.cpu0.dcache.overall_miss_latency 47885794500 # number of overall miss cycles -system.cpu0.dcache.overall_miss_rate::0 0.098910 # miss rate for overall accesses +system.cpu0.dcache.overall_hits::total 10880255 # number of overall hits +system.cpu0.dcache.overall_miss_latency 40944854500 # number of overall miss cycles +system.cpu0.dcache.overall_miss_rate::0 0.101023 # miss rate for overall accesses system.cpu0.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses system.cpu0.dcache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu0.dcache.overall_misses::0 1417958 # number of overall misses +system.cpu0.dcache.overall_misses::0 1222672 # number of overall misses system.cpu0.dcache.overall_misses::1 0 # number of overall misses -system.cpu0.dcache.overall_misses::total 1417958 # number of overall misses +system.cpu0.dcache.overall_misses::total 1222672 # number of overall misses system.cpu0.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_miss_latency 43631879500 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_rate::0 0.098910 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_latency 37276790000 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_rate::0 0.101023 # mshr miss rate for overall accesses system.cpu0.dcache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses system.cpu0.dcache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_misses 1417958 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_uncacheable_latency 2124474000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_misses 1222672 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_uncacheable_latency 2235239000 # number of overall MSHR uncacheable cycles system.cpu0.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu0.dcache.replacements 1338610 # number of replacements -system.cpu0.dcache.sampled_refs 1339122 # Sample count of references to valid blocks. +system.cpu0.dcache.replacements 1168722 # number of replacements +system.cpu0.dcache.sampled_refs 1169234 # Sample count of references to valid blocks. system.cpu0.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu0.dcache.tagsinuse 503.609177 # Cycle average of tags in use -system.cpu0.dcache.total_refs 13378935 # Total number of references to valid blocks. -system.cpu0.dcache.warmup_cycle 84055000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.writebacks 403520 # number of writebacks +system.cpu0.dcache.tagsinuse 496.638883 # Cycle average of tags in use +system.cpu0.dcache.total_refs 11218608 # Total number of references to valid blocks. +system.cpu0.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.writebacks 339648 # number of writebacks system.cpu0.dtb.data_accesses 719860 # DTB accesses system.cpu0.dtb.data_acv 289 # DTB access violations -system.cpu0.dtb.data_hits 14704826 # DTB hits +system.cpu0.dtb.data_hits 12394366 # DTB hits system.cpu0.dtb.data_misses 8485 # DTB misses system.cpu0.dtb.fetch_accesses 0 # ITB accesses system.cpu0.dtb.fetch_acv 0 # ITB acv @@ -159,106 +161,106 @@ system.cpu0.dtb.fetch_hits 0 # IT system.cpu0.dtb.fetch_misses 0 # ITB misses system.cpu0.dtb.read_accesses 524201 # DTB read accesses system.cpu0.dtb.read_acv 174 # DTB read access violations -system.cpu0.dtb.read_hits 8664724 # DTB read hits +system.cpu0.dtb.read_hits 7418432 # DTB read hits system.cpu0.dtb.read_misses 7687 # DTB read misses system.cpu0.dtb.write_accesses 195659 # DTB write accesses system.cpu0.dtb.write_acv 115 # DTB write access violations -system.cpu0.dtb.write_hits 6040102 # DTB write hits +system.cpu0.dtb.write_hits 4975934 # DTB write hits system.cpu0.dtb.write_misses 798 # DTB write misses -system.cpu0.icache.ReadReq_accesses::0 54164416 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 54164416 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_avg_miss_latency::0 14681.637172 # average ReadReq miss latency +system.cpu0.icache.ReadReq_accesses::0 47254591 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 47254591 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_avg_miss_latency::0 14914.060222 # average ReadReq miss latency system.cpu0.icache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency system.cpu0.icache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency 11680.885800 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_hits::0 53248092 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 53248092 # number of ReadReq hits -system.cpu0.icache.ReadReq_miss_latency 13453136500 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_rate::0 0.016917 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_misses::0 916324 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 916324 # number of ReadReq misses -system.cpu0.icache.ReadReq_mshr_miss_latency 10703476000 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::0 0.016917 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency 11912.744970 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_hits::0 46572212 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 46572212 # number of ReadReq hits +system.cpu0.icache.ReadReq_miss_latency 10177041500 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_rate::0 0.014440 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_misses::0 682379 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 682379 # number of ReadReq misses +system.cpu0.icache.ReadReq_mshr_miss_latency 8129007000 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::0 0.014440 # mshr miss rate for ReadReq accesses system.cpu0.icache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses system.cpu0.icache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_misses 916324 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses 682379 # number of ReadReq MSHR misses system.cpu0.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu0.icache.avg_refs 58.118732 # Average number of references to valid blocks. +system.cpu0.icache.avg_refs 68.262978 # Average number of references to valid blocks. system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.demand_accesses::0 54164416 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::0 47254591 # number of demand (read+write) accesses system.cpu0.icache.demand_accesses::1 0 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 54164416 # number of demand (read+write) accesses -system.cpu0.icache.demand_avg_miss_latency::0 14681.637172 # average overall miss latency +system.cpu0.icache.demand_accesses::total 47254591 # number of demand (read+write) accesses +system.cpu0.icache.demand_avg_miss_latency::0 14914.060222 # average overall miss latency system.cpu0.icache.demand_avg_miss_latency::1 inf # average overall miss latency system.cpu0.icache.demand_avg_miss_latency::total inf # average overall miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency 11680.885800 # average overall mshr miss latency -system.cpu0.icache.demand_hits::0 53248092 # number of demand (read+write) hits +system.cpu0.icache.demand_avg_mshr_miss_latency 11912.744970 # average overall mshr miss latency +system.cpu0.icache.demand_hits::0 46572212 # number of demand (read+write) hits system.cpu0.icache.demand_hits::1 0 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 53248092 # number of demand (read+write) hits -system.cpu0.icache.demand_miss_latency 13453136500 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_rate::0 0.016917 # miss rate for demand accesses +system.cpu0.icache.demand_hits::total 46572212 # number of demand (read+write) hits +system.cpu0.icache.demand_miss_latency 10177041500 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_rate::0 0.014440 # miss rate for demand accesses system.cpu0.icache.demand_miss_rate::1 no_value # miss rate for demand accesses system.cpu0.icache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu0.icache.demand_misses::0 916324 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::0 682379 # number of demand (read+write) misses system.cpu0.icache.demand_misses::1 0 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 916324 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 682379 # number of demand (read+write) misses system.cpu0.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_miss_latency 10703476000 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_rate::0 0.016917 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_latency 8129007000 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_rate::0 0.014440 # mshr miss rate for demand accesses system.cpu0.icache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses system.cpu0.icache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_misses 916324 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses 682379 # number of demand (read+write) MSHR misses system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.icache.occ_%::0 0.993443 # Average percentage of cache occupancy -system.cpu0.icache.occ_blocks::0 508.642782 # Average occupied blocks per context -system.cpu0.icache.overall_accesses::0 54164416 # number of overall (read+write) accesses +system.cpu0.icache.occ_%::0 0.993449 # Average percentage of cache occupancy +system.cpu0.icache.occ_blocks::0 508.646096 # Average occupied blocks per context +system.cpu0.icache.overall_accesses::0 47254591 # number of overall (read+write) accesses system.cpu0.icache.overall_accesses::1 0 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 54164416 # number of overall (read+write) accesses -system.cpu0.icache.overall_avg_miss_latency::0 14681.637172 # average overall miss latency +system.cpu0.icache.overall_accesses::total 47254591 # number of overall (read+write) accesses +system.cpu0.icache.overall_avg_miss_latency::0 14914.060222 # average overall miss latency system.cpu0.icache.overall_avg_miss_latency::1 inf # average overall miss latency system.cpu0.icache.overall_avg_miss_latency::total inf # average overall miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency 11680.885800 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency 11912.744970 # average overall mshr miss latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu0.icache.overall_hits::0 53248092 # number of overall hits +system.cpu0.icache.overall_hits::0 46572212 # number of overall hits system.cpu0.icache.overall_hits::1 0 # number of overall hits -system.cpu0.icache.overall_hits::total 53248092 # number of overall hits -system.cpu0.icache.overall_miss_latency 13453136500 # number of overall miss cycles -system.cpu0.icache.overall_miss_rate::0 0.016917 # miss rate for overall accesses +system.cpu0.icache.overall_hits::total 46572212 # number of overall hits +system.cpu0.icache.overall_miss_latency 10177041500 # number of overall miss cycles +system.cpu0.icache.overall_miss_rate::0 0.014440 # miss rate for overall accesses system.cpu0.icache.overall_miss_rate::1 no_value # miss rate for overall accesses system.cpu0.icache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu0.icache.overall_misses::0 916324 # number of overall misses +system.cpu0.icache.overall_misses::0 682379 # number of overall misses system.cpu0.icache.overall_misses::1 0 # number of overall misses -system.cpu0.icache.overall_misses::total 916324 # number of overall misses +system.cpu0.icache.overall_misses::total 682379 # number of overall misses system.cpu0.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_miss_latency 10703476000 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_rate::0 0.016917 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_latency 8129007000 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_rate::0 0.014440 # mshr miss rate for overall accesses system.cpu0.icache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses system.cpu0.icache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_misses 916324 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses 682379 # number of overall MSHR misses system.cpu0.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu0.icache.replacements 915684 # number of replacements -system.cpu0.icache.sampled_refs 916195 # Sample count of references to valid blocks. +system.cpu0.icache.replacements 681735 # number of replacements +system.cpu0.icache.sampled_refs 682247 # Sample count of references to valid blocks. system.cpu0.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu0.icache.tagsinuse 508.642782 # Cycle average of tags in use -system.cpu0.icache.total_refs 53248092 # Total number of references to valid blocks. -system.cpu0.icache.warmup_cycle 39455749000 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tagsinuse 508.646096 # Cycle average of tags in use +system.cpu0.icache.total_refs 46572212 # Total number of references to valid blocks. +system.cpu0.icache.warmup_cycle 38669170000 # Cycle when the warmup percentage was hit. system.cpu0.icache.writebacks 0 # number of writebacks -system.cpu0.idle_fraction 0.933160 # Percentage of idle cycles +system.cpu0.idle_fraction 0.943058 # Percentage of idle cycles system.cpu0.itb.data_accesses 0 # DTB accesses system.cpu0.itb.data_acv 0 # DTB access violations system.cpu0.itb.data_hits 0 # DTB hits system.cpu0.itb.data_misses 0 # DTB misses -system.cpu0.itb.fetch_accesses 3953747 # ITB accesses +system.cpu0.itb.fetch_accesses 3572127 # ITB accesses system.cpu0.itb.fetch_acv 143 # ITB acv -system.cpu0.itb.fetch_hits 3949906 # ITB hits +system.cpu0.itb.fetch_hits 3568286 # ITB hits system.cpu0.itb.fetch_misses 3841 # ITB misses system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.read_acv 0 # DTB read access violations @@ -269,63 +271,63 @@ system.cpu0.itb.write_acv 0 # DT system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses system.cpu0.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed -system.cpu0.kern.callpal::wripir 91 0.05% 0.05% # number of callpals executed -system.cpu0.kern.callpal::wrmces 1 0.00% 0.05% # number of callpals executed -system.cpu0.kern.callpal::wrfen 1 0.00% 0.05% # number of callpals executed -system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.05% # number of callpals executed -system.cpu0.kern.callpal::swpctx 3868 2.06% 2.11% # number of callpals executed -system.cpu0.kern.callpal::tbi 44 0.02% 2.13% # number of callpals executed -system.cpu0.kern.callpal::wrent 7 0.00% 2.13% # number of callpals executed -system.cpu0.kern.callpal::swpipl 172068 91.52% 93.65% # number of callpals executed -system.cpu0.kern.callpal::rdps 6698 3.56% 97.22% # number of callpals executed -system.cpu0.kern.callpal::wrkgp 1 0.00% 97.22% # number of callpals executed -system.cpu0.kern.callpal::wrusp 4 0.00% 97.22% # number of callpals executed -system.cpu0.kern.callpal::rdusp 7 0.00% 97.22% # number of callpals executed -system.cpu0.kern.callpal::whami 2 0.00% 97.22% # number of callpals executed -system.cpu0.kern.callpal::rti 4713 2.51% 99.73% # number of callpals executed -system.cpu0.kern.callpal::callsys 356 0.19% 99.92% # number of callpals executed -system.cpu0.kern.callpal::imb 149 0.08% 100.00% # number of callpals executed -system.cpu0.kern.callpal::total 188012 # number of callpals executed +system.cpu0.kern.callpal::wripir 540 0.37% 0.37% # number of callpals executed +system.cpu0.kern.callpal::wrmces 1 0.00% 0.37% # number of callpals executed +system.cpu0.kern.callpal::wrfen 1 0.00% 0.37% # number of callpals executed +system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.37% # number of callpals executed +system.cpu0.kern.callpal::swpctx 2975 2.03% 2.41% # number of callpals executed +system.cpu0.kern.callpal::tbi 44 0.03% 2.44% # number of callpals executed +system.cpu0.kern.callpal::wrent 7 0.00% 2.44% # number of callpals executed +system.cpu0.kern.callpal::swpipl 131234 89.72% 92.16% # number of callpals executed +system.cpu0.kern.callpal::rdps 6694 4.58% 96.73% # number of callpals executed +system.cpu0.kern.callpal::wrkgp 1 0.00% 96.73% # number of callpals executed +system.cpu0.kern.callpal::wrusp 4 0.00% 96.74% # number of callpals executed +system.cpu0.kern.callpal::rdusp 7 0.00% 96.74% # number of callpals executed +system.cpu0.kern.callpal::whami 2 0.00% 96.74% # number of callpals executed +system.cpu0.kern.callpal::rti 4260 2.91% 99.65% # number of callpals executed +system.cpu0.kern.callpal::callsys 356 0.24% 99.90% # number of callpals executed +system.cpu0.kern.callpal::imb 149 0.10% 100.00% # number of callpals executed +system.cpu0.kern.callpal::total 146277 # number of callpals executed system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.hwrei 202896 # number of hwrei instructions executed -system.cpu0.kern.inst.quiesce 6369 # number of quiesce instructions executed -system.cpu0.kern.ipl_count::0 72641 40.60% 40.60% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::21 131 0.07% 40.68% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::22 1987 1.11% 41.79% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::30 6 0.00% 41.79% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::31 104141 58.21% 100.00% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::total 178906 # number of times we switched to this ipl -system.cpu0.kern.ipl_good::0 71272 49.27% 49.27% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::21 131 0.09% 49.36% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::22 1987 1.37% 50.73% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::30 6 0.00% 50.74% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::31 71266 49.26% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::total 144662 # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_ticks::0 1908230091000 96.76% 96.76% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::21 96186500 0.00% 96.76% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::22 576952000 0.03% 96.79% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::30 5442500 0.00% 96.79% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::31 63226031000 3.21% 100.00% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::total 1972134703000 # number of cycles we spent at this ipl -system.cpu0.kern.ipl_used::0 0.981154 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.inst.hwrei 161605 # number of hwrei instructions executed +system.cpu0.kern.inst.quiesce 6835 # number of quiesce instructions executed +system.cpu0.kern.ipl_count::0 55380 40.11% 40.11% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::21 131 0.09% 40.21% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::22 1982 1.44% 41.64% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::30 455 0.33% 41.97% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::31 80115 58.03% 100.00% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::total 138063 # number of times we switched to this ipl +system.cpu0.kern.ipl_good::0 54908 49.06% 49.06% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::21 131 0.12% 49.17% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::22 1982 1.77% 50.94% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::30 455 0.41% 51.35% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::31 54453 48.65% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::total 111929 # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_ticks::0 1909262510000 97.06% 97.06% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::21 87868000 0.00% 97.06% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::22 573921000 0.03% 97.09% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::30 337802000 0.02% 97.11% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::31 56900501000 2.89% 100.00% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::total 1967162602000 # number of cycles we spent at this ipl +system.cpu0.kern.ipl_used::0 0.991477 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::31 0.684322 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::31 0.679685 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.mode_good::kernel 1231 system.cpu0.kern.mode_good::user 1232 system.cpu0.kern.mode_good::idle 0 -system.cpu0.kern.mode_switch::kernel 7237 # number of protection mode switches +system.cpu0.kern.mode_switch::kernel 6788 # number of protection mode switches system.cpu0.kern.mode_switch::user 1232 # number of protection mode switches system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches -system.cpu0.kern.mode_switch_good::kernel 0.170098 # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good::kernel 0.181349 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::idle no_value # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::total no_value # fraction of useful protection mode switches -system.cpu0.kern.mode_ticks::kernel 1968330503000 99.81% 99.81% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks::user 3804198000 0.19% 100.00% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::kernel 1963346065000 99.81% 99.81% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::user 3816535000 0.19% 100.00% # number of ticks spent at the given mode system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode -system.cpu0.kern.swap_context 3869 # number of times the context was actually changed +system.cpu0.kern.swap_context 2976 # number of times the context was actually changed system.cpu0.kern.syscall::2 6 2.68% 2.68% # number of syscalls executed system.cpu0.kern.syscall::3 19 8.48% 11.16% # number of syscalls executed system.cpu0.kern.syscall::4 3 1.34% 12.50% # number of syscalls executed @@ -357,154 +359,154 @@ system.cpu0.kern.syscall::132 2 0.89% 98.66% # nu system.cpu0.kern.syscall::144 1 0.45% 99.11% # number of syscalls executed system.cpu0.kern.syscall::147 2 0.89% 100.00% # number of syscalls executed system.cpu0.kern.syscall::total 224 # number of syscalls executed -system.cpu0.not_idle_fraction 0.066840 # Percentage of non-idle cycles -system.cpu0.numCycles 3944270922 # number of cpu cycles simulated -system.cpu0.num_insts 54155641 # Number of instructions executed -system.cpu0.num_refs 14946215 # Number of memory references -system.cpu1.dcache.LoadLockedReq_accesses::0 12334 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 12334 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::0 13303.501946 # average LoadLockedReq miss latency +system.cpu0.not_idle_fraction 0.056942 # Percentage of non-idle cycles +system.cpu0.numCycles 3934326694 # number of cpu cycles simulated +system.cpu0.num_insts 47245816 # Number of instructions executed +system.cpu0.num_refs 12627213 # Number of memory references +system.cpu1.dcache.LoadLockedReq_accesses::0 61432 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 61432 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::0 10283.624203 # average LoadLockedReq miss latency system.cpu1.dcache.LoadLockedReq_avg_miss_latency::1 inf # average LoadLockedReq miss latency system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total inf # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency 10303.501946 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_hits::0 11306 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 11306 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_miss_latency 13676000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_rate::0 0.083347 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_misses::0 1028 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 1028 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency 10592000 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::0 0.083347 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency 7283.624203 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_hits::0 51863 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 51863 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_miss_latency 98404000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_rate::0 0.155766 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_misses::0 9569 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 9569 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency 69697000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::0 0.155766 # mshr miss rate for LoadLockedReq accesses system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::1 inf # mshr miss rate for LoadLockedReq accesses system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total inf # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_misses 1028 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.ReadReq_accesses::0 1020543 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 1020543 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_avg_miss_latency::0 15771.782317 # average ReadReq miss latency +system.cpu1.dcache.LoadLockedReq_mshr_misses 9569 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.ReadReq_accesses::0 2468175 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 2468175 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_avg_miss_latency::0 13829.556740 # average ReadReq miss latency system.cpu1.dcache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency system.cpu1.dcache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency 12771.684387 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency 10829.528932 # average ReadReq mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.cpu1.dcache.ReadReq_hits::0 984803 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 984803 # number of ReadReq hits -system.cpu1.dcache.ReadReq_miss_latency 563683500 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_rate::0 0.035021 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_misses::0 35740 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 35740 # number of ReadReq misses -system.cpu1.dcache.ReadReq_mshr_miss_latency 456460000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::0 0.035021 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_hits::0 2342312 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 2342312 # number of ReadReq hits +system.cpu1.dcache.ReadReq_miss_latency 1740629500 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_rate::0 0.050994 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_misses::0 125863 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 125863 # number of ReadReq misses +system.cpu1.dcache.ReadReq_mshr_miss_latency 1363037000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::0 0.050994 # mshr miss rate for ReadReq accesses system.cpu1.dcache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses system.cpu1.dcache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_misses 35740 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses 125863 # number of ReadReq MSHR misses system.cpu1.dcache.ReadReq_mshr_uncacheable_latency 12526000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.StoreCondReq_accesses::0 12270 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 12270 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_avg_miss_latency::0 46841.453344 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_accesses::0 60921 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 60921 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_avg_miss_latency::0 35881.530265 # average StoreCondReq miss latency system.cpu1.dcache.StoreCondReq_avg_miss_latency::1 inf # average StoreCondReq miss latency system.cpu1.dcache.StoreCondReq_avg_miss_latency::total inf # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency 43841.453344 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_hits::0 9848 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 9848 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_miss_latency 113450000 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_rate::0 0.197392 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_misses::0 2422 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 2422 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_mshr_miss_latency 106184000 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::0 0.197392 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency 32881.530265 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_hits::0 47407 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 47407 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_miss_latency 484903000 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_rate::0 0.221828 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_misses::0 13514 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 13514 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_mshr_miss_latency 444361000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::0 0.221828 # mshr miss rate for StoreCondReq accesses system.cpu1.dcache.StoreCondReq_mshr_miss_rate::1 inf # mshr miss rate for StoreCondReq accesses system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total inf # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_misses 2422 # number of StoreCondReq MSHR misses -system.cpu1.dcache.WriteReq_accesses::0 650008 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 650008 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_avg_miss_latency::0 54644.846691 # average WriteReq miss latency +system.cpu1.dcache.StoreCondReq_mshr_misses 13514 # number of StoreCondReq MSHR misses +system.cpu1.dcache.WriteReq_accesses::0 1805806 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 1805806 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_avg_miss_latency::0 52324.342254 # average WriteReq miss latency system.cpu1.dcache.WriteReq_avg_miss_latency::1 inf # average WriteReq miss latency system.cpu1.dcache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency 51644.846691 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency 49324.342254 # average WriteReq mshr miss latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency -system.cpu1.dcache.WriteReq_hits::0 623656 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 623656 # number of WriteReq hits -system.cpu1.dcache.WriteReq_miss_latency 1440001000 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_rate::0 0.040541 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_misses::0 26352 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 26352 # number of WriteReq misses -system.cpu1.dcache.WriteReq_mshr_miss_latency 1360945000 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_rate::0 0.040541 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_hits::0 1713103 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 1713103 # number of WriteReq hits +system.cpu1.dcache.WriteReq_miss_latency 4850623500 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_rate::0 0.051336 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_misses::0 92703 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 92703 # number of WriteReq misses +system.cpu1.dcache.WriteReq_mshr_miss_latency 4572514500 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_rate::0 0.051336 # mshr miss rate for WriteReq accesses system.cpu1.dcache.WriteReq_mshr_miss_rate::1 inf # mshr miss rate for WriteReq accesses system.cpu1.dcache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_misses 26352 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency 303019000 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_misses 92703 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency 413889500 # number of WriteReq MSHR uncacheable cycles system.cpu1.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu1.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu1.dcache.avg_refs 30.141759 # Average number of references to valid blocks. +system.cpu1.dcache.avg_refs 23.182705 # Average number of references to valid blocks. system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.demand_accesses::0 1670551 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::0 4273981 # number of demand (read+write) accesses system.cpu1.dcache.demand_accesses::1 0 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 1670551 # number of demand (read+write) accesses -system.cpu1.dcache.demand_avg_miss_latency::0 32269.608001 # average overall miss latency +system.cpu1.dcache.demand_accesses::total 4273981 # number of demand (read+write) accesses +system.cpu1.dcache.demand_avg_miss_latency::0 30156.808470 # average overall miss latency system.cpu1.dcache.demand_avg_miss_latency::1 inf # average overall miss latency system.cpu1.dcache.demand_avg_miss_latency::total inf # average overall miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency 29269.551633 # average overall mshr miss latency -system.cpu1.dcache.demand_hits::0 1608459 # number of demand (read+write) hits +system.cpu1.dcache.demand_avg_mshr_miss_latency 27156.792456 # average overall mshr miss latency +system.cpu1.dcache.demand_hits::0 4055415 # number of demand (read+write) hits system.cpu1.dcache.demand_hits::1 0 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 1608459 # number of demand (read+write) hits -system.cpu1.dcache.demand_miss_latency 2003684500 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_rate::0 0.037169 # miss rate for demand accesses +system.cpu1.dcache.demand_hits::total 4055415 # number of demand (read+write) hits +system.cpu1.dcache.demand_miss_latency 6591253000 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_rate::0 0.051139 # miss rate for demand accesses system.cpu1.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses system.cpu1.dcache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu1.dcache.demand_misses::0 62092 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::0 218566 # number of demand (read+write) misses system.cpu1.dcache.demand_misses::1 0 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 62092 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 218566 # number of demand (read+write) misses system.cpu1.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_miss_latency 1817405000 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_rate::0 0.037169 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_latency 5935551500 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_rate::0 0.051139 # mshr miss rate for demand accesses system.cpu1.dcache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses system.cpu1.dcache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_misses 62092 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses 218566 # number of demand (read+write) MSHR misses system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.dcache.occ_%::0 0.759529 # Average percentage of cache occupancy -system.cpu1.dcache.occ_blocks::0 388.878897 # Average occupied blocks per context -system.cpu1.dcache.overall_accesses::0 1670551 # number of overall (read+write) accesses +system.cpu1.dcache.occ_%::0 0.916301 # Average percentage of cache occupancy +system.cpu1.dcache.occ_blocks::0 469.145893 # Average occupied blocks per context +system.cpu1.dcache.overall_accesses::0 4273981 # number of overall (read+write) accesses system.cpu1.dcache.overall_accesses::1 0 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 1670551 # number of overall (read+write) accesses -system.cpu1.dcache.overall_avg_miss_latency::0 32269.608001 # average overall miss latency +system.cpu1.dcache.overall_accesses::total 4273981 # number of overall (read+write) accesses +system.cpu1.dcache.overall_avg_miss_latency::0 30156.808470 # average overall miss latency system.cpu1.dcache.overall_avg_miss_latency::1 inf # average overall miss latency system.cpu1.dcache.overall_avg_miss_latency::total inf # average overall miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency 29269.551633 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency 27156.792456 # average overall mshr miss latency system.cpu1.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.cpu1.dcache.overall_hits::0 1608459 # number of overall hits +system.cpu1.dcache.overall_hits::0 4055415 # number of overall hits system.cpu1.dcache.overall_hits::1 0 # number of overall hits -system.cpu1.dcache.overall_hits::total 1608459 # number of overall hits -system.cpu1.dcache.overall_miss_latency 2003684500 # number of overall miss cycles -system.cpu1.dcache.overall_miss_rate::0 0.037169 # miss rate for overall accesses +system.cpu1.dcache.overall_hits::total 4055415 # number of overall hits +system.cpu1.dcache.overall_miss_latency 6591253000 # number of overall miss cycles +system.cpu1.dcache.overall_miss_rate::0 0.051139 # miss rate for overall accesses system.cpu1.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses system.cpu1.dcache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu1.dcache.overall_misses::0 62092 # number of overall misses +system.cpu1.dcache.overall_misses::0 218566 # number of overall misses system.cpu1.dcache.overall_misses::1 0 # number of overall misses -system.cpu1.dcache.overall_misses::total 62092 # number of overall misses +system.cpu1.dcache.overall_misses::total 218566 # number of overall misses system.cpu1.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_miss_latency 1817405000 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_rate::0 0.037169 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_latency 5935551500 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_rate::0 0.051139 # mshr miss rate for overall accesses system.cpu1.dcache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses system.cpu1.dcache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_misses 62092 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_uncacheable_latency 315545000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_misses 218566 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_uncacheable_latency 426415500 # number of overall MSHR uncacheable cycles system.cpu1.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu1.dcache.replacements 53724 # number of replacements -system.cpu1.dcache.sampled_refs 54120 # Sample count of references to valid blocks. +system.cpu1.dcache.replacements 180512 # number of replacements +system.cpu1.dcache.sampled_refs 180909 # Sample count of references to valid blocks. system.cpu1.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu1.dcache.tagsinuse 388.878897 # Cycle average of tags in use -system.cpu1.dcache.total_refs 1631272 # Total number of references to valid blocks. -system.cpu1.dcache.warmup_cycle 1954643578000 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.writebacks 26831 # number of writebacks +system.cpu1.dcache.tagsinuse 469.145893 # Cycle average of tags in use +system.cpu1.dcache.total_refs 4193960 # Total number of references to valid blocks. +system.cpu1.dcache.warmup_cycle 1949703501000 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.writebacks 96724 # number of writebacks system.cpu1.dtb.data_accesses 302878 # DTB accesses system.cpu1.dtb.data_acv 84 # DTB access violations -system.cpu1.dtb.data_hits 1693851 # DTB hits +system.cpu1.dtb.data_hits 4382020 # DTB hits system.cpu1.dtb.data_misses 3106 # DTB misses system.cpu1.dtb.fetch_accesses 0 # ITB accesses system.cpu1.dtb.fetch_acv 0 # ITB acv @@ -512,106 +514,106 @@ system.cpu1.dtb.fetch_hits 0 # IT system.cpu1.dtb.fetch_misses 0 # ITB misses system.cpu1.dtb.read_accesses 205838 # DTB read accesses system.cpu1.dtb.read_acv 36 # DTB read access violations -system.cpu1.dtb.read_hits 1029710 # DTB read hits +system.cpu1.dtb.read_hits 2517470 # DTB read hits system.cpu1.dtb.read_misses 2750 # DTB read misses system.cpu1.dtb.write_accesses 97040 # DTB write accesses system.cpu1.dtb.write_acv 48 # DTB write access violations -system.cpu1.dtb.write_hits 664141 # DTB write hits +system.cpu1.dtb.write_hits 1864550 # DTB write hits system.cpu1.dtb.write_misses 356 # DTB write misses -system.cpu1.icache.ReadReq_accesses::0 5268142 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 5268142 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_avg_miss_latency::0 14617.211446 # average ReadReq miss latency +system.cpu1.icache.ReadReq_accesses::0 13824268 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 13824268 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_avg_miss_latency::0 14182.361205 # average ReadReq miss latency system.cpu1.icache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency system.cpu1.icache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency 11616.771124 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_hits::0 5180706 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 5180706 # number of ReadReq hits -system.cpu1.icache.ReadReq_miss_latency 1278070500 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_rate::0 0.016597 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_misses::0 87436 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 87436 # number of ReadReq misses -system.cpu1.icache.ReadReq_mshr_miss_latency 1015724000 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::0 0.016597 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency 11182.239180 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_hits::0 13488270 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 13488270 # number of ReadReq hits +system.cpu1.icache.ReadReq_miss_latency 4765245000 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_rate::0 0.024305 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_misses::0 335998 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 335998 # number of ReadReq misses +system.cpu1.icache.ReadReq_mshr_miss_latency 3757210000 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::0 0.024305 # mshr miss rate for ReadReq accesses system.cpu1.icache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses system.cpu1.icache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_misses 87436 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses 335998 # number of ReadReq MSHR misses system.cpu1.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu1.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu1.icache.avg_refs 59.270387 # Average number of references to valid blocks. +system.cpu1.icache.avg_refs 40.147245 # Average number of references to valid blocks. system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.demand_accesses::0 5268142 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::0 13824268 # number of demand (read+write) accesses system.cpu1.icache.demand_accesses::1 0 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 5268142 # number of demand (read+write) accesses -system.cpu1.icache.demand_avg_miss_latency::0 14617.211446 # average overall miss latency +system.cpu1.icache.demand_accesses::total 13824268 # number of demand (read+write) accesses +system.cpu1.icache.demand_avg_miss_latency::0 14182.361205 # average overall miss latency system.cpu1.icache.demand_avg_miss_latency::1 inf # average overall miss latency system.cpu1.icache.demand_avg_miss_latency::total inf # average overall miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency 11616.771124 # average overall mshr miss latency -system.cpu1.icache.demand_hits::0 5180706 # number of demand (read+write) hits +system.cpu1.icache.demand_avg_mshr_miss_latency 11182.239180 # average overall mshr miss latency +system.cpu1.icache.demand_hits::0 13488270 # number of demand (read+write) hits system.cpu1.icache.demand_hits::1 0 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 5180706 # number of demand (read+write) hits -system.cpu1.icache.demand_miss_latency 1278070500 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_rate::0 0.016597 # miss rate for demand accesses +system.cpu1.icache.demand_hits::total 13488270 # number of demand (read+write) hits +system.cpu1.icache.demand_miss_latency 4765245000 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_rate::0 0.024305 # miss rate for demand accesses system.cpu1.icache.demand_miss_rate::1 no_value # miss rate for demand accesses system.cpu1.icache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu1.icache.demand_misses::0 87436 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::0 335998 # number of demand (read+write) misses system.cpu1.icache.demand_misses::1 0 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 87436 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 335998 # number of demand (read+write) misses system.cpu1.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu1.icache.demand_mshr_miss_latency 1015724000 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_rate::0 0.016597 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_latency 3757210000 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_rate::0 0.024305 # mshr miss rate for demand accesses system.cpu1.icache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses system.cpu1.icache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_misses 87436 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses 335998 # number of demand (read+write) MSHR misses system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.icache.occ_%::0 0.819152 # Average percentage of cache occupancy -system.cpu1.icache.occ_blocks::0 419.405627 # Average occupied blocks per context -system.cpu1.icache.overall_accesses::0 5268142 # number of overall (read+write) accesses +system.cpu1.icache.occ_%::0 0.872600 # Average percentage of cache occupancy +system.cpu1.icache.occ_blocks::0 446.771254 # Average occupied blocks per context +system.cpu1.icache.overall_accesses::0 13824268 # number of overall (read+write) accesses system.cpu1.icache.overall_accesses::1 0 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 5268142 # number of overall (read+write) accesses -system.cpu1.icache.overall_avg_miss_latency::0 14617.211446 # average overall miss latency +system.cpu1.icache.overall_accesses::total 13824268 # number of overall (read+write) accesses +system.cpu1.icache.overall_avg_miss_latency::0 14182.361205 # average overall miss latency system.cpu1.icache.overall_avg_miss_latency::1 inf # average overall miss latency system.cpu1.icache.overall_avg_miss_latency::total inf # average overall miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency 11616.771124 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency 11182.239180 # average overall mshr miss latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu1.icache.overall_hits::0 5180706 # number of overall hits +system.cpu1.icache.overall_hits::0 13488270 # number of overall hits system.cpu1.icache.overall_hits::1 0 # number of overall hits -system.cpu1.icache.overall_hits::total 5180706 # number of overall hits -system.cpu1.icache.overall_miss_latency 1278070500 # number of overall miss cycles -system.cpu1.icache.overall_miss_rate::0 0.016597 # miss rate for overall accesses +system.cpu1.icache.overall_hits::total 13488270 # number of overall hits +system.cpu1.icache.overall_miss_latency 4765245000 # number of overall miss cycles +system.cpu1.icache.overall_miss_rate::0 0.024305 # miss rate for overall accesses system.cpu1.icache.overall_miss_rate::1 no_value # miss rate for overall accesses system.cpu1.icache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu1.icache.overall_misses::0 87436 # number of overall misses +system.cpu1.icache.overall_misses::0 335998 # number of overall misses system.cpu1.icache.overall_misses::1 0 # number of overall misses -system.cpu1.icache.overall_misses::total 87436 # number of overall misses +system.cpu1.icache.overall_misses::total 335998 # number of overall misses system.cpu1.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu1.icache.overall_mshr_miss_latency 1015724000 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_rate::0 0.016597 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_latency 3757210000 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_rate::0 0.024305 # mshr miss rate for overall accesses system.cpu1.icache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses system.cpu1.icache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_misses 87436 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses 335998 # number of overall MSHR misses system.cpu1.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu1.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu1.icache.replacements 86896 # number of replacements -system.cpu1.icache.sampled_refs 87408 # Sample count of references to valid blocks. +system.cpu1.icache.replacements 335458 # number of replacements +system.cpu1.icache.sampled_refs 335970 # Sample count of references to valid blocks. system.cpu1.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu1.icache.tagsinuse 419.405627 # Cycle average of tags in use -system.cpu1.icache.total_refs 5180706 # Total number of references to valid blocks. -system.cpu1.icache.warmup_cycle 1967880295000 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tagsinuse 446.771254 # Cycle average of tags in use +system.cpu1.icache.total_refs 13488270 # Total number of references to valid blocks. +system.cpu1.icache.warmup_cycle 1962800602000 # Cycle when the warmup percentage was hit. system.cpu1.icache.writebacks 0 # number of writebacks -system.cpu1.idle_fraction 0.994655 # Percentage of idle cycles +system.cpu1.idle_fraction 0.984741 # Percentage of idle cycles system.cpu1.itb.data_accesses 0 # DTB accesses system.cpu1.itb.data_acv 0 # DTB access violations system.cpu1.itb.data_hits 0 # DTB hits system.cpu1.itb.data_misses 0 # DTB misses -system.cpu1.itb.fetch_accesses 1397517 # ITB accesses +system.cpu1.itb.fetch_accesses 1913285 # ITB accesses system.cpu1.itb.fetch_acv 41 # ITB acv -system.cpu1.itb.fetch_hits 1396271 # ITB hits +system.cpu1.itb.fetch_hits 1912039 # ITB hits system.cpu1.itb.fetch_misses 1246 # ITB misses system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.read_acv 0 # DTB read access violations @@ -622,59 +624,59 @@ system.cpu1.itb.write_acv 0 # DT system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses system.cpu1.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed -system.cpu1.kern.callpal::wripir 6 0.02% 0.02% # number of callpals executed -system.cpu1.kern.callpal::wrmces 1 0.00% 0.03% # number of callpals executed -system.cpu1.kern.callpal::wrfen 1 0.00% 0.03% # number of callpals executed -system.cpu1.kern.callpal::swpctx 365 1.24% 1.27% # number of callpals executed -system.cpu1.kern.callpal::tbi 10 0.03% 1.30% # number of callpals executed -system.cpu1.kern.callpal::wrent 7 0.02% 1.33% # number of callpals executed -system.cpu1.kern.callpal::swpipl 24144 81.84% 83.16% # number of callpals executed -system.cpu1.kern.callpal::rdps 2172 7.36% 90.52% # number of callpals executed -system.cpu1.kern.callpal::wrkgp 1 0.00% 90.53% # number of callpals executed -system.cpu1.kern.callpal::wrusp 3 0.01% 90.54% # number of callpals executed -system.cpu1.kern.callpal::rdusp 2 0.01% 90.54% # number of callpals executed -system.cpu1.kern.callpal::whami 3 0.01% 90.55% # number of callpals executed -system.cpu1.kern.callpal::rti 2594 8.79% 99.35% # number of callpals executed -system.cpu1.kern.callpal::callsys 161 0.55% 99.89% # number of callpals executed -system.cpu1.kern.callpal::imb 31 0.11% 100.00% # number of callpals executed +system.cpu1.kern.callpal::wripir 455 0.60% 0.60% # number of callpals executed +system.cpu1.kern.callpal::wrmces 1 0.00% 0.60% # number of callpals executed +system.cpu1.kern.callpal::wrfen 1 0.00% 0.61% # number of callpals executed +system.cpu1.kern.callpal::swpctx 2159 2.85% 3.46% # number of callpals executed +system.cpu1.kern.callpal::tbi 10 0.01% 3.47% # number of callpals executed +system.cpu1.kern.callpal::wrent 7 0.01% 3.48% # number of callpals executed +system.cpu1.kern.callpal::swpipl 66683 88.18% 91.66% # number of callpals executed +system.cpu1.kern.callpal::rdps 2168 2.87% 94.53% # number of callpals executed +system.cpu1.kern.callpal::wrkgp 1 0.00% 94.53% # number of callpals executed +system.cpu1.kern.callpal::wrusp 3 0.00% 94.53% # number of callpals executed +system.cpu1.kern.callpal::rdusp 2 0.00% 94.54% # number of callpals executed +system.cpu1.kern.callpal::whami 3 0.00% 94.54% # number of callpals executed +system.cpu1.kern.callpal::rti 3936 5.20% 99.74% # number of callpals executed +system.cpu1.kern.callpal::callsys 161 0.21% 99.96% # number of callpals executed +system.cpu1.kern.callpal::imb 31 0.04% 100.00% # number of callpals executed system.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed -system.cpu1.kern.callpal::total 29503 # number of callpals executed +system.cpu1.kern.callpal::total 75623 # number of callpals executed system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.hwrei 36053 # number of hwrei instructions executed -system.cpu1.kern.inst.quiesce 2351 # number of quiesce instructions executed -system.cpu1.kern.ipl_count::0 9173 31.84% 31.84% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::22 1980 6.87% 38.71% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::30 91 0.32% 39.03% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::31 17566 60.97% 100.00% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::total 28810 # number of times we switched to this ipl -system.cpu1.kern.ipl_good::0 9165 45.13% 45.13% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::22 1980 9.75% 54.87% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::30 91 0.45% 55.32% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::31 9074 44.68% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::total 20310 # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_ticks::0 1927968787500 97.78% 97.78% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::22 511194500 0.03% 97.81% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::30 58584000 0.00% 97.81% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::31 43145271000 2.19% 100.00% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::total 1971683837000 # number of cycles we spent at this ipl -system.cpu1.kern.ipl_used::0 0.999128 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.inst.hwrei 82618 # number of hwrei instructions executed +system.cpu1.kern.inst.quiesce 2771 # number of quiesce instructions executed +system.cpu1.kern.ipl_count::0 28203 38.56% 38.56% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::22 1977 2.70% 41.27% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::30 540 0.74% 42.00% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::31 42416 58.00% 100.00% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::total 73136 # number of times we switched to this ipl +system.cpu1.kern.ipl_good::0 27298 48.25% 48.25% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::22 1977 3.49% 51.75% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::30 540 0.95% 52.70% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::31 26759 47.30% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::total 56574 # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_ticks::0 1915291540500 97.38% 97.38% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::22 515904000 0.03% 97.41% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::30 422495500 0.02% 97.43% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::31 50571037000 2.57% 100.00% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::total 1966800977000 # number of cycles we spent at this ipl +system.cpu1.kern.ipl_used::0 0.967911 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::31 0.516566 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.mode_good::kernel 532 -system.cpu1.kern.mode_good::user 516 -system.cpu1.kern.mode_good::idle 16 -system.cpu1.kern.mode_switch::kernel 880 # number of protection mode switches -system.cpu1.kern.mode_switch::user 516 # number of protection mode switches -system.cpu1.kern.mode_switch::idle 2081 # number of protection mode switches -system.cpu1.kern.mode_switch_good::kernel 0.604545 # fraction of useful protection mode switches +system.cpu1.kern.ipl_used::31 0.630870 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.mode_good::kernel 981 +system.cpu1.kern.mode_good::user 517 +system.cpu1.kern.mode_good::idle 464 +system.cpu1.kern.mode_switch::kernel 2246 # number of protection mode switches +system.cpu1.kern.mode_switch::user 517 # number of protection mode switches +system.cpu1.kern.mode_switch::idle 2954 # number of protection mode switches +system.cpu1.kern.mode_switch_good::kernel 0.436776 # fraction of useful protection mode switches system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::idle 0.007689 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::total 1.612234 # fraction of useful protection mode switches -system.cpu1.kern.mode_ticks::kernel 4596640000 0.23% 0.23% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::user 1703543000 0.09% 0.32% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::idle 1964670722000 99.68% 100.00% # number of ticks spent at the given mode -system.cpu1.kern.swap_context 366 # number of times the context was actually changed +system.cpu1.kern.mode_switch_good::idle 0.157075 # fraction of useful protection mode switches +system.cpu1.kern.mode_switch_good::total 1.593852 # fraction of useful protection mode switches +system.cpu1.kern.mode_ticks::kernel 23054472000 1.17% 1.17% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::user 1704524000 0.09% 1.26% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::idle 1941246244000 98.74% 100.00% # number of ticks spent at the given mode +system.cpu1.kern.swap_context 2160 # number of times the context was actually changed system.cpu1.kern.syscall::2 2 1.96% 1.96% # number of syscalls executed system.cpu1.kern.syscall::3 11 10.78% 12.75% # number of syscalls executed system.cpu1.kern.syscall::4 1 0.98% 13.73% # number of syscalls executed @@ -697,10 +699,10 @@ system.cpu1.kern.syscall::92 2 1.96% 97.06% # nu system.cpu1.kern.syscall::132 2 1.96% 99.02% # number of syscalls executed system.cpu1.kern.syscall::144 1 0.98% 100.00% # number of syscalls executed system.cpu1.kern.syscall::total 102 # number of syscalls executed -system.cpu1.not_idle_fraction 0.005345 # Percentage of non-idle cycles -system.cpu1.numCycles 3943367734 # number of cpu cycles simulated -system.cpu1.num_insts 5264952 # Number of instructions executed -system.cpu1.num_refs 1703740 # Number of memory references +system.cpu1.not_idle_fraction 0.015259 # Percentage of non-idle cycles +system.cpu1.numCycles 3933602014 # number of cpu cycles simulated +system.cpu1.num_insts 13821078 # Number of instructions executed +system.cpu1.num_refs 4410345 # Number of memory references system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). @@ -713,282 +715,290 @@ system.disk2.dma_read_txs 0 # Nu system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. system.disk2.dma_write_txs 1 # Number of DMA write transactions. -system.iocache.ReadReq_accesses::1 178 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 178 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::1 174 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 174 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_avg_miss_latency::0 inf # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::1 115196.617978 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::1 115247.114943 # average ReadReq miss latency system.iocache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.iocache.ReadReq_avg_mshr_miss_latency 63196.617978 # average ReadReq mshr miss latency -system.iocache.ReadReq_miss_latency 20504998 # number of ReadReq miss cycles +system.iocache.ReadReq_avg_mshr_miss_latency 63247.114943 # average ReadReq mshr miss latency +system.iocache.ReadReq_miss_latency 20052998 # number of ReadReq miss cycles system.iocache.ReadReq_miss_rate::1 1 # miss rate for ReadReq accesses -system.iocache.ReadReq_misses::1 178 # number of ReadReq misses -system.iocache.ReadReq_misses::total 178 # number of ReadReq misses -system.iocache.ReadReq_mshr_miss_latency 11248998 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_misses::1 174 # number of ReadReq misses +system.iocache.ReadReq_misses::total 174 # number of ReadReq misses +system.iocache.ReadReq_mshr_miss_latency 11004998 # number of ReadReq MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::0 inf # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::1 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.iocache.ReadReq_mshr_misses 178 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses 174 # number of ReadReq MSHR misses system.iocache.WriteReq_accesses::1 41552 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 41552 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_avg_miss_latency::0 inf # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::1 137902.310503 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::1 137872.733106 # average WriteReq miss latency system.iocache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency -system.iocache.WriteReq_avg_mshr_miss_latency 85898.702349 # average WriteReq mshr miss latency -system.iocache.WriteReq_miss_latency 5730116806 # number of WriteReq miss cycles +system.iocache.WriteReq_avg_mshr_miss_latency 85869.242491 # average WriteReq mshr miss latency +system.iocache.WriteReq_miss_latency 5728887806 # number of WriteReq miss cycles system.iocache.WriteReq_miss_rate::1 1 # miss rate for WriteReq accesses system.iocache.WriteReq_misses::1 41552 # number of WriteReq misses system.iocache.WriteReq_misses::total 41552 # number of WriteReq misses -system.iocache.WriteReq_mshr_miss_latency 3569262880 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency 3568038764 # number of WriteReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_rate::0 inf # mshr miss rate for WriteReq accesses system.iocache.WriteReq_mshr_miss_rate::1 1 # mshr miss rate for WriteReq accesses system.iocache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses system.iocache.WriteReq_mshr_misses 41552 # number of WriteReq MSHR misses -system.iocache.avg_blocked_cycles::no_mshrs 6169.706090 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 6165.774548 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.iocache.avg_refs 0 # Average number of references to valid blocks. system.iocache.blocked::no_mshrs 10459 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.blocked_cycles::no_mshrs 64528956 # number of cycles access was blocked +system.iocache.blocked_cycles::no_mshrs 64487836 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.iocache.cache_copies 0 # number of cache copies performed system.iocache.demand_accesses::0 0 # number of demand (read+write) accesses -system.iocache.demand_accesses::1 41730 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 41730 # number of demand (read+write) accesses +system.iocache.demand_accesses::1 41726 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 41726 # number of demand (read+write) accesses system.iocache.demand_avg_miss_latency::0 inf # average overall miss latency -system.iocache.demand_avg_miss_latency::1 137805.458998 # average overall miss latency +system.iocache.demand_avg_miss_latency::1 137778.382879 # average overall miss latency system.iocache.demand_avg_miss_latency::total inf # average overall miss latency -system.iocache.demand_avg_mshr_miss_latency 85801.866235 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency 85774.906821 # average overall mshr miss latency system.iocache.demand_hits::0 0 # number of demand (read+write) hits system.iocache.demand_hits::1 0 # number of demand (read+write) hits system.iocache.demand_hits::total 0 # number of demand (read+write) hits -system.iocache.demand_miss_latency 5750621804 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency 5748940804 # number of demand (read+write) miss cycles system.iocache.demand_miss_rate::0 no_value # miss rate for demand accesses system.iocache.demand_miss_rate::1 1 # miss rate for demand accesses system.iocache.demand_miss_rate::total no_value # miss rate for demand accesses system.iocache.demand_misses::0 0 # number of demand (read+write) misses -system.iocache.demand_misses::1 41730 # number of demand (read+write) misses -system.iocache.demand_misses::total 41730 # number of demand (read+write) misses +system.iocache.demand_misses::1 41726 # number of demand (read+write) misses +system.iocache.demand_misses::total 41726 # number of demand (read+write) misses system.iocache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.iocache.demand_mshr_miss_latency 3580511878 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency 3579043762 # number of demand (read+write) MSHR miss cycles system.iocache.demand_mshr_miss_rate::0 inf # mshr miss rate for demand accesses system.iocache.demand_mshr_miss_rate::1 1 # mshr miss rate for demand accesses system.iocache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.iocache.demand_mshr_misses 41730 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses 41726 # number of demand (read+write) MSHR misses system.iocache.fast_writes 0 # number of fast writes performed system.iocache.mshr_cap_events 0 # number of times MSHR cap was activated system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.iocache.occ_%::1 0.036380 # Average percentage of cache occupancy -system.iocache.occ_blocks::1 0.582075 # Average occupied blocks per context +system.iocache.occ_%::1 0.036248 # Average percentage of cache occupancy +system.iocache.occ_blocks::1 0.579966 # Average occupied blocks per context system.iocache.overall_accesses::0 0 # number of overall (read+write) accesses -system.iocache.overall_accesses::1 41730 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 41730 # number of overall (read+write) accesses +system.iocache.overall_accesses::1 41726 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 41726 # number of overall (read+write) accesses system.iocache.overall_avg_miss_latency::0 inf # average overall miss latency -system.iocache.overall_avg_miss_latency::1 137805.458998 # average overall miss latency +system.iocache.overall_avg_miss_latency::1 137778.382879 # average overall miss latency system.iocache.overall_avg_miss_latency::total inf # average overall miss latency -system.iocache.overall_avg_mshr_miss_latency 85801.866235 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency 85774.906821 # average overall mshr miss latency system.iocache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.iocache.overall_hits::0 0 # number of overall hits system.iocache.overall_hits::1 0 # number of overall hits system.iocache.overall_hits::total 0 # number of overall hits -system.iocache.overall_miss_latency 5750621804 # number of overall miss cycles +system.iocache.overall_miss_latency 5748940804 # number of overall miss cycles system.iocache.overall_miss_rate::0 no_value # miss rate for overall accesses system.iocache.overall_miss_rate::1 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total no_value # miss rate for overall accesses system.iocache.overall_misses::0 0 # number of overall misses -system.iocache.overall_misses::1 41730 # number of overall misses -system.iocache.overall_misses::total 41730 # number of overall misses +system.iocache.overall_misses::1 41726 # number of overall misses +system.iocache.overall_misses::total 41726 # number of overall misses system.iocache.overall_mshr_hits 0 # number of overall MSHR hits -system.iocache.overall_mshr_miss_latency 3580511878 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency 3579043762 # number of overall MSHR miss cycles system.iocache.overall_mshr_miss_rate::0 inf # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::1 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.iocache.overall_mshr_misses 41730 # number of overall MSHR misses +system.iocache.overall_mshr_misses 41726 # number of overall MSHR misses system.iocache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.iocache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.iocache.replacements 41698 # number of replacements -system.iocache.sampled_refs 41714 # Sample count of references to valid blocks. +system.iocache.replacements 41694 # number of replacements +system.iocache.sampled_refs 41710 # Sample count of references to valid blocks. system.iocache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.iocache.tagsinuse 0.582075 # Cycle average of tags in use +system.iocache.tagsinuse 0.579966 # Cycle average of tags in use system.iocache.total_refs 0 # Total number of references to valid blocks. -system.iocache.warmup_cycle 1762323389000 # Cycle when the warmup percentage was hit. +system.iocache.warmup_cycle 1759378217000 # Cycle when the warmup percentage was hit. system.iocache.writebacks 41520 # number of writebacks -system.l2c.ReadExReq_accesses::0 285538 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::1 21276 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 306814 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_avg_miss_latency::0 55877.476903 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::1 749912.718556 # average ReadExReq miss latency +system.l2c.ReadExReq_accesses::0 236787 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::1 61172 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 297959 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_avg_miss_latency::0 65502.824330 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::1 252326.309748 # average ReadExReq miss latency system.l2c.ReadExReq_avg_miss_latency::2 inf # average ReadExReq miss latency system.l2c.ReadExReq_avg_miss_latency::total inf # average ReadExReq miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency 40002.656333 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_miss_latency 15955143000 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_rate::0 1 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::1 1 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_misses::0 285538 # number of ReadExReq misses -system.l2c.ReadExReq_misses::1 21276 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 306814 # number of ReadExReq misses -system.l2c.ReadExReq_mshr_miss_latency 12273375000 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_rate::0 1.074512 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::1 14.420662 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_avg_mshr_miss_latency 40003.055004 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_hits::0 1864 # number of ReadExReq hits +system.l2c.ReadExReq_hits::1 187 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 2051 # number of ReadExReq hits +system.l2c.ReadExReq_miss_latency 15388120000 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_rate::0 0.992128 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::1 0.996943 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_misses::0 234923 # number of ReadExReq misses +system.l2c.ReadExReq_misses::1 60985 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 295908 # number of ReadExReq misses +system.l2c.ReadExReq_mshr_miss_latency 11837224000 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_rate::0 1.249680 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::1 4.837311 # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::2 inf # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::total inf # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_misses 306814 # number of ReadExReq MSHR misses -system.l2c.ReadReq_accesses::0 1969770 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::1 120535 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 2090305 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_avg_miss_latency::0 52549.257150 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::1 5128541.212316 # average ReadReq miss latency +system.l2c.ReadExReq_mshr_misses 295908 # number of ReadExReq MSHR misses +system.l2c.ReadReq_accesses::0 1614705 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::1 454179 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 2068884 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_avg_miss_latency::0 52561.218952 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::1 5017624.332810 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::2 inf # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.l2c.ReadReq_avg_mshr_miss_latency 40016.323583 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency 40016.414894 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_hits::0 1665469 # number of ReadReq hits -system.l2c.ReadReq_hits::1 117417 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1782886 # number of ReadReq hits -system.l2c.ReadReq_miss_latency 15990791500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_rate::0 0.154486 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::1 0.025868 # miss rate for ReadReq accesses -system.l2c.ReadReq_misses::0 304301 # number of ReadReq misses -system.l2c.ReadReq_misses::1 3118 # number of ReadReq misses -system.l2c.ReadReq_misses::total 307419 # number of ReadReq misses -system.l2c.ReadReq_mshr_hits 11 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_miss_latency 12301338000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_rate::0 0.156063 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::1 2.550363 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_hits::0 1310657 # number of ReadReq hits +system.l2c.ReadReq_hits::1 450994 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1761651 # number of ReadReq hits +system.l2c.ReadReq_miss_latency 15981133500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_rate::0 0.188299 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::1 0.007013 # miss rate for ReadReq accesses +system.l2c.ReadReq_misses::0 304048 # number of ReadReq misses +system.l2c.ReadReq_misses::1 3185 # number of ReadReq misses +system.l2c.ReadReq_misses::total 307233 # number of ReadReq misses +system.l2c.ReadReq_mshr_hits 12 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_miss_latency 12293883000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_rate::0 0.190264 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::1 0.676432 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::2 inf # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_misses 307408 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_uncacheable_latency 802543000 # number of ReadReq MSHR uncacheable cycles -system.l2c.SCUpgradeReq_accesses::0 27944 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::1 1988 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 29932 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_avg_miss_latency::0 55471.228171 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::1 779722.334004 # average SCUpgradeReq miss latency +system.l2c.ReadReq_mshr_misses 307221 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_uncacheable_latency 802535000 # number of ReadReq MSHR uncacheable cycles +system.l2c.SCUpgradeReq_accesses::0 12669 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::1 8188 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::total 20857 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_avg_miss_latency::0 78597.820938 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::1 121582.804104 # average SCUpgradeReq miss latency system.l2c.SCUpgradeReq_avg_miss_latency::2 inf # average SCUpgradeReq miss latency system.l2c.SCUpgradeReq_avg_miss_latency::total inf # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency 40002.405452 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_miss_latency 1550088000 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_rate::0 1 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_avg_mshr_miss_latency 40004.028004 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_hits::0 3 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 3 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_miss_latency 995520000 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_rate::0 0.999763 # miss rate for SCUpgradeReq accesses system.l2c.SCUpgradeReq_miss_rate::1 1 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_misses::0 27944 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::1 1988 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 29932 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_mshr_miss_latency 1197352000 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_rate::0 1.071142 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::1 15.056338 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_misses::0 12666 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::1 8188 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::total 20854 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_mshr_miss_latency 834244000 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_rate::0 1.646065 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::1 2.546898 # mshr miss rate for SCUpgradeReq accesses system.l2c.SCUpgradeReq_mshr_miss_rate::2 inf # mshr miss rate for SCUpgradeReq accesses system.l2c.SCUpgradeReq_mshr_miss_rate::total inf # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_misses 29932 # number of SCUpgradeReq MSHR misses -system.l2c.UpgradeReq_accesses::0 92926 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::1 4380 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 97306 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_avg_miss_latency::0 52795.955922 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::1 1120118.036530 # average UpgradeReq miss latency +system.l2c.SCUpgradeReq_mshr_misses 20854 # number of SCUpgradeReq MSHR misses +system.l2c.UpgradeReq_accesses::0 46404 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::1 25015 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 71419 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_avg_miss_latency::0 74757.458826 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::1 138647.409244 # average UpgradeReq miss latency system.l2c.UpgradeReq_avg_miss_latency::2 inf # average UpgradeReq miss latency system.l2c.UpgradeReq_avg_miss_latency::total inf # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency 40006.114731 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_miss_latency 4906117000 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_rate::0 1 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::1 1 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_misses::0 92926 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::1 4380 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 97306 # number of UpgradeReq misses -system.l2c.UpgradeReq_mshr_miss_latency 3892835000 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_rate::0 1.047134 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::1 22.215982 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_avg_mshr_miss_latency 40008.977591 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_hits::0 16 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::1 3 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 19 # number of UpgradeReq hits +system.l2c.UpgradeReq_miss_latency 3467849000 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_rate::0 0.999655 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::1 0.999880 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_misses::0 46388 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::1 25012 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 71400 # number of UpgradeReq misses +system.l2c.UpgradeReq_mshr_miss_latency 2856641000 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_rate::0 1.538660 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::1 2.854287 # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::2 inf # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::total inf # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_misses 97306 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses 71400 # number of UpgradeReq MSHR misses system.l2c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_mshr_uncacheable_latency 1394774000 # number of WriteReq MSHR uncacheable cycles -system.l2c.Writeback_accesses::0 430351 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 430351 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_hits::0 430351 # number of Writeback hits -system.l2c.Writeback_hits::total 430351 # number of Writeback hits +system.l2c.WriteReq_mshr_uncacheable_latency 1594965500 # number of WriteReq MSHR uncacheable cycles +system.l2c.Writeback_accesses::0 436372 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 436372 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_hits::0 436372 # number of Writeback hits +system.l2c.Writeback_hits::total 436372 # number of Writeback hits system.l2c.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.l2c.avg_refs 4.554189 # Average number of references to valid blocks. +system.l2c.avg_refs 4.549954 # Average number of references to valid blocks. system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked::no_targets 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.demand_accesses::0 2255308 # number of demand (read+write) accesses -system.l2c.demand_accesses::1 141811 # number of demand (read+write) accesses +system.l2c.demand_accesses::0 1851492 # number of demand (read+write) accesses +system.l2c.demand_accesses::1 515351 # number of demand (read+write) accesses system.l2c.demand_accesses::2 0 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 2397119 # number of demand (read+write) accesses -system.l2c.demand_avg_miss_latency::0 54160.431067 # average overall miss latency -system.l2c.demand_avg_miss_latency::1 1309581.638928 # average overall miss latency +system.l2c.demand_accesses::total 2366843 # number of demand (read+write) accesses +system.l2c.demand_avg_miss_latency::0 58202.117554 # average overall miss latency +system.l2c.demand_avg_miss_latency::1 488846.088515 # average overall miss latency system.l2c.demand_avg_miss_latency::2 inf # average overall miss latency system.l2c.demand_avg_miss_latency::total inf # average overall miss latency -system.l2c.demand_avg_mshr_miss_latency 40009.496566 # average overall mshr miss latency -system.l2c.demand_hits::0 1665469 # number of demand (read+write) hits -system.l2c.demand_hits::1 117417 # number of demand (read+write) hits +system.l2c.demand_avg_mshr_miss_latency 40009.860245 # average overall mshr miss latency +system.l2c.demand_hits::0 1312521 # number of demand (read+write) hits +system.l2c.demand_hits::1 451181 # number of demand (read+write) hits system.l2c.demand_hits::2 0 # number of demand (read+write) hits -system.l2c.demand_hits::total 1782886 # number of demand (read+write) hits -system.l2c.demand_miss_latency 31945934500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_rate::0 0.261534 # miss rate for demand accesses -system.l2c.demand_miss_rate::1 0.172018 # miss rate for demand accesses +system.l2c.demand_hits::total 1763702 # number of demand (read+write) hits +system.l2c.demand_miss_latency 31369253500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_rate::0 0.291101 # miss rate for demand accesses +system.l2c.demand_miss_rate::1 0.124517 # miss rate for demand accesses system.l2c.demand_miss_rate::2 no_value # miss rate for demand accesses system.l2c.demand_miss_rate::total no_value # miss rate for demand accesses -system.l2c.demand_misses::0 589839 # number of demand (read+write) misses -system.l2c.demand_misses::1 24394 # number of demand (read+write) misses +system.l2c.demand_misses::0 538971 # number of demand (read+write) misses +system.l2c.demand_misses::1 64170 # number of demand (read+write) misses system.l2c.demand_misses::2 0 # number of demand (read+write) misses -system.l2c.demand_misses::total 614233 # number of demand (read+write) misses -system.l2c.demand_mshr_hits 11 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_miss_latency 24574713000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_rate::0 0.272345 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::1 4.331272 # mshr miss rate for demand accesses +system.l2c.demand_misses::total 603141 # number of demand (read+write) misses +system.l2c.demand_mshr_hits 12 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_miss_latency 24131107000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_rate::0 0.325753 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::1 1.170327 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::2 inf # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.l2c.demand_mshr_misses 614222 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses 603129 # number of demand (read+write) MSHR misses system.l2c.fast_writes 0 # number of fast writes performed system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.occ_%::0 0.090499 # Average percentage of cache occupancy -system.l2c.occ_%::1 0.002713 # Average percentage of cache occupancy -system.l2c.occ_%::2 0.377667 # Average percentage of cache occupancy -system.l2c.occ_blocks::0 5930.966720 # Average occupied blocks per context -system.l2c.occ_blocks::1 177.784506 # Average occupied blocks per context -system.l2c.occ_blocks::2 24750.754224 # Average occupied blocks per context -system.l2c.overall_accesses::0 2255308 # number of overall (read+write) accesses -system.l2c.overall_accesses::1 141811 # number of overall (read+write) accesses +system.l2c.occ_%::0 0.162138 # Average percentage of cache occupancy +system.l2c.occ_%::1 0.003912 # Average percentage of cache occupancy +system.l2c.occ_%::2 0.340573 # Average percentage of cache occupancy +system.l2c.occ_blocks::0 10625.898715 # Average occupied blocks per context +system.l2c.occ_blocks::1 256.359763 # Average occupied blocks per context +system.l2c.occ_blocks::2 22319.780586 # Average occupied blocks per context +system.l2c.overall_accesses::0 1851492 # number of overall (read+write) accesses +system.l2c.overall_accesses::1 515351 # number of overall (read+write) accesses system.l2c.overall_accesses::2 0 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 2397119 # number of overall (read+write) accesses -system.l2c.overall_avg_miss_latency::0 54160.431067 # average overall miss latency -system.l2c.overall_avg_miss_latency::1 1309581.638928 # average overall miss latency +system.l2c.overall_accesses::total 2366843 # number of overall (read+write) accesses +system.l2c.overall_avg_miss_latency::0 58202.117554 # average overall miss latency +system.l2c.overall_avg_miss_latency::1 488846.088515 # average overall miss latency system.l2c.overall_avg_miss_latency::2 inf # average overall miss latency system.l2c.overall_avg_miss_latency::total inf # average overall miss latency -system.l2c.overall_avg_mshr_miss_latency 40009.496566 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency 40009.860245 # average overall mshr miss latency system.l2c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.l2c.overall_hits::0 1665469 # number of overall hits -system.l2c.overall_hits::1 117417 # number of overall hits +system.l2c.overall_hits::0 1312521 # number of overall hits +system.l2c.overall_hits::1 451181 # number of overall hits system.l2c.overall_hits::2 0 # number of overall hits -system.l2c.overall_hits::total 1782886 # number of overall hits -system.l2c.overall_miss_latency 31945934500 # number of overall miss cycles -system.l2c.overall_miss_rate::0 0.261534 # miss rate for overall accesses -system.l2c.overall_miss_rate::1 0.172018 # miss rate for overall accesses +system.l2c.overall_hits::total 1763702 # number of overall hits +system.l2c.overall_miss_latency 31369253500 # number of overall miss cycles +system.l2c.overall_miss_rate::0 0.291101 # miss rate for overall accesses +system.l2c.overall_miss_rate::1 0.124517 # miss rate for overall accesses system.l2c.overall_miss_rate::2 no_value # miss rate for overall accesses system.l2c.overall_miss_rate::total no_value # miss rate for overall accesses -system.l2c.overall_misses::0 589839 # number of overall misses -system.l2c.overall_misses::1 24394 # number of overall misses +system.l2c.overall_misses::0 538971 # number of overall misses +system.l2c.overall_misses::1 64170 # number of overall misses system.l2c.overall_misses::2 0 # number of overall misses -system.l2c.overall_misses::total 614233 # number of overall misses -system.l2c.overall_mshr_hits 11 # number of overall MSHR hits -system.l2c.overall_mshr_miss_latency 24574713000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_rate::0 0.272345 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::1 4.331272 # mshr miss rate for overall accesses +system.l2c.overall_misses::total 603141 # number of overall misses +system.l2c.overall_mshr_hits 12 # number of overall MSHR hits +system.l2c.overall_mshr_miss_latency 24131107000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_rate::0 0.325753 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::1 1.170327 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::2 inf # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.l2c.overall_mshr_misses 614222 # number of overall MSHR misses -system.l2c.overall_mshr_uncacheable_latency 2197317000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_misses 603129 # number of overall MSHR misses +system.l2c.overall_mshr_uncacheable_latency 2397500500 # number of overall MSHR uncacheable cycles system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.l2c.replacements 399005 # number of replacements -system.l2c.sampled_refs 430732 # Sample count of references to valid blocks. +system.l2c.replacements 398396 # number of replacements +system.l2c.sampled_refs 431420 # Sample count of references to valid blocks. system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.l2c.tagsinuse 30859.505450 # Cycle average of tags in use -system.l2c.total_refs 1961635 # Total number of references to valid blocks. -system.l2c.warmup_cycle 10912833000 # Cycle when the warmup percentage was hit. -system.l2c.writebacks 123162 # number of writebacks +system.l2c.tagsinuse 33202.039064 # Cycle average of tags in use +system.l2c.total_refs 1962941 # Total number of references to valid blocks. +system.l2c.warmup_cycle 10911264000 # Cycle when the warmup percentage was hit. +system.l2c.writebacks 122806 # number of writebacks system.tsunami.ethernet.coalescedRxDesc no_value # average number of RxDesc's coalesced into each post system.tsunami.ethernet.coalescedRxIdle no_value # average number of RxIdle's coalesced into each post system.tsunami.ethernet.coalescedRxOk no_value # average number of RxOk's coalesced into each post diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini index 38041459e..14a4f1725 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini @@ -8,11 +8,12 @@ type=LinuxAlphaSystem children=bridge cpu disk0 disk2 intrctrl iobus iocache l2c membus physmem simple_disk terminal toL2Bus tsunami boot_cpu_frequency=500 boot_osflags=root=/dev/hda1 console=ttyS0 -console=/home/stever/m5/m5_system_2.0b3/binaries/console +console=/dist/m5/system/binaries/console init_param=0 -kernel=/home/stever/m5/m5_system_2.0b3/binaries/vmlinux +kernel=/dist/m5/system/binaries/vmlinux +load_addr_mask=1099511627775 mem_mode=timing -pal=/home/stever/m5/m5_system_2.0b3/binaries/ts_osfpal +pal=/dist/m5/system/binaries/ts_osfpal physmem=system.physmem readfile=tests/halt.sh symbolfile= @@ -154,7 +155,7 @@ table_size=65536 [system.disk0.image.child] type=RawDiskImage -image_file=/home/stever/m5/m5_system_2.0b3/disks/linux-latest.img +image_file=/dist/m5/system/disks/linux-latest.img read_only=true [system.disk2] @@ -174,7 +175,7 @@ table_size=65536 [system.disk2.image.child] type=RawDiskImage -image_file=/home/stever/m5/m5_system_2.0b3/disks/linux-bigswap2.img +image_file=/dist/m5/system/disks/linux-bigswap2.img read_only=true [system.intrctrl] @@ -300,7 +301,7 @@ system=system [system.simple_disk.disk] type=RawDiskImage -image_file=/home/stever/m5/m5_system_2.0b3/disks/linux-latest.img +image_file=/dist/m5/system/disks/linux-latest.img read_only=true [system.terminal] diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simout b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simout index 7b8726b2e..8049df732 100755 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simout +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simout @@ -1,5 +1,5 @@ -Redirecting stdout to build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-timing/simout -Redirecting stderr to build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-timing/simerr +Redirecting stdout to build/ALPHA_FS/tests/opt/quick/10.linux-boot/alpha/linux/tsunami-simple-timing/simout +Redirecting stderr to build/ALPHA_FS/tests/opt/quick/10.linux-boot/alpha/linux/tsunami-simple-timing/simerr M5 Simulator System Copyright (c) 2001-2008 @@ -7,12 +7,13 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Jun 16 2010 10:39:13 -M5 revision b85fd4ba5453 7466 default qtip tip llsc-fix-stats -M5 started Jun 16 2010 10:44:55 -M5 executing on phenom -command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-timing -re tests/run.py build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-timing +M5 compiled Aug 26 2010 12:51:14 +M5 revision 85cafc6ccb42 7662 default qtip tip sc-fail-fix +M5 started Aug 26 2010 12:51:16 +M5 executing on zizzer +command line: build/ALPHA_FS/m5.opt -d build/ALPHA_FS/tests/opt/quick/10.linux-boot/alpha/linux/tsunami-simple-timing -re tests/run.py build/ALPHA_FS/tests/opt/quick/10.linux-boot/alpha/linux/tsunami-simple-timing Global frequency set at 1000000000000 ticks per second -info: kernel located at: /home/stever/m5/m5_system_2.0b3/binaries/vmlinux +info: kernel located at: /dist/m5/system/binaries/vmlinux + 0: system.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009 info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 1930164593000 because m5_exit instruction encountered +Exiting @ tick 1927951878000 because m5_exit instruction encountered diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt index f93fce19a..3b140faa7 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt @@ -1,157 +1,157 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1511189 # Simulator instruction rate (inst/s) -host_mem_usage 272256 # Number of bytes of host memory used -host_seconds 37.19 # Real time elapsed on the host -host_tick_rate 51895589412 # Simulator tick rate (ticks/s) +host_inst_rate 1563603 # Simulator instruction rate (inst/s) +host_mem_usage 288804 # Number of bytes of host memory used +host_seconds 35.93 # Real time elapsed on the host +host_tick_rate 53658174093 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 56205703 # Number of instructions simulated -sim_seconds 1.930165 # Number of seconds simulated -sim_ticks 1930164593000 # Number of ticks simulated -system.cpu.dcache.LoadLockedReq_accesses::0 200404 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 200404 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_avg_miss_latency::0 14361.546017 # average LoadLockedReq miss latency +sim_insts 56180319 # Number of instructions simulated +sim_seconds 1.927952 # Number of seconds simulated +sim_ticks 1927951878000 # Number of ticks simulated +system.cpu.dcache.LoadLockedReq_accesses::0 200373 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 200373 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_avg_miss_latency::0 14335.708080 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::1 inf # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::total inf # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency 11361.546017 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_hits::0 183095 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 183095 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_miss_latency 248584000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_rate::0 0.086371 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_misses::0 17309 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 17309 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_mshr_miss_latency 196657000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::0 0.086371 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency 11335.708080 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_hits::0 183108 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 183108 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_miss_latency 247506000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_rate::0 0.086164 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_misses::0 17265 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 17265 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_mshr_miss_latency 195711000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::0 0.086164 # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_mshr_miss_rate::1 inf # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total inf # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_misses 17309 # number of LoadLockedReq MSHR misses -system.cpu.dcache.ReadReq_accesses::0 8888653 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 8888653 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency::0 25452.354477 # average ReadReq miss latency +system.cpu.dcache.LoadLockedReq_mshr_misses 17265 # number of LoadLockedReq MSHR misses +system.cpu.dcache.ReadReq_accesses::0 8883579 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 8883579 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency::0 25418.459915 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 22452.311493 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 22418.417380 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.cpu.dcache.ReadReq_hits::0 7818479 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 7818479 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 27238448000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate::0 0.120398 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses::0 1070174 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1070174 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_miss_latency 24027880000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::0 0.120398 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_hits::0 7813872 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 7813872 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 27190304500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate::0 0.120414 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses::0 1069707 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1069707 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_miss_latency 23981138000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::0 0.120414 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 1070174 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses 1069707 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_uncacheable_latency 862763000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.StoreCondReq_accesses::0 199383 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 199383 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_avg_miss_latency::0 56004.366085 # average StoreCondReq miss latency +system.cpu.dcache.StoreCondReq_accesses::0 199352 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 199352 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_avg_miss_latency::0 56004.626718 # average StoreCondReq miss latency system.cpu.dcache.StoreCondReq_avg_miss_latency::1 inf # average StoreCondReq miss latency system.cpu.dcache.StoreCondReq_avg_miss_latency::total inf # average StoreCondReq miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency 53004.366085 # average StoreCondReq mshr miss latency -system.cpu.dcache.StoreCondReq_hits::0 169379 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 169379 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_miss_latency 1680355000 # number of StoreCondReq miss cycles -system.cpu.dcache.StoreCondReq_miss_rate::0 0.150484 # miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_misses::0 30004 # number of StoreCondReq misses -system.cpu.dcache.StoreCondReq_misses::total 30004 # number of StoreCondReq misses -system.cpu.dcache.StoreCondReq_mshr_miss_latency 1590343000 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_rate::0 0.150484 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency 53004.626718 # average StoreCondReq mshr miss latency +system.cpu.dcache.StoreCondReq_hits::0 177090 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 177090 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_miss_latency 1246775000 # number of StoreCondReq miss cycles +system.cpu.dcache.StoreCondReq_miss_rate::0 0.111672 # miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_misses::0 22262 # number of StoreCondReq misses +system.cpu.dcache.StoreCondReq_misses::total 22262 # number of StoreCondReq misses +system.cpu.dcache.StoreCondReq_mshr_miss_latency 1179989000 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_rate::0 0.111672 # mshr miss rate for StoreCondReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::1 inf # mshr miss rate for StoreCondReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::total inf # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_mshr_misses 30004 # number of StoreCondReq MSHR misses -system.cpu.dcache.WriteReq_accesses::0 6160337 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 6160337 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency::0 56004.022652 # average WriteReq miss latency +system.cpu.dcache.StoreCondReq_mshr_misses 22262 # number of StoreCondReq MSHR misses +system.cpu.dcache.WriteReq_accesses::0 6156793 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 6156793 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_avg_miss_latency::0 55757.232436 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::1 inf # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53004.022652 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 52757.232436 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency -system.cpu.dcache.WriteReq_hits::0 5759482 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 5759482 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 22449492500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate::0 0.065070 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses::0 400855 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 400855 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_miss_latency 21246927500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate::0 0.065070 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_hits::0 5786171 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 5786171 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 20664857000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate::0 0.060197 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses::0 370622 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 370622 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_miss_latency 19552991000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate::0 0.060197 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::1 inf # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 400855 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_uncacheable_latency 1201243500 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_misses 370622 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_uncacheable_latency 1200971000 # number of WriteReq MSHR uncacheable cycles system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 10.097318 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 10.097149 # Average number of references to valid blocks. system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses::0 15048990 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::0 15040372 # number of demand (read+write) accesses system.cpu.dcache.demand_accesses::1 0 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 15048990 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency::0 33777.675695 # average overall miss latency +system.cpu.dcache.demand_accesses::total 15040372 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency::0 33225.160016 # average overall miss latency system.cpu.dcache.demand_avg_miss_latency::1 inf # average overall miss latency system.cpu.dcache.demand_avg_miss_latency::total inf # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 30777.644424 # average overall mshr miss latency -system.cpu.dcache.demand_hits::0 13577961 # number of demand (read+write) hits +system.cpu.dcache.demand_avg_mshr_miss_latency 30225.128426 # average overall mshr miss latency +system.cpu.dcache.demand_hits::0 13600043 # number of demand (read+write) hits system.cpu.dcache.demand_hits::1 0 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 13577961 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 49687940500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate::0 0.097749 # miss rate for demand accesses +system.cpu.dcache.demand_hits::total 13600043 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 47855161500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate::0 0.095764 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu.dcache.demand_misses::0 1471029 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::0 1440329 # number of demand (read+write) misses system.cpu.dcache.demand_misses::1 0 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1471029 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1440329 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 45274807500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate::0 0.097749 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_latency 43534129000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate::0 0.095764 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 1471029 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses 1440329 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.occ_%::0 0.999969 # Average percentage of cache occupancy -system.cpu.dcache.occ_blocks::0 511.984142 # Average occupied blocks per context -system.cpu.dcache.overall_accesses::0 15048990 # number of overall (read+write) accesses +system.cpu.dcache.occ_blocks::0 511.984152 # Average occupied blocks per context +system.cpu.dcache.overall_accesses::0 15040372 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::1 0 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 15048990 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency::0 33777.675695 # average overall miss latency +system.cpu.dcache.overall_accesses::total 15040372 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency::0 33225.160016 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::1 inf # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::total inf # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 30777.644424 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 30225.128426 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits::0 13577961 # number of overall hits +system.cpu.dcache.overall_hits::0 13600043 # number of overall hits system.cpu.dcache.overall_hits::1 0 # number of overall hits -system.cpu.dcache.overall_hits::total 13577961 # number of overall hits -system.cpu.dcache.overall_miss_latency 49687940500 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate::0 0.097749 # miss rate for overall accesses +system.cpu.dcache.overall_hits::total 13600043 # number of overall hits +system.cpu.dcache.overall_miss_latency 47855161500 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate::0 0.095764 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu.dcache.overall_misses::0 1471029 # number of overall misses +system.cpu.dcache.overall_misses::0 1440329 # number of overall misses system.cpu.dcache.overall_misses::1 0 # number of overall misses -system.cpu.dcache.overall_misses::total 1471029 # number of overall misses +system.cpu.dcache.overall_misses::total 1440329 # number of overall misses system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 45274807500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate::0 0.097749 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_latency 43534129000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate::0 0.095764 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 1471029 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_uncacheable_latency 2064006500 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_misses 1440329 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_uncacheable_latency 2063734000 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.replacements 1391606 # number of replacements -system.cpu.dcache.sampled_refs 1392118 # Sample count of references to valid blocks. +system.cpu.dcache.replacements 1390845 # number of replacements +system.cpu.dcache.sampled_refs 1391357 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 511.984142 # Cycle average of tags in use -system.cpu.dcache.total_refs 14056658 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 84139000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 430459 # number of writebacks +system.cpu.dcache.tagsinuse 511.984152 # Cycle average of tags in use +system.cpu.dcache.total_refs 14048739 # Total number of references to valid blocks. +system.cpu.dcache.warmup_cycle 84029000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.writebacks 452168 # number of writebacks system.cpu.dtb.data_accesses 1020784 # DTB accesses system.cpu.dtb.data_acv 367 # DTB access violations -system.cpu.dtb.data_hits 15429793 # DTB hits +system.cpu.dtb.data_hits 15421062 # DTB hits system.cpu.dtb.data_misses 11466 # DTB misses system.cpu.dtb.fetch_accesses 0 # ITB accesses system.cpu.dtb.fetch_acv 0 # ITB acv @@ -159,106 +159,106 @@ system.cpu.dtb.fetch_hits 0 # IT system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.read_accesses 728853 # DTB read accesses system.cpu.dtb.read_acv 210 # DTB read access violations -system.cpu.dtb.read_hits 9069700 # DTB read hits +system.cpu.dtb.read_hits 9064565 # DTB read hits system.cpu.dtb.read_misses 10324 # DTB read misses system.cpu.dtb.write_accesses 291931 # DTB write accesses system.cpu.dtb.write_acv 157 # DTB write access violations -system.cpu.dtb.write_hits 6360093 # DTB write hits +system.cpu.dtb.write_hits 6356497 # DTB write hits system.cpu.dtb.write_misses 1142 # DTB write misses -system.cpu.icache.ReadReq_accesses::0 56217537 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 56217537 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency::0 14711.221983 # average ReadReq miss latency +system.cpu.icache.ReadReq_accesses::0 56192153 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 56192153 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency::0 14699.293599 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency system.cpu.icache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 11710.491665 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits::0 55286436 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 55286436 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 13697633500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate::0 0.016562 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses::0 931101 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 931101 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_miss_latency 10903650500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::0 0.016562 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency 11698.559265 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits::0 55261378 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 55261378 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 13681735000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate::0 0.016564 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses::0 930775 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 930775 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_miss_latency 10888726500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::0 0.016564 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 931101 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses 930775 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.icache.avg_refs 59.387754 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 59.381568 # Average number of references to valid blocks. system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses::0 56217537 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::0 56192153 # number of demand (read+write) accesses system.cpu.icache.demand_accesses::1 0 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 56217537 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency::0 14711.221983 # average overall miss latency +system.cpu.icache.demand_accesses::total 56192153 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency::0 14699.293599 # average overall miss latency system.cpu.icache.demand_avg_miss_latency::1 inf # average overall miss latency system.cpu.icache.demand_avg_miss_latency::total inf # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 11710.491665 # average overall mshr miss latency -system.cpu.icache.demand_hits::0 55286436 # number of demand (read+write) hits +system.cpu.icache.demand_avg_mshr_miss_latency 11698.559265 # average overall mshr miss latency +system.cpu.icache.demand_hits::0 55261378 # number of demand (read+write) hits system.cpu.icache.demand_hits::1 0 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 55286436 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 13697633500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate::0 0.016562 # miss rate for demand accesses +system.cpu.icache.demand_hits::total 55261378 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 13681735000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate::0 0.016564 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::1 no_value # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu.icache.demand_misses::0 931101 # number of demand (read+write) misses +system.cpu.icache.demand_misses::0 930775 # number of demand (read+write) misses system.cpu.icache.demand_misses::1 0 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 931101 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 930775 # number of demand (read+write) misses system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 10903650500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate::0 0.016562 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_latency 10888726500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate::0 0.016564 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 931101 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses 930775 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_%::0 0.993281 # Average percentage of cache occupancy -system.cpu.icache.occ_blocks::0 508.559728 # Average occupied blocks per context -system.cpu.icache.overall_accesses::0 56217537 # number of overall (read+write) accesses +system.cpu.icache.occ_%::0 0.993310 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::0 508.574724 # Average occupied blocks per context +system.cpu.icache.overall_accesses::0 56192153 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::1 0 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 56217537 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency::0 14711.221983 # average overall miss latency +system.cpu.icache.overall_accesses::total 56192153 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency::0 14699.293599 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::1 inf # average overall miss latency system.cpu.icache.overall_avg_miss_latency::total inf # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 11710.491665 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 11698.559265 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.overall_hits::0 55286436 # number of overall hits +system.cpu.icache.overall_hits::0 55261378 # number of overall hits system.cpu.icache.overall_hits::1 0 # number of overall hits -system.cpu.icache.overall_hits::total 55286436 # number of overall hits -system.cpu.icache.overall_miss_latency 13697633500 # number of overall miss cycles -system.cpu.icache.overall_miss_rate::0 0.016562 # miss rate for overall accesses +system.cpu.icache.overall_hits::total 55261378 # number of overall hits +system.cpu.icache.overall_miss_latency 13681735000 # number of overall miss cycles +system.cpu.icache.overall_miss_rate::0 0.016564 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::1 no_value # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu.icache.overall_misses::0 931101 # number of overall misses +system.cpu.icache.overall_misses::0 930775 # number of overall misses system.cpu.icache.overall_misses::1 0 # number of overall misses -system.cpu.icache.overall_misses::total 931101 # number of overall misses +system.cpu.icache.overall_misses::total 930775 # number of overall misses system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 10903650500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate::0 0.016562 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_latency 10888726500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate::0 0.016564 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 931101 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses 930775 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.replacements 930429 # number of replacements -system.cpu.icache.sampled_refs 930940 # Sample count of references to valid blocks. +system.cpu.icache.replacements 930104 # number of replacements +system.cpu.icache.sampled_refs 930615 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 508.559728 # Cycle average of tags in use -system.cpu.icache.total_refs 55286436 # Total number of references to valid blocks. -system.cpu.icache.warmup_cycle 39055604000 # Cycle when the warmup percentage was hit. +system.cpu.icache.tagsinuse 508.574724 # Cycle average of tags in use +system.cpu.icache.total_refs 55261378 # Total number of references to valid blocks. +system.cpu.icache.warmup_cycle 38310365000 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idle_fraction 0.929209 # Percentage of idle cycles +system.cpu.idle_fraction 0.930310 # Percentage of idle cycles system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_hits 0 # DTB hits system.cpu.itb.data_misses 0 # DTB misses -system.cpu.itb.fetch_accesses 4982987 # ITB accesses +system.cpu.itb.fetch_accesses 4982567 # ITB accesses system.cpu.itb.fetch_acv 184 # ITB acv -system.cpu.itb.fetch_hits 4977977 # ITB hits +system.cpu.itb.fetch_hits 4977557 # ITB hits system.cpu.itb.fetch_misses 5010 # ITB misses system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.read_acv 0 # DTB read access violations @@ -272,55 +272,55 @@ system.cpu.kern.callpal::cserve 1 0.00% 0.00% # nu system.cpu.kern.callpal::wrmces 1 0.00% 0.00% # number of callpals executed system.cpu.kern.callpal::wrfen 1 0.00% 0.00% # number of callpals executed system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # number of callpals executed -system.cpu.kern.callpal::swpctx 4171 2.16% 2.16% # number of callpals executed +system.cpu.kern.callpal::swpctx 4177 2.16% 2.16% # number of callpals executed system.cpu.kern.callpal::tbi 54 0.03% 2.19% # number of callpals executed -system.cpu.kern.callpal::wrent 7 0.00% 2.19% # number of callpals executed -system.cpu.kern.callpal::swpipl 176257 91.22% 93.41% # number of callpals executed -system.cpu.kern.callpal::rdps 6844 3.54% 96.95% # number of callpals executed +system.cpu.kern.callpal::wrent 7 0.00% 2.20% # number of callpals executed +system.cpu.kern.callpal::swpipl 176202 91.22% 93.41% # number of callpals executed +system.cpu.kern.callpal::rdps 6843 3.54% 96.95% # number of callpals executed system.cpu.kern.callpal::wrkgp 1 0.00% 96.96% # number of callpals executed system.cpu.kern.callpal::wrusp 7 0.00% 96.96% # number of callpals executed system.cpu.kern.callpal::rdusp 9 0.00% 96.96% # number of callpals executed system.cpu.kern.callpal::whami 2 0.00% 96.96% # number of callpals executed -system.cpu.kern.callpal::rti 5169 2.68% 99.64% # number of callpals executed +system.cpu.kern.callpal::rti 5167 2.67% 99.64% # number of callpals executed system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed -system.cpu.kern.callpal::total 193221 # number of callpals executed +system.cpu.kern.callpal::total 193169 # number of callpals executed system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.hwrei 212325 # number of hwrei instructions executed -system.cpu.kern.inst.quiesce 6374 # number of quiesce instructions executed -system.cpu.kern.ipl_count::0 75001 40.87% 40.87% # number of times we switched to this ipl +system.cpu.kern.inst.hwrei 212271 # number of hwrei instructions executed +system.cpu.kern.inst.quiesce 6373 # number of quiesce instructions executed +system.cpu.kern.ipl_count::0 74979 40.87% 40.87% # number of times we switched to this ipl system.cpu.kern.ipl_count::21 131 0.07% 40.94% # number of times we switched to this ipl -system.cpu.kern.ipl_count::22 1944 1.06% 42.00% # number of times we switched to this ipl -system.cpu.kern.ipl_count::31 106426 58.00% 100.00% # number of times we switched to this ipl -system.cpu.kern.ipl_count::total 183502 # number of times we switched to this ipl -system.cpu.kern.ipl_good::0 73634 49.31% 49.31% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_count::22 1942 1.06% 42.00% # number of times we switched to this ipl +system.cpu.kern.ipl_count::31 106391 58.00% 100.00% # number of times we switched to this ipl +system.cpu.kern.ipl_count::total 183443 # number of times we switched to this ipl +system.cpu.kern.ipl_good::0 73612 49.31% 49.31% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good::21 131 0.09% 49.39% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::22 1944 1.30% 50.69% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::31 73634 49.31% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::total 149343 # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_ticks::0 1866810523000 96.72% 96.72% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::21 96331500 0.00% 96.72% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::22 565310500 0.03% 96.75% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::31 62691670000 3.25% 100.00% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::total 1930163835000 # number of cycles we spent at this ipl -system.cpu.kern.ipl_used::0 0.981774 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_good::22 1942 1.30% 50.69% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::31 73612 49.31% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::total 149297 # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_ticks::0 1865248449500 96.75% 96.75% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::21 84324500 0.00% 96.75% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::22 564095000 0.03% 96.78% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::31 62054251000 3.22% 100.00% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::total 1927951120000 # number of cycles we spent at this ipl +system.cpu.kern.ipl_used::0 0.981768 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::31 0.691880 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.mode_good::kernel 1911 +system.cpu.kern.ipl_used::31 0.691901 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.mode_good::kernel 1914 system.cpu.kern.mode_good::user 1744 -system.cpu.kern.mode_good::idle 167 -system.cpu.kern.mode_switch::kernel 5917 # number of protection mode switches +system.cpu.kern.mode_good::idle 170 +system.cpu.kern.mode_switch::kernel 5914 # number of protection mode switches system.cpu.kern.mode_switch::user 1744 # number of protection mode switches -system.cpu.kern.mode_switch::idle 2089 # number of protection mode switches -system.cpu.kern.mode_switch_good::kernel 0.322968 # fraction of useful protection mode switches +system.cpu.kern.mode_switch::idle 2096 # number of protection mode switches +system.cpu.kern.mode_switch_good::kernel 0.323639 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::idle 0.079943 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::total 1.402910 # fraction of useful protection mode switches -system.cpu.kern.mode_ticks::kernel 48447088000 2.51% 2.51% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::user 5539986000 0.29% 2.80% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::idle 1876176759000 97.20% 100.00% # number of ticks spent at the given mode -system.cpu.kern.swap_context 4172 # number of times the context was actually changed +system.cpu.kern.mode_switch_good::idle 0.081107 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good::total 1.404746 # fraction of useful protection mode switches +system.cpu.kern.mode_ticks::kernel 47869140000 2.48% 2.48% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::user 5515150000 0.29% 2.77% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::idle 1874566828000 97.23% 100.00% # number of ticks spent at the given mode +system.cpu.kern.swap_context 4178 # number of times the context was actually changed system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed @@ -352,10 +352,10 @@ system.cpu.kern.syscall::132 4 1.23% 98.77% # nu system.cpu.kern.syscall::144 2 0.61% 99.39% # number of syscalls executed system.cpu.kern.syscall::147 2 0.61% 100.00% # number of syscalls executed system.cpu.kern.syscall::total 326 # number of syscalls executed -system.cpu.not_idle_fraction 0.070791 # Percentage of non-idle cycles -system.cpu.numCycles 3860329186 # number of cpu cycles simulated -system.cpu.num_insts 56205703 # Number of instructions executed -system.cpu.num_refs 15677891 # Number of memory references +system.cpu.not_idle_fraction 0.069690 # Percentage of non-idle cycles +system.cpu.numCycles 3855903756 # number of cpu cycles simulated +system.cpu.num_insts 56180319 # Number of instructions executed +system.cpu.num_refs 15669216 # Number of memory references system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). @@ -386,37 +386,37 @@ system.iocache.ReadReq_mshr_misses 173 # nu system.iocache.WriteReq_accesses::1 41552 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 41552 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_avg_miss_latency::0 inf # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::1 137876.559636 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::1 137846.765643 # average WriteReq miss latency system.iocache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency -system.iocache.WriteReq_avg_mshr_miss_latency 85873.072921 # average WriteReq mshr miss latency -system.iocache.WriteReq_miss_latency 5729046806 # number of WriteReq miss cycles +system.iocache.WriteReq_avg_mshr_miss_latency 85843.300347 # average WriteReq mshr miss latency +system.iocache.WriteReq_miss_latency 5727808806 # number of WriteReq miss cycles system.iocache.WriteReq_miss_rate::1 1 # miss rate for WriteReq accesses system.iocache.WriteReq_misses::1 41552 # number of WriteReq misses system.iocache.WriteReq_misses::total 41552 # number of WriteReq misses -system.iocache.WriteReq_mshr_miss_latency 3568197926 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency 3566960816 # number of WriteReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_rate::0 inf # mshr miss rate for WriteReq accesses system.iocache.WriteReq_mshr_miss_rate::1 1 # mshr miss rate for WriteReq accesses system.iocache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses system.iocache.WriteReq_mshr_misses 41552 # number of WriteReq MSHR misses -system.iocache.avg_blocked_cycles::no_mshrs 6163.674943 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 6165.192131 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.iocache.avg_refs 0 # Average number of references to valid blocks. system.iocache.blocked::no_mshrs 10472 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.blocked_cycles::no_mshrs 64546004 # number of cycles access was blocked +system.iocache.blocked_cycles::no_mshrs 64561892 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.iocache.cache_copies 0 # number of cache copies performed system.iocache.demand_accesses::0 0 # number of demand (read+write) accesses system.iocache.demand_accesses::1 41725 # number of demand (read+write) accesses system.iocache.demand_accesses::total 41725 # number of demand (read+write) accesses system.iocache.demand_avg_miss_latency::0 inf # average overall miss latency -system.iocache.demand_avg_miss_latency::1 137782.763427 # average overall miss latency +system.iocache.demand_avg_miss_latency::1 137753.092966 # average overall miss latency system.iocache.demand_avg_miss_latency::total inf # average overall miss latency -system.iocache.demand_avg_mshr_miss_latency 85779.291168 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency 85749.642037 # average overall mshr miss latency system.iocache.demand_hits::0 0 # number of demand (read+write) hits system.iocache.demand_hits::1 0 # number of demand (read+write) hits system.iocache.demand_hits::total 0 # number of demand (read+write) hits -system.iocache.demand_miss_latency 5748985804 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency 5747747804 # number of demand (read+write) miss cycles system.iocache.demand_miss_rate::0 no_value # miss rate for demand accesses system.iocache.demand_miss_rate::1 1 # miss rate for demand accesses system.iocache.demand_miss_rate::total no_value # miss rate for demand accesses @@ -424,7 +424,7 @@ system.iocache.demand_misses::0 0 # nu system.iocache.demand_misses::1 41725 # number of demand (read+write) misses system.iocache.demand_misses::total 41725 # number of demand (read+write) misses system.iocache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.iocache.demand_mshr_miss_latency 3579140924 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency 3577903814 # number of demand (read+write) MSHR miss cycles system.iocache.demand_mshr_miss_rate::0 inf # mshr miss rate for demand accesses system.iocache.demand_mshr_miss_rate::1 1 # mshr miss rate for demand accesses system.iocache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses @@ -432,20 +432,20 @@ system.iocache.demand_mshr_misses 41725 # nu system.iocache.fast_writes 0 # number of fast writes performed system.iocache.mshr_cap_events 0 # number of times MSHR cap was activated system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.iocache.occ_%::1 0.084587 # Average percentage of cache occupancy -system.iocache.occ_blocks::1 1.353399 # Average occupied blocks per context +system.iocache.occ_%::1 0.084569 # Average percentage of cache occupancy +system.iocache.occ_blocks::1 1.353112 # Average occupied blocks per context system.iocache.overall_accesses::0 0 # number of overall (read+write) accesses system.iocache.overall_accesses::1 41725 # number of overall (read+write) accesses system.iocache.overall_accesses::total 41725 # number of overall (read+write) accesses system.iocache.overall_avg_miss_latency::0 inf # average overall miss latency -system.iocache.overall_avg_miss_latency::1 137782.763427 # average overall miss latency +system.iocache.overall_avg_miss_latency::1 137753.092966 # average overall miss latency system.iocache.overall_avg_miss_latency::total inf # average overall miss latency -system.iocache.overall_avg_mshr_miss_latency 85779.291168 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency 85749.642037 # average overall mshr miss latency system.iocache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.iocache.overall_hits::0 0 # number of overall hits system.iocache.overall_hits::1 0 # number of overall hits system.iocache.overall_hits::total 0 # number of overall hits -system.iocache.overall_miss_latency 5748985804 # number of overall miss cycles +system.iocache.overall_miss_latency 5747747804 # number of overall miss cycles system.iocache.overall_miss_rate::0 no_value # miss rate for overall accesses system.iocache.overall_miss_rate::1 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total no_value # miss rate for overall accesses @@ -453,7 +453,7 @@ system.iocache.overall_misses::0 0 # nu system.iocache.overall_misses::1 41725 # number of overall misses system.iocache.overall_misses::total 41725 # number of overall misses system.iocache.overall_mshr_hits 0 # number of overall MSHR hits -system.iocache.overall_mshr_miss_latency 3579140924 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency 3577903814 # number of overall MSHR miss cycles system.iocache.overall_mshr_miss_rate::0 inf # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::1 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses @@ -463,151 +463,153 @@ system.iocache.overall_mshr_uncacheable_misses 0 system.iocache.replacements 41685 # number of replacements system.iocache.sampled_refs 41701 # Sample count of references to valid blocks. system.iocache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.iocache.tagsinuse 1.353399 # Cycle average of tags in use +system.iocache.tagsinuse 1.353112 # Cycle average of tags in use system.iocache.total_refs 0 # Total number of references to valid blocks. -system.iocache.warmup_cycle 1762299470000 # Cycle when the warmup percentage was hit. +system.iocache.warmup_cycle 1760339542000 # Cycle when the warmup percentage was hit. system.iocache.writebacks 41512 # number of writebacks -system.l2c.ReadExReq_accesses::0 304636 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 304636 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_avg_miss_latency::0 52003.289171 # average ReadExReq miss latency +system.l2c.ReadExReq_accesses::0 304386 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 304386 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_avg_miss_latency::0 52003.580327 # average ReadExReq miss latency system.l2c.ReadExReq_avg_miss_latency::1 inf # average ReadExReq miss latency system.l2c.ReadExReq_avg_miss_latency::total inf # average ReadExReq miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency 40003.289171 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_miss_latency 15842074000 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_rate::0 1 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_misses::0 304636 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 304636 # number of ReadExReq misses -system.l2c.ReadExReq_mshr_miss_latency 12186442000 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_rate::0 1 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_avg_mshr_miss_latency 40003.580327 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_hits::0 2179 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 2179 # number of ReadExReq hits +system.l2c.ReadExReq_miss_latency 15715846000 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_rate::0 0.992841 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_misses::0 302207 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 302207 # number of ReadExReq misses +system.l2c.ReadExReq_mshr_miss_latency 12089362000 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_rate::0 0.992841 # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::1 inf # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::total inf # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_misses 304636 # number of ReadExReq MSHR misses -system.l2c.ReadReq_accesses::0 2018564 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 2018564 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_avg_miss_latency::0 52016.377161 # average ReadReq miss latency +system.l2c.ReadExReq_mshr_misses 302207 # number of ReadExReq MSHR misses +system.l2c.ReadReq_accesses::0 2017728 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 2017728 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_avg_miss_latency::0 52016.477812 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.l2c.ReadReq_avg_mshr_miss_latency 40016.359280 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency 40016.459857 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_hits::0 1710971 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1710971 # number of ReadReq hits -system.l2c.ReadReq_miss_latency 15999873500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_rate::0 0.152382 # miss rate for ReadReq accesses -system.l2c.ReadReq_misses::0 307593 # number of ReadReq misses -system.l2c.ReadReq_misses::total 307593 # number of ReadReq misses -system.l2c.ReadReq_mshr_miss_latency 12308752000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_rate::0 0.152382 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_hits::0 1711407 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1711407 # number of ReadReq hits +system.l2c.ReadReq_miss_latency 15933739500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_rate::0 0.151815 # miss rate for ReadReq accesses +system.l2c.ReadReq_misses::0 306321 # number of ReadReq misses +system.l2c.ReadReq_misses::total 306321 # number of ReadReq misses +system.l2c.ReadReq_mshr_miss_latency 12257882000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_rate::0 0.151815 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_misses 307593 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses 306321 # number of ReadReq MSHR misses system.l2c.ReadReq_mshr_uncacheable_latency 772673000 # number of ReadReq MSHR uncacheable cycles -system.l2c.SCUpgradeReq_accesses::0 30004 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 30004 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_avg_miss_latency::0 52004.366085 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_accesses::0 22262 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::total 22262 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_avg_miss_latency::0 52004.626718 # average SCUpgradeReq miss latency system.l2c.SCUpgradeReq_avg_miss_latency::1 inf # average SCUpgradeReq miss latency system.l2c.SCUpgradeReq_avg_miss_latency::total inf # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency 40004.366085 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_miss_latency 1560339000 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_avg_mshr_miss_latency 40004.626718 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_miss_latency 1157727000 # number of SCUpgradeReq miss cycles system.l2c.SCUpgradeReq_miss_rate::0 1 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_misses::0 30004 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 30004 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_mshr_miss_latency 1200291000 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_misses::0 22262 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::total 22262 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_mshr_miss_latency 890583000 # number of SCUpgradeReq MSHR miss cycles system.l2c.SCUpgradeReq_mshr_miss_rate::0 1 # mshr miss rate for SCUpgradeReq accesses system.l2c.SCUpgradeReq_mshr_miss_rate::1 inf # mshr miss rate for SCUpgradeReq accesses system.l2c.SCUpgradeReq_mshr_miss_rate::total inf # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_misses 30004 # number of SCUpgradeReq MSHR misses -system.l2c.UpgradeReq_accesses::0 96219 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 96219 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_avg_miss_latency::0 52001.013313 # average UpgradeReq miss latency +system.l2c.SCUpgradeReq_mshr_misses 22262 # number of SCUpgradeReq MSHR misses +system.l2c.UpgradeReq_accesses::0 66236 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 66236 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_avg_miss_latency::0 52000.030195 # average UpgradeReq miss latency system.l2c.UpgradeReq_avg_miss_latency::1 inf # average UpgradeReq miss latency system.l2c.UpgradeReq_avg_miss_latency::total inf # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency 40006.391669 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_miss_latency 5003485500 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_avg_mshr_miss_latency 40007.095839 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_miss_latency 3444274000 # number of UpgradeReq miss cycles system.l2c.UpgradeReq_miss_rate::0 1 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_misses::0 96219 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 96219 # number of UpgradeReq misses -system.l2c.UpgradeReq_mshr_miss_latency 3849375000 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_misses::0 66236 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 66236 # number of UpgradeReq misses +system.l2c.UpgradeReq_mshr_miss_latency 2649910000 # number of UpgradeReq MSHR miss cycles system.l2c.UpgradeReq_mshr_miss_rate::0 1 # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::1 inf # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::total inf # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_misses 96219 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses 66236 # number of UpgradeReq MSHR misses system.l2c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_mshr_uncacheable_latency 1085299500 # number of WriteReq MSHR uncacheable cycles -system.l2c.Writeback_accesses::0 430459 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 430459 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_hits::0 430459 # number of Writeback hits -system.l2c.Writeback_hits::total 430459 # number of Writeback hits +system.l2c.WriteReq_mshr_uncacheable_latency 1085051000 # number of WriteReq MSHR uncacheable cycles +system.l2c.Writeback_accesses::0 452168 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 452168 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_hits::0 452168 # number of Writeback hits +system.l2c.Writeback_hits::total 452168 # number of Writeback hits system.l2c.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.l2c.avg_refs 4.436562 # Average number of references to valid blocks. +system.l2c.avg_refs 4.517115 # Average number of references to valid blocks. system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked::no_targets 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.demand_accesses::0 2323200 # number of demand (read+write) accesses +system.l2c.demand_accesses::0 2322114 # number of demand (read+write) accesses system.l2c.demand_accesses::1 0 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 2323200 # number of demand (read+write) accesses -system.l2c.demand_avg_miss_latency::0 52009.864773 # average overall miss latency +system.l2c.demand_accesses::total 2322114 # number of demand (read+write) accesses +system.l2c.demand_avg_miss_latency::0 52010.072667 # average overall miss latency system.l2c.demand_avg_miss_latency::1 inf # average overall miss latency system.l2c.demand_avg_miss_latency::total inf # average overall miss latency -system.l2c.demand_avg_mshr_miss_latency 40009.855789 # average overall mshr miss latency -system.l2c.demand_hits::0 1710971 # number of demand (read+write) hits +system.l2c.demand_avg_mshr_miss_latency 40010.063629 # average overall mshr miss latency +system.l2c.demand_hits::0 1713586 # number of demand (read+write) hits system.l2c.demand_hits::1 0 # number of demand (read+write) hits -system.l2c.demand_hits::total 1710971 # number of demand (read+write) hits -system.l2c.demand_miss_latency 31841947500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_rate::0 0.263528 # miss rate for demand accesses +system.l2c.demand_hits::total 1713586 # number of demand (read+write) hits +system.l2c.demand_miss_latency 31649585500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_rate::0 0.262058 # miss rate for demand accesses system.l2c.demand_miss_rate::1 no_value # miss rate for demand accesses system.l2c.demand_miss_rate::total no_value # miss rate for demand accesses -system.l2c.demand_misses::0 612229 # number of demand (read+write) misses +system.l2c.demand_misses::0 608528 # number of demand (read+write) misses system.l2c.demand_misses::1 0 # number of demand (read+write) misses -system.l2c.demand_misses::total 612229 # number of demand (read+write) misses +system.l2c.demand_misses::total 608528 # number of demand (read+write) misses system.l2c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_miss_latency 24495194000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_rate::0 0.263528 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_latency 24347244000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_rate::0 0.262058 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.l2c.demand_mshr_misses 612229 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses 608528 # number of demand (read+write) MSHR misses system.l2c.fast_writes 0 # number of fast writes performed system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.occ_%::0 0.086363 # Average percentage of cache occupancy -system.l2c.occ_%::1 0.380427 # Average percentage of cache occupancy -system.l2c.occ_blocks::0 5659.865751 # Average occupied blocks per context -system.l2c.occ_blocks::1 24931.678191 # Average occupied blocks per context -system.l2c.overall_accesses::0 2323200 # number of overall (read+write) accesses +system.l2c.occ_%::0 0.156745 # Average percentage of cache occupancy +system.l2c.occ_%::1 0.334961 # Average percentage of cache occupancy +system.l2c.occ_blocks::0 10272.459916 # Average occupied blocks per context +system.l2c.occ_blocks::1 21951.974033 # Average occupied blocks per context +system.l2c.overall_accesses::0 2322114 # number of overall (read+write) accesses system.l2c.overall_accesses::1 0 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 2323200 # number of overall (read+write) accesses -system.l2c.overall_avg_miss_latency::0 52009.864773 # average overall miss latency +system.l2c.overall_accesses::total 2322114 # number of overall (read+write) accesses +system.l2c.overall_avg_miss_latency::0 52010.072667 # average overall miss latency system.l2c.overall_avg_miss_latency::1 inf # average overall miss latency system.l2c.overall_avg_miss_latency::total inf # average overall miss latency -system.l2c.overall_avg_mshr_miss_latency 40009.855789 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency 40010.063629 # average overall mshr miss latency system.l2c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.l2c.overall_hits::0 1710971 # number of overall hits +system.l2c.overall_hits::0 1713586 # number of overall hits system.l2c.overall_hits::1 0 # number of overall hits -system.l2c.overall_hits::total 1710971 # number of overall hits -system.l2c.overall_miss_latency 31841947500 # number of overall miss cycles -system.l2c.overall_miss_rate::0 0.263528 # miss rate for overall accesses +system.l2c.overall_hits::total 1713586 # number of overall hits +system.l2c.overall_miss_latency 31649585500 # number of overall miss cycles +system.l2c.overall_miss_rate::0 0.262058 # miss rate for overall accesses system.l2c.overall_miss_rate::1 no_value # miss rate for overall accesses system.l2c.overall_miss_rate::total no_value # miss rate for overall accesses -system.l2c.overall_misses::0 612229 # number of overall misses +system.l2c.overall_misses::0 608528 # number of overall misses system.l2c.overall_misses::1 0 # number of overall misses -system.l2c.overall_misses::total 612229 # number of overall misses +system.l2c.overall_misses::total 608528 # number of overall misses system.l2c.overall_mshr_hits 0 # number of overall MSHR hits -system.l2c.overall_mshr_miss_latency 24495194000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_rate::0 0.263528 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_latency 24347244000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_rate::0 0.262058 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.l2c.overall_mshr_misses 612229 # number of overall MSHR misses -system.l2c.overall_mshr_uncacheable_latency 1857972500 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_misses 608528 # number of overall MSHR misses +system.l2c.overall_mshr_uncacheable_latency 1857724000 # number of overall MSHR uncacheable cycles system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.l2c.replacements 394928 # number of replacements -system.l2c.sampled_refs 425903 # Sample count of references to valid blocks. +system.l2c.replacements 393234 # number of replacements +system.l2c.sampled_refs 424575 # Sample count of references to valid blocks. system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.l2c.tagsinuse 30591.543942 # Cycle average of tags in use -system.l2c.total_refs 1889545 # Total number of references to valid blocks. -system.l2c.warmup_cycle 6968733000 # Cycle when the warmup percentage was hit. -system.l2c.writebacks 119060 # number of writebacks +system.l2c.tagsinuse 32224.433949 # Cycle average of tags in use +system.l2c.total_refs 1917854 # Total number of references to valid blocks. +system.l2c.warmup_cycle 6967096000 # Cycle when the warmup percentage was hit. +system.l2c.writebacks 118566 # number of writebacks system.tsunami.ethernet.coalescedRxDesc no_value # average number of RxDesc's coalesced into each post system.tsunami.ethernet.coalescedRxIdle no_value # average number of RxIdle's coalesced into each post system.tsunami.ethernet.coalescedRxOk no_value # average number of RxOk's coalesced into each post |