summaryrefslogtreecommitdiff
path: root/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt
diff options
context:
space:
mode:
Diffstat (limited to 'tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt')
-rw-r--r--tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt306
1 files changed, 153 insertions, 153 deletions
diff --git a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt
index 9bbce3daa..4bee82022 100644
--- a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt
+++ b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt
@@ -1,13 +1,13 @@
---------- Begin Simulation Statistics ----------
-host_inst_rate 1460315 # Simulator instruction rate (inst/s)
-host_mem_usage 380976 # Number of bytes of host memory used
-host_seconds 35.59 # Real time elapsed on the host
-host_tick_rate 740141754 # Simulator tick rate (ticks/s)
+host_inst_rate 2974441 # Simulator instruction rate (inst/s)
+host_mem_usage 381360 # Number of bytes of host memory used
+host_seconds 17.48 # Real time elapsed on the host
+host_tick_rate 1507548482 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
-sim_insts 51971087 # Number of instructions simulated
-sim_seconds 0.026341 # Number of seconds simulated
-sim_ticks 26341084000 # Number of ticks simulated
+sim_insts 51978646 # Number of instructions simulated
+sim_seconds 0.026345 # Number of seconds simulated
+sim_ticks 26344863500 # Number of ticks simulated
system.cpu.dcache.LoadLockedReq_accesses::0 100443 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total 100443 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_hits::0 95328 # number of LoadLockedReq hits
@@ -15,49 +15,49 @@ system.cpu.dcache.LoadLockedReq_hits::total 95328 #
system.cpu.dcache.LoadLockedReq_miss_rate::0 0.050924 # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_misses::0 5115 # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total 5115 # number of LoadLockedReq misses
-system.cpu.dcache.ReadReq_accesses::0 7807332 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total 7807332 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_hits::0 7570991 # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total 7570991 # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_rate::0 0.030272 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_misses::0 236341 # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total 236341 # number of ReadReq misses
+system.cpu.dcache.ReadReq_accesses::0 7808976 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total 7808976 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_hits::0 7572677 # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total 7572677 # number of ReadReq hits
+system.cpu.dcache.ReadReq_miss_rate::0 0.030260 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_misses::0 236299 # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total 236299 # number of ReadReq misses
system.cpu.dcache.StoreCondReq_accesses::0 100442 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total 100442 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_hits::0 100442 # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total 100442 # number of StoreCondReq hits
-system.cpu.dcache.WriteReq_accesses::0 6662917 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total 6662917 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_hits::0 6490820 # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total 6490820 # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_rate::0 0.025829 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses::0 172097 # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total 172097 # number of WriteReq misses
+system.cpu.dcache.WriteReq_accesses::0 6664019 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total 6664019 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_hits::0 6491936 # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total 6491936 # number of WriteReq hits
+system.cpu.dcache.WriteReq_miss_rate::0 0.025823 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_misses::0 172083 # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total 172083 # number of WriteReq misses
system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.cpu.dcache.avg_refs 34.634545 # Average number of references to valid blocks.
+system.cpu.dcache.avg_refs 34.645976 # Average number of references to valid blocks.
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.demand_accesses::0 14470249 # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::0 14472995 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::1 0 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total 14470249 # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total 14472995 # number of demand (read+write) accesses
system.cpu.dcache.demand_avg_miss_latency::0 0 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::1 no_value # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total no_value # average overall miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency
-system.cpu.dcache.demand_hits::0 14061811 # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::0 14064613 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::1 0 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total 14061811 # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total 14064613 # number of demand (read+write) hits
system.cpu.dcache.demand_miss_latency 0 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_rate::0 0.028226 # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::0 0.028217 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total no_value # miss rate for demand accesses
-system.cpu.dcache.demand_misses::0 408438 # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::0 408382 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::1 0 # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total 408438 # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total 408382 # number of demand (read+write) misses
system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_rate::0 0 # mshr miss rate for demand accesses
@@ -67,26 +67,26 @@ system.cpu.dcache.demand_mshr_misses 0 # nu
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.occ_blocks::0 511.736543 # Average occupied blocks per context
-system.cpu.dcache.occ_percent::0 0.999485 # Average percentage of cache occupancy
-system.cpu.dcache.overall_accesses::0 14470249 # number of overall (read+write) accesses
+system.cpu.dcache.occ_blocks::0 511.736581 # Average occupied blocks per context
+system.cpu.dcache.occ_percent::0 0.999486 # Average percentage of cache occupancy
+system.cpu.dcache.overall_accesses::0 14472995 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::1 0 # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total 14470249 # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total 14472995 # number of overall (read+write) accesses
system.cpu.dcache.overall_avg_miss_latency::0 0 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::1 no_value # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total no_value # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits::0 14061811 # number of overall hits
+system.cpu.dcache.overall_hits::0 14064613 # number of overall hits
system.cpu.dcache.overall_hits::1 0 # number of overall hits
-system.cpu.dcache.overall_hits::total 14061811 # number of overall hits
+system.cpu.dcache.overall_hits::total 14064613 # number of overall hits
system.cpu.dcache.overall_miss_latency 0 # number of overall miss cycles
-system.cpu.dcache.overall_miss_rate::0 0.028226 # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::0 0.028217 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total no_value # miss rate for overall accesses
-system.cpu.dcache.overall_misses::0 408438 # number of overall misses
+system.cpu.dcache.overall_misses::0 408382 # number of overall misses
system.cpu.dcache.overall_misses::1 0 # number of overall misses
-system.cpu.dcache.overall_misses::total 408438 # number of overall misses
+system.cpu.dcache.overall_misses::total 408382 # number of overall misses
system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_rate::0 0 # mshr miss rate for overall accesses
@@ -95,14 +95,14 @@ system.cpu.dcache.overall_mshr_miss_rate::total no_value
system.cpu.dcache.overall_mshr_misses 0 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.dcache.replacements 411199 # number of replacements
-system.cpu.dcache.sampled_refs 411711 # Sample count of references to valid blocks.
+system.cpu.dcache.replacements 411144 # number of replacements
+system.cpu.dcache.sampled_refs 411656 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse 511.736543 # Cycle average of tags in use
-system.cpu.dcache.total_refs 14259423 # Total number of references to valid blocks.
+system.cpu.dcache.tagsinuse 511.736581 # Cycle average of tags in use
+system.cpu.dcache.total_refs 14262224 # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle 21760500 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.writebacks 380342 # number of writebacks
-system.cpu.dtb.accesses 15494791 # DTB accesses
+system.cpu.dcache.writebacks 380291 # number of writebacks
+system.cpu.dtb.accesses 15497629 # DTB accesses
system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dtb.flush_entries 2239 # Number of entries that have been flushed from TLB
@@ -110,51 +110,51 @@ system.cpu.dtb.flush_tlb 2 # Nu
system.cpu.dtb.flush_tlb_asid 40 # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid 33678 # Number of times TLB was flushed by MVA & ASID
-system.cpu.dtb.hits 15489154 # DTB hits
+system.cpu.dtb.hits 15491993 # DTB hits
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
-system.cpu.dtb.misses 5637 # DTB misses
+system.cpu.dtb.misses 5636 # DTB misses
system.cpu.dtb.perms_faults 263 # Number of TLB faults due to permissions restrictions
system.cpu.dtb.prefetch_faults 787 # Number of TLB faults due to prefetch
-system.cpu.dtb.read_accesses 8719654 # DTB read accesses
-system.cpu.dtb.read_hits 8715002 # DTB read hits
-system.cpu.dtb.read_misses 4652 # DTB read misses
-system.cpu.dtb.write_accesses 6775137 # DTB write accesses
-system.cpu.dtb.write_hits 6774152 # DTB write hits
+system.cpu.dtb.read_accesses 8721338 # DTB read accesses
+system.cpu.dtb.read_hits 8716687 # DTB read hits
+system.cpu.dtb.read_misses 4651 # DTB read misses
+system.cpu.dtb.write_accesses 6776291 # DTB write accesses
+system.cpu.dtb.write_hits 6775306 # DTB write hits
system.cpu.dtb.write_misses 985 # DTB write misses
-system.cpu.icache.ReadReq_accesses::0 41451981 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total 41451981 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_hits::0 41019813 # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total 41019813 # number of ReadReq hits
-system.cpu.icache.ReadReq_miss_rate::0 0.010426 # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_misses::0 432168 # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total 432168 # number of ReadReq misses
+system.cpu.icache.ReadReq_accesses::0 41456992 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total 41456992 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_hits::0 41024796 # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total 41024796 # number of ReadReq hits
+system.cpu.icache.ReadReq_miss_rate::0 0.010425 # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_misses::0 432196 # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total 432196 # number of ReadReq misses
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.cpu.icache.avg_refs 94.916579 # Average number of references to valid blocks.
+system.cpu.icache.avg_refs 94.921959 # Average number of references to valid blocks.
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.demand_accesses::0 41451981 # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::0 41456992 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::1 0 # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total 41451981 # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total 41456992 # number of demand (read+write) accesses
system.cpu.icache.demand_avg_miss_latency::0 0 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::1 no_value # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total no_value # average overall miss latency
system.cpu.icache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency
-system.cpu.icache.demand_hits::0 41019813 # number of demand (read+write) hits
+system.cpu.icache.demand_hits::0 41024796 # number of demand (read+write) hits
system.cpu.icache.demand_hits::1 0 # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total 41019813 # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total 41024796 # number of demand (read+write) hits
system.cpu.icache.demand_miss_latency 0 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_rate::0 0.010426 # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::0 0.010425 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::1 no_value # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total no_value # miss rate for demand accesses
-system.cpu.icache.demand_misses::0 432168 # number of demand (read+write) misses
+system.cpu.icache.demand_misses::0 432196 # number of demand (read+write) misses
system.cpu.icache.demand_misses::1 0 # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total 432168 # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total 432196 # number of demand (read+write) misses
system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_rate::0 0 # mshr miss rate for demand accesses
@@ -164,26 +164,26 @@ system.cpu.icache.demand_mshr_misses 0 # nu
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.icache.occ_blocks::0 476.338478 # Average occupied blocks per context
-system.cpu.icache.occ_percent::0 0.930349 # Average percentage of cache occupancy
-system.cpu.icache.overall_accesses::0 41451981 # number of overall (read+write) accesses
+system.cpu.icache.occ_blocks::0 476.343594 # Average occupied blocks per context
+system.cpu.icache.occ_percent::0 0.930359 # Average percentage of cache occupancy
+system.cpu.icache.overall_accesses::0 41456992 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::1 0 # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total 41451981 # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total 41456992 # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency::0 0 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::1 no_value # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total no_value # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.icache.overall_hits::0 41019813 # number of overall hits
+system.cpu.icache.overall_hits::0 41024796 # number of overall hits
system.cpu.icache.overall_hits::1 0 # number of overall hits
-system.cpu.icache.overall_hits::total 41019813 # number of overall hits
+system.cpu.icache.overall_hits::total 41024796 # number of overall hits
system.cpu.icache.overall_miss_latency 0 # number of overall miss cycles
-system.cpu.icache.overall_miss_rate::0 0.010426 # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::0 0.010425 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::1 no_value # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total no_value # miss rate for overall accesses
-system.cpu.icache.overall_misses::0 432168 # number of overall misses
+system.cpu.icache.overall_misses::0 432196 # number of overall misses
system.cpu.icache.overall_misses::1 0 # number of overall misses
-system.cpu.icache.overall_misses::total 432168 # number of overall misses
+system.cpu.icache.overall_misses::total 432196 # number of overall misses
system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.icache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_rate::0 0 # mshr miss rate for overall accesses
@@ -192,15 +192,15 @@ system.cpu.icache.overall_mshr_miss_rate::total no_value
system.cpu.icache.overall_mshr_misses 0 # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.icache.replacements 431655 # number of replacements
-system.cpu.icache.sampled_refs 432167 # Sample count of references to valid blocks.
+system.cpu.icache.replacements 431683 # number of replacements
+system.cpu.icache.sampled_refs 432195 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse 476.338478 # Cycle average of tags in use
-system.cpu.icache.total_refs 41019813 # Total number of references to valid blocks.
+system.cpu.icache.tagsinuse 476.343594 # Cycle average of tags in use
+system.cpu.icache.total_refs 41024796 # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle 4572561500 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 33762 # number of writebacks
system.cpu.idle_fraction 0 # Percentage of idle cycles
-system.cpu.itb.accesses 41453108 # DTB accesses
+system.cpu.itb.accesses 41458119 # DTB accesses
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.itb.flush_entries 1476 # Number of entries that have been flushed from TLB
@@ -208,9 +208,9 @@ system.cpu.itb.flush_tlb 2 # Nu
system.cpu.itb.flush_tlb_asid 40 # Number of times TLB was flushed by ASID
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid 33678 # Number of times TLB was flushed by MVA & ASID
-system.cpu.itb.hits 41450178 # DTB hits
-system.cpu.itb.inst_accesses 41453108 # ITB inst accesses
-system.cpu.itb.inst_hits 41450178 # ITB inst hits
+system.cpu.itb.hits 41455189 # DTB hits
+system.cpu.itb.inst_accesses 41458119 # ITB inst accesses
+system.cpu.itb.inst_hits 41455189 # ITB inst hits
system.cpu.itb.inst_misses 2930 # ITB inst misses
system.cpu.itb.misses 2930 # DTB misses
system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
@@ -224,25 +224,25 @@ system.cpu.itb.write_misses 0 # DT
system.cpu.kern.inst.arm 0 # number of arm instructions executed
system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
-system.cpu.numCycles 52682169 # number of cpu cycles simulated
+system.cpu.numCycles 52689728 # number of cpu cycles simulated
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
-system.cpu.num_busy_cycles 52682169 # Number of busy cycles
-system.cpu.num_conditional_control_insts 7011337 # number of instructions that are conditional controls
+system.cpu.num_busy_cycles 52689728 # Number of busy cycles
+system.cpu.num_conditional_control_insts 7011782 # number of instructions that are conditional controls
system.cpu.num_fp_alu_accesses 6058 # Number of float alu accesses
system.cpu.num_fp_insts 6058 # number of float instructions
system.cpu.num_fp_register_reads 4226 # number of times the floating registers were read
system.cpu.num_fp_register_writes 1834 # number of times the floating registers were written
-system.cpu.num_func_calls 1107940 # number of times a function call or return occured
+system.cpu.num_func_calls 1108496 # number of times a function call or return occured
system.cpu.num_idle_cycles 0 # Number of idle cycles
-system.cpu.num_insts 51971087 # Number of instructions executed
-system.cpu.num_int_alu_accesses 42400620 # Number of integer alu accesses
-system.cpu.num_int_insts 42400620 # number of integer instructions
-system.cpu.num_int_register_reads 130759048 # number of times the integer registers were read
-system.cpu.num_int_register_writes 34454879 # number of times the integer registers were written
-system.cpu.num_load_insts 9174729 # Number of load instructions
-system.cpu.num_mem_refs 16247961 # number of memory refs
-system.cpu.num_store_insts 7073232 # Number of store instructions
+system.cpu.num_insts 51978646 # Number of instructions executed
+system.cpu.num_int_alu_accesses 42407849 # Number of integer alu accesses
+system.cpu.num_int_insts 42407849 # number of integer instructions
+system.cpu.num_int_register_reads 130779000 # number of times the integer registers were read
+system.cpu.num_int_register_writes 34467088 # number of times the integer registers were written
+system.cpu.num_load_insts 9176676 # Number of load instructions
+system.cpu.num_mem_refs 16251075 # number of memory refs
+system.cpu.num_store_insts 7074399 # Number of store instructions
system.iocache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.iocache.avg_refs no_value # Average number of references to valid blocks.
@@ -310,61 +310,61 @@ system.iocache.tagsinuse 0 # Cy
system.iocache.total_refs 0 # Total number of references to valid blocks.
system.iocache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.iocache.writebacks 0 # number of writebacks
-system.l2c.ReadExReq_accesses::0 170255 # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::total 170255 # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_hits::0 60589 # number of ReadExReq hits
-system.l2c.ReadExReq_hits::total 60589 # number of ReadExReq hits
-system.l2c.ReadExReq_miss_rate::0 0.644128 # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_misses::0 109666 # number of ReadExReq misses
-system.l2c.ReadExReq_misses::total 109666 # number of ReadExReq misses
-system.l2c.ReadReq_accesses::0 671527 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::1 7078 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::total 678605 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_hits::0 650296 # number of ReadReq hits
-system.l2c.ReadReq_hits::1 7047 # number of ReadReq hits
-system.l2c.ReadReq_hits::total 657343 # number of ReadReq hits
-system.l2c.ReadReq_miss_rate::0 0.031616 # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::1 0.004380 # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::total 0.035996 # miss rate for ReadReq accesses
-system.l2c.ReadReq_misses::0 21231 # number of ReadReq misses
+system.l2c.ReadExReq_accesses::0 170242 # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::total 170242 # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_hits::0 60575 # number of ReadExReq hits
+system.l2c.ReadExReq_hits::total 60575 # number of ReadExReq hits
+system.l2c.ReadExReq_miss_rate::0 0.644183 # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_misses::0 109667 # number of ReadExReq misses
+system.l2c.ReadExReq_misses::total 109667 # number of ReadExReq misses
+system.l2c.ReadReq_accesses::0 671513 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::1 7076 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::total 678589 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_hits::0 650281 # number of ReadReq hits
+system.l2c.ReadReq_hits::1 7045 # number of ReadReq hits
+system.l2c.ReadReq_hits::total 657326 # number of ReadReq hits
+system.l2c.ReadReq_miss_rate::0 0.031618 # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::1 0.004381 # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::total 0.035999 # miss rate for ReadReq accesses
+system.l2c.ReadReq_misses::0 21232 # number of ReadReq misses
system.l2c.ReadReq_misses::1 31 # number of ReadReq misses
-system.l2c.ReadReq_misses::total 21262 # number of ReadReq misses
-system.l2c.UpgradeReq_accesses::0 1842 # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::total 1842 # number of UpgradeReq accesses(hits+misses)
+system.l2c.ReadReq_misses::total 21263 # number of ReadReq misses
+system.l2c.UpgradeReq_accesses::0 1841 # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::total 1841 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_hits::0 19 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total 19 # number of UpgradeReq hits
-system.l2c.UpgradeReq_miss_rate::0 0.989685 # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_misses::0 1823 # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::total 1823 # number of UpgradeReq misses
-system.l2c.Writeback_accesses::0 414104 # number of Writeback accesses(hits+misses)
-system.l2c.Writeback_accesses::total 414104 # number of Writeback accesses(hits+misses)
-system.l2c.Writeback_hits::0 414104 # number of Writeback hits
-system.l2c.Writeback_hits::total 414104 # number of Writeback hits
+system.l2c.UpgradeReq_miss_rate::0 0.989680 # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_misses::0 1822 # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::total 1822 # number of UpgradeReq misses
+system.l2c.Writeback_accesses::0 414053 # number of Writeback accesses(hits+misses)
+system.l2c.Writeback_accesses::total 414053 # number of Writeback accesses(hits+misses)
+system.l2c.Writeback_hits::0 414053 # number of Writeback hits
+system.l2c.Writeback_hits::total 414053 # number of Writeback hits
system.l2c.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.l2c.avg_refs 6.723520 # Average number of references to valid blocks.
+system.l2c.avg_refs 6.728889 # Average number of references to valid blocks.
system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
system.l2c.blocked::no_targets 0 # number of cycles access was blocked
system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.l2c.cache_copies 0 # number of cache copies performed
-system.l2c.demand_accesses::0 841782 # number of demand (read+write) accesses
-system.l2c.demand_accesses::1 7078 # number of demand (read+write) accesses
-system.l2c.demand_accesses::total 848860 # number of demand (read+write) accesses
+system.l2c.demand_accesses::0 841755 # number of demand (read+write) accesses
+system.l2c.demand_accesses::1 7076 # number of demand (read+write) accesses
+system.l2c.demand_accesses::total 848831 # number of demand (read+write) accesses
system.l2c.demand_avg_miss_latency::0 0 # average overall miss latency
system.l2c.demand_avg_miss_latency::1 0 # average overall miss latency
system.l2c.demand_avg_miss_latency::total 0 # average overall miss latency
system.l2c.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency
-system.l2c.demand_hits::0 710885 # number of demand (read+write) hits
-system.l2c.demand_hits::1 7047 # number of demand (read+write) hits
-system.l2c.demand_hits::total 717932 # number of demand (read+write) hits
+system.l2c.demand_hits::0 710856 # number of demand (read+write) hits
+system.l2c.demand_hits::1 7045 # number of demand (read+write) hits
+system.l2c.demand_hits::total 717901 # number of demand (read+write) hits
system.l2c.demand_miss_latency 0 # number of demand (read+write) miss cycles
-system.l2c.demand_miss_rate::0 0.155500 # miss rate for demand accesses
-system.l2c.demand_miss_rate::1 0.004380 # miss rate for demand accesses
-system.l2c.demand_miss_rate::total 0.159880 # miss rate for demand accesses
-system.l2c.demand_misses::0 130897 # number of demand (read+write) misses
+system.l2c.demand_miss_rate::0 0.155507 # miss rate for demand accesses
+system.l2c.demand_miss_rate::1 0.004381 # miss rate for demand accesses
+system.l2c.demand_miss_rate::total 0.159888 # miss rate for demand accesses
+system.l2c.demand_misses::0 130899 # number of demand (read+write) misses
system.l2c.demand_misses::1 31 # number of demand (read+write) misses
-system.l2c.demand_misses::total 130928 # number of demand (read+write) misses
+system.l2c.demand_misses::total 130930 # number of demand (read+write) misses
system.l2c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_rate::0 0 # mshr miss rate for demand accesses
@@ -374,28 +374,28 @@ system.l2c.demand_mshr_misses 0 # nu
system.l2c.fast_writes 0 # number of fast writes performed
system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
-system.l2c.occ_blocks::0 5062.788087 # Average occupied blocks per context
-system.l2c.occ_blocks::1 31189.705520 # Average occupied blocks per context
-system.l2c.occ_percent::0 0.077252 # Average percentage of cache occupancy
-system.l2c.occ_percent::1 0.475917 # Average percentage of cache occupancy
-system.l2c.overall_accesses::0 841782 # number of overall (read+write) accesses
-system.l2c.overall_accesses::1 7078 # number of overall (read+write) accesses
-system.l2c.overall_accesses::total 848860 # number of overall (read+write) accesses
+system.l2c.occ_blocks::0 5062.983429 # Average occupied blocks per context
+system.l2c.occ_blocks::1 31189.392245 # Average occupied blocks per context
+system.l2c.occ_percent::0 0.077255 # Average percentage of cache occupancy
+system.l2c.occ_percent::1 0.475912 # Average percentage of cache occupancy
+system.l2c.overall_accesses::0 841755 # number of overall (read+write) accesses
+system.l2c.overall_accesses::1 7076 # number of overall (read+write) accesses
+system.l2c.overall_accesses::total 848831 # number of overall (read+write) accesses
system.l2c.overall_avg_miss_latency::0 0 # average overall miss latency
system.l2c.overall_avg_miss_latency::1 0 # average overall miss latency
system.l2c.overall_avg_miss_latency::total 0 # average overall miss latency
system.l2c.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency
system.l2c.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.l2c.overall_hits::0 710885 # number of overall hits
-system.l2c.overall_hits::1 7047 # number of overall hits
-system.l2c.overall_hits::total 717932 # number of overall hits
+system.l2c.overall_hits::0 710856 # number of overall hits
+system.l2c.overall_hits::1 7045 # number of overall hits
+system.l2c.overall_hits::total 717901 # number of overall hits
system.l2c.overall_miss_latency 0 # number of overall miss cycles
-system.l2c.overall_miss_rate::0 0.155500 # miss rate for overall accesses
-system.l2c.overall_miss_rate::1 0.004380 # miss rate for overall accesses
-system.l2c.overall_miss_rate::total 0.159880 # miss rate for overall accesses
-system.l2c.overall_misses::0 130897 # number of overall misses
+system.l2c.overall_miss_rate::0 0.155507 # miss rate for overall accesses
+system.l2c.overall_miss_rate::1 0.004381 # miss rate for overall accesses
+system.l2c.overall_miss_rate::total 0.159888 # miss rate for overall accesses
+system.l2c.overall_misses::0 130899 # number of overall misses
system.l2c.overall_misses::1 31 # number of overall misses
-system.l2c.overall_misses::total 130928 # number of overall misses
+system.l2c.overall_misses::total 130930 # number of overall misses
system.l2c.overall_mshr_hits 0 # number of overall MSHR hits
system.l2c.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_rate::0 0 # mshr miss rate for overall accesses
@@ -405,11 +405,11 @@ system.l2c.overall_mshr_misses 0 # nu
system.l2c.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.l2c.replacements 97110 # number of replacements
-system.l2c.sampled_refs 129684 # Sample count of references to valid blocks.
+system.l2c.sampled_refs 129685 # Sample count of references to valid blocks.
system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.l2c.tagsinuse 36252.493607 # Cycle average of tags in use
-system.l2c.total_refs 871933 # Total number of references to valid blocks.
+system.l2c.tagsinuse 36252.375674 # Cycle average of tags in use
+system.l2c.total_refs 872636 # Total number of references to valid blocks.
system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.l2c.writebacks 91106 # number of writebacks
+system.l2c.writebacks 91105 # number of writebacks
---------- End Simulation Statistics ----------