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Diffstat (limited to 'tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/config.ini')
-rw-r--r--tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/config.ini10
1 files changed, 7 insertions, 3 deletions
diff --git a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/config.ini b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/config.ini
index 49b04d190..54cda093b 100644
--- a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/config.ini
+++ b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/config.ini
@@ -75,6 +75,7 @@ assoc=4
block_size=64
forward_snoops=true
hash_delay=1
+is_top_level=true
latency=1000
max_miss_count=0
mshrs=4
@@ -119,6 +120,7 @@ assoc=1
block_size=64
forward_snoops=true
hash_delay=1
+is_top_level=true
latency=1000
max_miss_count=0
mshrs=4
@@ -170,7 +172,7 @@ latency_var=0
null=false
range=134217728:268435455
zero=false
-port=system.membus.port[2]
+port=system.membus.port[1]
[system.intrctrl]
type=IntrControl
@@ -193,6 +195,7 @@ assoc=8
block_size=64
forward_snoops=false
hash_delay=1
+is_top_level=false
latency=50000
max_miss_count=0
mshrs=20
@@ -224,6 +227,7 @@ assoc=8
block_size=64
forward_snoops=true
hash_delay=1
+is_top_level=false
latency=10000
max_miss_count=0
mshrs=92
@@ -258,7 +262,7 @@ header_cycles=1
use_default_range=false
width=64
default=system.membus.badaddr_responder.pio
-port=system.bridge.side_b system.physmem.port[0] system.diskmem.port[0] system.realview.gic.pio system.realview.l2x0_fake.pio system.iocache.mem_side system.l2c.mem_side
+port=system.bridge.side_b system.diskmem.port[0] system.physmem.port[0] system.realview.gic.pio system.realview.l2x0_fake.pio system.iocache.mem_side system.l2c.mem_side
[system.membus.badaddr_responder]
type=IsaFake
@@ -284,7 +288,7 @@ latency_var=0
null=false
range=0:134217727
zero=true
-port=system.membus.port[1]
+port=system.membus.port[2]
[system.realview]
type=RealView