diff options
Diffstat (limited to 'tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt')
| -rw-r--r-- | tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt | 526 |
1 files changed, 263 insertions, 263 deletions
diff --git a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt index 85fb99220..c96422cfa 100644 --- a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt +++ b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt @@ -1,254 +1,254 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 433208 # Simulator instruction rate (inst/s) -host_mem_usage 360908 # Number of bytes of host memory used -host_seconds 116.74 # Real time elapsed on the host -host_tick_rate 982709659 # Simulator tick rate (ticks/s) +host_inst_rate 1425483 # Simulator instruction rate (inst/s) +host_mem_usage 374960 # Number of bytes of host memory used +host_seconds 35.49 # Real time elapsed on the host +host_tick_rate 3232752918 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 50572425 # Number of instructions simulated -sim_seconds 0.114721 # Number of seconds simulated -sim_ticks 114721074000 # Number of ticks simulated -system.cpu.dcache.LoadLockedReq_accesses::0 100214 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 100214 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_avg_miss_latency::0 15147.115385 # average LoadLockedReq miss latency +sim_insts 50588397 # Number of instructions simulated +sim_seconds 0.114727 # Number of seconds simulated +sim_ticks 114726567000 # Number of ticks simulated +system.cpu.dcache.LoadLockedReq_accesses::0 100290 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 100290 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_avg_miss_latency::0 14562.978560 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::1 inf # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::total inf # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency 12147.115385 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency 11562.978560 # average LoadLockedReq mshr miss latency system.cpu.dcache.LoadLockedReq_avg_mshr_uncacheable_latency inf # average LoadLockedReq mshr uncacheable latency -system.cpu.dcache.LoadLockedReq_hits::0 95014 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 95014 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_miss_latency 78765000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_rate::0 0.051889 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_misses::0 5200 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 5200 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_mshr_miss_latency 63165000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::0 0.051889 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_hits::0 95066 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 95066 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_miss_latency 76077000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_rate::0 0.052089 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_misses::0 5224 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 5224 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_mshr_miss_latency 60405000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::0 0.052089 # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_mshr_miss_rate::1 inf # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total inf # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_misses 5200 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_uncacheable_latency 310267000 # number of LoadLockedReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_accesses::0 7824780 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 7824780 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency::0 15798.342892 # average ReadReq miss latency +system.cpu.dcache.LoadLockedReq_mshr_misses 5224 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_uncacheable_latency 310532000 # number of LoadLockedReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_accesses::0 7828656 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 7828656 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency::0 15679.539912 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 12798.015358 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 12679.195749 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.cpu.dcache.ReadReq_hits::0 7588163 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 7588163 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 3738156500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate::0 0.030239 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses::0 236617 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 236617 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_miss_latency 3028228000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::0 0.030239 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_hits::0 7590397 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 7590397 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 3735791500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate::0 0.030434 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses::0 238259 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 238259 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_miss_latency 3020932500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::0 0.030434 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 236617 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_uncacheable_latency 38190415500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.StoreCondReq_accesses::0 100213 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 100213 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_hits::0 100213 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 100213 # number of StoreCondReq hits -system.cpu.dcache.WriteReq_accesses::0 6671860 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 6671860 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency::0 40836.063764 # average WriteReq miss latency +system.cpu.dcache.ReadReq_mshr_misses 238259 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_uncacheable_latency 38191771500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.StoreCondReq_accesses::0 100289 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 100289 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_hits::0 100289 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 100289 # number of StoreCondReq hits +system.cpu.dcache.WriteReq_accesses::0 6674369 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 6674369 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_avg_miss_latency::0 40728.962545 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::1 inf # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 37835.781907 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 37728.712808 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency -system.cpu.dcache.WriteReq_hits::0 6499787 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 6499787 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 7026784000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate::0 0.025791 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses::0 172073 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 172073 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_miss_latency 6510516500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate::0 0.025791 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_hits::0 6502188 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 6502188 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 7012753500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate::0 0.025797 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses::0 172181 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 172181 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_miss_latency 6496167500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate::0 0.025797 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::1 inf # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 172073 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_uncacheable_latency 926046500 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_misses 172181 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_uncacheable_latency 927436000 # number of WriteReq MSHR uncacheable cycles system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 34.660375 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 34.529769 # Average number of references to valid blocks. system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses::0 14496640 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::0 14503025 # number of demand (read+write) accesses system.cpu.dcache.demand_accesses::1 0 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 14496640 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency::0 26340.112310 # average overall miss latency +system.cpu.dcache.demand_accesses::total 14503025 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency::0 26187.859370 # average overall miss latency system.cpu.dcache.demand_avg_miss_latency::1 inf # average overall miss latency system.cpu.dcache.demand_avg_miss_latency::total inf # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 23339.804008 # average overall mshr miss latency -system.cpu.dcache.demand_hits::0 14087950 # number of demand (read+write) hits +system.cpu.dcache.demand_avg_mshr_miss_latency 23187.554819 # average overall mshr miss latency +system.cpu.dcache.demand_hits::0 14092585 # number of demand (read+write) hits system.cpu.dcache.demand_hits::1 0 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 14087950 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 10764940500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate::0 0.028192 # miss rate for demand accesses +system.cpu.dcache.demand_hits::total 14092585 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 10748545000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate::0 0.028300 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu.dcache.demand_misses::0 408690 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::0 410440 # number of demand (read+write) misses system.cpu.dcache.demand_misses::1 0 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 408690 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 410440 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 9538744500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate::0 0.028192 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_latency 9517100000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate::0 0.028300 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 408690 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses 410440 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.occ_%::0 0.994530 # Average percentage of cache occupancy -system.cpu.dcache.occ_blocks::0 509.199113 # Average occupied blocks per context -system.cpu.dcache.overall_accesses::0 14496640 # number of overall (read+write) accesses +system.cpu.dcache.occ_blocks::0 509.199247 # Average occupied blocks per context +system.cpu.dcache.overall_accesses::0 14503025 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::1 0 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 14496640 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency::0 26340.112310 # average overall miss latency +system.cpu.dcache.overall_accesses::total 14503025 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency::0 26187.859370 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::1 inf # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::total inf # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 23339.804008 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 23187.554819 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits::0 14087950 # number of overall hits +system.cpu.dcache.overall_hits::0 14092585 # number of overall hits system.cpu.dcache.overall_hits::1 0 # number of overall hits -system.cpu.dcache.overall_hits::total 14087950 # number of overall hits -system.cpu.dcache.overall_miss_latency 10764940500 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate::0 0.028192 # miss rate for overall accesses +system.cpu.dcache.overall_hits::total 14092585 # number of overall hits +system.cpu.dcache.overall_miss_latency 10748545000 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate::0 0.028300 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu.dcache.overall_misses::0 408690 # number of overall misses +system.cpu.dcache.overall_misses::0 410440 # number of overall misses system.cpu.dcache.overall_misses::1 0 # number of overall misses -system.cpu.dcache.overall_misses::total 408690 # number of overall misses +system.cpu.dcache.overall_misses::total 410440 # number of overall misses system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 9538744500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate::0 0.028192 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_latency 9517100000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate::0 0.028300 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 408690 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_uncacheable_latency 39116462000 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_misses 410440 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_uncacheable_latency 39119207500 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.replacements 411628 # number of replacements -system.cpu.dcache.sampled_refs 412140 # Sample count of references to valid blocks. +system.cpu.dcache.replacements 413327 # number of replacements +system.cpu.dcache.sampled_refs 413839 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 509.199113 # Cycle average of tags in use -system.cpu.dcache.total_refs 14284927 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 509.199247 # Cycle average of tags in use +system.cpu.dcache.total_refs 14289765 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 658097000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 382676 # number of writebacks -system.cpu.dtb.accesses 15524935 # DTB accesses +system.cpu.dcache.writebacks 381698 # number of writebacks +system.cpu.dtb.accesses 15531532 # DTB accesses system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.flush_entries 2199 # Number of entries that have been flushed from TLB +system.cpu.dtb.flush_entries 2220 # Number of entries that have been flushed from TLB system.cpu.dtb.flush_tlb 2 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_asid 40 # Number of times TLB was flushed by ASID system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.dtb.flush_tlb_mva_asid 33670 # Number of times TLB was flushed by MVA & ASID -system.cpu.dtb.hits 15519414 # DTB hits +system.cpu.dtb.hits 15525999 # DTB hits system.cpu.dtb.inst_accesses 0 # ITB inst accesses system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.misses 5521 # DTB misses +system.cpu.dtb.misses 5533 # DTB misses system.cpu.dtb.perms_faults 255 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.prefetch_faults 756 # Number of TLB faults due to prefetch -system.cpu.dtb.read_accesses 8740303 # DTB read accesses -system.cpu.dtb.read_hits 8735762 # DTB read hits -system.cpu.dtb.read_misses 4541 # DTB read misses -system.cpu.dtb.write_accesses 6784632 # DTB write accesses -system.cpu.dtb.write_hits 6783652 # DTB write hits -system.cpu.dtb.write_misses 980 # DTB write misses -system.cpu.icache.ReadReq_accesses::0 41543801 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 41543801 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency::0 14800.791885 # average ReadReq miss latency +system.cpu.dtb.prefetch_faults 757 # Number of TLB faults due to prefetch +system.cpu.dtb.read_accesses 8744287 # DTB read accesses +system.cpu.dtb.read_hits 8739733 # DTB read hits +system.cpu.dtb.read_misses 4554 # DTB read misses +system.cpu.dtb.write_accesses 6787245 # DTB write accesses +system.cpu.dtb.write_hits 6786266 # DTB write hits +system.cpu.dtb.write_misses 979 # DTB write misses +system.cpu.icache.ReadReq_accesses::0 41555414 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 41555414 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency::0 14790.398445 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency system.cpu.icache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 11799.492843 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 11789.103925 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.cpu.icache.ReadReq_hits::0 41110405 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 41110405 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 6414604000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate::0 0.010432 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses::0 433396 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 433396 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_miss_latency 5113853000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::0 0.010432 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_hits::0 41121276 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 41121276 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 6421074000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate::0 0.010447 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses::0 434138 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 434138 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_miss_latency 5118098000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::0 0.010447 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 433396 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses 434138 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_uncacheable_latency 349111000 # number of ReadReq MSHR uncacheable cycles system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.icache.avg_refs 94.856667 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 94.719366 # Average number of references to valid blocks. system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses::0 41543801 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::0 41555414 # number of demand (read+write) accesses system.cpu.icache.demand_accesses::1 0 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 41543801 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency::0 14800.791885 # average overall miss latency +system.cpu.icache.demand_accesses::total 41555414 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency::0 14790.398445 # average overall miss latency system.cpu.icache.demand_avg_miss_latency::1 inf # average overall miss latency system.cpu.icache.demand_avg_miss_latency::total inf # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 11799.492843 # average overall mshr miss latency -system.cpu.icache.demand_hits::0 41110405 # number of demand (read+write) hits +system.cpu.icache.demand_avg_mshr_miss_latency 11789.103925 # average overall mshr miss latency +system.cpu.icache.demand_hits::0 41121276 # number of demand (read+write) hits system.cpu.icache.demand_hits::1 0 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 41110405 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 6414604000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate::0 0.010432 # miss rate for demand accesses +system.cpu.icache.demand_hits::total 41121276 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 6421074000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate::0 0.010447 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::1 no_value # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu.icache.demand_misses::0 433396 # number of demand (read+write) misses +system.cpu.icache.demand_misses::0 434138 # number of demand (read+write) misses system.cpu.icache.demand_misses::1 0 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 433396 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 434138 # number of demand (read+write) misses system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 5113853000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate::0 0.010432 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_latency 5118098000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate::0 0.010447 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 433396 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses 434138 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_%::0 0.945788 # Average percentage of cache occupancy -system.cpu.icache.occ_blocks::0 484.243503 # Average occupied blocks per context -system.cpu.icache.overall_accesses::0 41543801 # number of overall (read+write) accesses +system.cpu.icache.occ_%::0 0.946115 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::0 484.411008 # Average occupied blocks per context +system.cpu.icache.overall_accesses::0 41555414 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::1 0 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 41543801 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency::0 14800.791885 # average overall miss latency +system.cpu.icache.overall_accesses::total 41555414 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency::0 14790.398445 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::1 inf # average overall miss latency system.cpu.icache.overall_avg_miss_latency::total inf # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 11799.492843 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 11789.103925 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.cpu.icache.overall_hits::0 41110405 # number of overall hits +system.cpu.icache.overall_hits::0 41121276 # number of overall hits system.cpu.icache.overall_hits::1 0 # number of overall hits -system.cpu.icache.overall_hits::total 41110405 # number of overall hits -system.cpu.icache.overall_miss_latency 6414604000 # number of overall miss cycles -system.cpu.icache.overall_miss_rate::0 0.010432 # miss rate for overall accesses +system.cpu.icache.overall_hits::total 41121276 # number of overall hits +system.cpu.icache.overall_miss_latency 6421074000 # number of overall miss cycles +system.cpu.icache.overall_miss_rate::0 0.010447 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::1 no_value # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu.icache.overall_misses::0 433396 # number of overall misses +system.cpu.icache.overall_misses::0 434138 # number of overall misses system.cpu.icache.overall_misses::1 0 # number of overall misses -system.cpu.icache.overall_misses::total 433396 # number of overall misses +system.cpu.icache.overall_misses::total 434138 # number of overall misses system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 5113853000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate::0 0.010432 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_latency 5118098000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate::0 0.010447 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 433396 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses 434138 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 349111000 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.replacements 432883 # number of replacements -system.cpu.icache.sampled_refs 433395 # Sample count of references to valid blocks. +system.cpu.icache.replacements 433626 # number of replacements +system.cpu.icache.sampled_refs 434138 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 484.243503 # Cycle average of tags in use -system.cpu.icache.total_refs 41110405 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 484.411008 # Cycle average of tags in use +system.cpu.icache.total_refs 41121276 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 14253306000 # Cycle when the warmup percentage was hit. -system.cpu.icache.writebacks 33555 # number of writebacks +system.cpu.icache.writebacks 34007 # number of writebacks system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.itb.accesses 41546620 # DTB accesses +system.cpu.itb.accesses 41558233 # DTB accesses system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.itb.flush_entries 1478 # Number of entries that have been flushed from TLB @@ -256,9 +256,9 @@ system.cpu.itb.flush_tlb 2 # Nu system.cpu.itb.flush_tlb_asid 40 # Number of times TLB was flushed by ASID system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.itb.flush_tlb_mva_asid 33670 # Number of times TLB was flushed by MVA & ASID -system.cpu.itb.hits 41543801 # DTB hits -system.cpu.itb.inst_accesses 41546620 # ITB inst accesses -system.cpu.itb.inst_hits 41543801 # ITB inst hits +system.cpu.itb.hits 41555414 # DTB hits +system.cpu.itb.inst_accesses 41558233 # ITB inst accesses +system.cpu.itb.inst_hits 41555414 # ITB inst hits system.cpu.itb.inst_misses 2819 # ITB inst misses system.cpu.itb.misses 2819 # DTB misses system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions @@ -272,10 +272,10 @@ system.cpu.itb.write_misses 0 # DT system.cpu.kern.inst.arm 0 # number of arm instructions executed system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 229442148 # number of cpu cycles simulated +system.cpu.numCycles 229453134 # number of cpu cycles simulated system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.num_busy_cycles 229442148 # Number of busy cycles +system.cpu.num_busy_cycles 229453134 # Number of busy cycles system.cpu.num_conditional_control_insts 0 # number of instructions that are conditional controls system.cpu.num_fp_alu_accesses 6058 # Number of float alu accesses system.cpu.num_fp_insts 6058 # number of float instructions @@ -283,14 +283,14 @@ system.cpu.num_fp_register_reads 4226 # nu system.cpu.num_fp_register_writes 1834 # number of times the floating registers were written system.cpu.num_func_calls 0 # number of times a function call or return occured system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_insts 50572425 # Number of instructions executed -system.cpu.num_int_alu_accesses 41827211 # Number of integer alu accesses -system.cpu.num_int_insts 41827211 # number of integer instructions -system.cpu.num_int_register_reads 137988684 # number of times the integer registers were read -system.cpu.num_int_register_writes 34313952 # number of times the integer registers were written -system.cpu.num_load_insts 9208240 # Number of load instructions -system.cpu.num_mem_refs 16289993 # number of memory refs -system.cpu.num_store_insts 7081753 # Number of store instructions +system.cpu.num_insts 50588397 # Number of instructions executed +system.cpu.num_int_alu_accesses 41841366 # Number of integer alu accesses +system.cpu.num_int_insts 41841366 # number of integer instructions +system.cpu.num_int_register_reads 138034734 # number of times the integer registers were read +system.cpu.num_int_register_writes 34325875 # number of times the integer registers were written +system.cpu.num_load_insts 9211791 # Number of load instructions +system.cpu.num_mem_refs 16296219 # number of memory refs +system.cpu.num_store_insts 7084428 # Number of store instructions system.iocache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.iocache.avg_refs no_value # Average number of references to valid blocks. @@ -359,141 +359,141 @@ system.iocache.total_refs 0 # To system.iocache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.iocache.writebacks 0 # number of writebacks system.l2c.LoadLockedReq_avg_mshr_uncacheable_latency inf # average LoadLockedReq mshr uncacheable latency -system.l2c.LoadLockedReq_mshr_uncacheable_latency 234160000 # number of LoadLockedReq MSHR uncacheable cycles -system.l2c.ReadExReq_accesses::0 170323 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 170323 # number of ReadExReq accesses(hits+misses) +system.l2c.LoadLockedReq_mshr_uncacheable_latency 234360000 # number of LoadLockedReq MSHR uncacheable cycles +system.l2c.ReadExReq_accesses::0 170356 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 170356 # number of ReadExReq accesses(hits+misses) system.l2c.ReadExReq_avg_miss_latency::0 52000 # average ReadExReq miss latency system.l2c.ReadExReq_avg_miss_latency::1 inf # average ReadExReq miss latency system.l2c.ReadExReq_avg_miss_latency::total inf # average ReadExReq miss latency system.l2c.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_hits::0 62071 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 62071 # number of ReadExReq hits -system.l2c.ReadExReq_miss_latency 5629104000 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_rate::0 0.635569 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_misses::0 108252 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 108252 # number of ReadExReq misses -system.l2c.ReadExReq_mshr_miss_latency 4330080000 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_rate::0 0.635569 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_hits::0 62546 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 62546 # number of ReadExReq hits +system.l2c.ReadExReq_miss_latency 5606120000 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_rate::0 0.632851 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_misses::0 107810 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 107810 # number of ReadExReq misses +system.l2c.ReadExReq_mshr_miss_latency 4312400000 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_rate::0 0.632851 # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::1 inf # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::total inf # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_misses 108252 # number of ReadExReq MSHR misses -system.l2c.ReadReq_accesses::0 673101 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::1 5652 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 678753 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_avg_miss_latency::0 52096.523258 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::1 28127657.142857 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 28179753.666115 # average ReadReq miss latency +system.l2c.ReadExReq_mshr_misses 107810 # number of ReadExReq MSHR misses +system.l2c.ReadReq_accesses::0 675489 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::1 5600 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 681089 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_avg_miss_latency::0 52080.437900 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::1 33725803.571429 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 33777884.009328 # average ReadReq miss latency system.l2c.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_hits::0 654204 # number of ReadReq hits -system.l2c.ReadReq_hits::1 5617 # number of ReadReq hits -system.l2c.ReadReq_hits::total 659821 # number of ReadReq hits -system.l2c.ReadReq_miss_latency 984468000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_rate::0 0.028075 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::1 0.006192 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.034267 # miss rate for ReadReq accesses -system.l2c.ReadReq_misses::0 18897 # number of ReadReq misses -system.l2c.ReadReq_misses::1 35 # number of ReadReq misses -system.l2c.ReadReq_misses::total 18932 # number of ReadReq misses -system.l2c.ReadReq_mshr_miss_latency 757280000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_rate::0 0.028127 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::1 3.349611 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 3.377737 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_misses 18932 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_uncacheable_latency 29199338000 # number of ReadReq MSHR uncacheable cycles -system.l2c.UpgradeReq_accesses::0 1750 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 1750 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_avg_miss_latency::0 660.126947 # average UpgradeReq miss latency +system.l2c.ReadReq_hits::0 657357 # number of ReadReq hits +system.l2c.ReadReq_hits::1 5572 # number of ReadReq hits +system.l2c.ReadReq_hits::total 662929 # number of ReadReq hits +system.l2c.ReadReq_miss_latency 944322500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_rate::0 0.026843 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::1 0.005000 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.031843 # miss rate for ReadReq accesses +system.l2c.ReadReq_misses::0 18132 # number of ReadReq misses +system.l2c.ReadReq_misses::1 28 # number of ReadReq misses +system.l2c.ReadReq_misses::total 18160 # number of ReadReq misses +system.l2c.ReadReq_mshr_miss_latency 726400000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_rate::0 0.026884 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::1 3.242857 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 3.269741 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_misses 18160 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_uncacheable_latency 29200446000 # number of ReadReq MSHR uncacheable cycles +system.l2c.UpgradeReq_accesses::0 1825 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 1825 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_avg_miss_latency::0 489.208633 # average UpgradeReq miss latency system.l2c.UpgradeReq_avg_miss_latency::1 inf # average UpgradeReq miss latency system.l2c.UpgradeReq_avg_miss_latency::total inf # average UpgradeReq miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_hits::0 17 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 17 # number of UpgradeReq hits -system.l2c.UpgradeReq_miss_latency 1144000 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_rate::0 0.990286 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_misses::0 1733 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 1733 # number of UpgradeReq misses -system.l2c.UpgradeReq_mshr_miss_latency 69320000 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_rate::0 0.990286 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_hits::0 18 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 18 # number of UpgradeReq hits +system.l2c.UpgradeReq_miss_latency 884000 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_rate::0 0.990137 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_misses::0 1807 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 1807 # number of UpgradeReq misses +system.l2c.UpgradeReq_mshr_miss_latency 72280000 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_rate::0 0.990137 # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::1 inf # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::total inf # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_misses 1733 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses 1807 # number of UpgradeReq MSHR misses system.l2c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_mshr_uncacheable_latency 739844000 # number of WriteReq MSHR uncacheable cycles -system.l2c.Writeback_accesses::0 416231 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 416231 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_hits::0 416231 # number of Writeback hits -system.l2c.Writeback_hits::total 416231 # number of Writeback hits +system.l2c.WriteReq_mshr_uncacheable_latency 740884000 # number of WriteReq MSHR uncacheable cycles +system.l2c.Writeback_accesses::0 415705 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 415705 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_hits::0 415705 # number of Writeback hits +system.l2c.Writeback_hits::total 415705 # number of Writeback hits system.l2c.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.l2c.avg_refs 6.975292 # Average number of references to valid blocks. +system.l2c.avg_refs 7.060757 # Average number of references to valid blocks. system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked::no_targets 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.demand_accesses::0 843424 # number of demand (read+write) accesses -system.l2c.demand_accesses::1 5652 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 849076 # number of demand (read+write) accesses -system.l2c.demand_avg_miss_latency::0 52014.345374 # average overall miss latency -system.l2c.demand_avg_miss_latency::1 188959200 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 189011214.345374 # average overall miss latency +system.l2c.demand_accesses::0 845845 # number of demand (read+write) accesses +system.l2c.demand_accesses::1 5600 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 851445 # number of demand (read+write) accesses +system.l2c.demand_avg_miss_latency::0 52011.580728 # average overall miss latency +system.l2c.demand_avg_miss_latency::1 233944375 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 233996386.580728 # average overall miss latency system.l2c.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency -system.l2c.demand_hits::0 716275 # number of demand (read+write) hits -system.l2c.demand_hits::1 5617 # number of demand (read+write) hits -system.l2c.demand_hits::total 721892 # number of demand (read+write) hits -system.l2c.demand_miss_latency 6613572000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_rate::0 0.150753 # miss rate for demand accesses -system.l2c.demand_miss_rate::1 0.006192 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.156946 # miss rate for demand accesses -system.l2c.demand_misses::0 127149 # number of demand (read+write) misses -system.l2c.demand_misses::1 35 # number of demand (read+write) misses -system.l2c.demand_misses::total 127184 # number of demand (read+write) misses +system.l2c.demand_hits::0 719903 # number of demand (read+write) hits +system.l2c.demand_hits::1 5572 # number of demand (read+write) hits +system.l2c.demand_hits::total 725475 # number of demand (read+write) hits +system.l2c.demand_miss_latency 6550442500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_rate::0 0.148895 # miss rate for demand accesses +system.l2c.demand_miss_rate::1 0.005000 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.153895 # miss rate for demand accesses +system.l2c.demand_misses::0 125942 # number of demand (read+write) misses +system.l2c.demand_misses::1 28 # number of demand (read+write) misses +system.l2c.demand_misses::total 125970 # number of demand (read+write) misses system.l2c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_miss_latency 5087360000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_rate::0 0.150795 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::1 22.502477 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 22.653272 # mshr miss rate for demand accesses -system.l2c.demand_mshr_misses 127184 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_miss_latency 5038800000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_rate::0 0.148928 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::1 22.494643 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 22.643571 # mshr miss rate for demand accesses +system.l2c.demand_mshr_misses 125970 # number of demand (read+write) MSHR misses system.l2c.fast_writes 0 # number of fast writes performed system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.occ_%::0 0.086431 # Average percentage of cache occupancy -system.l2c.occ_%::1 0.477933 # Average percentage of cache occupancy -system.l2c.occ_blocks::0 5664.361976 # Average occupied blocks per context -system.l2c.occ_blocks::1 31321.847814 # Average occupied blocks per context -system.l2c.overall_accesses::0 843424 # number of overall (read+write) accesses -system.l2c.overall_accesses::1 5652 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 849076 # number of overall (read+write) accesses -system.l2c.overall_avg_miss_latency::0 52014.345374 # average overall miss latency -system.l2c.overall_avg_miss_latency::1 188959200 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 189011214.345374 # average overall miss latency +system.l2c.occ_%::0 0.081481 # Average percentage of cache occupancy +system.l2c.occ_%::1 0.477898 # Average percentage of cache occupancy +system.l2c.occ_blocks::0 5339.953820 # Average occupied blocks per context +system.l2c.occ_blocks::1 31319.548737 # Average occupied blocks per context +system.l2c.overall_accesses::0 845845 # number of overall (read+write) accesses +system.l2c.overall_accesses::1 5600 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 851445 # number of overall (read+write) accesses +system.l2c.overall_avg_miss_latency::0 52011.580728 # average overall miss latency +system.l2c.overall_avg_miss_latency::1 233944375 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 233996386.580728 # average overall miss latency system.l2c.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency system.l2c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.l2c.overall_hits::0 716275 # number of overall hits -system.l2c.overall_hits::1 5617 # number of overall hits -system.l2c.overall_hits::total 721892 # number of overall hits -system.l2c.overall_miss_latency 6613572000 # number of overall miss cycles -system.l2c.overall_miss_rate::0 0.150753 # miss rate for overall accesses -system.l2c.overall_miss_rate::1 0.006192 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.156946 # miss rate for overall accesses -system.l2c.overall_misses::0 127149 # number of overall misses -system.l2c.overall_misses::1 35 # number of overall misses -system.l2c.overall_misses::total 127184 # number of overall misses +system.l2c.overall_hits::0 719903 # number of overall hits +system.l2c.overall_hits::1 5572 # number of overall hits +system.l2c.overall_hits::total 725475 # number of overall hits +system.l2c.overall_miss_latency 6550442500 # number of overall miss cycles +system.l2c.overall_miss_rate::0 0.148895 # miss rate for overall accesses +system.l2c.overall_miss_rate::1 0.005000 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.153895 # miss rate for overall accesses +system.l2c.overall_misses::0 125942 # number of overall misses +system.l2c.overall_misses::1 28 # number of overall misses +system.l2c.overall_misses::total 125970 # number of overall misses system.l2c.overall_mshr_hits 0 # number of overall MSHR hits -system.l2c.overall_mshr_miss_latency 5087360000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_rate::0 0.150795 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::1 22.502477 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 22.653272 # mshr miss rate for overall accesses -system.l2c.overall_mshr_misses 127184 # number of overall MSHR misses -system.l2c.overall_mshr_uncacheable_latency 29939182000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_miss_latency 5038800000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_rate::0 0.148928 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::1 22.494643 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 22.643571 # mshr miss rate for overall accesses +system.l2c.overall_mshr_misses 125970 # number of overall MSHR misses +system.l2c.overall_mshr_uncacheable_latency 29941330000 # number of overall MSHR uncacheable cycles system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.l2c.replacements 94170 # number of replacements -system.l2c.sampled_refs 125831 # Sample count of references to valid blocks. +system.l2c.replacements 93233 # number of replacements +system.l2c.sampled_refs 124676 # Sample count of references to valid blocks. system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.l2c.tagsinuse 36986.209790 # Cycle average of tags in use -system.l2c.total_refs 877708 # Total number of references to valid blocks. +system.l2c.tagsinuse 36659.502556 # Cycle average of tags in use +system.l2c.total_refs 880307 # Total number of references to valid blocks. system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.writebacks 87626 # number of writebacks +system.l2c.writebacks 87349 # number of writebacks ---------- End Simulation Statistics ---------- |