diff options
Diffstat (limited to 'tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt')
| -rw-r--r-- | tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt | 483 |
1 files changed, 483 insertions, 0 deletions
diff --git a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt new file mode 100644 index 000000000..d35264510 --- /dev/null +++ b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt @@ -0,0 +1,483 @@ + +---------- Begin Simulation Statistics ---------- +host_inst_rate 546024 # Simulator instruction rate (inst/s) +host_mem_usage 378800 # Number of bytes of host memory used +host_seconds 92.51 # Real time elapsed on the host +host_tick_rate 1297642212 # Simulator tick rate (ticks/s) +sim_freq 1000000000000 # Frequency of simulated ticks +sim_insts 50513922 # Number of instructions simulated +sim_seconds 0.120048 # Number of seconds simulated +sim_ticks 120048264000 # Number of ticks simulated +system.cpu.dcache.LoadLockedReq_accesses::0 99871 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 99871 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_avg_miss_latency::0 14859.416446 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::1 inf # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total inf # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency 11859.416446 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_uncacheable_latency inf # average LoadLockedReq mshr uncacheable latency +system.cpu.dcache.LoadLockedReq_hits::0 94593 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 94593 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_miss_latency 78428000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_rate::0 0.052848 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_misses::0 5278 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 5278 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_mshr_miss_latency 62594000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::0 0.052848 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::1 inf # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total inf # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_misses 5278 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_uncacheable_latency 310054500 # number of LoadLockedReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_accesses::0 7793356 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 7793356 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency::0 15742.239268 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 12741.872084 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency +system.cpu.dcache.ReadReq_hits::0 7557779 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 7557779 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 3708509500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate::0 0.030228 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses::0 235577 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 235577 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_miss_latency 3001692000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::0 0.030228 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_misses 235577 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_uncacheable_latency 43427916500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.StoreCondReq_accesses::0 99870 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 99870 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_hits::0 99870 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 99870 # number of StoreCondReq hits +system.cpu.dcache.WriteReq_accesses::0 6647889 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 6647889 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_avg_miss_latency::0 40318.665363 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::1 inf # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 37318.368117 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency +system.cpu.dcache.WriteReq_hits::0 6472950 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 6472950 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 7053307000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate::0 0.026315 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses::0 174939 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 174939 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_miss_latency 6528438000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate::0 0.026315 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::1 inf # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses 174939 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_uncacheable_latency 926045500 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu.dcache.avg_refs 34.360003 # Average number of references to valid blocks. +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.demand_accesses::0 14441245 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::1 0 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 14441245 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency::0 26215.339962 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::1 inf # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total inf # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 23215.002582 # average overall mshr miss latency +system.cpu.dcache.demand_hits::0 14030729 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::1 0 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 14030729 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 10761816500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate::0 0.028427 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total no_value # miss rate for demand accesses +system.cpu.dcache.demand_misses::0 410516 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::1 0 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 410516 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 9530130000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate::0 0.028427 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 410516 # number of demand (read+write) MSHR misses +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.occ_%::0 0.994772 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::0 509.323403 # Average occupied blocks per context +system.cpu.dcache.overall_accesses::0 14441245 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::1 0 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 14441245 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency::0 26215.339962 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::1 inf # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total inf # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 23215.002582 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency +system.cpu.dcache.overall_hits::0 14030729 # number of overall hits +system.cpu.dcache.overall_hits::1 0 # number of overall hits +system.cpu.dcache.overall_hits::total 14030729 # number of overall hits +system.cpu.dcache.overall_miss_latency 10761816500 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate::0 0.028427 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total no_value # miss rate for overall accesses +system.cpu.dcache.overall_misses::0 410516 # number of overall misses +system.cpu.dcache.overall_misses::1 0 # number of overall misses +system.cpu.dcache.overall_misses::total 410516 # number of overall misses +system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 9530130000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate::0 0.028427 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 410516 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_uncacheable_latency 44353962000 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.dcache.replacements 413543 # number of replacements +system.cpu.dcache.sampled_refs 414055 # Sample count of references to valid blocks. +system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.dcache.tagsinuse 509.323403 # Cycle average of tags in use +system.cpu.dcache.total_refs 14226931 # Total number of references to valid blocks. +system.cpu.dcache.warmup_cycle 658097000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.writebacks 384690 # number of writebacks +system.cpu.dtb.accesses 15468820 # DTB accesses +system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dtb.flush_entries 2225 # Number of entries that have been flushed from TLB +system.cpu.dtb.flush_tlb 2 # Number of times complete TLB was flushed +system.cpu.dtb.flush_tlb_asid 40 # Number of times TLB was flushed by ASID +system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dtb.flush_tlb_mva_asid 33670 # Number of times TLB was flushed by MVA & ASID +system.cpu.dtb.hits 15463286 # DTB hits +system.cpu.dtb.inst_accesses 0 # ITB inst accesses +system.cpu.dtb.inst_hits 0 # ITB inst hits +system.cpu.dtb.inst_misses 0 # ITB inst misses +system.cpu.dtb.misses 5534 # DTB misses +system.cpu.dtb.perms_faults 255 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.prefetch_faults 764 # Number of TLB faults due to prefetch +system.cpu.dtb.read_accesses 8708503 # DTB read accesses +system.cpu.dtb.read_hits 8703948 # DTB read hits +system.cpu.dtb.read_misses 4555 # DTB read misses +system.cpu.dtb.write_accesses 6760317 # DTB write accesses +system.cpu.dtb.write_hits 6759338 # DTB write hits +system.cpu.dtb.write_misses 979 # DTB write misses +system.cpu.icache.ReadReq_accesses::0 41422231 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 41422231 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency::0 14804.202290 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 11802.928446 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency +system.cpu.icache.ReadReq_hits::0 40992037 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 40992037 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 6368679000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate::0 0.010386 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses::0 430194 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 430194 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_miss_latency 5077549000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::0 0.010386 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_misses 430194 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_uncacheable_latency 349111000 # number of ReadReq MSHR uncacheable cycles +system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu.icache.avg_refs 95.287550 # Average number of references to valid blocks. +system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.icache.cache_copies 0 # number of cache copies performed +system.cpu.icache.demand_accesses::0 41422231 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::1 0 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 41422231 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency::0 14804.202290 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::1 inf # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total inf # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 11802.928446 # average overall mshr miss latency +system.cpu.icache.demand_hits::0 40992037 # number of demand (read+write) hits +system.cpu.icache.demand_hits::1 0 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 40992037 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 6368679000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate::0 0.010386 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::1 no_value # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total no_value # miss rate for demand accesses +system.cpu.icache.demand_misses::0 430194 # number of demand (read+write) misses +system.cpu.icache.demand_misses::1 0 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 430194 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 5077549000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate::0 0.010386 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_misses 430194 # number of demand (read+write) MSHR misses +system.cpu.icache.fast_writes 0 # number of fast writes performed +system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.icache.occ_%::0 0.948192 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::0 485.474186 # Average occupied blocks per context +system.cpu.icache.overall_accesses::0 41422231 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::1 0 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 41422231 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency::0 14804.202290 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::1 inf # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total inf # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 11802.928446 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency +system.cpu.icache.overall_hits::0 40992037 # number of overall hits +system.cpu.icache.overall_hits::1 0 # number of overall hits +system.cpu.icache.overall_hits::total 40992037 # number of overall hits +system.cpu.icache.overall_miss_latency 6368679000 # number of overall miss cycles +system.cpu.icache.overall_miss_rate::0 0.010386 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::1 no_value # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total no_value # miss rate for overall accesses +system.cpu.icache.overall_misses::0 430194 # number of overall misses +system.cpu.icache.overall_misses::1 0 # number of overall misses +system.cpu.icache.overall_misses::total 430194 # number of overall misses +system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 5077549000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate::0 0.010386 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_misses 430194 # number of overall MSHR misses +system.cpu.icache.overall_mshr_uncacheable_latency 349111000 # number of overall MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.icache.replacements 429681 # number of replacements +system.cpu.icache.sampled_refs 430193 # Sample count of references to valid blocks. +system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.icache.tagsinuse 485.474186 # Cycle average of tags in use +system.cpu.icache.total_refs 40992037 # Total number of references to valid blocks. +system.cpu.icache.warmup_cycle 14253306000 # Cycle when the warmup percentage was hit. +system.cpu.icache.writebacks 30998 # number of writebacks +system.cpu.idle_fraction 0 # Percentage of idle cycles +system.cpu.itb.accesses 41425050 # DTB accesses +system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.itb.flush_entries 1478 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_tlb 2 # Number of times complete TLB was flushed +system.cpu.itb.flush_tlb_asid 40 # Number of times TLB was flushed by ASID +system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.itb.flush_tlb_mva_asid 33670 # Number of times TLB was flushed by MVA & ASID +system.cpu.itb.hits 41422231 # DTB hits +system.cpu.itb.inst_accesses 41425050 # ITB inst accesses +system.cpu.itb.inst_hits 41422231 # ITB inst hits +system.cpu.itb.inst_misses 2819 # ITB inst misses +system.cpu.itb.misses 2819 # DTB misses +system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.kern.inst.arm 0 # number of arm instructions executed +system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed +system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu.numCycles 240096528 # number of cpu cycles simulated +system.cpu.num_insts 50513922 # Number of instructions executed +system.cpu.num_refs 16229722 # Number of memory references +system.iocache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.iocache.avg_refs no_value # Average number of references to valid blocks. +system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked +system.iocache.blocked::no_targets 0 # number of cycles access was blocked +system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.iocache.cache_copies 0 # number of cache copies performed +system.iocache.demand_accesses::0 0 # number of demand (read+write) accesses +system.iocache.demand_accesses::1 0 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 0 # number of demand (read+write) accesses +system.iocache.demand_avg_miss_latency::0 no_value # average overall miss latency +system.iocache.demand_avg_miss_latency::1 no_value # average overall miss latency +system.iocache.demand_avg_miss_latency::total no_value # average overall miss latency +system.iocache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency +system.iocache.demand_hits::0 0 # number of demand (read+write) hits +system.iocache.demand_hits::1 0 # number of demand (read+write) hits +system.iocache.demand_hits::total 0 # number of demand (read+write) hits +system.iocache.demand_miss_latency 0 # number of demand (read+write) miss cycles +system.iocache.demand_miss_rate::0 no_value # miss rate for demand accesses +system.iocache.demand_miss_rate::1 no_value # miss rate for demand accesses +system.iocache.demand_miss_rate::total no_value # miss rate for demand accesses +system.iocache.demand_misses::0 0 # number of demand (read+write) misses +system.iocache.demand_misses::1 0 # number of demand (read+write) misses +system.iocache.demand_misses::total 0 # number of demand (read+write) misses +system.iocache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.iocache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_rate::0 no_value # mshr miss rate for demand accesses +system.iocache.demand_mshr_miss_rate::1 no_value # mshr miss rate for demand accesses +system.iocache.demand_mshr_miss_rate::total no_value # mshr miss rate for demand accesses +system.iocache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses +system.iocache.fast_writes 0 # number of fast writes performed +system.iocache.mshr_cap_events 0 # number of times MSHR cap was activated +system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate +system.iocache.overall_accesses::0 0 # number of overall (read+write) accesses +system.iocache.overall_accesses::1 0 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 0 # number of overall (read+write) accesses +system.iocache.overall_avg_miss_latency::0 no_value # average overall miss latency +system.iocache.overall_avg_miss_latency::1 no_value # average overall miss latency +system.iocache.overall_avg_miss_latency::total no_value # average overall miss latency +system.iocache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency +system.iocache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency +system.iocache.overall_hits::0 0 # number of overall hits +system.iocache.overall_hits::1 0 # number of overall hits +system.iocache.overall_hits::total 0 # number of overall hits +system.iocache.overall_miss_latency 0 # number of overall miss cycles +system.iocache.overall_miss_rate::0 no_value # miss rate for overall accesses +system.iocache.overall_miss_rate::1 no_value # miss rate for overall accesses +system.iocache.overall_miss_rate::total no_value # miss rate for overall accesses +system.iocache.overall_misses::0 0 # number of overall misses +system.iocache.overall_misses::1 0 # number of overall misses +system.iocache.overall_misses::total 0 # number of overall misses +system.iocache.overall_mshr_hits 0 # number of overall MSHR hits +system.iocache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_rate::0 no_value # mshr miss rate for overall accesses +system.iocache.overall_mshr_miss_rate::1 no_value # mshr miss rate for overall accesses +system.iocache.overall_mshr_miss_rate::total no_value # mshr miss rate for overall accesses +system.iocache.overall_mshr_misses 0 # number of overall MSHR misses +system.iocache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.iocache.replacements 0 # number of replacements +system.iocache.sampled_refs 0 # Sample count of references to valid blocks. +system.iocache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.iocache.tagsinuse 0 # Cycle average of tags in use +system.iocache.total_refs 0 # Total number of references to valid blocks. +system.iocache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.iocache.writebacks 0 # number of writebacks +system.l2c.LoadLockedReq_avg_mshr_uncacheable_latency inf # average LoadLockedReq mshr uncacheable latency +system.l2c.LoadLockedReq_mshr_uncacheable_latency 234000000 # number of LoadLockedReq MSHR uncacheable cycles +system.l2c.ReadExReq_accesses::0 173200 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 173200 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_avg_miss_latency::0 52000 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::1 inf # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total inf # average ReadExReq miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_hits::0 65260 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 65260 # number of ReadExReq hits +system.l2c.ReadExReq_miss_latency 5612880000 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_rate::0 0.623210 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_misses::0 107940 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 107940 # number of ReadExReq misses +system.l2c.ReadExReq_mshr_miss_latency 4317600000 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_rate::0 0.623210 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::1 inf # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total inf # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_misses 107940 # number of ReadExReq MSHR misses +system.l2c.ReadReq_accesses::0 669099 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::1 7756 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 676855 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_avg_miss_latency::0 52101.691699 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::1 26691986.111111 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 26744087.802810 # average ReadReq miss latency +system.l2c.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_hits::0 650656 # number of ReadReq hits +system.l2c.ReadReq_hits::1 7720 # number of ReadReq hits +system.l2c.ReadReq_hits::total 658376 # number of ReadReq hits +system.l2c.ReadReq_miss_latency 960911500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_rate::0 0.027564 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::1 0.004642 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.032206 # miss rate for ReadReq accesses +system.l2c.ReadReq_misses::0 18443 # number of ReadReq misses +system.l2c.ReadReq_misses::1 36 # number of ReadReq misses +system.l2c.ReadReq_misses::total 18479 # number of ReadReq misses +system.l2c.ReadReq_mshr_miss_latency 739160000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_rate::0 0.027618 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::1 2.382543 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 2.410160 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_misses 18479 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_uncacheable_latency 33151541000 # number of ReadReq MSHR uncacheable cycles +system.l2c.UpgradeReq_accesses::0 1739 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 1739 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_avg_miss_latency::0 392.794887 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::1 inf # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total inf # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_hits::0 18 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 18 # number of UpgradeReq hits +system.l2c.UpgradeReq_miss_latency 676000 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_rate::0 0.989649 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_misses::0 1721 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 1721 # number of UpgradeReq misses +system.l2c.UpgradeReq_mshr_miss_latency 68840000 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_rate::0 0.989649 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::1 inf # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total inf # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_misses 1721 # number of UpgradeReq MSHR misses +system.l2c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_mshr_uncacheable_latency 739844000 # number of WriteReq MSHR uncacheable cycles +system.l2c.Writeback_accesses::0 415688 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 415688 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_hits::0 415688 # number of Writeback hits +system.l2c.Writeback_hits::total 415688 # number of Writeback hits +system.l2c.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.l2c.avg_refs 6.983802 # Average number of references to valid blocks. +system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked +system.l2c.blocked::no_targets 0 # number of cycles access was blocked +system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.l2c.cache_copies 0 # number of cache copies performed +system.l2c.demand_accesses::0 842299 # number of demand (read+write) accesses +system.l2c.demand_accesses::1 7756 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 850055 # number of demand (read+write) accesses +system.l2c.demand_avg_miss_latency::0 52014.839812 # average overall miss latency +system.l2c.demand_avg_miss_latency::1 182605319.444444 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 182657334.284257 # average overall miss latency +system.l2c.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency +system.l2c.demand_hits::0 715916 # number of demand (read+write) hits +system.l2c.demand_hits::1 7720 # number of demand (read+write) hits +system.l2c.demand_hits::total 723636 # number of demand (read+write) hits +system.l2c.demand_miss_latency 6573791500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_rate::0 0.150045 # miss rate for demand accesses +system.l2c.demand_miss_rate::1 0.004642 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.154687 # miss rate for demand accesses +system.l2c.demand_misses::0 126383 # number of demand (read+write) misses +system.l2c.demand_misses::1 36 # number of demand (read+write) misses +system.l2c.demand_misses::total 126419 # number of demand (read+write) misses +system.l2c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_miss_latency 5056760000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_rate::0 0.150088 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::1 16.299510 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 16.449598 # mshr miss rate for demand accesses +system.l2c.demand_mshr_misses 126419 # number of demand (read+write) MSHR misses +system.l2c.fast_writes 0 # number of fast writes performed +system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated +system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate +system.l2c.occ_%::0 0.086001 # Average percentage of cache occupancy +system.l2c.occ_%::1 0.479853 # Average percentage of cache occupancy +system.l2c.occ_blocks::0 5636.151787 # Average occupied blocks per context +system.l2c.occ_blocks::1 31447.614519 # Average occupied blocks per context +system.l2c.overall_accesses::0 842299 # number of overall (read+write) accesses +system.l2c.overall_accesses::1 7756 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 850055 # number of overall (read+write) accesses +system.l2c.overall_avg_miss_latency::0 52014.839812 # average overall miss latency +system.l2c.overall_avg_miss_latency::1 182605319.444444 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 182657334.284257 # average overall miss latency +system.l2c.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency +system.l2c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency +system.l2c.overall_hits::0 715916 # number of overall hits +system.l2c.overall_hits::1 7720 # number of overall hits +system.l2c.overall_hits::total 723636 # number of overall hits +system.l2c.overall_miss_latency 6573791500 # number of overall miss cycles +system.l2c.overall_miss_rate::0 0.150045 # miss rate for overall accesses +system.l2c.overall_miss_rate::1 0.004642 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.154687 # miss rate for overall accesses +system.l2c.overall_misses::0 126383 # number of overall misses +system.l2c.overall_misses::1 36 # number of overall misses +system.l2c.overall_misses::total 126419 # number of overall misses +system.l2c.overall_mshr_hits 0 # number of overall MSHR hits +system.l2c.overall_mshr_miss_latency 5056760000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_rate::0 0.150088 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::1 16.299510 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 16.449598 # mshr miss rate for overall accesses +system.l2c.overall_mshr_misses 126419 # number of overall MSHR misses +system.l2c.overall_mshr_uncacheable_latency 33891385000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.l2c.replacements 93485 # number of replacements +system.l2c.sampled_refs 125077 # Sample count of references to valid blocks. +system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.l2c.tagsinuse 37083.766306 # Cycle average of tags in use +system.l2c.total_refs 873513 # Total number of references to valid blocks. +system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.l2c.writebacks 87014 # number of writebacks + +---------- End Simulation Statistics ---------- |