diff options
Diffstat (limited to 'tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt')
| -rw-r--r-- | tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt | 16 |
1 files changed, 8 insertions, 8 deletions
diff --git a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt index 6471ce023..1213d5a93 100644 --- a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt +++ b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 936835 # Simulator instruction rate (inst/s) -host_mem_usage 382000 # Number of bytes of host memory used -host_seconds 54.69 # Real time elapsed on the host -host_tick_rate 2092010024 # Simulator tick rate (ticks/s) +host_inst_rate 1969505 # Simulator instruction rate (inst/s) +host_mem_usage 333648 # Number of bytes of host memory used +host_seconds 26.01 # Real time elapsed on the host +host_tick_rate 4398008175 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 51232482 # Number of instructions simulated sim_seconds 0.114406 # Number of seconds simulated @@ -101,8 +101,8 @@ system.cpu.dcache.demand_mshr_misses 410569 # nu system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_%::0 0.994514 # Average percentage of cache occupancy system.cpu.dcache.occ_blocks::0 509.191392 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.994514 # Average percentage of cache occupancy system.cpu.dcache.overall_accesses::0 14503977 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::1 0 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 14503977 # number of overall (read+write) accesses @@ -210,8 +210,8 @@ system.cpu.icache.demand_mshr_misses 434434 # nu system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_%::0 0.945963 # Average percentage of cache occupancy system.cpu.icache.occ_blocks::0 484.333151 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.945963 # Average percentage of cache occupancy system.cpu.icache.overall_accesses::0 41556337 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::1 0 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::total 41556337 # number of overall (read+write) accesses @@ -454,10 +454,10 @@ system.l2c.demand_mshr_misses 125930 # nu system.l2c.fast_writes 0 # number of fast writes performed system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.occ_%::0 0.081395 # Average percentage of cache occupancy -system.l2c.occ_%::1 0.478089 # Average percentage of cache occupancy system.l2c.occ_blocks::0 5334.310202 # Average occupied blocks per context system.l2c.occ_blocks::1 31332.032709 # Average occupied blocks per context +system.l2c.occ_percent::0 0.081395 # Average percentage of cache occupancy +system.l2c.occ_percent::1 0.478089 # Average percentage of cache occupancy system.l2c.overall_accesses::0 846263 # number of overall (read+write) accesses system.l2c.overall_accesses::1 5729 # number of overall (read+write) accesses system.l2c.overall_accesses::total 851992 # number of overall (read+write) accesses |