diff options
Diffstat (limited to 'tests/quick/10.linux-boot/ref/arm')
12 files changed, 2147 insertions, 0 deletions
diff --git a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/config.ini b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/config.ini new file mode 100644 index 000000000..034c2aa0b --- /dev/null +++ b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/config.ini @@ -0,0 +1,578 @@ +[root] +type=Root +children=system +dummy=0 + +[system] +type=LinuxArmSystem +children=bridge cpu diskmem intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus +boot_cpu_frequency=500 +boot_osflags=earlyprintk mem=128MB console=ttyAMA0 lpj=19988480 norandmaps slram=slram0,0x8000000,+0x8000000 mtdparts=slram0:- rw loglevel=8 root=/dev/mtdblock0 +init_param=0 +kernel=/chips/pd/randd/dist/binaries/vmlinux.arm +load_addr_mask=268435455 +machine_type=RealView_PBX +mem_mode=atomic +physmem=system.physmem +readfile=tests/halt.sh +symbolfile= + +[system.bridge] +type=Bridge +delay=50000 +filter_ranges_a=0:18446744073709551615 +filter_ranges_b=0:134217727 +nack_delay=4000 +req_size_a=16 +req_size_b=16 +resp_size_a=16 +resp_size_b=16 +write_ack=false +side_a=system.iobus.port[0] +side_b=system.membus.port[0] + +[system.cpu] +type=AtomicSimpleCPU +children=dcache dtb icache interrupts itb tracer +checker=Null +clock=500 +cpu_id=0 +defer_registration=false +do_checkpoint_insts=true +do_quiesce=true +do_statistics_insts=true +dtb=system.cpu.dtb +function_trace=false +function_trace_start=0 +interrupts=system.cpu.interrupts +itb=system.cpu.itb +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +numThreads=1 +phase=0 +profile=0 +progress_interval=0 +simulate_data_stalls=false +simulate_inst_stalls=false +system=system +tracer=system.cpu.tracer +width=1 +dcache_port=system.cpu.dcache.cpu_side +icache_port=system.cpu.icache.cpu_side + +[system.cpu.dcache] +type=BaseCache +addr_range=0:18446744073709551615 +assoc=4 +block_size=64 +forward_snoops=true +hash_delay=1 +latency=1000 +max_miss_count=0 +mshrs=4 +num_cpus=1 +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10000 +prefetch_on_access=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +repl=Null +size=32768 +subblock_size=0 +tgts_per_mshr=8 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.dcache_port +mem_side=system.toL2Bus.port[2] + +[system.cpu.dtb] +type=ArmTLB +children=walker +size=64 +walker=system.cpu.dtb.walker + +[system.cpu.dtb.walker] +type=ArmTableWalker +max_backoff=100000 +min_backoff=0 +sys=system +port=system.toL2Bus.port[4] + +[system.cpu.icache] +type=BaseCache +addr_range=0:18446744073709551615 +assoc=1 +block_size=64 +forward_snoops=true +hash_delay=1 +latency=1000 +max_miss_count=0 +mshrs=4 +num_cpus=1 +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10000 +prefetch_on_access=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +repl=Null +size=32768 +subblock_size=0 +tgts_per_mshr=8 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.icache_port +mem_side=system.toL2Bus.port[1] + +[system.cpu.interrupts] +type=ArmInterrupts + +[system.cpu.itb] +type=ArmTLB +children=walker +size=64 +walker=system.cpu.itb.walker + +[system.cpu.itb.walker] +type=ArmTableWalker +max_backoff=100000 +min_backoff=0 +sys=system +port=system.toL2Bus.port[3] + +[system.cpu.tracer] +type=ExeTracer + +[system.diskmem] +type=PhysicalMemory +file=/chips/pd/randd/dist/disks/ael-arm.ext2 +latency=30000 +latency_var=0 +null=false +range=134217728:268435455 +zero=false +port=system.membus.port[2] + +[system.intrctrl] +type=IntrControl +sys=system + +[system.iobus] +type=Bus +block_size=64 +bus_id=0 +clock=1000 +header_cycles=1 +use_default_range=false +width=64 +port=system.bridge.side_a system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.dmac_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.smc_fake.pio system.realview.clcd_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.gpio0_fake.pio system.realview.gpio1_fake.pio system.realview.gpio2_fake.pio system.realview.ssp_fake.pio system.realview.sci_fake.pio system.realview.aaci_fake.pio system.realview.mmc_fake.pio system.realview.kmi0_fake.pio system.realview.kmi1_fake.pio system.realview.rtc_fake.pio system.realview.flash_fake.pio system.iocache.cpu_side + +[system.iocache] +type=BaseCache +addr_range=0:134217727 +assoc=8 +block_size=64 +forward_snoops=false +hash_delay=1 +latency=50000 +max_miss_count=0 +mshrs=20 +num_cpus=1 +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=500000 +prefetch_on_access=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +repl=Null +size=1024 +subblock_size=0 +tgts_per_mshr=12 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.iobus.port[24] +mem_side=system.membus.port[5] + +[system.l2c] +type=BaseCache +addr_range=0:18446744073709551615 +assoc=8 +block_size=64 +forward_snoops=true +hash_delay=1 +latency=10000 +max_miss_count=0 +mshrs=92 +num_cpus=1 +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=100000 +prefetch_on_access=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +repl=Null +size=4194304 +subblock_size=0 +tgts_per_mshr=16 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.toL2Bus.port[0] +mem_side=system.membus.port[6] + +[system.membus] +type=Bus +children=badaddr_responder +block_size=64 +bus_id=1 +clock=1000 +header_cycles=1 +use_default_range=false +width=64 +default=system.membus.badaddr_responder.pio +port=system.bridge.side_b system.physmem.port[0] system.diskmem.port[0] system.realview.gic.pio system.realview.l2x0_fake.pio system.iocache.mem_side system.l2c.mem_side + +[system.membus.badaddr_responder] +type=IsaFake +pio_addr=0 +pio_latency=1000 +pio_size=8 +platform=system.realview +ret_bad_addr=true +ret_data16=65535 +ret_data32=4294967295 +ret_data64=18446744073709551615 +ret_data8=255 +system=system +update_data=false +warn_access=warn +pio=system.membus.default + +[system.physmem] +type=PhysicalMemory +file= +latency=30000 +latency_var=0 +null=false +range=0:134217727 +zero=true +port=system.membus.port[1] + +[system.realview] +type=RealView +children=aaci_fake clcd_fake dmac_fake flash_fake gic gpio0_fake gpio1_fake gpio2_fake kmi0_fake kmi1_fake l2x0_fake mmc_fake realview_io rtc_fake sci_fake smc_fake sp810_fake ssp_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake watchdog_fake +intrctrl=system.intrctrl +system=system + +[system.realview.aaci_fake] +type=AmbaFake +amba_id=0 +ignore_access=false +pio_addr=268451840 +pio_latency=1000 +platform=system.realview +system=system +pio=system.iobus.port[18] + +[system.realview.clcd_fake] +type=AmbaFake +amba_id=0 +ignore_access=false +pio_addr=268566528 +pio_latency=1000 +platform=system.realview +system=system +pio=system.iobus.port[10] + +[system.realview.dmac_fake] +type=AmbaFake +amba_id=0 +ignore_access=false +pio_addr=268632064 +pio_latency=1000 +platform=system.realview +system=system +pio=system.iobus.port[5] + +[system.realview.flash_fake] +type=IsaFake +pio_addr=1073741824 +pio_latency=1000 +pio_size=67108864 +platform=system.realview +ret_bad_addr=false +ret_data16=65535 +ret_data32=4294967295 +ret_data64=18446744073709551615 +ret_data8=255 +system=system +update_data=false +warn_access= +pio=system.iobus.port[23] + +[system.realview.gic] +type=Gic +cpu_addr=520093952 +cpu_pio_delay=10000 +dist_addr=520097792 +dist_pio_delay=10000 +it_lines=128 +platform=system.realview +system=system +pio=system.membus.port[3] + +[system.realview.gpio0_fake] +type=AmbaFake +amba_id=0 +ignore_access=false +pio_addr=268513280 +pio_latency=1000 +platform=system.realview +system=system +pio=system.iobus.port[13] + +[system.realview.gpio1_fake] +type=AmbaFake +amba_id=0 +ignore_access=false +pio_addr=268517376 +pio_latency=1000 +platform=system.realview +system=system +pio=system.iobus.port[14] + +[system.realview.gpio2_fake] +type=AmbaFake +amba_id=0 +ignore_access=false +pio_addr=268521472 +pio_latency=1000 +platform=system.realview +system=system +pio=system.iobus.port[15] + +[system.realview.kmi0_fake] +type=AmbaFake +amba_id=0 +ignore_access=false +pio_addr=268460032 +pio_latency=1000 +platform=system.realview +system=system +pio=system.iobus.port[20] + +[system.realview.kmi1_fake] +type=AmbaFake +amba_id=0 +ignore_access=false +pio_addr=268464128 +pio_latency=1000 +platform=system.realview +system=system +pio=system.iobus.port[21] + +[system.realview.l2x0_fake] +type=IsaFake +pio_addr=520101888 +pio_latency=1000 +pio_size=4095 +platform=system.realview +ret_bad_addr=false +ret_data16=65535 +ret_data32=4294967295 +ret_data64=18446744073709551615 +ret_data8=255 +system=system +update_data=false +warn_access= +pio=system.membus.port[4] + +[system.realview.mmc_fake] +type=AmbaFake +amba_id=0 +ignore_access=false +pio_addr=268455936 +pio_latency=1000 +platform=system.realview +system=system +pio=system.iobus.port[19] + +[system.realview.realview_io] +type=RealViewCtrl +pio_addr=268435456 +pio_latency=1000 +platform=system.realview +proc_id=201326592 +system=system +pio=system.iobus.port[2] + +[system.realview.rtc_fake] +type=AmbaFake +amba_id=266289 +ignore_access=false +pio_addr=268529664 +pio_latency=1000 +platform=system.realview +system=system +pio=system.iobus.port[22] + +[system.realview.sci_fake] +type=AmbaFake +amba_id=0 +ignore_access=false +pio_addr=268492800 +pio_latency=1000 +platform=system.realview +system=system +pio=system.iobus.port[17] + +[system.realview.smc_fake] +type=AmbaFake +amba_id=0 +ignore_access=false +pio_addr=269357056 +pio_latency=1000 +platform=system.realview +system=system +pio=system.iobus.port[9] + +[system.realview.sp810_fake] +type=AmbaFake +amba_id=0 +ignore_access=true +pio_addr=268439552 +pio_latency=1000 +platform=system.realview +system=system +pio=system.iobus.port[11] + +[system.realview.ssp_fake] +type=AmbaFake +amba_id=0 +ignore_access=false +pio_addr=268488704 +pio_latency=1000 +platform=system.realview +system=system +pio=system.iobus.port[16] + +[system.realview.timer0] +type=Sp804 +amba_id=1316868 +clock0=1000000 +clock1=1000000 +gic=system.realview.gic +int_num0=36 +int_num1=36 +pio_addr=268505088 +pio_latency=1000 +platform=system.realview +system=system +pio=system.iobus.port[3] + +[system.realview.timer1] +type=Sp804 +amba_id=1316868 +clock0=1000000 +clock1=1000000 +gic=system.realview.gic +int_num0=37 +int_num1=37 +pio_addr=268509184 +pio_latency=1000 +platform=system.realview +system=system +pio=system.iobus.port[4] + +[system.realview.uart] +type=Pl011 +end_on_eot=false +gic=system.realview.gic +int_delay=100000 +int_num=44 +pio_addr=268472320 +pio_latency=1000 +platform=system.realview +system=system +terminal=system.terminal +pio=system.iobus.port[1] + +[system.realview.uart1_fake] +type=AmbaFake +amba_id=0 +ignore_access=false +pio_addr=268476416 +pio_latency=1000 +platform=system.realview +system=system +pio=system.iobus.port[6] + +[system.realview.uart2_fake] +type=AmbaFake +amba_id=0 +ignore_access=false +pio_addr=268480512 +pio_latency=1000 +platform=system.realview +system=system +pio=system.iobus.port[7] + +[system.realview.uart3_fake] +type=AmbaFake +amba_id=0 +ignore_access=false +pio_addr=268484608 +pio_latency=1000 +platform=system.realview +system=system +pio=system.iobus.port[8] + +[system.realview.watchdog_fake] +type=AmbaFake +amba_id=0 +ignore_access=false +pio_addr=268500992 +pio_latency=1000 +platform=system.realview +system=system +pio=system.iobus.port[12] + +[system.terminal] +type=Terminal +intr_control=system.intrctrl +number=0 +output=true +port=3456 + +[system.toL2Bus] +type=Bus +block_size=64 +bus_id=0 +clock=1000 +header_cycles=1 +use_default_range=false +width=64 +port=system.l2c.cpu_side system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port + diff --git a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/simerr b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/simerr new file mode 100755 index 000000000..122561307 --- /dev/null +++ b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/simerr @@ -0,0 +1,39 @@ +warn: Sockets disabled, not accepting terminal connections +For more information see: http://www.m5sim.org/warn/8742226b +warn: Sockets disabled, not accepting gdb connections +For more information see: http://www.m5sim.org/warn/d946bea6 +warn: The clidr register always reports 0 caches. +For more information see: http://www.m5sim.org/warn/23a3c326 +warn: The csselr register isn't implemented. +For more information see: http://www.m5sim.org/warn/c0c486b8 +warn: Need to flush all TLBs in MP +For more information see: http://www.m5sim.org/warn/6cccf999 +warn: instruction 'mcr bpiall' unimplemented +For more information see: http://www.m5sim.org/warn/21b09adb +warn: The ccsidr register isn't implemented and always reads as 0. +For more information see: http://www.m5sim.org/warn/2c4acb9c +warn: instruction 'mcr dccimvac' unimplemented +For more information see: http://www.m5sim.org/warn/21b09adb +warn: Need to flush all TLBs in MP +For more information see: http://www.m5sim.org/warn/6cccf999 +warn: instruction 'mcr bpiall' unimplemented +For more information see: http://www.m5sim.org/warn/21b09adb +warn: instruction 'mcr dccmvau' unimplemented +For more information see: http://www.m5sim.org/warn/21b09adb +warn: instruction 'mcr icimvau' unimplemented +For more information see: http://www.m5sim.org/warn/21b09adb +warn: instruction 'mcr bpiall' unimplemented +For more information see: http://www.m5sim.org/warn/21b09adb +warn: instruction 'mcr bpiall' unimplemented +For more information see: http://www.m5sim.org/warn/21b09adb +warn: Returning thumbEE disabled for now since we don't support CP14config registers and jumping to ThumbEE vectors +For more information see: http://www.m5sim.org/warn/7998f2ea +warn: instruction 'mcr bpiall' unimplemented +For more information see: http://www.m5sim.org/warn/21b09adb +warn: instruction 'mcr bpiall' unimplemented +For more information see: http://www.m5sim.org/warn/21b09adb +warn: Need to flush all TLBs in MP +For more information see: http://www.m5sim.org/warn/6cccf999 +warn: instruction 'mcr bpiall' unimplemented +For more information see: http://www.m5sim.org/warn/21b09adb +hack: be nice to actually delete the event here diff --git a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/simout b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/simout new file mode 100755 index 000000000..7d0a8d3b5 --- /dev/null +++ b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/simout @@ -0,0 +1,16 @@ +M5 Simulator System + +Copyright (c) 2001-2008 +The Regents of The University of Michigan +All Rights Reserved + + +M5 compiled Oct 1 2010 22:55:27 +M5 revision 8dd1bd50f739 7724 default qtip tip ext/vfp_serial_nonspec_flags.patch +M5 started Oct 1 2010 23:07:06 +M5 executing on aus-bc3-b7 +command line: build/ARM_FS/m5.opt -d build/ARM_FS/tests/opt/quick/10.linux-boot/arm/linux/realview-simple-atomic -re tests/run.py build/ARM_FS/tests/opt/quick/10.linux-boot/arm/linux/realview-simple-atomic +Global frequency set at 1000000000000 ticks per second +info: kernel located at: /chips/pd/randd/dist/binaries/vmlinux.arm +info: Entering event queue @ 0. Starting simulation... +Exiting @ tick 25749159000 because m5_exit instruction encountered diff --git a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt new file mode 100644 index 000000000..11c550b7b --- /dev/null +++ b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt @@ -0,0 +1,399 @@ + +---------- Begin Simulation Statistics ---------- +host_inst_rate 1902681 # Simulator instruction rate (inst/s) +host_mem_usage 378772 # Number of bytes of host memory used +host_seconds 26.70 # Real time elapsed on the host +host_tick_rate 964308738 # Simulator tick rate (ticks/s) +sim_freq 1000000000000 # Frequency of simulated ticks +sim_insts 50805202 # Number of instructions simulated +sim_seconds 0.025749 # Number of seconds simulated +sim_ticks 25749159000 # Number of ticks simulated +system.cpu.dcache.LoadLockedReq_accesses::0 96510 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 96510 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_hits::0 91456 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 91456 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_miss_rate::0 0.052368 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_misses::0 5054 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 5054 # number of LoadLockedReq misses +system.cpu.dcache.ReadReq_accesses::0 7686910 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 7686910 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_hits::0 7455461 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 7455461 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_rate::0 0.030109 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses::0 231449 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 231449 # number of ReadReq misses +system.cpu.dcache.StoreCondReq_accesses::0 96509 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 96509 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_hits::0 96509 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 96509 # number of StoreCondReq hits +system.cpu.dcache.WriteReq_accesses::0 6583516 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 6583516 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_hits::0 6409119 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 6409119 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_rate::0 0.026490 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses::0 174397 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 174397 # number of WriteReq misses +system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu.dcache.avg_refs 34.349377 # Average number of references to valid blocks. +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.demand_accesses::0 14270426 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::1 0 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 14270426 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency::0 0 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::1 no_value # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total no_value # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency +system.cpu.dcache.demand_hits::0 13864580 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::1 0 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 13864580 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 0 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate::0 0.028440 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total no_value # miss rate for demand accesses +system.cpu.dcache.demand_misses::0 405846 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::1 0 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 405846 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate::0 0 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::1 no_value # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total no_value # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.occ_%::0 0.999474 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::0 511.730497 # Average occupied blocks per context +system.cpu.dcache.overall_accesses::0 14270426 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::1 0 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 14270426 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency::0 0 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::1 no_value # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total no_value # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency +system.cpu.dcache.overall_hits::0 13864580 # number of overall hits +system.cpu.dcache.overall_hits::1 0 # number of overall hits +system.cpu.dcache.overall_hits::total 13864580 # number of overall hits +system.cpu.dcache.overall_miss_latency 0 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate::0 0.028440 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total no_value # miss rate for overall accesses +system.cpu.dcache.overall_misses::0 405846 # number of overall misses +system.cpu.dcache.overall_misses::1 0 # number of overall misses +system.cpu.dcache.overall_misses::total 405846 # number of overall misses +system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate::0 0 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::1 no_value # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total no_value # mshr miss rate for overall accesses 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TLB faults due to domain restrictions +system.cpu.dtb.flush_entries 2258 # Number of entries that have been flushed from TLB +system.cpu.dtb.flush_tlb 2 # Number of times complete TLB was flushed +system.cpu.dtb.flush_tlb_asid 40 # Number of times TLB was flushed by ASID +system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dtb.flush_tlb_mva_asid 33670 # Number of times TLB was flushed by MVA & ASID +system.cpu.dtb.hits 15281544 # DTB hits +system.cpu.dtb.inst_accesses 0 # ITB inst accesses +system.cpu.dtb.inst_hits 0 # ITB inst hits +system.cpu.dtb.inst_misses 0 # ITB inst misses +system.cpu.dtb.misses 5494 # DTB misses +system.cpu.dtb.perms_faults 255 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.prefetch_faults 771 # Number of TLB faults due to prefetch +system.cpu.dtb.read_accesses 8595265 # DTB read accesses +system.cpu.dtb.read_hits 8590763 # DTB read hits +system.cpu.dtb.read_misses 4502 # DTB read misses +system.cpu.dtb.write_accesses 6691773 # DTB write accesses +system.cpu.dtb.write_hits 6690781 # DTB write hits +system.cpu.dtb.write_misses 992 # DTB write misses +system.cpu.icache.ReadReq_accesses::0 41062986 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 41062986 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_hits::0 40634897 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 40634897 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_rate::0 0.010425 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses::0 428089 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 428089 # number of ReadReq misses +system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu.icache.avg_refs 94.921831 # Average number of references to valid blocks. +system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.icache.cache_copies 0 # number of cache copies performed +system.cpu.icache.demand_accesses::0 41062986 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::1 0 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 41062986 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency::0 0 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::1 no_value # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total no_value # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency +system.cpu.icache.demand_hits::0 40634897 # number of demand (read+write) hits +system.cpu.icache.demand_hits::1 0 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 40634897 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 0 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate::0 0.010425 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::1 no_value # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total no_value # miss rate for demand accesses +system.cpu.icache.demand_misses::0 428089 # number of demand (read+write) misses +system.cpu.icache.demand_misses::1 0 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 428089 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate::0 0 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::1 no_value # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total no_value # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses +system.cpu.icache.fast_writes 0 # number of fast writes performed +system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.icache.occ_%::0 0.928964 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::0 475.629536 # Average occupied blocks per context +system.cpu.icache.overall_accesses::0 41062986 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::1 0 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 41062986 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency::0 0 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::1 no_value # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total no_value # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency +system.cpu.icache.overall_hits::0 40634897 # number of overall hits +system.cpu.icache.overall_hits::1 0 # number of overall hits +system.cpu.icache.overall_hits::total 40634897 # number of overall hits +system.cpu.icache.overall_miss_latency 0 # number of overall miss cycles +system.cpu.icache.overall_miss_rate::0 0.010425 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::1 no_value # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total no_value # miss rate for overall accesses +system.cpu.icache.overall_misses::0 428089 # number of overall misses +system.cpu.icache.overall_misses::1 0 # number of overall misses +system.cpu.icache.overall_misses::total 428089 # number of overall misses +system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate::0 0 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::1 no_value # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total no_value # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_misses 0 # number of overall MSHR misses +system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.icache.replacements 427576 # number of replacements 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+system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu.numCycles 51498319 # number of cpu cycles simulated +system.cpu.num_insts 50805202 # Number of instructions executed +system.cpu.num_refs 16039990 # Number of memory references +system.iocache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.iocache.avg_refs no_value # Average number of references to valid blocks. +system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked +system.iocache.blocked::no_targets 0 # number of cycles access was blocked +system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.iocache.cache_copies 0 # number of cache copies performed +system.iocache.demand_accesses::0 0 # number of demand (read+write) accesses +system.iocache.demand_accesses::1 0 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 0 # number of demand (read+write) accesses +system.iocache.demand_avg_miss_latency::0 no_value # average overall miss latency +system.iocache.demand_avg_miss_latency::1 no_value # average overall miss latency +system.iocache.demand_avg_miss_latency::total no_value # average overall miss latency +system.iocache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency +system.iocache.demand_hits::0 0 # number of demand (read+write) hits +system.iocache.demand_hits::1 0 # number of demand (read+write) hits +system.iocache.demand_hits::total 0 # number of demand (read+write) hits +system.iocache.demand_miss_latency 0 # number of demand (read+write) miss cycles +system.iocache.demand_miss_rate::0 no_value # miss rate for demand accesses +system.iocache.demand_miss_rate::1 no_value # miss rate for demand accesses +system.iocache.demand_miss_rate::total no_value # miss rate for demand accesses +system.iocache.demand_misses::0 0 # number of demand (read+write) misses +system.iocache.demand_misses::1 0 # number of demand (read+write) misses +system.iocache.demand_misses::total 0 # number of demand (read+write) misses +system.iocache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.iocache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_rate::0 no_value # mshr miss rate for demand accesses +system.iocache.demand_mshr_miss_rate::1 no_value # mshr miss rate for demand accesses +system.iocache.demand_mshr_miss_rate::total no_value # mshr miss rate for demand accesses +system.iocache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses +system.iocache.fast_writes 0 # number of fast writes performed +system.iocache.mshr_cap_events 0 # number of times MSHR cap was activated +system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate +system.iocache.overall_accesses::0 0 # number of overall (read+write) accesses +system.iocache.overall_accesses::1 0 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 0 # number of overall (read+write) accesses +system.iocache.overall_avg_miss_latency::0 no_value # average overall miss latency +system.iocache.overall_avg_miss_latency::1 no_value # average overall miss latency +system.iocache.overall_avg_miss_latency::total no_value # average overall miss latency +system.iocache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency +system.iocache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency +system.iocache.overall_hits::0 0 # number of overall hits +system.iocache.overall_hits::1 0 # number of overall hits +system.iocache.overall_hits::total 0 # number of overall hits +system.iocache.overall_miss_latency 0 # number of overall miss cycles +system.iocache.overall_miss_rate::0 no_value # miss rate for overall accesses +system.iocache.overall_miss_rate::1 no_value # miss rate for overall accesses +system.iocache.overall_miss_rate::total no_value # miss rate for overall accesses +system.iocache.overall_misses::0 0 # number of overall misses +system.iocache.overall_misses::1 0 # number of overall misses +system.iocache.overall_misses::total 0 # number of overall misses +system.iocache.overall_mshr_hits 0 # number of overall MSHR hits +system.iocache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_rate::0 no_value # mshr miss rate for overall accesses +system.iocache.overall_mshr_miss_rate::1 no_value # mshr miss rate for overall accesses +system.iocache.overall_mshr_miss_rate::total no_value # mshr miss rate for overall accesses +system.iocache.overall_mshr_misses 0 # number of overall MSHR misses +system.iocache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.iocache.replacements 0 # number of replacements +system.iocache.sampled_refs 0 # Sample count of references to valid blocks. +system.iocache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.iocache.tagsinuse 0 # Cycle average of tags in use +system.iocache.total_refs 0 # Total number of references to valid blocks. +system.iocache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.iocache.writebacks 0 # number of writebacks +system.l2c.ReadExReq_accesses::0 172654 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 172654 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_hits::0 63568 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 63568 # number of ReadExReq hits +system.l2c.ReadExReq_miss_rate::0 0.631819 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_misses::0 109086 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 109086 # number of ReadExReq misses +system.l2c.ReadReq_accesses::0 662584 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::1 6745 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 669329 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_hits::0 644874 # number of ReadReq hits +system.l2c.ReadReq_hits::1 6723 # number of ReadReq hits +system.l2c.ReadReq_hits::total 651597 # number of ReadReq hits +system.l2c.ReadReq_miss_rate::0 0.026729 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::1 0.003262 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.029990 # miss rate for ReadReq accesses +system.l2c.ReadReq_misses::0 17710 # number of ReadReq misses +system.l2c.ReadReq_misses::1 22 # number of ReadReq misses +system.l2c.ReadReq_misses::total 17732 # number of ReadReq misses +system.l2c.UpgradeReq_accesses::0 1743 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 1743 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_hits::0 17 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 17 # number of UpgradeReq hits +system.l2c.UpgradeReq_miss_rate::0 0.990247 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_misses::0 1726 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 1726 # number of UpgradeReq misses +system.l2c.Writeback_accesses::0 411271 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 411271 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_hits::0 411271 # number of Writeback hits +system.l2c.Writeback_hits::total 411271 # number of Writeback hits +system.l2c.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.l2c.avg_refs 6.881395 # Average number of references to valid blocks. +system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked +system.l2c.blocked::no_targets 0 # number of cycles access was blocked +system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.l2c.cache_copies 0 # number of cache copies performed +system.l2c.demand_accesses::0 835238 # number of demand (read+write) accesses +system.l2c.demand_accesses::1 6745 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 841983 # number of demand (read+write) accesses +system.l2c.demand_avg_miss_latency::0 0 # average overall miss latency +system.l2c.demand_avg_miss_latency::1 0 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 0 # average overall miss latency +system.l2c.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency +system.l2c.demand_hits::0 708442 # number of demand (read+write) hits +system.l2c.demand_hits::1 6723 # number of demand (read+write) hits +system.l2c.demand_hits::total 715165 # number of demand (read+write) hits +system.l2c.demand_miss_latency 0 # number of demand (read+write) miss cycles +system.l2c.demand_miss_rate::0 0.151808 # miss rate for demand accesses +system.l2c.demand_miss_rate::1 0.003262 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.155070 # miss rate for demand accesses +system.l2c.demand_misses::0 126796 # number of demand (read+write) misses +system.l2c.demand_misses::1 22 # number of demand (read+write) misses +system.l2c.demand_misses::total 126818 # number of demand (read+write) misses +system.l2c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_rate::0 0 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::1 0 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0 # mshr miss rate for demand accesses +system.l2c.demand_mshr_misses 0 # number of demand (read+write) MSHR misses +system.l2c.fast_writes 0 # number of fast writes performed +system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated +system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate +system.l2c.occ_%::0 0.072867 # Average percentage of cache occupancy +system.l2c.occ_%::1 0.479441 # Average percentage of cache occupancy +system.l2c.occ_blocks::0 4775.385687 # Average occupied blocks per context +system.l2c.occ_blocks::1 31420.668700 # Average occupied blocks per context +system.l2c.overall_accesses::0 835238 # number of overall (read+write) accesses +system.l2c.overall_accesses::1 6745 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 841983 # number of overall (read+write) accesses +system.l2c.overall_avg_miss_latency::0 0 # average overall miss latency +system.l2c.overall_avg_miss_latency::1 0 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 0 # average overall miss latency +system.l2c.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency +system.l2c.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency +system.l2c.overall_hits::0 708442 # number of overall hits +system.l2c.overall_hits::1 6723 # number of overall hits +system.l2c.overall_hits::total 715165 # number of overall hits +system.l2c.overall_miss_latency 0 # number of overall miss cycles +system.l2c.overall_miss_rate::0 0.151808 # miss rate for overall accesses +system.l2c.overall_miss_rate::1 0.003262 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.155070 # miss rate for overall accesses +system.l2c.overall_misses::0 126796 # number of overall misses +system.l2c.overall_misses::1 22 # number of overall misses +system.l2c.overall_misses::total 126818 # number of overall misses +system.l2c.overall_mshr_hits 0 # number of overall MSHR hits +system.l2c.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_rate::0 0 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::1 0 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0 # mshr miss rate for overall accesses +system.l2c.overall_mshr_misses 0 # number of overall MSHR misses +system.l2c.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.l2c.replacements 94668 # number of replacements +system.l2c.sampled_refs 125475 # Sample count of references to valid blocks. +system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.l2c.tagsinuse 36196.054387 # Cycle average of tags in use +system.l2c.total_refs 863443 # Total number of references to valid blocks. +system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.l2c.writebacks 88928 # number of writebacks + +---------- End Simulation Statistics ---------- diff --git a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/status b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/status new file mode 100644 index 000000000..82440bd4a --- /dev/null +++ b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/status @@ -0,0 +1 @@ +build/ARM_FS/tests/opt/quick/10.linux-boot/arm/linux/realview-simple-atomic passed. diff --git a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/system.terminal b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/system.terminal Binary files differnew file mode 100644 index 000000000..afc1a18fe --- /dev/null +++ b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/system.terminal diff --git a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/config.ini b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/config.ini new file mode 100644 index 000000000..a4062b9b2 --- /dev/null +++ b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/config.ini @@ -0,0 +1,575 @@ +[root] +type=Root +children=system +dummy=0 + +[system] +type=LinuxArmSystem +children=bridge cpu diskmem intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus +boot_cpu_frequency=500 +boot_osflags=earlyprintk mem=128MB console=ttyAMA0 lpj=19988480 norandmaps slram=slram0,0x8000000,+0x8000000 mtdparts=slram0:- rw loglevel=8 root=/dev/mtdblock0 +init_param=0 +kernel=/chips/pd/randd/dist/binaries/vmlinux.arm +load_addr_mask=268435455 +machine_type=RealView_PBX +mem_mode=timing +physmem=system.physmem +readfile=tests/halt.sh +symbolfile= + +[system.bridge] +type=Bridge +delay=50000 +filter_ranges_a=0:18446744073709551615 +filter_ranges_b=0:134217727 +nack_delay=4000 +req_size_a=16 +req_size_b=16 +resp_size_a=16 +resp_size_b=16 +write_ack=false +side_a=system.iobus.port[0] +side_b=system.membus.port[0] + +[system.cpu] +type=TimingSimpleCPU +children=dcache dtb icache interrupts itb tracer +checker=Null +clock=500 +cpu_id=0 +defer_registration=false +do_checkpoint_insts=true +do_quiesce=true +do_statistics_insts=true +dtb=system.cpu.dtb +function_trace=false +function_trace_start=0 +interrupts=system.cpu.interrupts +itb=system.cpu.itb +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +numThreads=1 +phase=0 +profile=0 +progress_interval=0 +system=system +tracer=system.cpu.tracer +dcache_port=system.cpu.dcache.cpu_side +icache_port=system.cpu.icache.cpu_side + +[system.cpu.dcache] +type=BaseCache +addr_range=0:18446744073709551615 +assoc=4 +block_size=64 +forward_snoops=true +hash_delay=1 +latency=1000 +max_miss_count=0 +mshrs=4 +num_cpus=1 +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10000 +prefetch_on_access=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +repl=Null +size=32768 +subblock_size=0 +tgts_per_mshr=8 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.dcache_port +mem_side=system.toL2Bus.port[2] + +[system.cpu.dtb] +type=ArmTLB +children=walker +size=64 +walker=system.cpu.dtb.walker + +[system.cpu.dtb.walker] +type=ArmTableWalker +max_backoff=100000 +min_backoff=0 +sys=system +port=system.toL2Bus.port[4] + +[system.cpu.icache] +type=BaseCache +addr_range=0:18446744073709551615 +assoc=1 +block_size=64 +forward_snoops=true +hash_delay=1 +latency=1000 +max_miss_count=0 +mshrs=4 +num_cpus=1 +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10000 +prefetch_on_access=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +repl=Null +size=32768 +subblock_size=0 +tgts_per_mshr=8 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.icache_port +mem_side=system.toL2Bus.port[1] + +[system.cpu.interrupts] +type=ArmInterrupts + +[system.cpu.itb] +type=ArmTLB +children=walker +size=64 +walker=system.cpu.itb.walker + +[system.cpu.itb.walker] +type=ArmTableWalker +max_backoff=100000 +min_backoff=0 +sys=system +port=system.toL2Bus.port[3] + +[system.cpu.tracer] +type=ExeTracer + +[system.diskmem] +type=PhysicalMemory +file=/chips/pd/randd/dist/disks/ael-arm.ext2 +latency=30000 +latency_var=0 +null=false +range=134217728:268435455 +zero=false +port=system.membus.port[2] + +[system.intrctrl] +type=IntrControl +sys=system + +[system.iobus] +type=Bus +block_size=64 +bus_id=0 +clock=1000 +header_cycles=1 +use_default_range=false +width=64 +port=system.bridge.side_a system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.dmac_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.smc_fake.pio system.realview.clcd_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.gpio0_fake.pio system.realview.gpio1_fake.pio system.realview.gpio2_fake.pio system.realview.ssp_fake.pio system.realview.sci_fake.pio system.realview.aaci_fake.pio system.realview.mmc_fake.pio system.realview.kmi0_fake.pio system.realview.kmi1_fake.pio system.realview.rtc_fake.pio system.realview.flash_fake.pio system.iocache.cpu_side + +[system.iocache] +type=BaseCache +addr_range=0:134217727 +assoc=8 +block_size=64 +forward_snoops=false +hash_delay=1 +latency=50000 +max_miss_count=0 +mshrs=20 +num_cpus=1 +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=500000 +prefetch_on_access=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +repl=Null +size=1024 +subblock_size=0 +tgts_per_mshr=12 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.iobus.port[24] +mem_side=system.membus.port[5] + +[system.l2c] +type=BaseCache +addr_range=0:18446744073709551615 +assoc=8 +block_size=64 +forward_snoops=true +hash_delay=1 +latency=10000 +max_miss_count=0 +mshrs=92 +num_cpus=1 +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=100000 +prefetch_on_access=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +repl=Null +size=4194304 +subblock_size=0 +tgts_per_mshr=16 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.toL2Bus.port[0] +mem_side=system.membus.port[6] + +[system.membus] +type=Bus +children=badaddr_responder +block_size=64 +bus_id=1 +clock=1000 +header_cycles=1 +use_default_range=false +width=64 +default=system.membus.badaddr_responder.pio +port=system.bridge.side_b system.physmem.port[0] system.diskmem.port[0] system.realview.gic.pio system.realview.l2x0_fake.pio system.iocache.mem_side system.l2c.mem_side + +[system.membus.badaddr_responder] +type=IsaFake +pio_addr=0 +pio_latency=1000 +pio_size=8 +platform=system.realview +ret_bad_addr=true +ret_data16=65535 +ret_data32=4294967295 +ret_data64=18446744073709551615 +ret_data8=255 +system=system +update_data=false +warn_access=warn +pio=system.membus.default + +[system.physmem] +type=PhysicalMemory +file= +latency=30000 +latency_var=0 +null=false +range=0:134217727 +zero=true +port=system.membus.port[1] + +[system.realview] +type=RealView +children=aaci_fake clcd_fake dmac_fake flash_fake gic gpio0_fake gpio1_fake gpio2_fake kmi0_fake kmi1_fake l2x0_fake mmc_fake realview_io rtc_fake sci_fake smc_fake sp810_fake ssp_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake watchdog_fake +intrctrl=system.intrctrl +system=system + +[system.realview.aaci_fake] +type=AmbaFake +amba_id=0 +ignore_access=false +pio_addr=268451840 +pio_latency=1000 +platform=system.realview +system=system +pio=system.iobus.port[18] + +[system.realview.clcd_fake] +type=AmbaFake +amba_id=0 +ignore_access=false +pio_addr=268566528 +pio_latency=1000 +platform=system.realview +system=system +pio=system.iobus.port[10] + +[system.realview.dmac_fake] +type=AmbaFake +amba_id=0 +ignore_access=false +pio_addr=268632064 +pio_latency=1000 +platform=system.realview +system=system +pio=system.iobus.port[5] + +[system.realview.flash_fake] +type=IsaFake +pio_addr=1073741824 +pio_latency=1000 +pio_size=67108864 +platform=system.realview +ret_bad_addr=false +ret_data16=65535 +ret_data32=4294967295 +ret_data64=18446744073709551615 +ret_data8=255 +system=system +update_data=false +warn_access= +pio=system.iobus.port[23] + +[system.realview.gic] +type=Gic +cpu_addr=520093952 +cpu_pio_delay=10000 +dist_addr=520097792 +dist_pio_delay=10000 +it_lines=128 +platform=system.realview +system=system +pio=system.membus.port[3] + +[system.realview.gpio0_fake] +type=AmbaFake +amba_id=0 +ignore_access=false +pio_addr=268513280 +pio_latency=1000 +platform=system.realview +system=system +pio=system.iobus.port[13] + +[system.realview.gpio1_fake] +type=AmbaFake +amba_id=0 +ignore_access=false +pio_addr=268517376 +pio_latency=1000 +platform=system.realview +system=system +pio=system.iobus.port[14] + +[system.realview.gpio2_fake] +type=AmbaFake +amba_id=0 +ignore_access=false +pio_addr=268521472 +pio_latency=1000 +platform=system.realview +system=system +pio=system.iobus.port[15] + +[system.realview.kmi0_fake] +type=AmbaFake +amba_id=0 +ignore_access=false +pio_addr=268460032 +pio_latency=1000 +platform=system.realview +system=system +pio=system.iobus.port[20] + +[system.realview.kmi1_fake] +type=AmbaFake +amba_id=0 +ignore_access=false +pio_addr=268464128 +pio_latency=1000 +platform=system.realview +system=system +pio=system.iobus.port[21] + +[system.realview.l2x0_fake] +type=IsaFake +pio_addr=520101888 +pio_latency=1000 +pio_size=4095 +platform=system.realview +ret_bad_addr=false +ret_data16=65535 +ret_data32=4294967295 +ret_data64=18446744073709551615 +ret_data8=255 +system=system +update_data=false +warn_access= +pio=system.membus.port[4] + +[system.realview.mmc_fake] +type=AmbaFake +amba_id=0 +ignore_access=false +pio_addr=268455936 +pio_latency=1000 +platform=system.realview +system=system +pio=system.iobus.port[19] + +[system.realview.realview_io] +type=RealViewCtrl +pio_addr=268435456 +pio_latency=1000 +platform=system.realview +proc_id=201326592 +system=system +pio=system.iobus.port[2] + +[system.realview.rtc_fake] +type=AmbaFake +amba_id=266289 +ignore_access=false +pio_addr=268529664 +pio_latency=1000 +platform=system.realview +system=system +pio=system.iobus.port[22] + +[system.realview.sci_fake] +type=AmbaFake +amba_id=0 +ignore_access=false +pio_addr=268492800 +pio_latency=1000 +platform=system.realview +system=system +pio=system.iobus.port[17] + +[system.realview.smc_fake] +type=AmbaFake +amba_id=0 +ignore_access=false +pio_addr=269357056 +pio_latency=1000 +platform=system.realview +system=system +pio=system.iobus.port[9] + +[system.realview.sp810_fake] +type=AmbaFake +amba_id=0 +ignore_access=true +pio_addr=268439552 +pio_latency=1000 +platform=system.realview +system=system +pio=system.iobus.port[11] + +[system.realview.ssp_fake] +type=AmbaFake +amba_id=0 +ignore_access=false +pio_addr=268488704 +pio_latency=1000 +platform=system.realview +system=system +pio=system.iobus.port[16] + +[system.realview.timer0] +type=Sp804 +amba_id=1316868 +clock0=1000000 +clock1=1000000 +gic=system.realview.gic +int_num0=36 +int_num1=36 +pio_addr=268505088 +pio_latency=1000 +platform=system.realview +system=system +pio=system.iobus.port[3] + +[system.realview.timer1] +type=Sp804 +amba_id=1316868 +clock0=1000000 +clock1=1000000 +gic=system.realview.gic +int_num0=37 +int_num1=37 +pio_addr=268509184 +pio_latency=1000 +platform=system.realview +system=system +pio=system.iobus.port[4] + +[system.realview.uart] +type=Pl011 +end_on_eot=false +gic=system.realview.gic +int_delay=100000 +int_num=44 +pio_addr=268472320 +pio_latency=1000 +platform=system.realview +system=system +terminal=system.terminal +pio=system.iobus.port[1] + +[system.realview.uart1_fake] +type=AmbaFake +amba_id=0 +ignore_access=false +pio_addr=268476416 +pio_latency=1000 +platform=system.realview +system=system +pio=system.iobus.port[6] + +[system.realview.uart2_fake] +type=AmbaFake +amba_id=0 +ignore_access=false +pio_addr=268480512 +pio_latency=1000 +platform=system.realview +system=system +pio=system.iobus.port[7] + +[system.realview.uart3_fake] +type=AmbaFake +amba_id=0 +ignore_access=false +pio_addr=268484608 +pio_latency=1000 +platform=system.realview +system=system +pio=system.iobus.port[8] + +[system.realview.watchdog_fake] +type=AmbaFake +amba_id=0 +ignore_access=false +pio_addr=268500992 +pio_latency=1000 +platform=system.realview +system=system +pio=system.iobus.port[12] + +[system.terminal] +type=Terminal +intr_control=system.intrctrl +number=0 +output=true +port=3456 + +[system.toL2Bus] +type=Bus +block_size=64 +bus_id=0 +clock=1000 +header_cycles=1 +use_default_range=false +width=64 +port=system.l2c.cpu_side system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port + diff --git a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/simerr b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/simerr new file mode 100755 index 000000000..122561307 --- /dev/null +++ b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/simerr @@ -0,0 +1,39 @@ +warn: Sockets disabled, not accepting terminal connections +For more information see: http://www.m5sim.org/warn/8742226b +warn: Sockets disabled, not accepting gdb connections +For more information see: http://www.m5sim.org/warn/d946bea6 +warn: The clidr register always reports 0 caches. +For more information see: http://www.m5sim.org/warn/23a3c326 +warn: The csselr register isn't implemented. +For more information see: http://www.m5sim.org/warn/c0c486b8 +warn: Need to flush all TLBs in MP +For more information see: http://www.m5sim.org/warn/6cccf999 +warn: instruction 'mcr bpiall' unimplemented +For more information see: http://www.m5sim.org/warn/21b09adb +warn: The ccsidr register isn't implemented and always reads as 0. +For more information see: http://www.m5sim.org/warn/2c4acb9c +warn: instruction 'mcr dccimvac' unimplemented +For more information see: http://www.m5sim.org/warn/21b09adb +warn: Need to flush all TLBs in MP +For more information see: http://www.m5sim.org/warn/6cccf999 +warn: instruction 'mcr bpiall' unimplemented +For more information see: http://www.m5sim.org/warn/21b09adb +warn: instruction 'mcr dccmvau' unimplemented +For more information see: http://www.m5sim.org/warn/21b09adb +warn: instruction 'mcr icimvau' unimplemented +For more information see: http://www.m5sim.org/warn/21b09adb +warn: instruction 'mcr bpiall' unimplemented +For more information see: http://www.m5sim.org/warn/21b09adb +warn: instruction 'mcr bpiall' unimplemented +For more information see: http://www.m5sim.org/warn/21b09adb +warn: Returning thumbEE disabled for now since we don't support CP14config registers and jumping to ThumbEE vectors +For more information see: http://www.m5sim.org/warn/7998f2ea +warn: instruction 'mcr bpiall' unimplemented +For more information see: http://www.m5sim.org/warn/21b09adb +warn: instruction 'mcr bpiall' unimplemented +For more information see: http://www.m5sim.org/warn/21b09adb +warn: Need to flush all TLBs in MP +For more information see: http://www.m5sim.org/warn/6cccf999 +warn: instruction 'mcr bpiall' unimplemented +For more information see: http://www.m5sim.org/warn/21b09adb +hack: be nice to actually delete the event here diff --git a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/simout b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/simout new file mode 100755 index 000000000..981efa137 --- /dev/null +++ b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/simout @@ -0,0 +1,16 @@ +M5 Simulator System + +Copyright (c) 2001-2008 +The Regents of The University of Michigan +All Rights Reserved + + +M5 compiled Oct 1 2010 22:55:27 +M5 revision 8dd1bd50f739 7724 default qtip tip ext/vfp_serial_nonspec_flags.patch +M5 started Oct 1 2010 23:07:34 +M5 executing on aus-bc3-b7 +command line: build/ARM_FS/m5.opt -d build/ARM_FS/tests/opt/quick/10.linux-boot/arm/linux/realview-simple-timing -re tests/run.py build/ARM_FS/tests/opt/quick/10.linux-boot/arm/linux/realview-simple-timing +Global frequency set at 1000000000000 ticks per second +info: kernel located at: /chips/pd/randd/dist/binaries/vmlinux.arm +info: Entering event queue @ 0. Starting simulation... +Exiting @ tick 120048264000 because m5_exit instruction encountered diff --git a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt new file mode 100644 index 000000000..d35264510 --- /dev/null +++ b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt @@ -0,0 +1,483 @@ + +---------- Begin Simulation Statistics ---------- +host_inst_rate 546024 # Simulator instruction rate (inst/s) +host_mem_usage 378800 # Number of bytes of host memory used +host_seconds 92.51 # Real time elapsed on the host +host_tick_rate 1297642212 # Simulator tick rate (ticks/s) +sim_freq 1000000000000 # Frequency of simulated ticks +sim_insts 50513922 # Number of instructions simulated +sim_seconds 0.120048 # Number of seconds simulated +sim_ticks 120048264000 # Number of ticks simulated +system.cpu.dcache.LoadLockedReq_accesses::0 99871 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 99871 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_avg_miss_latency::0 14859.416446 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::1 inf # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total inf # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency 11859.416446 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_uncacheable_latency inf # average LoadLockedReq mshr uncacheable latency +system.cpu.dcache.LoadLockedReq_hits::0 94593 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 94593 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_miss_latency 78428000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_rate::0 0.052848 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_misses::0 5278 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 5278 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_mshr_miss_latency 62594000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::0 0.052848 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::1 inf # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total inf # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_misses 5278 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_uncacheable_latency 310054500 # number of LoadLockedReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_accesses::0 7793356 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 7793356 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency::0 15742.239268 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 12741.872084 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency +system.cpu.dcache.ReadReq_hits::0 7557779 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 7557779 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 3708509500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate::0 0.030228 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses::0 235577 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 235577 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_miss_latency 3001692000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::0 0.030228 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_misses 235577 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_uncacheable_latency 43427916500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.StoreCondReq_accesses::0 99870 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 99870 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_hits::0 99870 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 99870 # number of StoreCondReq hits +system.cpu.dcache.WriteReq_accesses::0 6647889 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 6647889 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_avg_miss_latency::0 40318.665363 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::1 inf # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 37318.368117 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency +system.cpu.dcache.WriteReq_hits::0 6472950 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 6472950 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 7053307000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate::0 0.026315 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses::0 174939 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 174939 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_miss_latency 6528438000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate::0 0.026315 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::1 inf # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses 174939 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_uncacheable_latency 926045500 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu.dcache.avg_refs 34.360003 # Average number of references to valid blocks. +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.demand_accesses::0 14441245 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::1 0 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 14441245 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency::0 26215.339962 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::1 inf # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total inf # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 23215.002582 # average overall mshr miss latency +system.cpu.dcache.demand_hits::0 14030729 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::1 0 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 14030729 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 10761816500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate::0 0.028427 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total no_value # miss rate for demand accesses +system.cpu.dcache.demand_misses::0 410516 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::1 0 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 410516 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 9530130000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate::0 0.028427 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 410516 # number of demand (read+write) MSHR misses +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.occ_%::0 0.994772 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::0 509.323403 # Average occupied blocks per context +system.cpu.dcache.overall_accesses::0 14441245 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::1 0 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 14441245 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency::0 26215.339962 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::1 inf # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total inf # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 23215.002582 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency +system.cpu.dcache.overall_hits::0 14030729 # number of overall hits +system.cpu.dcache.overall_hits::1 0 # number of overall hits +system.cpu.dcache.overall_hits::total 14030729 # number of overall hits +system.cpu.dcache.overall_miss_latency 10761816500 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate::0 0.028427 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total no_value # miss rate for overall accesses +system.cpu.dcache.overall_misses::0 410516 # number of overall misses +system.cpu.dcache.overall_misses::1 0 # number of overall misses +system.cpu.dcache.overall_misses::total 410516 # number of overall misses +system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 9530130000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate::0 0.028427 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 410516 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_uncacheable_latency 44353962000 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.dcache.replacements 413543 # number of replacements +system.cpu.dcache.sampled_refs 414055 # Sample count of references to valid blocks. +system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.dcache.tagsinuse 509.323403 # Cycle average of tags in use +system.cpu.dcache.total_refs 14226931 # Total number of references to valid blocks. +system.cpu.dcache.warmup_cycle 658097000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.writebacks 384690 # number of writebacks +system.cpu.dtb.accesses 15468820 # DTB accesses +system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dtb.flush_entries 2225 # Number of entries that have been flushed from TLB +system.cpu.dtb.flush_tlb 2 # Number of times complete TLB was flushed +system.cpu.dtb.flush_tlb_asid 40 # Number of times TLB was flushed by ASID +system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dtb.flush_tlb_mva_asid 33670 # Number of times TLB was flushed by MVA & ASID +system.cpu.dtb.hits 15463286 # DTB hits +system.cpu.dtb.inst_accesses 0 # ITB inst accesses +system.cpu.dtb.inst_hits 0 # ITB inst hits +system.cpu.dtb.inst_misses 0 # ITB inst misses +system.cpu.dtb.misses 5534 # DTB misses +system.cpu.dtb.perms_faults 255 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.prefetch_faults 764 # Number of TLB faults due to prefetch +system.cpu.dtb.read_accesses 8708503 # DTB read accesses +system.cpu.dtb.read_hits 8703948 # DTB read hits +system.cpu.dtb.read_misses 4555 # DTB read misses +system.cpu.dtb.write_accesses 6760317 # DTB write accesses +system.cpu.dtb.write_hits 6759338 # DTB write hits +system.cpu.dtb.write_misses 979 # DTB write misses +system.cpu.icache.ReadReq_accesses::0 41422231 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 41422231 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency::0 14804.202290 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 11802.928446 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency +system.cpu.icache.ReadReq_hits::0 40992037 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 40992037 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 6368679000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate::0 0.010386 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses::0 430194 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 430194 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_miss_latency 5077549000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::0 0.010386 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_misses 430194 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_uncacheable_latency 349111000 # number of ReadReq MSHR uncacheable cycles +system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu.icache.avg_refs 95.287550 # Average number of references to valid blocks. +system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.icache.cache_copies 0 # number of cache copies performed +system.cpu.icache.demand_accesses::0 41422231 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::1 0 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 41422231 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency::0 14804.202290 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::1 inf # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total inf # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 11802.928446 # average overall mshr miss latency +system.cpu.icache.demand_hits::0 40992037 # number of demand (read+write) hits +system.cpu.icache.demand_hits::1 0 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 40992037 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 6368679000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate::0 0.010386 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::1 no_value # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total no_value # miss rate for demand accesses +system.cpu.icache.demand_misses::0 430194 # number of demand (read+write) misses +system.cpu.icache.demand_misses::1 0 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 430194 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 5077549000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate::0 0.010386 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_misses 430194 # number of demand (read+write) MSHR misses +system.cpu.icache.fast_writes 0 # number of fast writes performed +system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.icache.occ_%::0 0.948192 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::0 485.474186 # Average occupied blocks per context +system.cpu.icache.overall_accesses::0 41422231 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::1 0 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 41422231 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency::0 14804.202290 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::1 inf # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total inf # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 11802.928446 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency +system.cpu.icache.overall_hits::0 40992037 # number of overall hits +system.cpu.icache.overall_hits::1 0 # number of overall hits +system.cpu.icache.overall_hits::total 40992037 # number of overall hits +system.cpu.icache.overall_miss_latency 6368679000 # number of overall miss cycles +system.cpu.icache.overall_miss_rate::0 0.010386 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::1 no_value # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total no_value # miss rate for overall accesses +system.cpu.icache.overall_misses::0 430194 # number of overall misses +system.cpu.icache.overall_misses::1 0 # number of overall misses +system.cpu.icache.overall_misses::total 430194 # number of overall misses +system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 5077549000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate::0 0.010386 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_misses 430194 # number of overall MSHR misses +system.cpu.icache.overall_mshr_uncacheable_latency 349111000 # number of overall MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.icache.replacements 429681 # number of replacements +system.cpu.icache.sampled_refs 430193 # Sample count of references to valid blocks. +system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.icache.tagsinuse 485.474186 # Cycle average of tags in use +system.cpu.icache.total_refs 40992037 # Total number of references to valid blocks. +system.cpu.icache.warmup_cycle 14253306000 # Cycle when the warmup percentage was hit. +system.cpu.icache.writebacks 30998 # number of writebacks +system.cpu.idle_fraction 0 # Percentage of idle cycles +system.cpu.itb.accesses 41425050 # DTB accesses +system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.itb.flush_entries 1478 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_tlb 2 # Number of times complete TLB was flushed +system.cpu.itb.flush_tlb_asid 40 # Number of times TLB was flushed by ASID +system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.itb.flush_tlb_mva_asid 33670 # Number of times TLB was flushed by MVA & ASID +system.cpu.itb.hits 41422231 # DTB hits +system.cpu.itb.inst_accesses 41425050 # ITB inst accesses +system.cpu.itb.inst_hits 41422231 # ITB inst hits +system.cpu.itb.inst_misses 2819 # ITB inst misses +system.cpu.itb.misses 2819 # DTB misses +system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.kern.inst.arm 0 # number of arm instructions executed +system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed +system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu.numCycles 240096528 # number of cpu cycles simulated +system.cpu.num_insts 50513922 # Number of instructions executed +system.cpu.num_refs 16229722 # Number of memory references +system.iocache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.iocache.avg_refs no_value # Average number of references to valid blocks. +system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked +system.iocache.blocked::no_targets 0 # number of cycles access was blocked +system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.iocache.cache_copies 0 # number of cache copies performed +system.iocache.demand_accesses::0 0 # number of demand (read+write) accesses +system.iocache.demand_accesses::1 0 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 0 # number of demand (read+write) accesses +system.iocache.demand_avg_miss_latency::0 no_value # average overall miss latency +system.iocache.demand_avg_miss_latency::1 no_value # average overall miss latency +system.iocache.demand_avg_miss_latency::total no_value # average overall miss latency +system.iocache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency +system.iocache.demand_hits::0 0 # number of demand (read+write) hits +system.iocache.demand_hits::1 0 # number of demand (read+write) hits +system.iocache.demand_hits::total 0 # number of demand (read+write) hits +system.iocache.demand_miss_latency 0 # number of demand (read+write) miss cycles +system.iocache.demand_miss_rate::0 no_value # miss rate for demand accesses +system.iocache.demand_miss_rate::1 no_value # miss rate for demand accesses +system.iocache.demand_miss_rate::total no_value # miss rate for demand accesses +system.iocache.demand_misses::0 0 # number of demand (read+write) misses +system.iocache.demand_misses::1 0 # number of demand (read+write) misses +system.iocache.demand_misses::total 0 # number of demand (read+write) misses +system.iocache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.iocache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_rate::0 no_value # mshr miss rate for demand accesses +system.iocache.demand_mshr_miss_rate::1 no_value # mshr miss rate for demand accesses +system.iocache.demand_mshr_miss_rate::total no_value # mshr miss rate for demand accesses +system.iocache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses +system.iocache.fast_writes 0 # number of fast writes performed +system.iocache.mshr_cap_events 0 # number of times MSHR cap was activated +system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate +system.iocache.overall_accesses::0 0 # number of overall (read+write) accesses +system.iocache.overall_accesses::1 0 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 0 # number of overall (read+write) accesses +system.iocache.overall_avg_miss_latency::0 no_value # average overall miss latency +system.iocache.overall_avg_miss_latency::1 no_value # average overall miss latency +system.iocache.overall_avg_miss_latency::total no_value # average overall miss latency +system.iocache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency +system.iocache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency +system.iocache.overall_hits::0 0 # number of overall hits +system.iocache.overall_hits::1 0 # number of overall hits +system.iocache.overall_hits::total 0 # number of overall hits +system.iocache.overall_miss_latency 0 # number of overall miss cycles +system.iocache.overall_miss_rate::0 no_value # miss rate for overall accesses +system.iocache.overall_miss_rate::1 no_value # miss rate for overall accesses +system.iocache.overall_miss_rate::total no_value # miss rate for overall accesses +system.iocache.overall_misses::0 0 # number of overall misses +system.iocache.overall_misses::1 0 # number of overall misses +system.iocache.overall_misses::total 0 # number of overall misses +system.iocache.overall_mshr_hits 0 # number of overall MSHR hits +system.iocache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_rate::0 no_value # mshr miss rate for overall accesses +system.iocache.overall_mshr_miss_rate::1 no_value # mshr miss rate for overall accesses +system.iocache.overall_mshr_miss_rate::total no_value # mshr miss rate for overall accesses +system.iocache.overall_mshr_misses 0 # number of overall MSHR misses +system.iocache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.iocache.replacements 0 # number of replacements +system.iocache.sampled_refs 0 # Sample count of references to valid blocks. +system.iocache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.iocache.tagsinuse 0 # Cycle average of tags in use +system.iocache.total_refs 0 # Total number of references to valid blocks. +system.iocache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.iocache.writebacks 0 # number of writebacks +system.l2c.LoadLockedReq_avg_mshr_uncacheable_latency inf # average LoadLockedReq mshr uncacheable latency +system.l2c.LoadLockedReq_mshr_uncacheable_latency 234000000 # number of LoadLockedReq MSHR uncacheable cycles +system.l2c.ReadExReq_accesses::0 173200 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 173200 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_avg_miss_latency::0 52000 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::1 inf # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total inf # average ReadExReq miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_hits::0 65260 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 65260 # number of ReadExReq hits +system.l2c.ReadExReq_miss_latency 5612880000 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_rate::0 0.623210 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_misses::0 107940 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 107940 # number of ReadExReq misses +system.l2c.ReadExReq_mshr_miss_latency 4317600000 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_rate::0 0.623210 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::1 inf # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total inf # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_misses 107940 # number of ReadExReq MSHR misses +system.l2c.ReadReq_accesses::0 669099 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::1 7756 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 676855 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_avg_miss_latency::0 52101.691699 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::1 26691986.111111 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 26744087.802810 # average ReadReq miss latency +system.l2c.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_hits::0 650656 # number of ReadReq hits +system.l2c.ReadReq_hits::1 7720 # number of ReadReq hits +system.l2c.ReadReq_hits::total 658376 # number of ReadReq hits +system.l2c.ReadReq_miss_latency 960911500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_rate::0 0.027564 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::1 0.004642 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.032206 # miss rate for ReadReq accesses +system.l2c.ReadReq_misses::0 18443 # number of ReadReq misses +system.l2c.ReadReq_misses::1 36 # number of ReadReq misses +system.l2c.ReadReq_misses::total 18479 # number of ReadReq misses +system.l2c.ReadReq_mshr_miss_latency 739160000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_rate::0 0.027618 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::1 2.382543 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 2.410160 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_misses 18479 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_uncacheable_latency 33151541000 # number of ReadReq MSHR uncacheable cycles +system.l2c.UpgradeReq_accesses::0 1739 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 1739 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_avg_miss_latency::0 392.794887 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::1 inf # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total inf # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_hits::0 18 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 18 # number of UpgradeReq hits +system.l2c.UpgradeReq_miss_latency 676000 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_rate::0 0.989649 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_misses::0 1721 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 1721 # number of UpgradeReq misses +system.l2c.UpgradeReq_mshr_miss_latency 68840000 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_rate::0 0.989649 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::1 inf # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total inf # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_misses 1721 # number of UpgradeReq MSHR misses +system.l2c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_mshr_uncacheable_latency 739844000 # number of WriteReq MSHR uncacheable cycles +system.l2c.Writeback_accesses::0 415688 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 415688 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_hits::0 415688 # number of Writeback hits +system.l2c.Writeback_hits::total 415688 # number of Writeback hits +system.l2c.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.l2c.avg_refs 6.983802 # Average number of references to valid blocks. +system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked +system.l2c.blocked::no_targets 0 # number of cycles access was blocked +system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.l2c.cache_copies 0 # number of cache copies performed +system.l2c.demand_accesses::0 842299 # number of demand (read+write) accesses +system.l2c.demand_accesses::1 7756 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 850055 # number of demand (read+write) accesses +system.l2c.demand_avg_miss_latency::0 52014.839812 # average overall miss latency +system.l2c.demand_avg_miss_latency::1 182605319.444444 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 182657334.284257 # average overall miss latency +system.l2c.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency +system.l2c.demand_hits::0 715916 # number of demand (read+write) hits +system.l2c.demand_hits::1 7720 # number of demand (read+write) hits +system.l2c.demand_hits::total 723636 # number of demand (read+write) hits +system.l2c.demand_miss_latency 6573791500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_rate::0 0.150045 # miss rate for demand accesses +system.l2c.demand_miss_rate::1 0.004642 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.154687 # miss rate for demand accesses +system.l2c.demand_misses::0 126383 # number of demand (read+write) misses +system.l2c.demand_misses::1 36 # number of demand (read+write) misses +system.l2c.demand_misses::total 126419 # number of demand (read+write) misses +system.l2c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_miss_latency 5056760000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_rate::0 0.150088 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::1 16.299510 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 16.449598 # mshr miss rate for demand accesses +system.l2c.demand_mshr_misses 126419 # number of demand (read+write) MSHR misses +system.l2c.fast_writes 0 # number of fast writes performed +system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated +system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate +system.l2c.occ_%::0 0.086001 # Average percentage of cache occupancy +system.l2c.occ_%::1 0.479853 # Average percentage of cache occupancy +system.l2c.occ_blocks::0 5636.151787 # Average occupied blocks per context +system.l2c.occ_blocks::1 31447.614519 # Average occupied blocks per context +system.l2c.overall_accesses::0 842299 # number of overall (read+write) accesses +system.l2c.overall_accesses::1 7756 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 850055 # number of overall (read+write) accesses +system.l2c.overall_avg_miss_latency::0 52014.839812 # average overall miss latency +system.l2c.overall_avg_miss_latency::1 182605319.444444 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 182657334.284257 # average overall miss latency +system.l2c.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency +system.l2c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency +system.l2c.overall_hits::0 715916 # number of overall hits +system.l2c.overall_hits::1 7720 # number of overall hits +system.l2c.overall_hits::total 723636 # number of overall hits +system.l2c.overall_miss_latency 6573791500 # number of overall miss cycles +system.l2c.overall_miss_rate::0 0.150045 # miss rate for overall accesses +system.l2c.overall_miss_rate::1 0.004642 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.154687 # miss rate for overall accesses +system.l2c.overall_misses::0 126383 # number of overall misses +system.l2c.overall_misses::1 36 # number of overall misses +system.l2c.overall_misses::total 126419 # number of overall misses +system.l2c.overall_mshr_hits 0 # number of overall MSHR hits +system.l2c.overall_mshr_miss_latency 5056760000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_rate::0 0.150088 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::1 16.299510 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 16.449598 # mshr miss rate for overall accesses +system.l2c.overall_mshr_misses 126419 # number of overall MSHR misses +system.l2c.overall_mshr_uncacheable_latency 33891385000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.l2c.replacements 93485 # number of replacements +system.l2c.sampled_refs 125077 # Sample count of references to valid blocks. +system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.l2c.tagsinuse 37083.766306 # Cycle average of tags in use +system.l2c.total_refs 873513 # Total number of references to valid blocks. +system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.l2c.writebacks 87014 # number of writebacks + +---------- End Simulation Statistics ---------- diff --git a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/status b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/status new file mode 100644 index 000000000..8953751c2 --- /dev/null +++ b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/status @@ -0,0 +1 @@ +build/ARM_FS/tests/opt/quick/10.linux-boot/arm/linux/realview-simple-timing FAILED! diff --git a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/system.terminal b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/system.terminal Binary files differnew file mode 100644 index 000000000..b44fac3a0 --- /dev/null +++ b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/system.terminal |