diff options
Diffstat (limited to 'tests/quick/10.linux-boot/ref')
8 files changed, 388 insertions, 368 deletions
diff --git a/tests/quick/10.linux-boot/ref/x86/linux/pc-simple-atomic/config.ini b/tests/quick/10.linux-boot/ref/x86/linux/pc-simple-atomic/config.ini index 1f83b404b..bea7090e9 100644 --- a/tests/quick/10.linux-boot/ref/x86/linux/pc-simple-atomic/config.ini +++ b/tests/quick/10.linux-boot/ref/x86/linux/pc-simple-atomic/config.ini @@ -15,9 +15,11 @@ e820_table=system.e820_table init_param=0 intel_mp_pointer=system.intel_mp_pointer intel_mp_table=system.intel_mp_table -kernel=/dist/m5/system/binaries/x86_64-vmlinux-2.6.22.9 +kernel=/scratch/nilay/GEM5/system/binaries/x86_64-vmlinux-2.6.22.9 load_addr_mask=18446744073709551615 mem_mode=atomic +memories=system.physmem +num_work_ids=16 physmem=system.physmem readfile=tests/halt.sh smbios_table=system.smbios_table @@ -707,6 +709,7 @@ port=system.physmem.port[0] system.bridge.side_b system.iocache.mem_side system. [system.membus.badaddr_responder] type=IsaFake +fake_mem=false pio_addr=0 pio_latency=1000 pio_size=8 @@ -729,6 +732,7 @@ system=system [system.pc.behind_pci] type=IsaFake +fake_mem=false pio_addr=9223372036854779128 pio_latency=1000 pio_size=8 @@ -745,15 +749,31 @@ pio=system.iobus.port[12] [system.pc.com_1] type=Uart8250 +children=terminal pio_addr=9223372036854776824 pio_latency=1000 platform=system.pc system=system -terminal=system.pc.terminal +terminal=system.pc.com_1.terminal pio=system.iobus.port[13] +[system.pc.com_1.terminal] +type=Terminal +intr_control=system.intrctrl +number=0 +output=true +port=3456 + +[system.pc.com_1.terminal] +type=Terminal +intr_control=system.intrctrl +number=0 +output=true +port=3456 + [system.pc.fake_com_2] type=IsaFake +fake_mem=false pio_addr=9223372036854776568 pio_latency=1000 pio_size=8 @@ -770,6 +790,7 @@ pio=system.iobus.port[14] [system.pc.fake_com_3] type=IsaFake +fake_mem=false pio_addr=9223372036854776808 pio_latency=1000 pio_size=8 @@ -786,6 +807,7 @@ pio=system.iobus.port[15] [system.pc.fake_com_4] type=IsaFake +fake_mem=false pio_addr=9223372036854776552 pio_latency=1000 pio_size=8 @@ -802,6 +824,7 @@ pio=system.iobus.port[16] [system.pc.fake_floppy] type=IsaFake +fake_mem=false pio_addr=9223372036854776818 pio_latency=1000 pio_size=2 @@ -818,6 +841,7 @@ pio=system.iobus.port[17] [system.pc.i_dont_exist] type=IsaFake +fake_mem=false pio_addr=9223372036854775936 pio_latency=1000 pio_size=1 @@ -846,7 +870,6 @@ type=SouthBridge children=cmos dma1 ide int_lines0 int_lines1 int_lines2 int_lines3 int_lines4 int_lines5 int_lines6 io_apic keyboard pic1 pic2 pit speaker cmos=system.pc.south_bridge.cmos dma1=system.pc.south_bridge.dma1 -int_lines=system.pc.south_bridge.int_lines0 system.pc.south_bridge.int_lines1 system.pc.south_bridge.int_lines2 system.pc.south_bridge.int_lines3 system.pc.south_bridge.int_lines4 system.pc.south_bridge.int_lines5 system.pc.south_bridge.int_lines6 io_apic=system.pc.south_bridge.io_apic keyboard=system.pc.south_bridge.keyboard pic1=system.pc.south_bridge.pic1 @@ -858,7 +881,8 @@ speaker=system.pc.south_bridge.speaker [system.pc.south_bridge.cmos] type=Cmos -int_pin=system.pc.south_bridge.int_lines2.source +children=int_pin +int_pin=system.pc.south_bridge.cmos.int_pin pio_addr=9223372036854775920 pio_latency=1000 platform=system.pc @@ -866,6 +890,9 @@ system=system time=Sun Jan 1 00:00:00 2012 pio=system.iobus.port[1] +[system.pc.south_bridge.cmos.int_pin] +type=X86IntSourcePin + [system.pc.south_bridge.dma1] type=I8237 pio_addr=9223372036854775808 @@ -948,7 +975,7 @@ table_size=65536 [system.pc.south_bridge.ide.disks0.image.child] type=RawDiskImage -image_file=/dist/m5/system/disks/linux-x86.img +image_file=/scratch/nilay/GEM5/system/disks/linux-x86.img read_only=true [system.pc.south_bridge.ide.disks1] @@ -968,70 +995,58 @@ table_size=65536 [system.pc.south_bridge.ide.disks1.image.child] type=RawDiskImage -image_file=/dist/m5/system/disks/linux-bigswap2.img +image_file=/scratch/nilay/GEM5/system/disks/linux-bigswap2.img read_only=true [system.pc.south_bridge.int_lines0] type=X86IntLine -children=sink source +children=sink sink=system.pc.south_bridge.int_lines0.sink -source=system.pc.south_bridge.int_lines0.source +source=system.pc.south_bridge.pic1.output [system.pc.south_bridge.int_lines0.sink] type=X86IntSinkPin device=system.pc.south_bridge.io_apic number=0 -[system.pc.south_bridge.int_lines0.source] -type=X86IntSourcePin - [system.pc.south_bridge.int_lines1] type=X86IntLine -children=sink source +children=sink sink=system.pc.south_bridge.int_lines1.sink -source=system.pc.south_bridge.int_lines1.source +source=system.pc.south_bridge.pic2.output [system.pc.south_bridge.int_lines1.sink] type=X86IntSinkPin device=system.pc.south_bridge.pic1 number=2 -[system.pc.south_bridge.int_lines1.source] -type=X86IntSourcePin - [system.pc.south_bridge.int_lines2] type=X86IntLine -children=sink source +children=sink sink=system.pc.south_bridge.int_lines2.sink -source=system.pc.south_bridge.int_lines2.source +source=system.pc.south_bridge.cmos.int_pin [system.pc.south_bridge.int_lines2.sink] type=X86IntSinkPin device=system.pc.south_bridge.pic2 number=0 -[system.pc.south_bridge.int_lines2.source] -type=X86IntSourcePin - [system.pc.south_bridge.int_lines3] type=X86IntLine -children=sink source +children=sink sink=system.pc.south_bridge.int_lines3.sink -source=system.pc.south_bridge.int_lines3.source +source=system.pc.south_bridge.pit.int_pin [system.pc.south_bridge.int_lines3.sink] type=X86IntSinkPin device=system.pc.south_bridge.pic1 number=0 -[system.pc.south_bridge.int_lines3.source] -type=X86IntSourcePin - [system.pc.south_bridge.int_lines4] type=X86IntLine children=sink sink=system.pc.south_bridge.int_lines4.sink -source=system.pc.south_bridge.int_lines3.source +source=system.pc.south_bridge.pit.int_pin [system.pc.south_bridge.int_lines4.sink] type=X86IntSinkPin @@ -1040,32 +1055,26 @@ number=2 [system.pc.south_bridge.int_lines5] type=X86IntLine -children=sink source +children=sink sink=system.pc.south_bridge.int_lines5.sink -source=system.pc.south_bridge.int_lines5.source +source=system.pc.south_bridge.keyboard.keyboard_int_pin [system.pc.south_bridge.int_lines5.sink] type=X86IntSinkPin device=system.pc.south_bridge.io_apic number=1 -[system.pc.south_bridge.int_lines5.source] -type=X86IntSourcePin - [system.pc.south_bridge.int_lines6] type=X86IntLine -children=sink source +children=sink sink=system.pc.south_bridge.int_lines6.sink -source=system.pc.south_bridge.int_lines6.source +source=system.pc.south_bridge.keyboard.mouse_int_pin [system.pc.south_bridge.int_lines6.sink] type=X86IntSinkPin device=system.pc.south_bridge.io_apic number=12 -[system.pc.south_bridge.int_lines6.source] -type=X86IntSourcePin - [system.pc.south_bridge.io_apic] type=I82094AA apic_id=1 @@ -1080,20 +1089,28 @@ pio=system.iobus.port[9] [system.pc.south_bridge.keyboard] type=I8042 +children=keyboard_int_pin mouse_int_pin command_port=9223372036854775908 data_port=9223372036854775904 -keyboard_int_pin=system.pc.south_bridge.int_lines5.source -mouse_int_pin=system.pc.south_bridge.int_lines6.source +keyboard_int_pin=system.pc.south_bridge.keyboard.keyboard_int_pin +mouse_int_pin=system.pc.south_bridge.keyboard.mouse_int_pin pio_addr=0 pio_latency=1000 platform=system.pc system=system pio=system.iobus.port[4] +[system.pc.south_bridge.keyboard.keyboard_int_pin] +type=X86IntSourcePin + +[system.pc.south_bridge.keyboard.mouse_int_pin] +type=X86IntSourcePin + [system.pc.south_bridge.pic1] type=I8259 +children=output mode=I8259Master -output=system.pc.south_bridge.int_lines0.source +output=system.pc.south_bridge.pic1.output pio_addr=9223372036854775840 pio_latency=1000 platform=system.pc @@ -1101,10 +1118,14 @@ slave=system.pc.south_bridge.pic2 system=system pio=system.iobus.port[5] +[system.pc.south_bridge.pic1.output] +type=X86IntSourcePin + [system.pc.south_bridge.pic2] type=I8259 +children=output mode=I8259Slave -output=system.pc.south_bridge.int_lines1.source +output=system.pc.south_bridge.pic2.output pio_addr=9223372036854775968 pio_latency=1000 platform=system.pc @@ -1112,15 +1133,22 @@ slave=Null system=system pio=system.iobus.port[6] +[system.pc.south_bridge.pic2.output] +type=X86IntSourcePin + [system.pc.south_bridge.pit] type=I8254 -int_pin=system.pc.south_bridge.int_lines3.source +children=int_pin +int_pin=system.pc.south_bridge.pit.int_pin pio_addr=9223372036854775872 pio_latency=1000 platform=system.pc system=system pio=system.iobus.port[7] +[system.pc.south_bridge.pit.int_pin] +type=X86IntSourcePin + [system.pc.south_bridge.speaker] type=PcSpeaker i8254=system.pc.south_bridge.pit @@ -1130,13 +1158,6 @@ platform=system.pc system=system pio=system.iobus.port[8] -[system.pc.terminal] -type=Terminal -intr_control=system.intrctrl -number=0 -output=true -port=3456 - [system.physmem] type=PhysicalMemory file= diff --git a/tests/quick/10.linux-boot/ref/x86/linux/pc-simple-atomic/simerr b/tests/quick/10.linux-boot/ref/x86/linux/pc-simple-atomic/simerr index 99f9676e9..fd09f1faf 100755 --- a/tests/quick/10.linux-boot/ref/x86/linux/pc-simple-atomic/simerr +++ b/tests/quick/10.linux-boot/ref/x86/linux/pc-simple-atomic/simerr @@ -1,17 +1,9 @@ warn: Sockets disabled, not accepting terminal connections -For more information see: http://www.m5sim.org/warn/8742226b warn: Reading current count from inactive timer. -For more information see: http://www.m5sim.org/warn/1ea2be46 warn: Sockets disabled, not accepting gdb connections -For more information see: http://www.m5sim.org/warn/d946bea6 warn: Don't know what interrupt to clear for console. -For more information see: http://www.m5sim.org/warn/7fe1004f warn: instruction 'fxsave' unimplemented -For more information see: http://www.m5sim.org/warn/437d5238 warn: Tried to clear PCI interrupt 14 -For more information see: http://www.m5sim.org/warn/77378d57 warn: Unknown mouse command 0xe1. -For more information see: http://www.m5sim.org/warn/2447512a warn: instruction 'wbinvd' unimplemented -For more information see: http://www.m5sim.org/warn/437d5238 hack: be nice to actually delete the event here diff --git a/tests/quick/10.linux-boot/ref/x86/linux/pc-simple-atomic/simout b/tests/quick/10.linux-boot/ref/x86/linux/pc-simple-atomic/simout index b12d01305..bd3613cfe 100755 --- a/tests/quick/10.linux-boot/ref/x86/linux/pc-simple-atomic/simout +++ b/tests/quick/10.linux-boot/ref/x86/linux/pc-simple-atomic/simout @@ -1,15 +1,12 @@ -M5 Simulator System +gem5 Simulator System. http://gem5.org +gem5 is copyrighted software; use the --copyright option for details. -Copyright (c) 2001-2008 -The Regents of The University of Michigan -All Rights Reserved - - -M5 compiled Apr 19 2011 12:44:38 -M5 started Apr 19 2011 12:44:44 -M5 executing on maize -command line: build/X86_FS/m5.fast -d build/X86_FS/tests/fast/quick/10.linux-boot/x86/linux/pc-simple-atomic -re tests/run.py build/X86_FS/tests/fast/quick/10.linux-boot/x86/linux/pc-simple-atomic +gem5 compiled Jan 9 2012 20:47:38 +gem5 started Jan 9 2012 21:03:15 +gem5 executing on ribera.cs.wisc.edu +command line: build/X86_FS/gem5.fast -d build/X86_FS/tests/fast/quick/10.linux-boot/x86/linux/pc-simple-atomic -re tests/run.py build/X86_FS/tests/fast/quick/10.linux-boot/x86/linux/pc-simple-atomic +warning: add_child('terminal'): child 'terminal' already has parent Global frequency set at 1000000000000 ticks per second -info: kernel located at: /dist/m5/system/binaries/x86_64-vmlinux-2.6.22.9 +info: kernel located at: /scratch/nilay/GEM5/system/binaries/x86_64-vmlinux-2.6.22.9 info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 5112051446000 because m5_exit instruction encountered +Exiting @ tick 5112043255000 because m5_exit instruction encountered diff --git a/tests/quick/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt b/tests/quick/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt index eef6427c6..dc005fb66 100644 --- a/tests/quick/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt +++ b/tests/quick/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt @@ -1,79 +1,79 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 5.112037 # Number of seconds simulated -sim_ticks 5112036996000 # Number of ticks simulated +sim_seconds 5.112043 # Number of seconds simulated +sim_ticks 5112043255000 # Number of ticks simulated sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 2883648 # Simulator instruction rate (inst/s) -host_tick_rate 36256565088 # Simulator tick rate (ticks/s) -host_mem_usage 375496 # Number of bytes of host memory used -host_seconds 141.00 # Real time elapsed on the host -sim_insts 406583262 # Number of instructions simulated -system.l2c.replacements 163860 # number of replacements -system.l2c.tagsinuse 36838.766351 # Cycle average of tags in use -system.l2c.total_refs 3334365 # Total number of references to valid blocks. -system.l2c.sampled_refs 195829 # Sample count of references to valid blocks. -system.l2c.avg_refs 17.026921 # Average number of references to valid blocks. +host_inst_rate 2860366 # Simulator instruction rate (inst/s) +host_tick_rate 35739722021 # Simulator tick rate (ticks/s) +host_mem_usage 375540 # Number of bytes of host memory used +host_seconds 143.04 # Real time elapsed on the host +sim_insts 409133277 # Number of instructions simulated +system.l2c.replacements 164044 # number of replacements +system.l2c.tagsinuse 36842.944085 # Cycle average of tags in use +system.l2c.total_refs 3332458 # Total number of references to valid blocks. +system.l2c.sampled_refs 196390 # Sample count of references to valid blocks. +system.l2c.avg_refs 16.968573 # Average number of references to valid blocks. system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::0 9696.304444 # Average occupied blocks per context -system.l2c.occ_blocks::1 27142.461907 # Average occupied blocks per context -system.l2c.occ_percent::0 0.147954 # Average percentage of cache occupancy -system.l2c.occ_percent::1 0.414161 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::0 2042982 # number of ReadReq hits -system.l2c.ReadReq_hits::1 10263 # number of ReadReq hits -system.l2c.ReadReq_hits::total 2053245 # number of ReadReq hits -system.l2c.Writeback_hits::0 1528802 # number of Writeback hits -system.l2c.Writeback_hits::total 1528802 # number of Writeback hits -system.l2c.UpgradeReq_hits::0 28 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 28 # number of UpgradeReq hits -system.l2c.ReadExReq_hits::0 168885 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 168885 # number of ReadExReq hits -system.l2c.demand_hits::0 2211867 # number of demand (read+write) hits -system.l2c.demand_hits::1 10263 # number of demand (read+write) hits -system.l2c.demand_hits::total 2222130 # number of demand (read+write) hits -system.l2c.overall_hits::0 2211867 # number of overall hits -system.l2c.overall_hits::1 10263 # number of overall hits -system.l2c.overall_hits::total 2222130 # number of overall hits -system.l2c.ReadReq_misses::0 56047 # number of ReadReq misses -system.l2c.ReadReq_misses::1 29 # number of ReadReq misses -system.l2c.ReadReq_misses::total 56076 # number of ReadReq misses -system.l2c.UpgradeReq_misses::0 1784 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 1784 # number of UpgradeReq misses -system.l2c.ReadExReq_misses::0 144391 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 144391 # number of ReadExReq misses -system.l2c.demand_misses::0 200438 # number of demand (read+write) misses -system.l2c.demand_misses::1 29 # number of demand (read+write) misses -system.l2c.demand_misses::total 200467 # number of demand (read+write) misses -system.l2c.overall_misses::0 200438 # number of overall misses -system.l2c.overall_misses::1 29 # number of overall misses -system.l2c.overall_misses::total 200467 # number of overall misses +system.l2c.occ_blocks::0 9701.563280 # Average occupied blocks per context +system.l2c.occ_blocks::1 27141.380805 # Average occupied blocks per context +system.l2c.occ_percent::0 0.148034 # Average percentage of cache occupancy +system.l2c.occ_percent::1 0.414145 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::0 2042917 # number of ReadReq hits +system.l2c.ReadReq_hits::1 9538 # number of ReadReq hits +system.l2c.ReadReq_hits::total 2052455 # number of ReadReq hits +system.l2c.Writeback_hits::0 1529403 # number of Writeback hits +system.l2c.Writeback_hits::total 1529403 # number of Writeback hits +system.l2c.UpgradeReq_hits::0 31 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 31 # number of UpgradeReq hits +system.l2c.ReadExReq_hits::0 168948 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 168948 # number of ReadExReq hits +system.l2c.demand_hits::0 2211865 # number of demand (read+write) hits +system.l2c.demand_hits::1 9538 # number of demand (read+write) hits +system.l2c.demand_hits::total 2221403 # number of demand (read+write) hits +system.l2c.overall_hits::0 2211865 # number of overall hits +system.l2c.overall_hits::1 9538 # number of overall hits +system.l2c.overall_hits::total 2221403 # number of overall hits +system.l2c.ReadReq_misses::0 55972 # number of ReadReq misses +system.l2c.ReadReq_misses::1 27 # number of ReadReq misses +system.l2c.ReadReq_misses::total 55999 # number of ReadReq misses +system.l2c.UpgradeReq_misses::0 1792 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 1792 # number of UpgradeReq misses +system.l2c.ReadExReq_misses::0 144639 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 144639 # number of ReadExReq misses +system.l2c.demand_misses::0 200611 # number of demand (read+write) misses +system.l2c.demand_misses::1 27 # number of demand (read+write) misses +system.l2c.demand_misses::total 200638 # number of demand (read+write) misses +system.l2c.overall_misses::0 200611 # number of overall misses +system.l2c.overall_misses::1 27 # number of overall misses +system.l2c.overall_misses::total 200638 # number of overall misses system.l2c.demand_miss_latency 0 # number of demand (read+write) miss cycles system.l2c.overall_miss_latency 0 # number of overall miss cycles -system.l2c.ReadReq_accesses::0 2099029 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::1 10292 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 2109321 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::0 1528802 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 1528802 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::0 1812 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 1812 # number of UpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::0 313276 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 313276 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::0 2412305 # number of demand (read+write) accesses -system.l2c.demand_accesses::1 10292 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 2422597 # number of demand (read+write) accesses -system.l2c.overall_accesses::0 2412305 # number of overall (read+write) accesses -system.l2c.overall_accesses::1 10292 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 2422597 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::0 0.026701 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::1 0.002818 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.029519 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::0 0.984547 # miss rate for UpgradeReq accesses -system.l2c.ReadExReq_miss_rate::0 0.460907 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::0 0.083090 # miss rate for demand accesses -system.l2c.demand_miss_rate::1 0.002818 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.085908 # miss rate for demand accesses -system.l2c.overall_miss_rate::0 0.083090 # miss rate for overall accesses -system.l2c.overall_miss_rate::1 0.002818 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.085908 # miss rate for overall accesses +system.l2c.ReadReq_accesses::0 2098889 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::1 9565 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 2108454 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::0 1529403 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 1529403 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::0 1823 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 1823 # number of UpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::0 313587 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 313587 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::0 2412476 # number of demand (read+write) accesses +system.l2c.demand_accesses::1 9565 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 2422041 # number of demand (read+write) accesses +system.l2c.overall_accesses::0 2412476 # number of overall (read+write) accesses +system.l2c.overall_accesses::1 9565 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 2422041 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::0 0.026667 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::1 0.002823 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.029490 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::0 0.982995 # miss rate for UpgradeReq accesses +system.l2c.ReadExReq_miss_rate::0 0.461240 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::0 0.083156 # miss rate for demand accesses +system.l2c.demand_miss_rate::1 0.002823 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.085978 # miss rate for demand accesses +system.l2c.overall_miss_rate::0 0.083156 # miss rate for overall accesses +system.l2c.overall_miss_rate::1 0.002823 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.085978 # miss rate for overall accesses system.l2c.demand_avg_miss_latency::0 0 # average overall miss latency system.l2c.demand_avg_miss_latency::1 0 # average overall miss latency system.l2c.demand_avg_miss_latency::total 0 # average overall miss latency @@ -88,7 +88,7 @@ system.l2c.avg_blocked_cycles::no_mshrs no_value # av system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks 144360 # number of writebacks +system.l2c.writebacks 144472 # number of writebacks system.l2c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.l2c.overall_mshr_hits 0 # number of overall MSHR hits system.l2c.demand_mshr_misses 0 # number of demand (read+write) MSHR misses @@ -109,42 +109,42 @@ system.l2c.overall_avg_mshr_uncacheable_latency no_value system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.iocache.replacements 47572 # number of replacements -system.iocache.tagsinuse 0.042404 # Cycle average of tags in use +system.iocache.replacements 47570 # number of replacements +system.iocache.tagsinuse 0.042409 # Cycle average of tags in use system.iocache.total_refs 0 # Total number of references to valid blocks. -system.iocache.sampled_refs 47588 # Sample count of references to valid blocks. +system.iocache.sampled_refs 47586 # Sample count of references to valid blocks. system.iocache.avg_refs 0 # Average number of references to valid blocks. -system.iocache.warmup_cycle 4994772178509 # Cycle when the warmup percentage was hit. -system.iocache.occ_blocks::1 0.042404 # Average occupied blocks per context -system.iocache.occ_percent::1 0.002650 # Average percentage of cache occupancy +system.iocache.warmup_cycle 4994776740009 # Cycle when the warmup percentage was hit. +system.iocache.occ_blocks::1 0.042409 # Average occupied blocks per context +system.iocache.occ_percent::1 0.002651 # Average percentage of cache occupancy system.iocache.demand_hits::0 0 # number of demand (read+write) hits system.iocache.demand_hits::1 0 # number of demand (read+write) hits system.iocache.demand_hits::total 0 # number of demand (read+write) hits system.iocache.overall_hits::0 0 # number of overall hits system.iocache.overall_hits::1 0 # number of overall hits system.iocache.overall_hits::total 0 # number of overall hits -system.iocache.ReadReq_misses::1 907 # number of ReadReq misses -system.iocache.ReadReq_misses::total 907 # number of ReadReq misses +system.iocache.ReadReq_misses::1 905 # number of ReadReq misses +system.iocache.ReadReq_misses::total 905 # number of ReadReq misses system.iocache.WriteReq_misses::1 46720 # number of WriteReq misses system.iocache.WriteReq_misses::total 46720 # number of WriteReq misses system.iocache.demand_misses::0 0 # number of demand (read+write) misses -system.iocache.demand_misses::1 47627 # number of demand (read+write) misses -system.iocache.demand_misses::total 47627 # number of demand (read+write) misses +system.iocache.demand_misses::1 47625 # number of demand (read+write) misses +system.iocache.demand_misses::total 47625 # number of demand (read+write) misses system.iocache.overall_misses::0 0 # number of overall misses -system.iocache.overall_misses::1 47627 # number of overall misses -system.iocache.overall_misses::total 47627 # number of overall misses +system.iocache.overall_misses::1 47625 # number of overall misses +system.iocache.overall_misses::total 47625 # number of overall misses system.iocache.demand_miss_latency 0 # number of demand (read+write) miss cycles system.iocache.overall_miss_latency 0 # number of overall miss cycles -system.iocache.ReadReq_accesses::1 907 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 907 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::1 905 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 905 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::1 46720 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 46720 # number of WriteReq accesses(hits+misses) system.iocache.demand_accesses::0 0 # number of demand (read+write) accesses -system.iocache.demand_accesses::1 47627 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 47627 # number of demand (read+write) accesses +system.iocache.demand_accesses::1 47625 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 47625 # number of demand (read+write) accesses system.iocache.overall_accesses::0 0 # number of overall (read+write) accesses -system.iocache.overall_accesses::1 47627 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 47627 # number of overall (read+write) accesses +system.iocache.overall_accesses::1 47625 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 47625 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::1 1 # miss rate for ReadReq accesses system.iocache.WriteReq_miss_rate::1 1 # miss rate for WriteReq accesses system.iocache.demand_miss_rate::0 no_value # miss rate for demand accesses @@ -200,68 +200,68 @@ system.pc.south_bridge.ide.disks1.dma_read_txs 0 system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes. system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes. system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions. -system.cpu.numCycles 10224074013 # number of cpu cycles simulated +system.cpu.numCycles 10224086531 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.num_insts 406583262 # Number of instructions executed -system.cpu.num_int_alu_accesses 391790000 # Number of integer alu accesses +system.cpu.num_insts 409133277 # Number of instructions executed +system.cpu.num_int_alu_accesses 374297244 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses system.cpu.num_func_calls 0 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 42454615 # number of instructions that are conditional controls -system.cpu.num_int_insts 391790000 # number of integer instructions +system.cpu.num_conditional_control_insts 39954968 # number of instructions that are conditional controls +system.cpu.num_int_insts 374297244 # number of integer instructions system.cpu.num_fp_insts 0 # number of float instructions -system.cpu.num_int_register_reads 836247135 # number of times the integer registers were read -system.cpu.num_int_register_writes 419118732 # number of times the integer registers were written +system.cpu.num_int_register_reads 801267455 # number of times the integer registers were read +system.cpu.num_int_register_writes 401624559 # number of times the integer registers were written system.cpu.num_fp_register_reads 0 # number of times the floating registers were read system.cpu.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu.num_mem_refs 38123075 # number of memory refs -system.cpu.num_load_insts 29716799 # Number of load instructions -system.cpu.num_store_insts 8406276 # Number of store instructions -system.cpu.num_idle_cycles 9770647500.086761 # Number of idle cycles -system.cpu.num_busy_cycles 453426512.913238 # Number of busy cycles -system.cpu.not_idle_fraction 0.044349 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.955651 # Percentage of idle cycles +system.cpu.num_mem_refs 35626519 # number of memory refs +system.cpu.num_load_insts 27217784 # Number of load instructions +system.cpu.num_store_insts 8408735 # Number of store instructions +system.cpu.num_idle_cycles 9770605338.086651 # Number of idle cycles +system.cpu.num_busy_cycles 453481192.913350 # Number of busy cycles +system.cpu.not_idle_fraction 0.044354 # Percentage of non-idle cycles +system.cpu.idle_fraction 0.955646 # Percentage of idle cycles system.cpu.kern.inst.arm 0 # number of arm instructions executed system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed -system.cpu.icache.replacements 790768 # number of replacements -system.cpu.icache.tagsinuse 510.627880 # Cycle average of tags in use -system.cpu.icache.total_refs 253353258 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 791280 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 320.181551 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 148756117000 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 510.627880 # Average occupied blocks per context +system.cpu.icache.replacements 790795 # number of replacements +system.cpu.icache.tagsinuse 510.627676 # Cycle average of tags in use +system.cpu.icache.total_refs 243365777 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 791307 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 307.549127 # Average number of references to valid blocks. +system.cpu.icache.warmup_cycle 148763105500 # Cycle when the warmup percentage was hit. +system.cpu.icache.occ_blocks::0 510.627676 # Average occupied blocks per context system.cpu.icache.occ_percent::0 0.997320 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::0 253353258 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 253353258 # number of ReadReq hits -system.cpu.icache.demand_hits::0 253353258 # number of demand (read+write) hits +system.cpu.icache.ReadReq_hits::0 243365777 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 243365777 # number of ReadReq hits +system.cpu.icache.demand_hits::0 243365777 # number of demand (read+write) hits system.cpu.icache.demand_hits::1 0 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 253353258 # number of demand (read+write) hits -system.cpu.icache.overall_hits::0 253353258 # number of overall hits +system.cpu.icache.demand_hits::total 243365777 # number of demand (read+write) hits +system.cpu.icache.overall_hits::0 243365777 # number of overall hits system.cpu.icache.overall_hits::1 0 # number of overall hits -system.cpu.icache.overall_hits::total 253353258 # number of overall hits -system.cpu.icache.ReadReq_misses::0 791287 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 791287 # number of ReadReq misses -system.cpu.icache.demand_misses::0 791287 # number of demand (read+write) misses +system.cpu.icache.overall_hits::total 243365777 # number of overall hits +system.cpu.icache.ReadReq_misses::0 791314 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 791314 # number of ReadReq misses +system.cpu.icache.demand_misses::0 791314 # number of demand (read+write) misses system.cpu.icache.demand_misses::1 0 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 791287 # number of demand (read+write) misses -system.cpu.icache.overall_misses::0 791287 # number of overall misses +system.cpu.icache.demand_misses::total 791314 # number of demand (read+write) misses +system.cpu.icache.overall_misses::0 791314 # number of overall misses system.cpu.icache.overall_misses::1 0 # number of overall misses -system.cpu.icache.overall_misses::total 791287 # number of overall misses +system.cpu.icache.overall_misses::total 791314 # number of overall misses system.cpu.icache.demand_miss_latency 0 # number of demand (read+write) miss cycles system.cpu.icache.overall_miss_latency 0 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::0 254144545 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 254144545 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::0 254144545 # number of demand (read+write) accesses +system.cpu.icache.ReadReq_accesses::0 244157091 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 244157091 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::0 244157091 # number of demand (read+write) accesses system.cpu.icache.demand_accesses::1 0 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 254144545 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::0 254144545 # number of overall (read+write) accesses +system.cpu.icache.demand_accesses::total 244157091 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::0 244157091 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::1 0 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 254144545 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::0 0.003114 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::0 0.003114 # miss rate for demand accesses +system.cpu.icache.overall_accesses::total 244157091 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::0 0.003241 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::0 0.003241 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::1 no_value # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::0 0.003114 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::0 0.003241 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::1 no_value # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total no_value # miss rate for overall accesses system.cpu.icache.demand_avg_miss_latency::0 0 # average overall miss latency @@ -278,7 +278,7 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs no_value system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.writebacks 806 # number of writebacks +system.cpu.icache.writebacks 809 # number of writebacks system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits system.cpu.icache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses @@ -299,50 +299,50 @@ system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.itb_walker_cache.replacements 3656 # number of replacements -system.cpu.itb_walker_cache.tagsinuse 3.021422 # Cycle average of tags in use -system.cpu.itb_walker_cache.total_refs 7713 # Total number of references to valid blocks. -system.cpu.itb_walker_cache.sampled_refs 3666 # Sample count of references to valid blocks. -system.cpu.itb_walker_cache.avg_refs 2.103928 # Average number of references to valid blocks. -system.cpu.itb_walker_cache.warmup_cycle 5105310674000 # Cycle when the warmup percentage was hit. -system.cpu.itb_walker_cache.occ_blocks::1 3.021422 # Average occupied blocks per context -system.cpu.itb_walker_cache.occ_percent::1 0.188839 # Average percentage of cache occupancy -system.cpu.itb_walker_cache.ReadReq_hits::1 7719 # number of ReadReq hits -system.cpu.itb_walker_cache.ReadReq_hits::total 7719 # number of ReadReq hits +system.cpu.itb_walker_cache.replacements 3435 # number of replacements +system.cpu.itb_walker_cache.tagsinuse 3.021701 # Cycle average of tags in use +system.cpu.itb_walker_cache.total_refs 7940 # Total number of references to valid blocks. +system.cpu.itb_walker_cache.sampled_refs 3444 # Sample count of references to valid blocks. +system.cpu.itb_walker_cache.avg_refs 2.305459 # Average number of references to valid blocks. +system.cpu.itb_walker_cache.warmup_cycle 5105275407500 # Cycle when the warmup percentage was hit. +system.cpu.itb_walker_cache.occ_blocks::1 3.021701 # Average occupied blocks per context +system.cpu.itb_walker_cache.occ_percent::1 0.188856 # Average percentage of cache occupancy +system.cpu.itb_walker_cache.ReadReq_hits::1 7947 # number of ReadReq hits +system.cpu.itb_walker_cache.ReadReq_hits::total 7947 # number of ReadReq hits system.cpu.itb_walker_cache.WriteReq_hits::1 2 # number of WriteReq hits system.cpu.itb_walker_cache.WriteReq_hits::total 2 # number of WriteReq hits system.cpu.itb_walker_cache.demand_hits::0 0 # number of demand (read+write) hits -system.cpu.itb_walker_cache.demand_hits::1 7721 # number of demand (read+write) hits -system.cpu.itb_walker_cache.demand_hits::total 7721 # number of demand (read+write) hits +system.cpu.itb_walker_cache.demand_hits::1 7949 # number of demand (read+write) hits +system.cpu.itb_walker_cache.demand_hits::total 7949 # number of demand (read+write) hits system.cpu.itb_walker_cache.overall_hits::0 0 # number of overall hits -system.cpu.itb_walker_cache.overall_hits::1 7721 # number of overall hits -system.cpu.itb_walker_cache.overall_hits::total 7721 # number of overall hits -system.cpu.itb_walker_cache.ReadReq_misses::1 4507 # number of ReadReq misses -system.cpu.itb_walker_cache.ReadReq_misses::total 4507 # number of ReadReq misses +system.cpu.itb_walker_cache.overall_hits::1 7949 # number of overall hits +system.cpu.itb_walker_cache.overall_hits::total 7949 # number of overall hits +system.cpu.itb_walker_cache.ReadReq_misses::1 4278 # number of ReadReq misses +system.cpu.itb_walker_cache.ReadReq_misses::total 4278 # number of ReadReq misses system.cpu.itb_walker_cache.demand_misses::0 0 # number of demand (read+write) misses -system.cpu.itb_walker_cache.demand_misses::1 4507 # number of demand (read+write) misses -system.cpu.itb_walker_cache.demand_misses::total 4507 # number of demand (read+write) misses +system.cpu.itb_walker_cache.demand_misses::1 4278 # number of demand (read+write) misses +system.cpu.itb_walker_cache.demand_misses::total 4278 # number of demand (read+write) misses system.cpu.itb_walker_cache.overall_misses::0 0 # number of overall misses -system.cpu.itb_walker_cache.overall_misses::1 4507 # number of overall misses -system.cpu.itb_walker_cache.overall_misses::total 4507 # number of overall misses +system.cpu.itb_walker_cache.overall_misses::1 4278 # number of overall misses +system.cpu.itb_walker_cache.overall_misses::total 4278 # number of overall misses system.cpu.itb_walker_cache.demand_miss_latency 0 # number of demand (read+write) miss cycles system.cpu.itb_walker_cache.overall_miss_latency 0 # number of overall miss cycles -system.cpu.itb_walker_cache.ReadReq_accesses::1 12226 # number of ReadReq accesses(hits+misses) -system.cpu.itb_walker_cache.ReadReq_accesses::total 12226 # number of ReadReq accesses(hits+misses) +system.cpu.itb_walker_cache.ReadReq_accesses::1 12225 # number of ReadReq accesses(hits+misses) +system.cpu.itb_walker_cache.ReadReq_accesses::total 12225 # number of ReadReq accesses(hits+misses) system.cpu.itb_walker_cache.WriteReq_accesses::1 2 # number of WriteReq accesses(hits+misses) system.cpu.itb_walker_cache.WriteReq_accesses::total 2 # number of WriteReq accesses(hits+misses) system.cpu.itb_walker_cache.demand_accesses::0 0 # number of demand (read+write) accesses -system.cpu.itb_walker_cache.demand_accesses::1 12228 # number of demand (read+write) accesses -system.cpu.itb_walker_cache.demand_accesses::total 12228 # number of demand (read+write) accesses +system.cpu.itb_walker_cache.demand_accesses::1 12227 # number of demand (read+write) accesses +system.cpu.itb_walker_cache.demand_accesses::total 12227 # number of demand (read+write) accesses system.cpu.itb_walker_cache.overall_accesses::0 0 # number of overall (read+write) accesses -system.cpu.itb_walker_cache.overall_accesses::1 12228 # number of overall (read+write) accesses -system.cpu.itb_walker_cache.overall_accesses::total 12228 # number of overall (read+write) accesses -system.cpu.itb_walker_cache.ReadReq_miss_rate::1 0.368641 # miss rate for ReadReq accesses +system.cpu.itb_walker_cache.overall_accesses::1 12227 # number of overall (read+write) accesses +system.cpu.itb_walker_cache.overall_accesses::total 12227 # number of overall (read+write) accesses +system.cpu.itb_walker_cache.ReadReq_miss_rate::1 0.349939 # miss rate for ReadReq accesses system.cpu.itb_walker_cache.demand_miss_rate::0 no_value # miss rate for demand accesses -system.cpu.itb_walker_cache.demand_miss_rate::1 0.368580 # miss rate for demand accesses +system.cpu.itb_walker_cache.demand_miss_rate::1 0.349881 # miss rate for demand accesses system.cpu.itb_walker_cache.demand_miss_rate::total no_value # miss rate for demand accesses system.cpu.itb_walker_cache.overall_miss_rate::0 no_value # miss rate for overall accesses -system.cpu.itb_walker_cache.overall_miss_rate::1 0.368580 # miss rate for overall accesses +system.cpu.itb_walker_cache.overall_miss_rate::1 0.349881 # miss rate for overall accesses system.cpu.itb_walker_cache.overall_miss_rate::total no_value # miss rate for overall accesses system.cpu.itb_walker_cache.demand_avg_miss_latency::0 no_value # average overall miss latency system.cpu.itb_walker_cache.demand_avg_miss_latency::1 0 # average overall miss latency @@ -358,7 +358,7 @@ system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs no_value system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed -system.cpu.itb_walker_cache.writebacks 405 # number of writebacks +system.cpu.itb_walker_cache.writebacks 518 # number of writebacks system.cpu.itb_walker_cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.cpu.itb_walker_cache.overall_mshr_hits 0 # number of overall MSHR hits system.cpu.itb_walker_cache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses @@ -379,46 +379,46 @@ system.cpu.itb_walker_cache.overall_avg_mshr_uncacheable_latency no_value system.cpu.itb_walker_cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.itb_walker_cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dtb_walker_cache.replacements 8177 # number of replacements -system.cpu.dtb_walker_cache.tagsinuse 5.011395 # Cycle average of tags in use -system.cpu.dtb_walker_cache.total_refs 12378 # Total number of references to valid blocks. -system.cpu.dtb_walker_cache.sampled_refs 8191 # Sample count of references to valid blocks. -system.cpu.dtb_walker_cache.avg_refs 1.511171 # Average number of references to valid blocks. -system.cpu.dtb_walker_cache.warmup_cycle 5101233676500 # Cycle when the warmup percentage was hit. -system.cpu.dtb_walker_cache.occ_blocks::1 5.011395 # Average occupied blocks per context -system.cpu.dtb_walker_cache.occ_percent::1 0.313212 # Average percentage of cache occupancy -system.cpu.dtb_walker_cache.ReadReq_hits::1 12392 # number of ReadReq hits -system.cpu.dtb_walker_cache.ReadReq_hits::total 12392 # number of ReadReq hits +system.cpu.dtb_walker_cache.replacements 7755 # number of replacements +system.cpu.dtb_walker_cache.tagsinuse 5.010998 # Cycle average of tags in use +system.cpu.dtb_walker_cache.total_refs 12854 # Total number of references to valid blocks. +system.cpu.dtb_walker_cache.sampled_refs 7767 # Sample count of references to valid blocks. +system.cpu.dtb_walker_cache.avg_refs 1.654950 # Average number of references to valid blocks. +system.cpu.dtb_walker_cache.warmup_cycle 5101232849000 # Cycle when the warmup percentage was hit. +system.cpu.dtb_walker_cache.occ_blocks::1 5.010998 # Average occupied blocks per context +system.cpu.dtb_walker_cache.occ_percent::1 0.313187 # Average percentage of cache occupancy +system.cpu.dtb_walker_cache.ReadReq_hits::1 12875 # number of ReadReq hits +system.cpu.dtb_walker_cache.ReadReq_hits::total 12875 # number of ReadReq hits system.cpu.dtb_walker_cache.demand_hits::0 0 # number of demand (read+write) hits -system.cpu.dtb_walker_cache.demand_hits::1 12392 # number of demand (read+write) hits -system.cpu.dtb_walker_cache.demand_hits::total 12392 # number of demand (read+write) hits +system.cpu.dtb_walker_cache.demand_hits::1 12875 # number of demand (read+write) hits +system.cpu.dtb_walker_cache.demand_hits::total 12875 # number of demand (read+write) hits system.cpu.dtb_walker_cache.overall_hits::0 0 # number of overall hits -system.cpu.dtb_walker_cache.overall_hits::1 12392 # number of overall hits -system.cpu.dtb_walker_cache.overall_hits::total 12392 # number of overall hits -system.cpu.dtb_walker_cache.ReadReq_misses::1 9345 # number of ReadReq misses -system.cpu.dtb_walker_cache.ReadReq_misses::total 9345 # number of ReadReq misses +system.cpu.dtb_walker_cache.overall_hits::1 12875 # number of overall hits +system.cpu.dtb_walker_cache.overall_hits::total 12875 # number of overall hits +system.cpu.dtb_walker_cache.ReadReq_misses::1 8933 # number of ReadReq misses +system.cpu.dtb_walker_cache.ReadReq_misses::total 8933 # number of ReadReq misses system.cpu.dtb_walker_cache.demand_misses::0 0 # number of demand (read+write) misses -system.cpu.dtb_walker_cache.demand_misses::1 9345 # number of demand (read+write) misses -system.cpu.dtb_walker_cache.demand_misses::total 9345 # number of demand (read+write) misses +system.cpu.dtb_walker_cache.demand_misses::1 8933 # number of demand (read+write) misses +system.cpu.dtb_walker_cache.demand_misses::total 8933 # number of demand (read+write) misses system.cpu.dtb_walker_cache.overall_misses::0 0 # number of overall misses -system.cpu.dtb_walker_cache.overall_misses::1 9345 # number of overall misses -system.cpu.dtb_walker_cache.overall_misses::total 9345 # number of overall misses +system.cpu.dtb_walker_cache.overall_misses::1 8933 # number of overall misses +system.cpu.dtb_walker_cache.overall_misses::total 8933 # number of overall misses system.cpu.dtb_walker_cache.demand_miss_latency 0 # number of demand (read+write) miss cycles system.cpu.dtb_walker_cache.overall_miss_latency 0 # number of overall miss cycles -system.cpu.dtb_walker_cache.ReadReq_accesses::1 21737 # number of ReadReq accesses(hits+misses) -system.cpu.dtb_walker_cache.ReadReq_accesses::total 21737 # number of ReadReq accesses(hits+misses) +system.cpu.dtb_walker_cache.ReadReq_accesses::1 21808 # number of ReadReq accesses(hits+misses) +system.cpu.dtb_walker_cache.ReadReq_accesses::total 21808 # number of ReadReq accesses(hits+misses) system.cpu.dtb_walker_cache.demand_accesses::0 0 # number of demand (read+write) accesses -system.cpu.dtb_walker_cache.demand_accesses::1 21737 # number of demand (read+write) accesses -system.cpu.dtb_walker_cache.demand_accesses::total 21737 # number of demand (read+write) accesses +system.cpu.dtb_walker_cache.demand_accesses::1 21808 # number of demand (read+write) accesses +system.cpu.dtb_walker_cache.demand_accesses::total 21808 # number of demand (read+write) accesses system.cpu.dtb_walker_cache.overall_accesses::0 0 # number of overall (read+write) accesses -system.cpu.dtb_walker_cache.overall_accesses::1 21737 # number of overall (read+write) accesses -system.cpu.dtb_walker_cache.overall_accesses::total 21737 # number of overall (read+write) accesses -system.cpu.dtb_walker_cache.ReadReq_miss_rate::1 0.429912 # miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.overall_accesses::1 21808 # number of overall (read+write) accesses +system.cpu.dtb_walker_cache.overall_accesses::total 21808 # number of overall (read+write) accesses +system.cpu.dtb_walker_cache.ReadReq_miss_rate::1 0.409620 # miss rate for ReadReq accesses system.cpu.dtb_walker_cache.demand_miss_rate::0 no_value # miss rate for demand accesses -system.cpu.dtb_walker_cache.demand_miss_rate::1 0.429912 # miss rate for demand accesses +system.cpu.dtb_walker_cache.demand_miss_rate::1 0.409620 # miss rate for demand accesses system.cpu.dtb_walker_cache.demand_miss_rate::total no_value # miss rate for demand accesses system.cpu.dtb_walker_cache.overall_miss_rate::0 no_value # miss rate for overall accesses -system.cpu.dtb_walker_cache.overall_miss_rate::1 0.429912 # miss rate for overall accesses +system.cpu.dtb_walker_cache.overall_miss_rate::1 0.409620 # miss rate for overall accesses system.cpu.dtb_walker_cache.overall_miss_rate::total no_value # miss rate for overall accesses system.cpu.dtb_walker_cache.demand_avg_miss_latency::0 no_value # average overall miss latency system.cpu.dtb_walker_cache.demand_avg_miss_latency::1 0 # average overall miss latency @@ -434,7 +434,7 @@ system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs no_value system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed -system.cpu.dtb_walker_cache.writebacks 2332 # number of writebacks +system.cpu.dtb_walker_cache.writebacks 2517 # number of writebacks system.cpu.dtb_walker_cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.cpu.dtb_walker_cache.overall_mshr_hits 0 # number of overall MSHR hits system.cpu.dtb_walker_cache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses @@ -455,52 +455,52 @@ system.cpu.dtb_walker_cache.overall_avg_mshr_uncacheable_latency no_value system.cpu.dtb_walker_cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dtb_walker_cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 1621118 # number of replacements +system.cpu.dcache.replacements 1621277 # number of replacements system.cpu.dcache.tagsinuse 511.999417 # Cycle average of tags in use -system.cpu.dcache.total_refs 20138941 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 1621630 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 12.418949 # Average number of references to valid blocks. +system.cpu.dcache.total_refs 20142220 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 1621789 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 12.419754 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 7549500 # Cycle when the warmup percentage was hit. system.cpu.dcache.occ_blocks::0 511.999417 # Average occupied blocks per context system.cpu.dcache.occ_percent::0 0.999999 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::0 12055886 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 12055886 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::0 8080806 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 8080806 # number of WriteReq hits -system.cpu.dcache.demand_hits::0 20136692 # number of demand (read+write) hits +system.cpu.dcache.ReadReq_hits::0 12057024 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 12057024 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::0 8082938 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 8082938 # number of WriteReq hits +system.cpu.dcache.demand_hits::0 20139962 # number of demand (read+write) hits system.cpu.dcache.demand_hits::1 0 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 20136692 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::0 20136692 # number of overall hits +system.cpu.dcache.demand_hits::total 20139962 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::0 20139962 # number of overall hits system.cpu.dcache.overall_hits::1 0 # number of overall hits -system.cpu.dcache.overall_hits::total 20136692 # number of overall hits -system.cpu.dcache.ReadReq_misses::0 1308365 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1308365 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::0 315530 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 315530 # number of WriteReq misses -system.cpu.dcache.demand_misses::0 1623895 # number of demand (read+write) misses +system.cpu.dcache.overall_hits::total 20139962 # number of overall hits +system.cpu.dcache.ReadReq_misses::0 1308207 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1308207 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::0 315850 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 315850 # number of WriteReq misses +system.cpu.dcache.demand_misses::0 1624057 # number of demand (read+write) misses system.cpu.dcache.demand_misses::1 0 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1623895 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::0 1623895 # number of overall misses +system.cpu.dcache.demand_misses::total 1624057 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::0 1624057 # number of overall misses system.cpu.dcache.overall_misses::1 0 # number of overall misses -system.cpu.dcache.overall_misses::total 1623895 # number of overall misses +system.cpu.dcache.overall_misses::total 1624057 # number of overall misses system.cpu.dcache.demand_miss_latency 0 # number of demand (read+write) miss cycles system.cpu.dcache.overall_miss_latency 0 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::0 13364251 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 13364251 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::0 8396336 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 8396336 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::0 21760587 # number of demand (read+write) accesses +system.cpu.dcache.ReadReq_accesses::0 13365231 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 13365231 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::0 8398788 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 8398788 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::0 21764019 # number of demand (read+write) accesses system.cpu.dcache.demand_accesses::1 0 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 21760587 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::0 21760587 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::total 21764019 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::0 21764019 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::1 0 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 21760587 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::0 0.097900 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::0 0.037579 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::0 0.074626 # miss rate for demand accesses +system.cpu.dcache.overall_accesses::total 21764019 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::0 0.097881 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::0 0.037607 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::0 0.074621 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::0 0.074626 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::0 0.074621 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total no_value # miss rate for overall accesses system.cpu.dcache.demand_avg_miss_latency::0 0 # average overall miss latency @@ -517,7 +517,7 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks 1525259 # number of writebacks +system.cpu.dcache.writebacks 1525559 # number of writebacks system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits system.cpu.dcache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses diff --git a/tests/quick/10.linux-boot/ref/x86/linux/pc-simple-timing/config.ini b/tests/quick/10.linux-boot/ref/x86/linux/pc-simple-timing/config.ini index f05a137d3..3130a22aa 100644 --- a/tests/quick/10.linux-boot/ref/x86/linux/pc-simple-timing/config.ini +++ b/tests/quick/10.linux-boot/ref/x86/linux/pc-simple-timing/config.ini @@ -15,9 +15,11 @@ e820_table=system.e820_table init_param=0 intel_mp_pointer=system.intel_mp_pointer intel_mp_table=system.intel_mp_table -kernel=/dist/m5/system/binaries/x86_64-vmlinux-2.6.22.9 +kernel=/scratch/nilay/GEM5/system/binaries/x86_64-vmlinux-2.6.22.9 load_addr_mask=18446744073709551615 mem_mode=timing +memories=system.physmem +num_work_ids=16 physmem=system.physmem readfile=tests/halt.sh smbios_table=system.smbios_table @@ -704,6 +706,7 @@ port=system.physmem.port[0] system.bridge.side_b system.iocache.mem_side system. [system.membus.badaddr_responder] type=IsaFake +fake_mem=false pio_addr=0 pio_latency=1000 pio_size=8 @@ -726,6 +729,7 @@ system=system [system.pc.behind_pci] type=IsaFake +fake_mem=false pio_addr=9223372036854779128 pio_latency=1000 pio_size=8 @@ -742,15 +746,31 @@ pio=system.iobus.port[12] [system.pc.com_1] type=Uart8250 +children=terminal pio_addr=9223372036854776824 pio_latency=1000 platform=system.pc system=system -terminal=system.pc.terminal +terminal=system.pc.com_1.terminal pio=system.iobus.port[13] +[system.pc.com_1.terminal] +type=Terminal +intr_control=system.intrctrl +number=0 +output=true +port=3456 + +[system.pc.com_1.terminal] +type=Terminal +intr_control=system.intrctrl +number=0 +output=true +port=3456 + [system.pc.fake_com_2] type=IsaFake +fake_mem=false pio_addr=9223372036854776568 pio_latency=1000 pio_size=8 @@ -767,6 +787,7 @@ pio=system.iobus.port[14] [system.pc.fake_com_3] type=IsaFake +fake_mem=false pio_addr=9223372036854776808 pio_latency=1000 pio_size=8 @@ -783,6 +804,7 @@ pio=system.iobus.port[15] [system.pc.fake_com_4] type=IsaFake +fake_mem=false pio_addr=9223372036854776552 pio_latency=1000 pio_size=8 @@ -799,6 +821,7 @@ pio=system.iobus.port[16] [system.pc.fake_floppy] type=IsaFake +fake_mem=false pio_addr=9223372036854776818 pio_latency=1000 pio_size=2 @@ -815,6 +838,7 @@ pio=system.iobus.port[17] [system.pc.i_dont_exist] type=IsaFake +fake_mem=false pio_addr=9223372036854775936 pio_latency=1000 pio_size=1 @@ -843,7 +867,6 @@ type=SouthBridge children=cmos dma1 ide int_lines0 int_lines1 int_lines2 int_lines3 int_lines4 int_lines5 int_lines6 io_apic keyboard pic1 pic2 pit speaker cmos=system.pc.south_bridge.cmos dma1=system.pc.south_bridge.dma1 -int_lines=system.pc.south_bridge.int_lines0 system.pc.south_bridge.int_lines1 system.pc.south_bridge.int_lines2 system.pc.south_bridge.int_lines3 system.pc.south_bridge.int_lines4 system.pc.south_bridge.int_lines5 system.pc.south_bridge.int_lines6 io_apic=system.pc.south_bridge.io_apic keyboard=system.pc.south_bridge.keyboard pic1=system.pc.south_bridge.pic1 @@ -855,7 +878,8 @@ speaker=system.pc.south_bridge.speaker [system.pc.south_bridge.cmos] type=Cmos -int_pin=system.pc.south_bridge.int_lines2.source +children=int_pin +int_pin=system.pc.south_bridge.cmos.int_pin pio_addr=9223372036854775920 pio_latency=1000 platform=system.pc @@ -863,6 +887,9 @@ system=system time=Sun Jan 1 00:00:00 2012 pio=system.iobus.port[1] +[system.pc.south_bridge.cmos.int_pin] +type=X86IntSourcePin + [system.pc.south_bridge.dma1] type=I8237 pio_addr=9223372036854775808 @@ -945,7 +972,7 @@ table_size=65536 [system.pc.south_bridge.ide.disks0.image.child] type=RawDiskImage -image_file=/dist/m5/system/disks/linux-x86.img +image_file=/scratch/nilay/GEM5/system/disks/linux-x86.img read_only=true [system.pc.south_bridge.ide.disks1] @@ -965,70 +992,58 @@ table_size=65536 [system.pc.south_bridge.ide.disks1.image.child] type=RawDiskImage -image_file=/dist/m5/system/disks/linux-bigswap2.img +image_file=/scratch/nilay/GEM5/system/disks/linux-bigswap2.img read_only=true [system.pc.south_bridge.int_lines0] type=X86IntLine -children=sink source +children=sink sink=system.pc.south_bridge.int_lines0.sink -source=system.pc.south_bridge.int_lines0.source +source=system.pc.south_bridge.pic1.output [system.pc.south_bridge.int_lines0.sink] type=X86IntSinkPin device=system.pc.south_bridge.io_apic number=0 -[system.pc.south_bridge.int_lines0.source] -type=X86IntSourcePin - [system.pc.south_bridge.int_lines1] type=X86IntLine -children=sink source +children=sink sink=system.pc.south_bridge.int_lines1.sink -source=system.pc.south_bridge.int_lines1.source +source=system.pc.south_bridge.pic2.output [system.pc.south_bridge.int_lines1.sink] type=X86IntSinkPin device=system.pc.south_bridge.pic1 number=2 -[system.pc.south_bridge.int_lines1.source] -type=X86IntSourcePin - [system.pc.south_bridge.int_lines2] type=X86IntLine -children=sink source +children=sink sink=system.pc.south_bridge.int_lines2.sink -source=system.pc.south_bridge.int_lines2.source +source=system.pc.south_bridge.cmos.int_pin [system.pc.south_bridge.int_lines2.sink] type=X86IntSinkPin device=system.pc.south_bridge.pic2 number=0 -[system.pc.south_bridge.int_lines2.source] -type=X86IntSourcePin - [system.pc.south_bridge.int_lines3] type=X86IntLine -children=sink source +children=sink sink=system.pc.south_bridge.int_lines3.sink -source=system.pc.south_bridge.int_lines3.source +source=system.pc.south_bridge.pit.int_pin [system.pc.south_bridge.int_lines3.sink] type=X86IntSinkPin device=system.pc.south_bridge.pic1 number=0 -[system.pc.south_bridge.int_lines3.source] -type=X86IntSourcePin - [system.pc.south_bridge.int_lines4] type=X86IntLine children=sink sink=system.pc.south_bridge.int_lines4.sink -source=system.pc.south_bridge.int_lines3.source +source=system.pc.south_bridge.pit.int_pin [system.pc.south_bridge.int_lines4.sink] type=X86IntSinkPin @@ -1037,32 +1052,26 @@ number=2 [system.pc.south_bridge.int_lines5] type=X86IntLine -children=sink source +children=sink sink=system.pc.south_bridge.int_lines5.sink -source=system.pc.south_bridge.int_lines5.source +source=system.pc.south_bridge.keyboard.keyboard_int_pin [system.pc.south_bridge.int_lines5.sink] type=X86IntSinkPin device=system.pc.south_bridge.io_apic number=1 -[system.pc.south_bridge.int_lines5.source] -type=X86IntSourcePin - [system.pc.south_bridge.int_lines6] type=X86IntLine -children=sink source +children=sink sink=system.pc.south_bridge.int_lines6.sink -source=system.pc.south_bridge.int_lines6.source +source=system.pc.south_bridge.keyboard.mouse_int_pin [system.pc.south_bridge.int_lines6.sink] type=X86IntSinkPin device=system.pc.south_bridge.io_apic number=12 -[system.pc.south_bridge.int_lines6.source] -type=X86IntSourcePin - [system.pc.south_bridge.io_apic] type=I82094AA apic_id=1 @@ -1077,20 +1086,28 @@ pio=system.iobus.port[9] [system.pc.south_bridge.keyboard] type=I8042 +children=keyboard_int_pin mouse_int_pin command_port=9223372036854775908 data_port=9223372036854775904 -keyboard_int_pin=system.pc.south_bridge.int_lines5.source -mouse_int_pin=system.pc.south_bridge.int_lines6.source +keyboard_int_pin=system.pc.south_bridge.keyboard.keyboard_int_pin +mouse_int_pin=system.pc.south_bridge.keyboard.mouse_int_pin pio_addr=0 pio_latency=1000 platform=system.pc system=system pio=system.iobus.port[4] +[system.pc.south_bridge.keyboard.keyboard_int_pin] +type=X86IntSourcePin + +[system.pc.south_bridge.keyboard.mouse_int_pin] +type=X86IntSourcePin + [system.pc.south_bridge.pic1] type=I8259 +children=output mode=I8259Master -output=system.pc.south_bridge.int_lines0.source +output=system.pc.south_bridge.pic1.output pio_addr=9223372036854775840 pio_latency=1000 platform=system.pc @@ -1098,10 +1115,14 @@ slave=system.pc.south_bridge.pic2 system=system pio=system.iobus.port[5] +[system.pc.south_bridge.pic1.output] +type=X86IntSourcePin + [system.pc.south_bridge.pic2] type=I8259 +children=output mode=I8259Slave -output=system.pc.south_bridge.int_lines1.source +output=system.pc.south_bridge.pic2.output pio_addr=9223372036854775968 pio_latency=1000 platform=system.pc @@ -1109,15 +1130,22 @@ slave=Null system=system pio=system.iobus.port[6] +[system.pc.south_bridge.pic2.output] +type=X86IntSourcePin + [system.pc.south_bridge.pit] type=I8254 -int_pin=system.pc.south_bridge.int_lines3.source +children=int_pin +int_pin=system.pc.south_bridge.pit.int_pin pio_addr=9223372036854775872 pio_latency=1000 platform=system.pc system=system pio=system.iobus.port[7] +[system.pc.south_bridge.pit.int_pin] +type=X86IntSourcePin + [system.pc.south_bridge.speaker] type=PcSpeaker i8254=system.pc.south_bridge.pit @@ -1127,13 +1155,6 @@ platform=system.pc system=system pio=system.iobus.port[8] -[system.pc.terminal] -type=Terminal -intr_control=system.intrctrl -number=0 -output=true -port=3456 - [system.physmem] type=PhysicalMemory file= diff --git a/tests/quick/10.linux-boot/ref/x86/linux/pc-simple-timing/simerr b/tests/quick/10.linux-boot/ref/x86/linux/pc-simple-timing/simerr index 99f9676e9..fd09f1faf 100755 --- a/tests/quick/10.linux-boot/ref/x86/linux/pc-simple-timing/simerr +++ b/tests/quick/10.linux-boot/ref/x86/linux/pc-simple-timing/simerr @@ -1,17 +1,9 @@ warn: Sockets disabled, not accepting terminal connections -For more information see: http://www.m5sim.org/warn/8742226b warn: Reading current count from inactive timer. -For more information see: http://www.m5sim.org/warn/1ea2be46 warn: Sockets disabled, not accepting gdb connections -For more information see: http://www.m5sim.org/warn/d946bea6 warn: Don't know what interrupt to clear for console. -For more information see: http://www.m5sim.org/warn/7fe1004f warn: instruction 'fxsave' unimplemented -For more information see: http://www.m5sim.org/warn/437d5238 warn: Tried to clear PCI interrupt 14 -For more information see: http://www.m5sim.org/warn/77378d57 warn: Unknown mouse command 0xe1. -For more information see: http://www.m5sim.org/warn/2447512a warn: instruction 'wbinvd' unimplemented -For more information see: http://www.m5sim.org/warn/437d5238 hack: be nice to actually delete the event here diff --git a/tests/quick/10.linux-boot/ref/x86/linux/pc-simple-timing/simout b/tests/quick/10.linux-boot/ref/x86/linux/pc-simple-timing/simout index f1baa96ff..ec51a2abf 100755 --- a/tests/quick/10.linux-boot/ref/x86/linux/pc-simple-timing/simout +++ b/tests/quick/10.linux-boot/ref/x86/linux/pc-simple-timing/simout @@ -1,15 +1,12 @@ -M5 Simulator System +gem5 Simulator System. http://gem5.org +gem5 is copyrighted software; use the --copyright option for details. -Copyright (c) 2001-2008 -The Regents of The University of Michigan -All Rights Reserved - - -M5 compiled Apr 19 2011 12:44:38 -M5 started Apr 19 2011 12:46:29 -M5 executing on maize -command line: build/X86_FS/m5.fast -d build/X86_FS/tests/fast/quick/10.linux-boot/x86/linux/pc-simple-timing -re tests/run.py build/X86_FS/tests/fast/quick/10.linux-boot/x86/linux/pc-simple-timing +gem5 compiled Jan 9 2012 20:47:38 +gem5 started Jan 9 2012 21:05:49 +gem5 executing on ribera.cs.wisc.edu +command line: build/X86_FS/gem5.fast -d build/X86_FS/tests/fast/quick/10.linux-boot/x86/linux/pc-simple-timing -re tests/run.py build/X86_FS/tests/fast/quick/10.linux-boot/x86/linux/pc-simple-timing +warning: add_child('terminal'): child 'terminal' already has parent Global frequency set at 1000000000000 ticks per second -info: kernel located at: /dist/m5/system/binaries/x86_64-vmlinux-2.6.22.9 +info: kernel located at: /scratch/nilay/GEM5/system/binaries/x86_64-vmlinux-2.6.22.9 info: Entering event queue @ 0. Starting simulation... Exiting @ tick 5195470393000 because m5_exit instruction encountered diff --git a/tests/quick/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt b/tests/quick/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt index f2563a156..3c6185134 100644 --- a/tests/quick/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt +++ b/tests/quick/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt @@ -3,11 +3,11 @@ sim_seconds 5.195470 # Number of seconds simulated sim_ticks 5195470393000 # Number of ticks simulated sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1914891 # Simulator instruction rate (inst/s) -host_tick_rate 37635937594 # Simulator tick rate (ticks/s) -host_mem_usage 372104 # Number of bytes of host memory used -host_seconds 138.05 # Real time elapsed on the host -sim_insts 264342001 # Number of instructions simulated +host_inst_rate 1858401 # Simulator instruction rate (inst/s) +host_tick_rate 36414646229 # Simulator tick rate (ticks/s) +host_mem_usage 372180 # Number of bytes of host memory used +host_seconds 142.68 # Real time elapsed on the host +sim_insts 265147881 # Number of instructions simulated system.l2c.replacements 136133 # number of replacements system.l2c.tagsinuse 31389.895470 # Cycle average of tags in use system.l2c.total_refs 3363370 # Total number of references to valid blocks. @@ -257,7 +257,7 @@ system.pc.south_bridge.ide.disks1.dma_write_txs 1 system.cpu.numCycles 10390940786 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.num_insts 264342001 # Number of instructions executed +system.cpu.num_insts 265147881 # Number of instructions executed system.cpu.num_int_alu_accesses 249556386 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses system.cpu.num_func_calls 0 # number of times a function call or return occured |