diff options
Diffstat (limited to 'tests/quick/20.eio-short/ref/alpha/eio/simple-atomic')
3 files changed, 15 insertions, 64 deletions
diff --git a/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/simerr b/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/simerr index c0312fe31..9c12ebd20 100755 --- a/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/simerr +++ b/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/simerr @@ -1,5 +1,9 @@ -warn: Sockets disabled, not accepting gdb connections -For more information see: http://www.m5sim.org/warn/d946bea6 -hack: be nice to actually delete the event here - -gzip: stdout: Broken pipe +Traceback (most recent call last): + File "<string>", line 1, in <module> + File "/arm/scratch/alisai01/m5/src/python/m5/main.py", line 359, in main + exec filecode in scope + File "tests/run.py", line 78, in <module> + execfile(joinpath(tests_root, category, name, 'test.py')) + File "tests/quick/20.eio-short/test.py", line 29, in <module> + root.system.cpu.workload = EioProcess(file = binpath('anagram', +NameError: name 'EioProcess' is not defined diff --git a/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/simout b/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/simout index c651bb2bf..ae0a2bbee 100755 --- a/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/simout +++ b/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/simout @@ -1,3 +1,5 @@ +Redirecting stdout to build/ALPHA_SE/tests/fast/quick/20.eio-short/alpha/eio/simple-atomic/simout +Redirecting stderr to build/ALPHA_SE/tests/fast/quick/20.eio-short/alpha/eio/simple-atomic/simerr M5 Simulator System Copyright (c) 2001-2008 @@ -5,13 +7,8 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 24 2010 23:12:40 -M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip -M5 started Feb 25 2010 03:02:04 -M5 executing on SC2B0619 +M5 compiled Nov 2 2010 21:30:55 +M5 revision 0af3760102ec+ 7713+ default qtip ext/alpha_prefetch.patch tip +M5 started Nov 2 2010 21:33:04 +M5 executing on aus-bc2-b15 command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/20.eio-short/alpha/eio/simple-atomic -re tests/run.py build/ALPHA_SE/tests/fast/quick/20.eio-short/alpha/eio/simple-atomic -Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... -main dictionary has 1245 entries -49508 bytes wasted ->Exiting @ tick 250015500 because a thread reached the max instruction count diff --git a/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/stats.txt b/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/stats.txt index 0e89d8fd8..e69de29bb 100644 --- a/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/stats.txt +++ b/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/stats.txt @@ -1,50 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -host_inst_rate 3013906 # Simulator instruction rate (inst/s) -host_mem_usage 181592 # Number of bytes of host memory used -host_seconds 0.17 # Real time elapsed on the host -host_tick_rate 1504585693 # Simulator tick rate (ticks/s) -sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 500001 # Number of instructions simulated -sim_seconds 0.000250 # Number of seconds simulated -sim_ticks 250015500 # Number of ticks simulated -system.cpu.dtb.data_accesses 180793 # DTB accesses -system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_hits 180775 # DTB hits -system.cpu.dtb.data_misses 18 # DTB misses -system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.fetch_acv 0 # ITB acv -system.cpu.dtb.fetch_hits 0 # ITB hits -system.cpu.dtb.fetch_misses 0 # ITB misses -system.cpu.dtb.read_accesses 124443 # DTB read accesses -system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_hits 124435 # DTB read hits -system.cpu.dtb.read_misses 8 # DTB read misses -system.cpu.dtb.write_accesses 56350 # DTB write accesses -system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_hits 56340 # DTB write hits -system.cpu.dtb.write_misses 10 # DTB write misses -system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.itb.data_acv 0 # DTB access violations -system.cpu.itb.data_hits 0 # DTB hits -system.cpu.itb.data_misses 0 # DTB misses -system.cpu.itb.fetch_accesses 500032 # ITB accesses -system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_hits 500019 # ITB hits -system.cpu.itb.fetch_misses 13 # ITB misses -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.read_acv 0 # DTB read access violations -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.write_acv 0 # DTB write access violations -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 500032 # number of cpu cycles simulated -system.cpu.num_insts 500001 # Number of instructions executed -system.cpu.num_refs 182222 # Number of memory references -system.cpu.workload.PROG:num_syscalls 18 # Number of system calls - ----------- End Simulation Statistics ---------- |