diff options
Diffstat (limited to 'tests/quick/20.eio-short/ref/alpha/eio/simple-timing/m5stats.txt')
| -rw-r--r-- | tests/quick/20.eio-short/ref/alpha/eio/simple-timing/m5stats.txt | 145 |
1 files changed, 82 insertions, 63 deletions
diff --git a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/m5stats.txt b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/m5stats.txt index 2ec710e81..d9f2463fd 100644 --- a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/m5stats.txt +++ b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/m5stats.txt @@ -1,32 +1,33 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 83773 # Simulator instruction rate (inst/s) -host_seconds 5.97 # Real time elapsed on the host -host_tick_rate 115920990 # Simulator tick rate (ticks/s) +host_inst_rate 1380632 # Simulator instruction rate (inst/s) +host_mem_usage 195668 # Number of bytes of host memory used +host_seconds 0.36 # Real time elapsed on the host +host_tick_rate 1946559093 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 500000 # Number of instructions simulated -sim_seconds 0.000692 # Number of seconds simulated -sim_ticks 691915000 # Number of ticks simulated +sim_seconds 0.000705 # Number of seconds simulated +sim_ticks 705470000 # Number of ticks simulated system.cpu.dcache.ReadReq_accesses 124435 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 14000 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 13000 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_miss_latency 25000 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 23000 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_hits 124120 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 4410000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency 7875000 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_rate 0.002531 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_misses 315 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_miss_latency 4095000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 7245000 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.002531 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_misses 315 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 56340 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 14000 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 13000 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 56201 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 1946000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.002467 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 139 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_miss_latency 1807000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.002467 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 139 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_avg_miss_latency 25000 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 23000 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 56029 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 7775000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.005520 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 311 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_miss_latency 7153000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate 0.005520 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses 311 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked system.cpu.dcache.avg_refs 397.182819 # Average number of references to valid blocks. @@ -36,31 +37,31 @@ system.cpu.dcache.blocked_cycles_no_mshrs 0 # n system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.demand_accesses 180775 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 14000 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 13000 # average overall mshr miss latency -system.cpu.dcache.demand_hits 180321 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 6356000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.002511 # miss rate for demand accesses -system.cpu.dcache.demand_misses 454 # number of demand (read+write) misses +system.cpu.dcache.demand_avg_miss_latency 25000 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 23000 # average overall mshr miss latency +system.cpu.dcache.demand_hits 180149 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 15650000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.003463 # miss rate for demand accesses +system.cpu.dcache.demand_misses 626 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 5902000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.002511 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 454 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_miss_latency 14398000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.003463 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 626 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.overall_accesses 180775 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 14000 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 13000 # average overall mshr miss latency +system.cpu.dcache.overall_avg_miss_latency 25000 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 23000 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 180321 # number of overall hits -system.cpu.dcache.overall_miss_latency 6356000 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.002511 # miss rate for overall accesses -system.cpu.dcache.overall_misses 454 # number of overall misses +system.cpu.dcache.overall_hits 180149 # number of overall hits +system.cpu.dcache.overall_miss_latency 15650000 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.003463 # miss rate for overall accesses +system.cpu.dcache.overall_misses 626 # number of overall misses system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 5902000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.002511 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 454 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_miss_latency 14398000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.003463 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 626 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -75,18 +76,18 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.sampled_refs 454 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 290.922203 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 289.564356 # Cycle average of tags in use system.cpu.dcache.total_refs 180321 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 0 # number of writebacks system.cpu.icache.ReadReq_accesses 500000 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 14000 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 13000 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_miss_latency 25000 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 23000 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_hits 499597 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 5642000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency 10075000 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_rate 0.000806 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_misses 403 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_miss_latency 5239000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 9269000 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.000806 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_misses 403 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked @@ -98,29 +99,29 @@ system.cpu.icache.blocked_cycles_no_mshrs 0 # n system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.demand_accesses 500000 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 14000 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 13000 # average overall mshr miss latency +system.cpu.icache.demand_avg_miss_latency 25000 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 23000 # average overall mshr miss latency system.cpu.icache.demand_hits 499597 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 5642000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency 10075000 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_rate 0.000806 # miss rate for demand accesses system.cpu.icache.demand_misses 403 # number of demand (read+write) misses system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 5239000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 9269000 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_rate 0.000806 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_misses 403 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.overall_accesses 500000 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 14000 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 13000 # average overall mshr miss latency +system.cpu.icache.overall_avg_miss_latency 25000 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 23000 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.icache.overall_hits 499597 # number of overall hits -system.cpu.icache.overall_miss_latency 5642000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency 10075000 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.000806 # miss rate for overall accesses system.cpu.icache.overall_misses 403 # number of overall misses system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 5239000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 9269000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_rate 0.000806 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_misses 403 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -137,20 +138,38 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.icache.replacements 0 # number of replacements system.cpu.icache.sampled_refs 403 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 267.665433 # Cycle average of tags in use +system.cpu.icache.tagsinuse 266.632904 # Cycle average of tags in use system.cpu.icache.total_refs 499597 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.l2cache.ReadReq_accesses 857 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 13000 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_accesses 139 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_avg_miss_latency 22000 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 11000 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_miss_latency 3058000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_misses 139 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency 1529000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_misses 139 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadReq_accesses 718 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 22000 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 11000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_miss_latency 11141000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency 15796000 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_rate 1 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 857 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 9427000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_misses 718 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 7898000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate 1 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 857 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses 718 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_accesses 172 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_avg_miss_latency 22000 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 11000 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_miss_latency 3784000 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_misses 172 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_mshr_miss_latency 1892000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_misses 172 # number of UpgradeReq MSHR misses system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked system.cpu.l2cache.avg_refs 0 # Average number of references to valid blocks. @@ -160,10 +179,10 @@ system.cpu.l2cache.blocked_cycles_no_mshrs 0 # system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.demand_accesses 857 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 13000 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency 22000 # average overall miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency 11000 # average overall mshr miss latency system.cpu.l2cache.demand_hits 0 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 11141000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency 18854000 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_rate 1 # miss rate for demand accesses system.cpu.l2cache.demand_misses 857 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits @@ -174,11 +193,11 @@ system.cpu.l2cache.fast_writes 0 # nu system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.overall_accesses 857 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 13000 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency 22000 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 11000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.l2cache.overall_hits 0 # number of overall hits -system.cpu.l2cache.overall_miss_latency 11141000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency 18854000 # number of overall miss cycles system.cpu.l2cache.overall_miss_rate 1 # miss rate for overall accesses system.cpu.l2cache.overall_misses 857 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits @@ -197,14 +216,14 @@ system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.sampled_refs 857 # Sample count of references to valid blocks. +system.cpu.l2cache.sampled_refs 546 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 558.588875 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 373.548776 # Cycle average of tags in use system.cpu.l2cache.total_refs 0 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 691915000 # number of cpu cycles simulated +system.cpu.numCycles 705470000 # number of cpu cycles simulated system.cpu.num_insts 500000 # Number of instructions executed system.cpu.num_refs 182203 # Number of memory references system.cpu.workload.PROG:num_syscalls 18 # Number of system calls |