diff options
Diffstat (limited to 'tests/quick/20.eio-short/ref/alpha/eio/simple-timing/stats.txt')
| -rw-r--r-- | tests/quick/20.eio-short/ref/alpha/eio/simple-timing/stats.txt | 14 |
1 files changed, 10 insertions, 4 deletions
diff --git a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/stats.txt b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/stats.txt index 2894da70d..fb5a17baa 100644 --- a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/stats.txt +++ b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 2302773 # Simulator instruction rate (inst/s) -host_mem_usage 201032 # Number of bytes of host memory used -host_seconds 0.22 # Real time elapsed on the host -host_tick_rate 3391978546 # Simulator tick rate (ticks/s) +host_inst_rate 1409192 # Simulator instruction rate (inst/s) +host_mem_usage 189184 # Number of bytes of host memory used +host_seconds 0.36 # Real time elapsed on the host +host_tick_rate 2076450214 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 500001 # Number of instructions simulated sim_seconds 0.000737 # Number of seconds simulated @@ -50,6 +50,8 @@ system.cpu.dcache.demand_mshr_misses 626 # nu system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.occ_%::0 0.069937 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::0 286.463742 # Average occupied blocks per context system.cpu.dcache.overall_accesses 180775 # number of overall (read+write) accesses system.cpu.dcache.overall_avg_miss_latency 56000 # average overall miss latency system.cpu.dcache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency @@ -119,6 +121,8 @@ system.cpu.icache.demand_mshr_misses 403 # nu system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.icache.occ_%::0 0.129067 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::0 264.328816 # Average occupied blocks per context system.cpu.icache.overall_accesses 500020 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency 56000 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency @@ -206,6 +210,8 @@ system.cpu.l2cache.demand_mshr_misses 857 # nu system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.l2cache.occ_%::0 0.011298 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::0 370.220381 # Average occupied blocks per context system.cpu.l2cache.overall_accesses 857 # number of overall (read+write) accesses system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency |