summaryrefslogtreecommitdiff
path: root/tests/quick/20.eio-short/ref/alpha
diff options
context:
space:
mode:
Diffstat (limited to 'tests/quick/20.eio-short/ref/alpha')
-rw-r--r--tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/config.ini1
-rw-r--r--tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/config.out1
-rw-r--r--tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/m5stats.txt6
-rw-r--r--tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/stdout4
-rw-r--r--tests/quick/20.eio-short/ref/alpha/eio/simple-timing/config.ini1
-rw-r--r--tests/quick/20.eio-short/ref/alpha/eio/simple-timing/config.out1
-rw-r--r--tests/quick/20.eio-short/ref/alpha/eio/simple-timing/m5stats.txt10
-rw-r--r--tests/quick/20.eio-short/ref/alpha/eio/simple-timing/stdout4
8 files changed, 16 insertions, 12 deletions
diff --git a/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/config.ini b/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/config.ini
index 8722c1b67..95cccfbf2 100644
--- a/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/config.ini
+++ b/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/config.ini
@@ -56,6 +56,7 @@ physmem=system.physmem
type=AtomicSimpleCPU
children=workload
clock=1
+cpu_id=0
defer_registration=false
function_trace=false
function_trace_start=0
diff --git a/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/config.out b/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/config.out
index 6ae80aecf..1138f2dbe 100644
--- a/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/config.out
+++ b/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/config.out
@@ -36,6 +36,7 @@ max_loads_all_threads=0
progress_interval=0
mem=system.physmem
system=system
+cpu_id=0
workload=system.cpu.workload
clock=1
defer_registration=false
diff --git a/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/m5stats.txt b/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/m5stats.txt
index 9fdf1d513..bbc6e55b5 100644
--- a/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/m5stats.txt
+++ b/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/m5stats.txt
@@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
-host_inst_rate 1393697 # Simulator instruction rate (inst/s)
+host_inst_rate 1432213 # Simulator instruction rate (inst/s)
host_mem_usage 147652 # Number of bytes of host memory used
-host_seconds 0.36 # Real time elapsed on the host
-host_tick_rate 1391995 # Simulator tick rate (ticks/s)
+host_seconds 0.35 # Real time elapsed on the host
+host_tick_rate 1430432 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 500000 # Number of instructions simulated
sim_seconds 0.000000 # Number of seconds simulated
diff --git a/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/stdout b/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/stdout
index 207a0046c..de2559c1c 100644
--- a/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/stdout
+++ b/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/stdout
@@ -7,8 +7,8 @@ The Regents of The University of Michigan
All Rights Reserved
-M5 compiled Oct 7 2006 11:12:49
-M5 started Sat Oct 7 11:13:17 2006
+M5 compiled Oct 8 2006 14:00:39
+M5 started Sun Oct 8 14:00:58 2006
M5 executing on zizzer.eecs.umich.edu
command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/quick/20.eio-short/alpha/eio/simple-atomic tests/run.py quick/20.eio-short/alpha/eio/simple-atomic
Exiting @ tick 499999 because a thread reached the max instruction count
diff --git a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/config.ini b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/config.ini
index f4bdc8171..72ea32994 100644
--- a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/config.ini
+++ b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/config.ini
@@ -56,6 +56,7 @@ physmem=system.physmem
type=TimingSimpleCPU
children=dcache icache l2cache toL2Bus workload
clock=1
+cpu_id=0
defer_registration=false
function_trace=false
function_trace_start=0
diff --git a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/config.out b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/config.out
index 71a6d33c4..14eb07351 100644
--- a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/config.out
+++ b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/config.out
@@ -75,6 +75,7 @@ max_loads_all_threads=0
progress_interval=0
mem=system.cpu.dcache
system=system
+cpu_id=0
workload=system.cpu.workload
clock=1
defer_registration=false
diff --git a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/m5stats.txt b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/m5stats.txt
index f8d2c4ea7..2a6a055ab 100644
--- a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/m5stats.txt
+++ b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/m5stats.txt
@@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
-host_inst_rate 618043 # Simulator instruction rate (inst/s)
-host_mem_usage 159232 # Number of bytes of host memory used
-host_seconds 0.81 # Real time elapsed on the host
-host_tick_rate 843177 # Simulator tick rate (ticks/s)
+host_inst_rate 598582 # Simulator instruction rate (inst/s)
+host_mem_usage 159216 # Number of bytes of host memory used
+host_seconds 0.84 # Real time elapsed on the host
+host_tick_rate 816632 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 500000 # Number of instructions simulated
sim_seconds 0.000001 # Number of seconds simulated
@@ -115,7 +115,7 @@ system.cpu.icache.no_allocate_misses 0 # Nu
system.cpu.icache.overall_accesses 500000 # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency 3 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 2 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
+system.cpu.icache.overall_avg_mshr_uncacheable_latency no value # average overall mshr uncacheable latency
system.cpu.icache.overall_hits 499597 # number of overall hits
system.cpu.icache.overall_miss_latency 1209 # number of overall miss cycles
system.cpu.icache.overall_miss_rate 0.000806 # miss rate for overall accesses
diff --git a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/stdout b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/stdout
index 409068a91..70c3f2454 100644
--- a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/stdout
+++ b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/stdout
@@ -7,8 +7,8 @@ The Regents of The University of Michigan
All Rights Reserved
-M5 compiled Oct 7 2006 12:38:12
-M5 started Sat Oct 7 12:38:52 2006
+M5 compiled Oct 8 2006 14:00:39
+M5 started Sun Oct 8 14:00:59 2006
M5 executing on zizzer.eecs.umich.edu
command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/quick/20.eio-short/alpha/eio/simple-timing tests/run.py quick/20.eio-short/alpha/eio/simple-timing
Exiting @ tick 682488 because a thread reached the max instruction count