diff options
Diffstat (limited to 'tests/quick/20.eio-short')
8 files changed, 92 insertions, 74 deletions
diff --git a/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/config.ini b/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/config.ini index a4b103732..95cccfbf2 100644 --- a/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/config.ini +++ b/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/config.ini @@ -56,6 +56,7 @@ physmem=system.physmem type=AtomicSimpleCPU children=workload clock=1 +cpu_id=0 defer_registration=false function_trace=false function_trace_start=0 @@ -64,6 +65,7 @@ max_insts_any_thread=500000 max_loads_all_threads=0 max_loads_any_thread=0 mem=system.physmem +progress_interval=0 simulate_stalls=false system=system width=1 @@ -92,6 +94,7 @@ port=system.membus.port[0] [trace] bufsize=0 +cycle=0 dump_on_exit=false file=cout flags= diff --git a/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/config.out b/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/config.out index 8f236d9cc..1138f2dbe 100644 --- a/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/config.out +++ b/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/config.out @@ -33,8 +33,10 @@ max_insts_any_thread=500000 max_insts_all_threads=0 max_loads_any_thread=0 max_loads_all_threads=0 +progress_interval=0 mem=system.physmem system=system +cpu_id=0 workload=system.cpu.workload clock=1 defer_registration=false @@ -46,6 +48,7 @@ simulate_stalls=false [trace] flags= start=0 +cycle=0 bufsize=0 file=cout dump_on_exit=false @@ -89,3 +92,6 @@ trace_system=client [debug] break_cycles= +[statsreset] +reset_cycle=0 + diff --git a/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/m5stats.txt b/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/m5stats.txt index 0132ecf1b..bbc6e55b5 100644 --- a/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/m5stats.txt +++ b/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/m5stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1397534 # Simulator instruction rate (inst/s) -host_mem_usage 147632 # Number of bytes of host memory used -host_seconds 0.36 # Real time elapsed on the host -host_tick_rate 1395943 # Simulator tick rate (ticks/s) +host_inst_rate 1432213 # Simulator instruction rate (inst/s) +host_mem_usage 147652 # Number of bytes of host memory used +host_seconds 0.35 # Real time elapsed on the host +host_tick_rate 1430432 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 500000 # Number of instructions simulated sim_seconds 0.000000 # Number of seconds simulated diff --git a/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/stdout b/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/stdout index d3edcdc0a..de2559c1c 100644 --- a/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/stdout +++ b/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/stdout @@ -7,8 +7,8 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Sep 5 2006 15:28:48 -M5 started Tue Sep 5 15:42:20 2006 +M5 compiled Oct 8 2006 14:00:39 +M5 started Sun Oct 8 14:00:58 2006 M5 executing on zizzer.eecs.umich.edu command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/quick/20.eio-short/alpha/eio/simple-atomic tests/run.py quick/20.eio-short/alpha/eio/simple-atomic Exiting @ tick 499999 because a thread reached the max instruction count diff --git a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/config.ini b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/config.ini index 27568ad50..72ea32994 100644 --- a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/config.ini +++ b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/config.ini @@ -56,6 +56,7 @@ physmem=system.physmem type=TimingSimpleCPU children=dcache icache l2cache toL2Bus workload clock=1 +cpu_id=0 defer_registration=false function_trace=false function_trace_start=0 @@ -64,6 +65,7 @@ max_insts_any_thread=500000 max_loads_all_threads=0 max_loads_any_thread=0 mem=system.cpu.dcache +progress_interval=0 system=system workload=system.cpu.workload dcache_port=system.cpu.dcache.cpu_side @@ -215,6 +217,7 @@ port=system.membus.port[0] [trace] bufsize=0 +cycle=0 dump_on_exit=false file=cout flags= diff --git a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/config.out b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/config.out index ba6875a7b..14eb07351 100644 --- a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/config.out +++ b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/config.out @@ -72,8 +72,10 @@ max_insts_any_thread=500000 max_insts_all_threads=0 max_loads_any_thread=0 max_loads_all_threads=0 +progress_interval=0 mem=system.cpu.dcache system=system +cpu_id=0 workload=system.cpu.workload clock=1 defer_registration=false @@ -167,6 +169,7 @@ hit_latency=1 [trace] flags= start=0 +cycle=0 bufsize=0 file=cout dump_on_exit=false @@ -210,3 +213,6 @@ trace_system=client [debug] break_cycles= +[statsreset] +reset_cycle=0 + diff --git a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/m5stats.txt b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/m5stats.txt index 6339e48b7..ebc70e1f0 100644 --- a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/m5stats.txt +++ b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/m5stats.txt @@ -1,67 +1,67 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 620120 # Simulator instruction rate (inst/s) -host_mem_usage 159196 # Number of bytes of host memory used +host_inst_rate 620088 # Simulator instruction rate (inst/s) +host_mem_usage 159272 # Number of bytes of host memory used host_seconds 0.81 # Real time elapsed on the host -host_tick_rate 845850 # Simulator tick rate (ticks/s) +host_tick_rate 845969 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 500000 # Number of instructions simulated sim_seconds 0.000001 # Number of seconds simulated -sim_ticks 682354 # Number of ticks simulated -system.cpu.dcache.ReadReq_accesses 124564 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 2.987952 # average ReadReq miss latency +sim_ticks 682488 # Number of ticks simulated +system.cpu.dcache.ReadReq_accesses 124435 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 3 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 124315 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 744 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.001999 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 249 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_miss_latency 496 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.001991 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 248 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_accesses 56744 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 1.256024 # average WriteReq miss latency +system.cpu.dcache.ReadReq_hits 124120 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 945 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.002531 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 315 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_miss_latency 630 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.002531 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_misses 315 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_accesses 56340 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_avg_miss_latency 3 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency 2 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 56412 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits 56201 # number of WriteReq hits system.cpu.dcache.WriteReq_miss_latency 417 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.005851 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 332 # number of WriteReq misses +system.cpu.dcache.WriteReq_miss_rate 0.002467 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 139 # number of WriteReq misses system.cpu.dcache.WriteReq_mshr_miss_latency 278 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.002450 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate 0.002467 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_misses 139 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 311.061962 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 397.182819 # Average number of references to valid blocks. system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 181308 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 1.998279 # average overall miss latency +system.cpu.dcache.demand_accesses 180775 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 3 # average overall miss latency system.cpu.dcache.demand_avg_mshr_miss_latency 2 # average overall mshr miss latency -system.cpu.dcache.demand_hits 180727 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 1161 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.003204 # miss rate for demand accesses -system.cpu.dcache.demand_misses 581 # number of demand (read+write) misses +system.cpu.dcache.demand_hits 180321 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 1362 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.002511 # miss rate for demand accesses +system.cpu.dcache.demand_misses 454 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 774 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.002134 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 387 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_miss_latency 908 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.002511 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 454 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.overall_accesses 181308 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 1.998279 # average overall miss latency +system.cpu.dcache.overall_accesses 180775 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 3 # average overall miss latency system.cpu.dcache.overall_avg_mshr_miss_latency 2 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 180727 # number of overall hits -system.cpu.dcache.overall_miss_latency 1161 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.003204 # miss rate for overall accesses -system.cpu.dcache.overall_misses 581 # number of overall misses +system.cpu.dcache.overall_hits 180321 # number of overall hits +system.cpu.dcache.overall_miss_latency 1362 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.002511 # miss rate for overall accesses +system.cpu.dcache.overall_misses 454 # number of overall misses system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 774 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.002134 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 387 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_miss_latency 908 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.002511 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 454 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -74,10 +74,10 @@ system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.sampled_refs 581 # Sample count of references to valid blocks. +system.cpu.dcache.sampled_refs 454 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 347.118131 # Cycle average of tags in use -system.cpu.dcache.total_refs 180727 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 291.968600 # Cycle average of tags in use +system.cpu.dcache.total_refs 180321 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 0 # number of writebacks system.cpu.icache.ReadReq_accesses 500000 # number of ReadReq accesses(hits+misses) @@ -138,20 +138,20 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.icache.replacements 0 # number of replacements system.cpu.icache.sampled_refs 403 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 268.434590 # Cycle average of tags in use +system.cpu.icache.tagsinuse 268.423238 # Cycle average of tags in use system.cpu.icache.total_refs 499597 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.l2cache.ReadReq_accesses 984 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 1.605691 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_accesses 857 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 2 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_miss_latency 1580 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency 1714 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_rate 1 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 984 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 790 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.802846 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 790 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_misses 857 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 857 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 1 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 857 # number of ReadReq MSHR misses system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked system.cpu.l2cache.avg_refs 0 # Average number of references to valid blocks. @@ -160,32 +160,32 @@ system.cpu.l2cache.blocked_no_targets 0 # nu system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 984 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 1.605691 # average overall miss latency +system.cpu.l2cache.demand_accesses 857 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 2 # average overall miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency 1 # average overall mshr miss latency system.cpu.l2cache.demand_hits 0 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 1580 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency 1714 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_rate 1 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 984 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses 857 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 790 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.802846 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 790 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_miss_latency 857 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 1 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 857 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.overall_accesses 984 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 1.605691 # average overall miss latency +system.cpu.l2cache.overall_accesses 857 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 2 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 1 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.l2cache.overall_hits 0 # number of overall hits -system.cpu.l2cache.overall_miss_latency 1580 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency 1714 # number of overall miss cycles system.cpu.l2cache.overall_miss_rate 1 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 984 # number of overall misses +system.cpu.l2cache.overall_misses 857 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 790 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.802846 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 790 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_miss_latency 857 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 1 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 857 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -198,9 +198,9 @@ system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.sampled_refs 984 # Sample count of references to valid blocks. +system.cpu.l2cache.sampled_refs 857 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 615.553879 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 560.393094 # Cycle average of tags in use system.cpu.l2cache.total_refs 0 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks diff --git a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/stdout b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/stdout index 158dcfe2b..076cf0a5a 100644 --- a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/stdout +++ b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/stdout @@ -7,8 +7,8 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Sep 5 2006 15:28:48 -M5 started Tue Sep 5 15:42:20 2006 +M5 compiled Oct 8 2006 20:54:51 +M5 started Sun Oct 8 20:55:29 2006 M5 executing on zizzer.eecs.umich.edu command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/quick/20.eio-short/alpha/eio/simple-timing tests/run.py quick/20.eio-short/alpha/eio/simple-timing -Exiting @ tick 682354 because a thread reached the max instruction count +Exiting @ tick 682488 because a thread reached the max instruction count |