diff options
Diffstat (limited to 'tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/stats.txt')
| -rw-r--r-- | tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/stats.txt | 42 |
1 files changed, 21 insertions, 21 deletions
diff --git a/tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/stats.txt b/tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/stats.txt index 9f848a332..f73f5744f 100644 --- a/tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/stats.txt +++ b/tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1366260 # Simulator instruction rate (inst/s) -host_mem_usage 1147168 # Number of bytes of host memory used -host_seconds 1.46 # Real time elapsed on the host -host_tick_rate 170760827 # Simulator tick rate (ticks/s) +host_inst_rate 5241411 # Simulator instruction rate (inst/s) +host_mem_usage 1126944 # Number of bytes of host memory used +host_seconds 0.38 # Real time elapsed on the host +host_tick_rate 654880397 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 2000004 # Number of instructions simulated sim_seconds 0.000250 # Number of seconds simulated @@ -38,8 +38,8 @@ system.cpu0.dcache.demand_mshr_misses 0 # nu system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.occ_%::0 0.540766 # Average percentage of cache occupancy system.cpu0.dcache.occ_blocks::0 276.872320 # Average occupied blocks per context +system.cpu0.dcache.occ_percent::0 0.540766 # Average percentage of cache occupancy system.cpu0.dcache.overall_accesses 180775 # number of overall (read+write) accesses system.cpu0.dcache.overall_avg_miss_latency 0 # average overall miss latency system.cpu0.dcache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency @@ -103,8 +103,8 @@ system.cpu0.icache.demand_mshr_misses 0 # nu system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.icache.occ_%::0 0.425950 # Average percentage of cache occupancy system.cpu0.icache.occ_blocks::0 218.086151 # Average occupied blocks per context +system.cpu0.icache.occ_percent::0 0.425950 # Average percentage of cache occupancy system.cpu0.icache.overall_accesses 500019 # number of overall (read+write) accesses system.cpu0.icache.overall_avg_miss_latency 0 # average overall miss latency system.cpu0.icache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency @@ -163,7 +163,7 @@ system.cpu0.num_int_register_writes 371542 # nu system.cpu0.num_load_insts 124443 # Number of load instructions system.cpu0.num_mem_refs 180793 # number of memory refs system.cpu0.num_store_insts 56350 # Number of store instructions -system.cpu0.workload.PROG:num_syscalls 18 # Number of system calls +system.cpu0.workload.num_syscalls 18 # Number of system calls system.cpu1.dcache.ReadReq_accesses 124435 # number of ReadReq accesses(hits+misses) system.cpu1.dcache.ReadReq_hits 124111 # number of ReadReq hits system.cpu1.dcache.ReadReq_miss_rate 0.002604 # miss rate for ReadReq accesses @@ -194,8 +194,8 @@ system.cpu1.dcache.demand_mshr_misses 0 # nu system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.dcache.occ_%::0 0.540766 # Average percentage of cache occupancy system.cpu1.dcache.occ_blocks::0 276.872320 # Average occupied blocks per context +system.cpu1.dcache.occ_percent::0 0.540766 # Average percentage of cache occupancy system.cpu1.dcache.overall_accesses 180775 # number of overall (read+write) accesses system.cpu1.dcache.overall_avg_miss_latency 0 # average overall miss latency system.cpu1.dcache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency @@ -259,8 +259,8 @@ system.cpu1.icache.demand_mshr_misses 0 # nu system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.icache.occ_%::0 0.425950 # Average percentage of cache occupancy system.cpu1.icache.occ_blocks::0 218.086151 # Average occupied blocks per context +system.cpu1.icache.occ_percent::0 0.425950 # Average percentage of cache occupancy system.cpu1.icache.overall_accesses 500019 # number of overall (read+write) accesses system.cpu1.icache.overall_avg_miss_latency 0 # average overall miss latency system.cpu1.icache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency @@ -319,7 +319,7 @@ system.cpu1.num_int_register_writes 371542 # nu system.cpu1.num_load_insts 124443 # Number of load instructions system.cpu1.num_mem_refs 180793 # number of memory refs system.cpu1.num_store_insts 56350 # Number of store instructions -system.cpu1.workload.PROG:num_syscalls 18 # Number of system calls +system.cpu1.workload.num_syscalls 18 # Number of system calls system.cpu2.dcache.ReadReq_accesses 124435 # number of ReadReq accesses(hits+misses) system.cpu2.dcache.ReadReq_hits 124111 # number of ReadReq hits system.cpu2.dcache.ReadReq_miss_rate 0.002604 # miss rate for ReadReq accesses @@ -350,8 +350,8 @@ system.cpu2.dcache.demand_mshr_misses 0 # nu system.cpu2.dcache.fast_writes 0 # number of fast writes performed system.cpu2.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu2.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu2.dcache.occ_%::0 0.540766 # Average percentage of cache occupancy system.cpu2.dcache.occ_blocks::0 276.872320 # Average occupied blocks per context +system.cpu2.dcache.occ_percent::0 0.540766 # Average percentage of cache occupancy system.cpu2.dcache.overall_accesses 180775 # number of overall (read+write) accesses system.cpu2.dcache.overall_avg_miss_latency 0 # average overall miss latency system.cpu2.dcache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency @@ -415,8 +415,8 @@ system.cpu2.icache.demand_mshr_misses 0 # nu system.cpu2.icache.fast_writes 0 # number of fast writes performed system.cpu2.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu2.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu2.icache.occ_%::0 0.425950 # Average percentage of cache occupancy system.cpu2.icache.occ_blocks::0 218.086151 # Average occupied blocks per context +system.cpu2.icache.occ_percent::0 0.425950 # Average percentage of cache occupancy system.cpu2.icache.overall_accesses 500019 # number of overall (read+write) accesses system.cpu2.icache.overall_avg_miss_latency 0 # average overall miss latency system.cpu2.icache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency @@ -475,7 +475,7 @@ system.cpu2.num_int_register_writes 371542 # nu system.cpu2.num_load_insts 124443 # Number of load instructions system.cpu2.num_mem_refs 180793 # number of memory refs system.cpu2.num_store_insts 56350 # Number of store instructions -system.cpu2.workload.PROG:num_syscalls 18 # Number of system calls +system.cpu2.workload.num_syscalls 18 # Number of system calls system.cpu3.dcache.ReadReq_accesses 124435 # number of ReadReq accesses(hits+misses) system.cpu3.dcache.ReadReq_hits 124111 # number of ReadReq hits system.cpu3.dcache.ReadReq_miss_rate 0.002604 # miss rate for ReadReq accesses @@ -506,8 +506,8 @@ system.cpu3.dcache.demand_mshr_misses 0 # nu system.cpu3.dcache.fast_writes 0 # number of fast writes performed system.cpu3.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu3.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu3.dcache.occ_%::0 0.540766 # Average percentage of cache occupancy system.cpu3.dcache.occ_blocks::0 276.872320 # Average occupied blocks per context +system.cpu3.dcache.occ_percent::0 0.540766 # Average percentage of cache occupancy system.cpu3.dcache.overall_accesses 180775 # number of overall (read+write) accesses system.cpu3.dcache.overall_avg_miss_latency 0 # average overall miss latency system.cpu3.dcache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency @@ -571,8 +571,8 @@ system.cpu3.icache.demand_mshr_misses 0 # nu system.cpu3.icache.fast_writes 0 # number of fast writes performed system.cpu3.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu3.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu3.icache.occ_%::0 0.425950 # Average percentage of cache occupancy system.cpu3.icache.occ_blocks::0 218.086151 # Average occupied blocks per context +system.cpu3.icache.occ_percent::0 0.425950 # Average percentage of cache occupancy system.cpu3.icache.overall_accesses 500019 # number of overall (read+write) accesses system.cpu3.icache.overall_avg_miss_latency 0 # average overall miss latency system.cpu3.icache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency @@ -631,7 +631,7 @@ system.cpu3.num_int_register_writes 371542 # nu system.cpu3.num_load_insts 124443 # Number of load instructions system.cpu3.num_mem_refs 180793 # number of memory refs system.cpu3.num_store_insts 56350 # Number of store instructions -system.cpu3.workload.PROG:num_syscalls 18 # Number of system calls +system.cpu3.workload.num_syscalls 18 # Number of system calls system.l2c.ReadExReq_accesses::0 139 # number of ReadExReq accesses(hits+misses) system.l2c.ReadExReq_accesses::1 139 # number of ReadExReq accesses(hits+misses) system.l2c.ReadExReq_accesses::2 139 # number of ReadExReq accesses(hits+misses) @@ -717,16 +717,16 @@ system.l2c.demand_mshr_misses 0 # nu system.l2c.fast_writes 0 # number of fast writes performed system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.occ_%::0 0.007421 # Average percentage of cache occupancy -system.l2c.occ_%::1 0.007421 # Average percentage of cache occupancy -system.l2c.occ_%::2 0.007421 # Average percentage of cache occupancy -system.l2c.occ_%::3 0.007421 # Average percentage of cache occupancy -system.l2c.occ_%::4 0.000267 # Average percentage of cache occupancy system.l2c.occ_blocks::0 486.328367 # Average occupied blocks per context system.l2c.occ_blocks::1 486.328367 # Average occupied blocks per context system.l2c.occ_blocks::2 486.328367 # Average occupied blocks per context system.l2c.occ_blocks::3 486.328367 # Average occupied blocks per context system.l2c.occ_blocks::4 17.466765 # Average occupied blocks per context +system.l2c.occ_percent::0 0.007421 # Average percentage of cache occupancy +system.l2c.occ_percent::1 0.007421 # Average percentage of cache occupancy +system.l2c.occ_percent::2 0.007421 # Average percentage of cache occupancy +system.l2c.occ_percent::3 0.007421 # Average percentage of cache occupancy +system.l2c.occ_percent::4 0.000267 # Average percentage of cache occupancy system.l2c.overall_accesses::0 926 # number of overall (read+write) accesses system.l2c.overall_accesses::1 926 # number of overall (read+write) accesses system.l2c.overall_accesses::2 926 # number of overall (read+write) accesses |