diff options
Diffstat (limited to 'tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/stats.txt')
| -rw-r--r-- | tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/stats.txt | 712 |
1 files changed, 712 insertions, 0 deletions
diff --git a/tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/stats.txt b/tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/stats.txt index e69de29bb..81431004c 100644 --- a/tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/stats.txt +++ b/tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/stats.txt @@ -0,0 +1,712 @@ + +---------- Begin Simulation Statistics ---------- +host_inst_rate 2770469 # Simulator instruction rate (inst/s) +host_mem_usage 1126824 # Number of bytes of host memory used +host_seconds 0.72 # Real time elapsed on the host +host_tick_rate 346193150 # Simulator tick rate (ticks/s) +sim_freq 1000000000000 # Frequency of simulated ticks +sim_insts 2000004 # Number of instructions simulated +sim_seconds 0.000250 # Number of seconds simulated +sim_ticks 250015500 # Number of ticks simulated +system.cpu0.dcache.ReadReq_accesses 124435 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_hits 124111 # number of ReadReq hits +system.cpu0.dcache.ReadReq_miss_rate 0.002604 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_misses 324 # number of ReadReq misses +system.cpu0.dcache.WriteReq_accesses 56340 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_hits 56201 # number of WriteReq hits +system.cpu0.dcache.WriteReq_miss_rate 0.002467 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_misses 139 # number of WriteReq misses +system.cpu0.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu0.dcache.avg_refs 389.442765 # Average number of references to valid blocks. +system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu0.dcache.cache_copies 0 # number of cache copies performed +system.cpu0.dcache.demand_accesses 180775 # number of demand (read+write) accesses +system.cpu0.dcache.demand_avg_miss_latency 0 # average overall miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency +system.cpu0.dcache.demand_hits 180312 # number of demand (read+write) hits +system.cpu0.dcache.demand_miss_latency 0 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_rate 0.002561 # miss rate for demand accesses +system.cpu0.dcache.demand_misses 463 # number of demand (read+write) misses +system.cpu0.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses +system.cpu0.dcache.fast_writes 0 # number of fast writes performed +system.cpu0.dcache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu0.dcache.occ_%::0 0.540766 # Average percentage of cache occupancy +system.cpu0.dcache.occ_blocks::0 276.872320 # Average occupied blocks per context +system.cpu0.dcache.overall_accesses 180775 # number of overall (read+write) accesses +system.cpu0.dcache.overall_avg_miss_latency 0 # average overall miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency +system.cpu0.dcache.overall_hits 180312 # number of overall hits +system.cpu0.dcache.overall_miss_latency 0 # number of overall miss cycles +system.cpu0.dcache.overall_miss_rate 0.002561 # miss rate for overall accesses +system.cpu0.dcache.overall_misses 463 # number of overall misses +system.cpu0.dcache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_misses 0 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu0.dcache.replacements 61 # number of replacements +system.cpu0.dcache.sampled_refs 463 # Sample count of references to valid blocks. +system.cpu0.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu0.dcache.tagsinuse 276.872320 # Cycle average of tags in use +system.cpu0.dcache.total_refs 180312 # Total number of references to valid blocks. +system.cpu0.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.writebacks 29 # number of writebacks +system.cpu0.dtb.data_accesses 180793 # DTB accesses +system.cpu0.dtb.data_acv 0 # DTB access violations +system.cpu0.dtb.data_hits 180775 # DTB hits +system.cpu0.dtb.data_misses 18 # DTB misses +system.cpu0.dtb.fetch_accesses 0 # ITB accesses +system.cpu0.dtb.fetch_acv 0 # ITB acv +system.cpu0.dtb.fetch_hits 0 # ITB hits +system.cpu0.dtb.fetch_misses 0 # ITB misses +system.cpu0.dtb.read_accesses 124443 # DTB read accesses +system.cpu0.dtb.read_acv 0 # DTB read access violations +system.cpu0.dtb.read_hits 124435 # DTB read hits +system.cpu0.dtb.read_misses 8 # DTB read misses +system.cpu0.dtb.write_accesses 56350 # DTB write accesses +system.cpu0.dtb.write_acv 0 # DTB write access violations +system.cpu0.dtb.write_hits 56340 # DTB write hits +system.cpu0.dtb.write_misses 10 # DTB write misses +system.cpu0.icache.ReadReq_accesses 500019 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_hits 499556 # number of ReadReq hits +system.cpu0.icache.ReadReq_miss_rate 0.000926 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_misses 463 # number of ReadReq misses +system.cpu0.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu0.icache.avg_refs 1078.954644 # Average number of references to valid blocks. +system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu0.icache.cache_copies 0 # number of cache copies performed +system.cpu0.icache.demand_accesses 500019 # number of demand (read+write) accesses +system.cpu0.icache.demand_avg_miss_latency 0 # average overall miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency +system.cpu0.icache.demand_hits 499556 # number of demand (read+write) hits +system.cpu0.icache.demand_miss_latency 0 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_rate 0.000926 # miss rate for demand accesses +system.cpu0.icache.demand_misses 463 # number of demand (read+write) misses +system.cpu0.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses +system.cpu0.icache.fast_writes 0 # number of fast writes performed +system.cpu0.icache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu0.icache.occ_%::0 0.425950 # Average percentage of cache occupancy +system.cpu0.icache.occ_blocks::0 218.086151 # Average occupied blocks per context +system.cpu0.icache.overall_accesses 500019 # number of overall (read+write) accesses +system.cpu0.icache.overall_avg_miss_latency 0 # average overall miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency +system.cpu0.icache.overall_hits 499556 # number of overall hits +system.cpu0.icache.overall_miss_latency 0 # number of overall miss cycles +system.cpu0.icache.overall_miss_rate 0.000926 # miss rate for overall accesses +system.cpu0.icache.overall_misses 463 # number of overall misses +system.cpu0.icache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_misses 0 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu0.icache.replacements 152 # number of replacements +system.cpu0.icache.sampled_refs 463 # Sample count of references to valid blocks. +system.cpu0.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu0.icache.tagsinuse 218.086151 # Cycle average of tags in use +system.cpu0.icache.total_refs 499556 # Total number of references to valid blocks. +system.cpu0.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu0.icache.writebacks 0 # number of writebacks +system.cpu0.idle_fraction 0 # Percentage of idle cycles +system.cpu0.itb.data_accesses 0 # DTB accesses +system.cpu0.itb.data_acv 0 # DTB access violations +system.cpu0.itb.data_hits 0 # DTB hits +system.cpu0.itb.data_misses 0 # DTB misses +system.cpu0.itb.fetch_accesses 500032 # ITB accesses +system.cpu0.itb.fetch_acv 0 # ITB acv +system.cpu0.itb.fetch_hits 500019 # ITB hits +system.cpu0.itb.fetch_misses 13 # ITB misses +system.cpu0.itb.read_accesses 0 # DTB read accesses +system.cpu0.itb.read_acv 0 # DTB read access violations +system.cpu0.itb.read_hits 0 # DTB read hits +system.cpu0.itb.read_misses 0 # DTB read misses +system.cpu0.itb.write_accesses 0 # DTB write accesses +system.cpu0.itb.write_acv 0 # DTB write access violations +system.cpu0.itb.write_hits 0 # DTB write hits +system.cpu0.itb.write_misses 0 # DTB write misses +system.cpu0.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu0.numCycles 500032 # number of cpu cycles simulated +system.cpu0.num_insts 500001 # Number of instructions executed +system.cpu0.num_refs 180793 # Number of memory references +system.cpu0.workload.PROG:num_syscalls 18 # Number of system calls +system.cpu1.dcache.ReadReq_accesses 124435 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_hits 124111 # number of ReadReq hits +system.cpu1.dcache.ReadReq_miss_rate 0.002604 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_misses 324 # number of ReadReq misses +system.cpu1.dcache.WriteReq_accesses 56340 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_hits 56201 # number of WriteReq hits +system.cpu1.dcache.WriteReq_miss_rate 0.002467 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_misses 139 # number of WriteReq misses +system.cpu1.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu1.dcache.avg_refs 389.442765 # Average number of references to valid blocks. +system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu1.dcache.cache_copies 0 # number of cache copies performed +system.cpu1.dcache.demand_accesses 180775 # number of demand (read+write) accesses +system.cpu1.dcache.demand_avg_miss_latency 0 # average overall miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency +system.cpu1.dcache.demand_hits 180312 # number of demand (read+write) hits +system.cpu1.dcache.demand_miss_latency 0 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_rate 0.002561 # miss rate for demand accesses +system.cpu1.dcache.demand_misses 463 # number of demand (read+write) misses +system.cpu1.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses +system.cpu1.dcache.fast_writes 0 # number of fast writes performed +system.cpu1.dcache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu1.dcache.occ_%::0 0.540766 # Average percentage of cache occupancy +system.cpu1.dcache.occ_blocks::0 276.872320 # Average occupied blocks per context +system.cpu1.dcache.overall_accesses 180775 # number of overall (read+write) accesses +system.cpu1.dcache.overall_avg_miss_latency 0 # average overall miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency +system.cpu1.dcache.overall_hits 180312 # number of overall hits +system.cpu1.dcache.overall_miss_latency 0 # number of overall miss cycles +system.cpu1.dcache.overall_miss_rate 0.002561 # miss rate for overall accesses +system.cpu1.dcache.overall_misses 463 # number of overall misses +system.cpu1.dcache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_misses 0 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu1.dcache.replacements 61 # number of replacements +system.cpu1.dcache.sampled_refs 463 # Sample count of references to valid blocks. +system.cpu1.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu1.dcache.tagsinuse 276.872320 # Cycle average of tags in use +system.cpu1.dcache.total_refs 180312 # Total number of references to valid blocks. +system.cpu1.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.writebacks 29 # number of writebacks +system.cpu1.dtb.data_accesses 180793 # DTB accesses +system.cpu1.dtb.data_acv 0 # DTB access violations +system.cpu1.dtb.data_hits 180775 # DTB hits +system.cpu1.dtb.data_misses 18 # DTB misses +system.cpu1.dtb.fetch_accesses 0 # ITB accesses +system.cpu1.dtb.fetch_acv 0 # ITB acv +system.cpu1.dtb.fetch_hits 0 # ITB hits +system.cpu1.dtb.fetch_misses 0 # ITB misses +system.cpu1.dtb.read_accesses 124443 # DTB read accesses +system.cpu1.dtb.read_acv 0 # DTB read access violations +system.cpu1.dtb.read_hits 124435 # DTB read hits +system.cpu1.dtb.read_misses 8 # DTB read misses +system.cpu1.dtb.write_accesses 56350 # DTB write accesses +system.cpu1.dtb.write_acv 0 # DTB write access violations +system.cpu1.dtb.write_hits 56340 # DTB write hits +system.cpu1.dtb.write_misses 10 # DTB write misses +system.cpu1.icache.ReadReq_accesses 500019 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_hits 499556 # number of ReadReq hits +system.cpu1.icache.ReadReq_miss_rate 0.000926 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_misses 463 # number of ReadReq misses +system.cpu1.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu1.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu1.icache.avg_refs 1078.954644 # Average number of references to valid blocks. +system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu1.icache.cache_copies 0 # number of cache copies performed +system.cpu1.icache.demand_accesses 500019 # number of demand (read+write) accesses +system.cpu1.icache.demand_avg_miss_latency 0 # average overall miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency +system.cpu1.icache.demand_hits 499556 # number of demand (read+write) hits +system.cpu1.icache.demand_miss_latency 0 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_rate 0.000926 # miss rate for demand accesses +system.cpu1.icache.demand_misses 463 # number of demand (read+write) misses +system.cpu1.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu1.icache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses +system.cpu1.icache.fast_writes 0 # number of fast writes performed +system.cpu1.icache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu1.icache.occ_%::0 0.425950 # Average percentage of cache occupancy +system.cpu1.icache.occ_blocks::0 218.086151 # Average occupied blocks per context +system.cpu1.icache.overall_accesses 500019 # number of overall (read+write) accesses +system.cpu1.icache.overall_avg_miss_latency 0 # average overall miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency +system.cpu1.icache.overall_hits 499556 # number of overall hits +system.cpu1.icache.overall_miss_latency 0 # number of overall miss cycles +system.cpu1.icache.overall_miss_rate 0.000926 # miss rate for overall accesses +system.cpu1.icache.overall_misses 463 # number of overall misses +system.cpu1.icache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu1.icache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_misses 0 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu1.icache.replacements 152 # number of replacements +system.cpu1.icache.sampled_refs 463 # Sample count of references to valid blocks. +system.cpu1.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu1.icache.tagsinuse 218.086151 # Cycle average of tags in use +system.cpu1.icache.total_refs 499556 # Total number of references to valid blocks. +system.cpu1.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu1.icache.writebacks 0 # number of writebacks +system.cpu1.idle_fraction 0 # Percentage of idle cycles +system.cpu1.itb.data_accesses 0 # DTB accesses +system.cpu1.itb.data_acv 0 # DTB access violations +system.cpu1.itb.data_hits 0 # DTB hits +system.cpu1.itb.data_misses 0 # DTB misses +system.cpu1.itb.fetch_accesses 500032 # ITB accesses +system.cpu1.itb.fetch_acv 0 # ITB acv +system.cpu1.itb.fetch_hits 500019 # ITB hits +system.cpu1.itb.fetch_misses 13 # ITB misses +system.cpu1.itb.read_accesses 0 # DTB read accesses +system.cpu1.itb.read_acv 0 # DTB read access violations +system.cpu1.itb.read_hits 0 # DTB read hits +system.cpu1.itb.read_misses 0 # DTB read misses +system.cpu1.itb.write_accesses 0 # DTB write accesses +system.cpu1.itb.write_acv 0 # DTB write access violations +system.cpu1.itb.write_hits 0 # DTB write hits +system.cpu1.itb.write_misses 0 # DTB write misses +system.cpu1.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu1.numCycles 500032 # number of cpu cycles simulated +system.cpu1.num_insts 500001 # Number of instructions executed +system.cpu1.num_refs 180793 # Number of memory references +system.cpu1.workload.PROG:num_syscalls 18 # Number of system calls +system.cpu2.dcache.ReadReq_accesses 124435 # number of ReadReq accesses(hits+misses) +system.cpu2.dcache.ReadReq_hits 124111 # number of ReadReq hits +system.cpu2.dcache.ReadReq_miss_rate 0.002604 # miss rate for ReadReq accesses +system.cpu2.dcache.ReadReq_misses 324 # number of ReadReq misses +system.cpu2.dcache.WriteReq_accesses 56340 # number of WriteReq accesses(hits+misses) +system.cpu2.dcache.WriteReq_hits 56201 # number of WriteReq hits +system.cpu2.dcache.WriteReq_miss_rate 0.002467 # miss rate for WriteReq accesses +system.cpu2.dcache.WriteReq_misses 139 # number of WriteReq misses +system.cpu2.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu2.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu2.dcache.avg_refs 389.442765 # Average number of references to valid blocks. +system.cpu2.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu2.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu2.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu2.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu2.dcache.cache_copies 0 # number of cache copies performed +system.cpu2.dcache.demand_accesses 180775 # number of demand (read+write) accesses +system.cpu2.dcache.demand_avg_miss_latency 0 # average overall miss latency +system.cpu2.dcache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency +system.cpu2.dcache.demand_hits 180312 # number of demand (read+write) hits +system.cpu2.dcache.demand_miss_latency 0 # number of demand (read+write) miss cycles +system.cpu2.dcache.demand_miss_rate 0.002561 # miss rate for demand accesses +system.cpu2.dcache.demand_misses 463 # number of demand (read+write) misses +system.cpu2.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu2.dcache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles +system.cpu2.dcache.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses +system.cpu2.dcache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses +system.cpu2.dcache.fast_writes 0 # number of fast writes performed +system.cpu2.dcache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu2.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu2.dcache.occ_%::0 0.540766 # Average percentage of cache occupancy +system.cpu2.dcache.occ_blocks::0 276.872320 # Average occupied blocks per context +system.cpu2.dcache.overall_accesses 180775 # number of overall (read+write) accesses +system.cpu2.dcache.overall_avg_miss_latency 0 # average overall miss latency +system.cpu2.dcache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency +system.cpu2.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency +system.cpu2.dcache.overall_hits 180312 # number of overall hits +system.cpu2.dcache.overall_miss_latency 0 # number of overall miss cycles +system.cpu2.dcache.overall_miss_rate 0.002561 # miss rate for overall accesses +system.cpu2.dcache.overall_misses 463 # number of overall misses +system.cpu2.dcache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu2.dcache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles +system.cpu2.dcache.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses +system.cpu2.dcache.overall_mshr_misses 0 # number of overall MSHR misses +system.cpu2.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu2.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu2.dcache.replacements 61 # number of replacements +system.cpu2.dcache.sampled_refs 463 # Sample count of references to valid blocks. +system.cpu2.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu2.dcache.tagsinuse 276.872320 # Cycle average of tags in use +system.cpu2.dcache.total_refs 180312 # Total number of references to valid blocks. +system.cpu2.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu2.dcache.writebacks 29 # number of writebacks +system.cpu2.dtb.data_accesses 180793 # DTB accesses +system.cpu2.dtb.data_acv 0 # DTB access violations +system.cpu2.dtb.data_hits 180775 # DTB hits +system.cpu2.dtb.data_misses 18 # DTB misses +system.cpu2.dtb.fetch_accesses 0 # ITB accesses +system.cpu2.dtb.fetch_acv 0 # ITB acv +system.cpu2.dtb.fetch_hits 0 # ITB hits +system.cpu2.dtb.fetch_misses 0 # ITB misses +system.cpu2.dtb.read_accesses 124443 # DTB read accesses +system.cpu2.dtb.read_acv 0 # DTB read access violations +system.cpu2.dtb.read_hits 124435 # DTB read hits +system.cpu2.dtb.read_misses 8 # DTB read misses +system.cpu2.dtb.write_accesses 56350 # DTB write accesses +system.cpu2.dtb.write_acv 0 # DTB write access violations +system.cpu2.dtb.write_hits 56340 # DTB write hits +system.cpu2.dtb.write_misses 10 # DTB write misses +system.cpu2.icache.ReadReq_accesses 500019 # number of ReadReq accesses(hits+misses) +system.cpu2.icache.ReadReq_hits 499556 # number of ReadReq hits +system.cpu2.icache.ReadReq_miss_rate 0.000926 # miss rate for ReadReq accesses +system.cpu2.icache.ReadReq_misses 463 # number of ReadReq misses +system.cpu2.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu2.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu2.icache.avg_refs 1078.954644 # Average number of references to valid blocks. +system.cpu2.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu2.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu2.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu2.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu2.icache.cache_copies 0 # number of cache copies performed +system.cpu2.icache.demand_accesses 500019 # number of demand (read+write) accesses +system.cpu2.icache.demand_avg_miss_latency 0 # average overall miss latency +system.cpu2.icache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency +system.cpu2.icache.demand_hits 499556 # number of demand (read+write) hits +system.cpu2.icache.demand_miss_latency 0 # number of demand (read+write) miss cycles +system.cpu2.icache.demand_miss_rate 0.000926 # miss rate for demand accesses +system.cpu2.icache.demand_misses 463 # number of demand (read+write) misses +system.cpu2.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu2.icache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles +system.cpu2.icache.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses +system.cpu2.icache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses +system.cpu2.icache.fast_writes 0 # number of fast writes performed +system.cpu2.icache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu2.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu2.icache.occ_%::0 0.425950 # Average percentage of cache occupancy +system.cpu2.icache.occ_blocks::0 218.086151 # Average occupied blocks per context +system.cpu2.icache.overall_accesses 500019 # number of overall (read+write) accesses +system.cpu2.icache.overall_avg_miss_latency 0 # average overall miss latency +system.cpu2.icache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency +system.cpu2.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency +system.cpu2.icache.overall_hits 499556 # number of overall hits +system.cpu2.icache.overall_miss_latency 0 # number of overall miss cycles +system.cpu2.icache.overall_miss_rate 0.000926 # miss rate for overall accesses +system.cpu2.icache.overall_misses 463 # number of overall misses +system.cpu2.icache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu2.icache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles +system.cpu2.icache.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses +system.cpu2.icache.overall_mshr_misses 0 # number of overall MSHR misses +system.cpu2.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu2.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu2.icache.replacements 152 # number of replacements +system.cpu2.icache.sampled_refs 463 # Sample count of references to valid blocks. +system.cpu2.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu2.icache.tagsinuse 218.086151 # Cycle average of tags in use +system.cpu2.icache.total_refs 499556 # Total number of references to valid blocks. +system.cpu2.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu2.icache.writebacks 0 # number of writebacks +system.cpu2.idle_fraction 0 # Percentage of idle cycles +system.cpu2.itb.data_accesses 0 # DTB accesses +system.cpu2.itb.data_acv 0 # DTB access violations +system.cpu2.itb.data_hits 0 # DTB hits +system.cpu2.itb.data_misses 0 # DTB misses +system.cpu2.itb.fetch_accesses 500032 # ITB accesses +system.cpu2.itb.fetch_acv 0 # ITB acv +system.cpu2.itb.fetch_hits 500019 # ITB hits +system.cpu2.itb.fetch_misses 13 # ITB misses +system.cpu2.itb.read_accesses 0 # DTB read accesses +system.cpu2.itb.read_acv 0 # DTB read access violations +system.cpu2.itb.read_hits 0 # DTB read hits +system.cpu2.itb.read_misses 0 # DTB read misses +system.cpu2.itb.write_accesses 0 # DTB write accesses +system.cpu2.itb.write_acv 0 # DTB write access violations +system.cpu2.itb.write_hits 0 # DTB write hits +system.cpu2.itb.write_misses 0 # DTB write misses +system.cpu2.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu2.numCycles 500032 # number of cpu cycles simulated +system.cpu2.num_insts 500001 # Number of instructions executed +system.cpu2.num_refs 180793 # Number of memory references +system.cpu2.workload.PROG:num_syscalls 18 # Number of system calls +system.cpu3.dcache.ReadReq_accesses 124435 # number of ReadReq accesses(hits+misses) +system.cpu3.dcache.ReadReq_hits 124111 # number of ReadReq hits +system.cpu3.dcache.ReadReq_miss_rate 0.002604 # miss rate for ReadReq accesses +system.cpu3.dcache.ReadReq_misses 324 # number of ReadReq misses +system.cpu3.dcache.WriteReq_accesses 56340 # number of WriteReq accesses(hits+misses) +system.cpu3.dcache.WriteReq_hits 56201 # number of WriteReq hits +system.cpu3.dcache.WriteReq_miss_rate 0.002467 # miss rate for WriteReq accesses +system.cpu3.dcache.WriteReq_misses 139 # number of WriteReq misses +system.cpu3.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu3.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu3.dcache.avg_refs 389.442765 # Average number of references to valid blocks. +system.cpu3.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu3.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu3.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu3.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu3.dcache.cache_copies 0 # number of cache copies performed +system.cpu3.dcache.demand_accesses 180775 # number of demand (read+write) accesses +system.cpu3.dcache.demand_avg_miss_latency 0 # average overall miss latency +system.cpu3.dcache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency +system.cpu3.dcache.demand_hits 180312 # number of demand (read+write) hits +system.cpu3.dcache.demand_miss_latency 0 # number of demand (read+write) miss cycles +system.cpu3.dcache.demand_miss_rate 0.002561 # miss rate for demand accesses +system.cpu3.dcache.demand_misses 463 # number of demand (read+write) misses +system.cpu3.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu3.dcache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles +system.cpu3.dcache.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses +system.cpu3.dcache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses +system.cpu3.dcache.fast_writes 0 # number of fast writes performed +system.cpu3.dcache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu3.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu3.dcache.occ_%::0 0.540766 # Average percentage of cache occupancy +system.cpu3.dcache.occ_blocks::0 276.872320 # Average occupied blocks per context +system.cpu3.dcache.overall_accesses 180775 # number of overall (read+write) accesses +system.cpu3.dcache.overall_avg_miss_latency 0 # average overall miss latency +system.cpu3.dcache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency +system.cpu3.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency +system.cpu3.dcache.overall_hits 180312 # number of overall hits +system.cpu3.dcache.overall_miss_latency 0 # number of overall miss cycles +system.cpu3.dcache.overall_miss_rate 0.002561 # miss rate for overall accesses +system.cpu3.dcache.overall_misses 463 # number of overall misses +system.cpu3.dcache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu3.dcache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles +system.cpu3.dcache.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses +system.cpu3.dcache.overall_mshr_misses 0 # number of overall MSHR misses +system.cpu3.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu3.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu3.dcache.replacements 61 # number of replacements +system.cpu3.dcache.sampled_refs 463 # Sample count of references to valid blocks. +system.cpu3.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu3.dcache.tagsinuse 276.872320 # Cycle average of tags in use +system.cpu3.dcache.total_refs 180312 # Total number of references to valid blocks. +system.cpu3.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu3.dcache.writebacks 29 # number of writebacks +system.cpu3.dtb.data_accesses 180793 # DTB accesses +system.cpu3.dtb.data_acv 0 # DTB access violations +system.cpu3.dtb.data_hits 180775 # DTB hits +system.cpu3.dtb.data_misses 18 # DTB misses +system.cpu3.dtb.fetch_accesses 0 # ITB accesses +system.cpu3.dtb.fetch_acv 0 # ITB acv +system.cpu3.dtb.fetch_hits 0 # ITB hits +system.cpu3.dtb.fetch_misses 0 # ITB misses +system.cpu3.dtb.read_accesses 124443 # DTB read accesses +system.cpu3.dtb.read_acv 0 # DTB read access violations +system.cpu3.dtb.read_hits 124435 # DTB read hits +system.cpu3.dtb.read_misses 8 # DTB read misses +system.cpu3.dtb.write_accesses 56350 # DTB write accesses +system.cpu3.dtb.write_acv 0 # DTB write access violations +system.cpu3.dtb.write_hits 56340 # DTB write hits +system.cpu3.dtb.write_misses 10 # DTB write misses +system.cpu3.icache.ReadReq_accesses 500019 # number of ReadReq accesses(hits+misses) +system.cpu3.icache.ReadReq_hits 499556 # number of ReadReq hits +system.cpu3.icache.ReadReq_miss_rate 0.000926 # miss rate for ReadReq accesses +system.cpu3.icache.ReadReq_misses 463 # number of ReadReq misses +system.cpu3.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu3.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu3.icache.avg_refs 1078.954644 # Average number of references to valid blocks. +system.cpu3.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu3.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu3.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu3.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu3.icache.cache_copies 0 # number of cache copies performed +system.cpu3.icache.demand_accesses 500019 # number of demand (read+write) accesses +system.cpu3.icache.demand_avg_miss_latency 0 # average overall miss latency +system.cpu3.icache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency +system.cpu3.icache.demand_hits 499556 # number of demand (read+write) hits +system.cpu3.icache.demand_miss_latency 0 # number of demand (read+write) miss cycles +system.cpu3.icache.demand_miss_rate 0.000926 # miss rate for demand accesses +system.cpu3.icache.demand_misses 463 # number of demand (read+write) misses +system.cpu3.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu3.icache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles +system.cpu3.icache.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses +system.cpu3.icache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses +system.cpu3.icache.fast_writes 0 # number of fast writes performed +system.cpu3.icache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu3.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu3.icache.occ_%::0 0.425950 # Average percentage of cache occupancy +system.cpu3.icache.occ_blocks::0 218.086151 # Average occupied blocks per context +system.cpu3.icache.overall_accesses 500019 # number of overall (read+write) accesses +system.cpu3.icache.overall_avg_miss_latency 0 # average overall miss latency +system.cpu3.icache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency +system.cpu3.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency +system.cpu3.icache.overall_hits 499556 # number of overall hits +system.cpu3.icache.overall_miss_latency 0 # number of overall miss cycles +system.cpu3.icache.overall_miss_rate 0.000926 # miss rate for overall accesses +system.cpu3.icache.overall_misses 463 # number of overall misses +system.cpu3.icache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu3.icache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles +system.cpu3.icache.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses +system.cpu3.icache.overall_mshr_misses 0 # number of overall MSHR misses +system.cpu3.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu3.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu3.icache.replacements 152 # number of replacements +system.cpu3.icache.sampled_refs 463 # Sample count of references to valid blocks. +system.cpu3.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu3.icache.tagsinuse 218.086151 # Cycle average of tags in use +system.cpu3.icache.total_refs 499556 # Total number of references to valid blocks. +system.cpu3.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu3.icache.writebacks 0 # number of writebacks +system.cpu3.idle_fraction 0 # Percentage of idle cycles +system.cpu3.itb.data_accesses 0 # DTB accesses +system.cpu3.itb.data_acv 0 # DTB access violations +system.cpu3.itb.data_hits 0 # DTB hits +system.cpu3.itb.data_misses 0 # DTB misses +system.cpu3.itb.fetch_accesses 500032 # ITB accesses +system.cpu3.itb.fetch_acv 0 # ITB acv +system.cpu3.itb.fetch_hits 500019 # ITB hits +system.cpu3.itb.fetch_misses 13 # ITB misses +system.cpu3.itb.read_accesses 0 # DTB read accesses +system.cpu3.itb.read_acv 0 # DTB read access violations +system.cpu3.itb.read_hits 0 # DTB read hits +system.cpu3.itb.read_misses 0 # DTB read misses +system.cpu3.itb.write_accesses 0 # DTB write accesses +system.cpu3.itb.write_acv 0 # DTB write access violations +system.cpu3.itb.write_hits 0 # DTB write hits +system.cpu3.itb.write_misses 0 # DTB write misses +system.cpu3.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu3.numCycles 500032 # number of cpu cycles simulated +system.cpu3.num_insts 500001 # Number of instructions executed +system.cpu3.num_refs 180793 # Number of memory references +system.cpu3.workload.PROG:num_syscalls 18 # Number of system calls +system.l2c.ReadExReq_accesses::0 139 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::1 139 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::2 139 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::3 139 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 556 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_miss_rate::0 1 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::1 1 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::2 1 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::3 1 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 4 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_misses::0 139 # number of ReadExReq misses +system.l2c.ReadExReq_misses::1 139 # number of ReadExReq misses +system.l2c.ReadExReq_misses::2 139 # number of ReadExReq misses +system.l2c.ReadExReq_misses::3 139 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 556 # number of ReadExReq misses +system.l2c.ReadReq_accesses::0 787 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::1 787 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::2 787 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::3 787 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 3148 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_hits::0 69 # number of ReadReq hits +system.l2c.ReadReq_hits::1 69 # number of ReadReq hits +system.l2c.ReadReq_hits::2 69 # number of ReadReq hits +system.l2c.ReadReq_hits::3 69 # number of ReadReq hits +system.l2c.ReadReq_hits::total 276 # number of ReadReq hits +system.l2c.ReadReq_miss_rate::0 0.912325 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::1 0.912325 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::2 0.912325 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::3 0.912325 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 3.649301 # miss rate for ReadReq accesses +system.l2c.ReadReq_misses::0 718 # number of ReadReq misses +system.l2c.ReadReq_misses::1 718 # number of ReadReq misses +system.l2c.ReadReq_misses::2 718 # number of ReadReq misses +system.l2c.ReadReq_misses::3 718 # number of ReadReq misses +system.l2c.ReadReq_misses::total 2872 # number of ReadReq misses +system.l2c.Writeback_accesses::0 116 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 116 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_hits::0 116 # number of Writeback hits +system.l2c.Writeback_hits::total 116 # number of Writeback hits +system.l2c.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.l2c.avg_refs 0.113233 # Average number of references to valid blocks. +system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked +system.l2c.blocked::no_targets 0 # number of cycles access was blocked +system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.l2c.cache_copies 0 # number of cache copies performed +system.l2c.demand_accesses::0 926 # number of demand (read+write) accesses +system.l2c.demand_accesses::1 926 # number of demand (read+write) accesses +system.l2c.demand_accesses::2 926 # number of demand (read+write) accesses +system.l2c.demand_accesses::3 926 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 3704 # number of demand (read+write) accesses +system.l2c.demand_avg_miss_latency::0 0 # average overall miss latency +system.l2c.demand_avg_miss_latency::1 0 # average overall miss latency +system.l2c.demand_avg_miss_latency::2 0 # average overall miss latency +system.l2c.demand_avg_miss_latency::3 0 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 0 # average overall miss latency +system.l2c.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency +system.l2c.demand_hits::0 69 # number of demand (read+write) hits +system.l2c.demand_hits::1 69 # number of demand (read+write) hits +system.l2c.demand_hits::2 69 # number of demand (read+write) hits +system.l2c.demand_hits::3 69 # number of demand (read+write) hits +system.l2c.demand_hits::total 276 # number of demand (read+write) hits +system.l2c.demand_miss_latency 0 # number of demand (read+write) miss cycles +system.l2c.demand_miss_rate::0 0.925486 # miss rate for demand accesses +system.l2c.demand_miss_rate::1 0.925486 # miss rate for demand accesses +system.l2c.demand_miss_rate::2 0.925486 # miss rate for demand accesses +system.l2c.demand_miss_rate::3 0.925486 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 3.701944 # miss rate for demand accesses +system.l2c.demand_misses::0 857 # number of demand (read+write) misses +system.l2c.demand_misses::1 857 # number of demand (read+write) misses +system.l2c.demand_misses::2 857 # number of demand (read+write) misses +system.l2c.demand_misses::3 857 # number of demand (read+write) misses +system.l2c.demand_misses::total 3428 # number of demand (read+write) misses +system.l2c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_rate::0 0 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::1 0 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::2 0 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::3 0 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0 # mshr miss rate for demand accesses +system.l2c.demand_mshr_misses 0 # number of demand (read+write) MSHR misses +system.l2c.fast_writes 0 # number of fast writes performed +system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated +system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate +system.l2c.occ_%::0 0.007421 # Average percentage of cache occupancy +system.l2c.occ_%::1 0.007421 # Average percentage of cache occupancy +system.l2c.occ_%::2 0.007421 # Average percentage of cache occupancy +system.l2c.occ_%::3 0.007421 # Average percentage of cache occupancy +system.l2c.occ_%::4 0.000267 # Average percentage of cache occupancy +system.l2c.occ_blocks::0 486.328367 # Average occupied blocks per context +system.l2c.occ_blocks::1 486.328367 # Average occupied blocks per context +system.l2c.occ_blocks::2 486.328367 # Average occupied blocks per context +system.l2c.occ_blocks::3 486.328367 # Average occupied blocks per context +system.l2c.occ_blocks::4 17.466765 # Average occupied blocks per context +system.l2c.overall_accesses::0 926 # number of overall (read+write) accesses +system.l2c.overall_accesses::1 926 # number of overall (read+write) accesses +system.l2c.overall_accesses::2 926 # number of overall (read+write) accesses +system.l2c.overall_accesses::3 926 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 3704 # number of overall (read+write) accesses +system.l2c.overall_avg_miss_latency::0 0 # average overall miss latency +system.l2c.overall_avg_miss_latency::1 0 # average overall miss latency +system.l2c.overall_avg_miss_latency::2 0 # average overall miss latency +system.l2c.overall_avg_miss_latency::3 0 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 0 # average overall miss latency +system.l2c.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency +system.l2c.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency +system.l2c.overall_hits::0 69 # number of overall hits +system.l2c.overall_hits::1 69 # number of overall hits +system.l2c.overall_hits::2 69 # number of overall hits +system.l2c.overall_hits::3 69 # number of overall hits +system.l2c.overall_hits::total 276 # number of overall hits +system.l2c.overall_miss_latency 0 # number of overall miss cycles +system.l2c.overall_miss_rate::0 0.925486 # miss rate for overall accesses +system.l2c.overall_miss_rate::1 0.925486 # miss rate for overall accesses +system.l2c.overall_miss_rate::2 0.925486 # miss rate for overall accesses +system.l2c.overall_miss_rate::3 0.925486 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 3.701944 # miss rate for overall accesses +system.l2c.overall_misses::0 857 # number of overall misses +system.l2c.overall_misses::1 857 # number of overall misses +system.l2c.overall_misses::2 857 # number of overall misses +system.l2c.overall_misses::3 857 # number of overall misses +system.l2c.overall_misses::total 3428 # number of overall misses +system.l2c.overall_mshr_hits 0 # number of overall MSHR hits +system.l2c.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_rate::0 0 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::1 0 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::2 0 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::3 0 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0 # mshr miss rate for overall accesses +system.l2c.overall_mshr_misses 0 # number of overall MSHR misses +system.l2c.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.l2c.replacements 0 # number of replacements +system.l2c.sampled_refs 2932 # Sample count of references to valid blocks. +system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.l2c.tagsinuse 1962.780232 # Cycle average of tags in use +system.l2c.total_refs 332 # Total number of references to valid blocks. +system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.l2c.writebacks 0 # number of writebacks + +---------- End Simulation Statistics ---------- |