diff options
Diffstat (limited to 'tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp')
4 files changed, 161 insertions, 49 deletions
diff --git a/tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/config.ini b/tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/config.ini index b801b4825..a6af5d880 100644 --- a/tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/config.ini +++ b/tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/config.ini @@ -48,7 +48,7 @@ hash_delay=1 latency=1000 max_miss_count=0 mshrs=4 -prefetch_cache_check_push=true +num_cpus=1 prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 @@ -83,7 +83,7 @@ hash_delay=1 latency=1000 max_miss_count=0 mshrs=4 -prefetch_cache_check_push=true +num_cpus=1 prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 @@ -115,7 +115,7 @@ type=ExeTracer type=EioProcess chkpt= errout=cerr -file=/dist/m5/regression/test-progs/anagram/bin/alpha/eio/anagram-vshort.eio.gz +file=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/anagram/bin/alpha/eio/anagram-vshort.eio.gz input=None max_stack_size=67108864 output=cout @@ -160,7 +160,7 @@ hash_delay=1 latency=1000 max_miss_count=0 mshrs=4 -prefetch_cache_check_push=true +num_cpus=1 prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 @@ -195,7 +195,7 @@ hash_delay=1 latency=1000 max_miss_count=0 mshrs=4 -prefetch_cache_check_push=true +num_cpus=1 prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 @@ -227,7 +227,7 @@ type=ExeTracer type=EioProcess chkpt= errout=cerr -file=/dist/m5/regression/test-progs/anagram/bin/alpha/eio/anagram-vshort.eio.gz +file=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/anagram/bin/alpha/eio/anagram-vshort.eio.gz input=None max_stack_size=67108864 output=cout @@ -272,7 +272,7 @@ hash_delay=1 latency=1000 max_miss_count=0 mshrs=4 -prefetch_cache_check_push=true +num_cpus=1 prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 @@ -307,7 +307,7 @@ hash_delay=1 latency=1000 max_miss_count=0 mshrs=4 -prefetch_cache_check_push=true +num_cpus=1 prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 @@ -339,7 +339,7 @@ type=ExeTracer type=EioProcess chkpt= errout=cerr -file=/dist/m5/regression/test-progs/anagram/bin/alpha/eio/anagram-vshort.eio.gz +file=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/anagram/bin/alpha/eio/anagram-vshort.eio.gz input=None max_stack_size=67108864 output=cout @@ -384,7 +384,7 @@ hash_delay=1 latency=1000 max_miss_count=0 mshrs=4 -prefetch_cache_check_push=true +num_cpus=1 prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 @@ -419,7 +419,7 @@ hash_delay=1 latency=1000 max_miss_count=0 mshrs=4 -prefetch_cache_check_push=true +num_cpus=1 prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 @@ -451,7 +451,7 @@ type=ExeTracer type=EioProcess chkpt= errout=cerr -file=/dist/m5/regression/test-progs/anagram/bin/alpha/eio/anagram-vshort.eio.gz +file=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/anagram/bin/alpha/eio/anagram-vshort.eio.gz input=None max_stack_size=67108864 output=cout @@ -467,7 +467,7 @@ hash_delay=1 latency=10000 max_miss_count=0 mshrs=92 -prefetch_cache_check_push=true +num_cpus=4 prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=100000 diff --git a/tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simerr b/tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simerr index 75c83d350..1abe4a9de 100755 --- a/tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simerr +++ b/tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simerr @@ -5,7 +5,3 @@ hack: be nice to actually delete the event here gzip: stdout: Broken pipe gzip: stdout: Broken pipe - -gzip: stdout: Broken pipe - -gzip: stdout: Broken pipe diff --git a/tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simout b/tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simout index 6828937b6..6a26281d0 100755 --- a/tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simout +++ b/tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 22 2009 06:58:26 -M5 revision ce26a627c841 6126 default qtip tip stats_no_compat.diff -M5 started Apr 22 2009 07:17:24 -M5 executing on maize +M5 compiled Feb 24 2010 23:12:40 +M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip +M5 started Feb 25 2010 02:22:16 +M5 executing on SC2B0619 command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/30.eio-mp/alpha/eio/simple-atomic-mp -re tests/run.py build/ALPHA_SE/tests/fast/quick/30.eio-mp/alpha/eio/simple-atomic-mp Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/stats.txt b/tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/stats.txt index 75b87a853..94c888d5d 100644 --- a/tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/stats.txt +++ b/tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 4530821 # Simulator instruction rate (inst/s) -host_mem_usage 1125932 # Number of bytes of host memory used -host_seconds 0.44 # Real time elapsed on the host -host_tick_rate 566039081 # Simulator tick rate (ticks/s) +host_inst_rate 1651065 # Simulator instruction rate (inst/s) +host_mem_usage 1114084 # Number of bytes of host memory used +host_seconds 1.21 # Real time elapsed on the host +host_tick_rate 206342663 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 2000004 # Number of instructions simulated sim_seconds 0.000250 # Number of seconds simulated @@ -38,6 +38,8 @@ system.cpu0.dcache.demand_mshr_misses 0 # nu system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu0.dcache.occ_%::0 0.540766 # Average percentage of cache occupancy +system.cpu0.dcache.occ_blocks::0 276.872320 # Average occupied blocks per context system.cpu0.dcache.overall_accesses 180775 # number of overall (read+write) accesses system.cpu0.dcache.overall_avg_miss_latency 0 # average overall miss latency system.cpu0.dcache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency @@ -101,6 +103,8 @@ system.cpu0.icache.demand_mshr_misses 0 # nu system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu0.icache.occ_%::0 0.425950 # Average percentage of cache occupancy +system.cpu0.icache.occ_blocks::0 218.086151 # Average occupied blocks per context system.cpu0.icache.overall_accesses 500019 # number of overall (read+write) accesses system.cpu0.icache.overall_avg_miss_latency 0 # average overall miss latency system.cpu0.icache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency @@ -174,6 +178,8 @@ system.cpu1.dcache.demand_mshr_misses 0 # nu system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu1.dcache.occ_%::0 0.540766 # Average percentage of cache occupancy +system.cpu1.dcache.occ_blocks::0 276.872320 # Average occupied blocks per context system.cpu1.dcache.overall_accesses 180775 # number of overall (read+write) accesses system.cpu1.dcache.overall_avg_miss_latency 0 # average overall miss latency system.cpu1.dcache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency @@ -237,6 +243,8 @@ system.cpu1.icache.demand_mshr_misses 0 # nu system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu1.icache.occ_%::0 0.425950 # Average percentage of cache occupancy +system.cpu1.icache.occ_blocks::0 218.086151 # Average occupied blocks per context system.cpu1.icache.overall_accesses 500019 # number of overall (read+write) accesses system.cpu1.icache.overall_avg_miss_latency 0 # average overall miss latency system.cpu1.icache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency @@ -310,6 +318,8 @@ system.cpu2.dcache.demand_mshr_misses 0 # nu system.cpu2.dcache.fast_writes 0 # number of fast writes performed system.cpu2.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu2.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu2.dcache.occ_%::0 0.540766 # Average percentage of cache occupancy +system.cpu2.dcache.occ_blocks::0 276.872320 # Average occupied blocks per context system.cpu2.dcache.overall_accesses 180775 # number of overall (read+write) accesses system.cpu2.dcache.overall_avg_miss_latency 0 # average overall miss latency system.cpu2.dcache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency @@ -373,6 +383,8 @@ system.cpu2.icache.demand_mshr_misses 0 # nu system.cpu2.icache.fast_writes 0 # number of fast writes performed system.cpu2.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu2.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu2.icache.occ_%::0 0.425950 # Average percentage of cache occupancy +system.cpu2.icache.occ_blocks::0 218.086151 # Average occupied blocks per context system.cpu2.icache.overall_accesses 500019 # number of overall (read+write) accesses system.cpu2.icache.overall_avg_miss_latency 0 # average overall miss latency system.cpu2.icache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency @@ -446,6 +458,8 @@ system.cpu3.dcache.demand_mshr_misses 0 # nu system.cpu3.dcache.fast_writes 0 # number of fast writes performed system.cpu3.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu3.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu3.dcache.occ_%::0 0.540766 # Average percentage of cache occupancy +system.cpu3.dcache.occ_blocks::0 276.872320 # Average occupied blocks per context system.cpu3.dcache.overall_accesses 180775 # number of overall (read+write) accesses system.cpu3.dcache.overall_avg_miss_latency 0 # average overall miss latency system.cpu3.dcache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency @@ -509,6 +523,8 @@ system.cpu3.icache.demand_mshr_misses 0 # nu system.cpu3.icache.fast_writes 0 # number of fast writes performed system.cpu3.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu3.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu3.icache.occ_%::0 0.425950 # Average percentage of cache occupancy +system.cpu3.icache.occ_blocks::0 218.086151 # Average occupied blocks per context system.cpu3.icache.overall_accesses 500019 # number of overall (read+write) accesses system.cpu3.icache.overall_avg_miss_latency 0 # average overall miss latency system.cpu3.icache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency @@ -552,18 +568,60 @@ system.cpu3.numCycles 500032 # nu system.cpu3.num_insts 500001 # Number of instructions executed system.cpu3.num_refs 182222 # Number of memory references system.cpu3.workload.PROG:num_syscalls 18 # Number of system calls -system.l2c.ReadExReq_accesses 556 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_misses 556 # number of ReadExReq misses -system.l2c.ReadReq_accesses 3148 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_hits 276 # number of ReadReq hits -system.l2c.ReadReq_miss_rate 0.912325 # miss rate for ReadReq accesses -system.l2c.ReadReq_misses 2872 # number of ReadReq misses -system.l2c.UpgradeReq_accesses 688 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_misses 688 # number of UpgradeReq misses -system.l2c.Writeback_accesses 116 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_hits 116 # number of Writeback hits +system.l2c.ReadExReq_accesses::0 139 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::1 139 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::2 139 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::3 139 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 556 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_miss_rate::0 1 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::1 1 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::2 1 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::3 1 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 4 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_misses::0 139 # number of ReadExReq misses +system.l2c.ReadExReq_misses::1 139 # number of ReadExReq misses +system.l2c.ReadExReq_misses::2 139 # number of ReadExReq misses +system.l2c.ReadExReq_misses::3 139 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 556 # number of ReadExReq misses +system.l2c.ReadReq_accesses::0 787 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::1 787 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::2 787 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::3 787 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 3148 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_hits::0 69 # number of ReadReq hits +system.l2c.ReadReq_hits::1 69 # number of ReadReq hits +system.l2c.ReadReq_hits::2 69 # number of ReadReq hits +system.l2c.ReadReq_hits::3 69 # number of ReadReq hits +system.l2c.ReadReq_hits::total 276 # number of ReadReq hits +system.l2c.ReadReq_miss_rate::0 0.912325 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::1 0.912325 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::2 0.912325 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::3 0.912325 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 3.649301 # miss rate for ReadReq accesses +system.l2c.ReadReq_misses::0 718 # number of ReadReq misses +system.l2c.ReadReq_misses::1 718 # number of ReadReq misses +system.l2c.ReadReq_misses::2 718 # number of ReadReq misses +system.l2c.ReadReq_misses::3 718 # number of ReadReq misses +system.l2c.ReadReq_misses::total 2872 # number of ReadReq misses +system.l2c.UpgradeReq_accesses::0 172 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::1 172 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::2 172 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::3 172 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 688 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_miss_rate::0 1 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::1 1 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::2 1 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::3 1 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 4 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_misses::0 172 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::1 172 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::2 172 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::3 172 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 688 # number of UpgradeReq misses +system.l2c.Writeback_accesses::0 116 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 116 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_hits::0 116 # number of Writeback hits +system.l2c.Writeback_hits::total 116 # number of Writeback hits system.l2c.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.l2c.avg_refs 0.120000 # Average number of references to valid blocks. @@ -572,31 +630,89 @@ system.l2c.blocked::no_targets 0 # nu system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.demand_accesses 3704 # number of demand (read+write) accesses -system.l2c.demand_avg_miss_latency 0 # average overall miss latency +system.l2c.demand_accesses::0 926 # number of demand (read+write) accesses +system.l2c.demand_accesses::1 926 # number of demand (read+write) accesses +system.l2c.demand_accesses::2 926 # number of demand (read+write) accesses +system.l2c.demand_accesses::3 926 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 3704 # number of demand (read+write) accesses +system.l2c.demand_avg_miss_latency::0 0 # average overall miss latency +system.l2c.demand_avg_miss_latency::1 0 # average overall miss latency +system.l2c.demand_avg_miss_latency::2 0 # average overall miss latency +system.l2c.demand_avg_miss_latency::3 0 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 0 # average overall miss latency system.l2c.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency -system.l2c.demand_hits 276 # number of demand (read+write) hits +system.l2c.demand_hits::0 69 # number of demand (read+write) hits +system.l2c.demand_hits::1 69 # number of demand (read+write) hits +system.l2c.demand_hits::2 69 # number of demand (read+write) hits +system.l2c.demand_hits::3 69 # number of demand (read+write) hits +system.l2c.demand_hits::total 276 # number of demand (read+write) hits system.l2c.demand_miss_latency 0 # number of demand (read+write) miss cycles -system.l2c.demand_miss_rate 0.925486 # miss rate for demand accesses -system.l2c.demand_misses 3428 # number of demand (read+write) misses +system.l2c.demand_miss_rate::0 0.925486 # miss rate for demand accesses +system.l2c.demand_miss_rate::1 0.925486 # miss rate for demand accesses +system.l2c.demand_miss_rate::2 0.925486 # miss rate for demand accesses +system.l2c.demand_miss_rate::3 0.925486 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 3.701944 # miss rate for demand accesses +system.l2c.demand_misses::0 857 # number of demand (read+write) misses +system.l2c.demand_misses::1 857 # number of demand (read+write) misses +system.l2c.demand_misses::2 857 # number of demand (read+write) misses +system.l2c.demand_misses::3 857 # number of demand (read+write) misses +system.l2c.demand_misses::total 3428 # number of demand (read+write) misses system.l2c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.l2c.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::0 0 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::1 0 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::2 0 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::3 0 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0 # mshr miss rate for demand accesses system.l2c.demand_mshr_misses 0 # number of demand (read+write) MSHR misses system.l2c.fast_writes 0 # number of fast writes performed system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.overall_accesses 3704 # number of overall (read+write) accesses -system.l2c.overall_avg_miss_latency 0 # average overall miss latency +system.l2c.occ_%::0 0.005715 # Average percentage of cache occupancy +system.l2c.occ_%::1 0.005715 # Average percentage of cache occupancy +system.l2c.occ_%::2 0.005715 # Average percentage of cache occupancy +system.l2c.occ_%::3 0.005715 # Average percentage of cache occupancy +system.l2c.occ_%::4 0.000475 # Average percentage of cache occupancy +system.l2c.occ_blocks::0 374.558766 # Average occupied blocks per context +system.l2c.occ_blocks::1 374.558766 # Average occupied blocks per context +system.l2c.occ_blocks::2 374.558766 # Average occupied blocks per context +system.l2c.occ_blocks::3 374.558766 # Average occupied blocks per context +system.l2c.occ_blocks::4 31.139534 # Average occupied blocks per context +system.l2c.overall_accesses::0 926 # number of overall (read+write) accesses +system.l2c.overall_accesses::1 926 # number of overall (read+write) accesses +system.l2c.overall_accesses::2 926 # number of overall (read+write) accesses +system.l2c.overall_accesses::3 926 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 3704 # number of overall (read+write) accesses +system.l2c.overall_avg_miss_latency::0 0 # average overall miss latency +system.l2c.overall_avg_miss_latency::1 0 # average overall miss latency +system.l2c.overall_avg_miss_latency::2 0 # average overall miss latency +system.l2c.overall_avg_miss_latency::3 0 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 0 # average overall miss latency system.l2c.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency system.l2c.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.l2c.overall_hits 276 # number of overall hits +system.l2c.overall_hits::0 69 # number of overall hits +system.l2c.overall_hits::1 69 # number of overall hits +system.l2c.overall_hits::2 69 # number of overall hits +system.l2c.overall_hits::3 69 # number of overall hits +system.l2c.overall_hits::total 276 # number of overall hits system.l2c.overall_miss_latency 0 # number of overall miss cycles -system.l2c.overall_miss_rate 0.925486 # miss rate for overall accesses -system.l2c.overall_misses 3428 # number of overall misses +system.l2c.overall_miss_rate::0 0.925486 # miss rate for overall accesses +system.l2c.overall_miss_rate::1 0.925486 # miss rate for overall accesses +system.l2c.overall_miss_rate::2 0.925486 # miss rate for overall accesses +system.l2c.overall_miss_rate::3 0.925486 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 3.701944 # miss rate for overall accesses +system.l2c.overall_misses::0 857 # number of overall misses +system.l2c.overall_misses::1 857 # number of overall misses +system.l2c.overall_misses::2 857 # number of overall misses +system.l2c.overall_misses::3 857 # number of overall misses +system.l2c.overall_misses::total 3428 # number of overall misses system.l2c.overall_mshr_hits 0 # number of overall MSHR hits system.l2c.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::0 0 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::1 0 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::2 0 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::3 0 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0 # mshr miss rate for overall accesses system.l2c.overall_mshr_misses 0 # number of overall MSHR misses system.l2c.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses |