diff options
Diffstat (limited to 'tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/stats.txt')
| -rw-r--r-- | tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/stats.txt | 136 |
1 files changed, 100 insertions, 36 deletions
diff --git a/tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/stats.txt b/tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/stats.txt index 1fb750134..78b7525ed 100644 --- a/tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/stats.txt +++ b/tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1521087 # Simulator instruction rate (inst/s) -host_mem_usage 206108 # Number of bytes of host memory used -host_seconds 1.32 # Real time elapsed on the host -host_tick_rate 561475161 # Simulator tick rate (ticks/s) +host_inst_rate 2309817 # Simulator instruction rate (inst/s) +host_mem_usage 208124 # Number of bytes of host memory used +host_seconds 0.87 # Real time elapsed on the host +host_tick_rate 852520777 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 1999941 # Number of instructions simulated sim_seconds 0.000738 # Number of seconds simulated @@ -71,10 +71,14 @@ system.cpu0.dcache.tagsinuse 272.914158 # Cy system.cpu0.dcache.total_refs 180308 # Total number of references to valid blocks. system.cpu0.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu0.dcache.writebacks 29 # number of writebacks -system.cpu0.dtb.accesses 180789 # DTB accesses -system.cpu0.dtb.acv 0 # DTB access violations -system.cpu0.dtb.hits 180771 # DTB hits -system.cpu0.dtb.misses 18 # DTB misses +system.cpu0.dtb.data_accesses 180789 # DTB accesses +system.cpu0.dtb.data_acv 0 # DTB access violations +system.cpu0.dtb.data_hits 180771 # DTB hits +system.cpu0.dtb.data_misses 18 # DTB misses +system.cpu0.dtb.fetch_accesses 0 # ITB accesses +system.cpu0.dtb.fetch_acv 0 # ITB acv +system.cpu0.dtb.fetch_hits 0 # ITB hits +system.cpu0.dtb.fetch_misses 0 # ITB misses system.cpu0.dtb.read_accesses 124440 # DTB read accesses system.cpu0.dtb.read_acv 0 # DTB read access violations system.cpu0.dtb.read_hits 124432 # DTB read hits @@ -137,10 +141,22 @@ system.cpu0.icache.total_refs 499537 # To system.cpu0.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu0.icache.writebacks 0 # number of writebacks system.cpu0.idle_fraction 0 # Percentage of idle cycles -system.cpu0.itb.accesses 500013 # ITB accesses -system.cpu0.itb.acv 0 # ITB acv -system.cpu0.itb.hits 500000 # ITB hits -system.cpu0.itb.misses 13 # ITB misses +system.cpu0.itb.data_accesses 0 # DTB accesses +system.cpu0.itb.data_acv 0 # DTB access violations +system.cpu0.itb.data_hits 0 # DTB hits +system.cpu0.itb.data_misses 0 # DTB misses +system.cpu0.itb.fetch_accesses 500013 # ITB accesses +system.cpu0.itb.fetch_acv 0 # ITB acv +system.cpu0.itb.fetch_hits 500000 # ITB hits +system.cpu0.itb.fetch_misses 13 # ITB misses +system.cpu0.itb.read_accesses 0 # DTB read accesses +system.cpu0.itb.read_acv 0 # DTB read access violations +system.cpu0.itb.read_hits 0 # DTB read hits +system.cpu0.itb.read_misses 0 # DTB read misses +system.cpu0.itb.write_accesses 0 # DTB write accesses +system.cpu0.itb.write_acv 0 # DTB write access violations +system.cpu0.itb.write_hits 0 # DTB write hits +system.cpu0.itb.write_misses 0 # DTB write misses system.cpu0.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu0.numCycles 1476774 # number of cpu cycles simulated system.cpu0.num_insts 499981 # Number of instructions executed @@ -209,10 +225,14 @@ system.cpu1.dcache.tagsinuse 272.910830 # Cy system.cpu1.dcache.total_refs 180305 # Total number of references to valid blocks. system.cpu1.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu1.dcache.writebacks 29 # number of writebacks -system.cpu1.dtb.accesses 180786 # DTB accesses -system.cpu1.dtb.acv 0 # DTB access violations -system.cpu1.dtb.hits 180768 # DTB hits -system.cpu1.dtb.misses 18 # DTB misses +system.cpu1.dtb.data_accesses 180786 # DTB accesses +system.cpu1.dtb.data_acv 0 # DTB access violations +system.cpu1.dtb.data_hits 180768 # DTB hits +system.cpu1.dtb.data_misses 18 # DTB misses +system.cpu1.dtb.fetch_accesses 0 # ITB accesses +system.cpu1.dtb.fetch_acv 0 # ITB acv +system.cpu1.dtb.fetch_hits 0 # ITB hits +system.cpu1.dtb.fetch_misses 0 # ITB misses system.cpu1.dtb.read_accesses 124437 # DTB read accesses system.cpu1.dtb.read_acv 0 # DTB read access violations system.cpu1.dtb.read_hits 124429 # DTB read hits @@ -275,10 +295,22 @@ system.cpu1.icache.total_refs 499531 # To system.cpu1.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu1.icache.writebacks 0 # number of writebacks system.cpu1.idle_fraction 0 # Percentage of idle cycles -system.cpu1.itb.accesses 500007 # ITB accesses -system.cpu1.itb.acv 0 # ITB acv -system.cpu1.itb.hits 499994 # ITB hits -system.cpu1.itb.misses 13 # ITB misses +system.cpu1.itb.data_accesses 0 # DTB accesses +system.cpu1.itb.data_acv 0 # DTB access violations +system.cpu1.itb.data_hits 0 # DTB hits +system.cpu1.itb.data_misses 0 # DTB misses +system.cpu1.itb.fetch_accesses 500007 # ITB accesses +system.cpu1.itb.fetch_acv 0 # ITB acv +system.cpu1.itb.fetch_hits 499994 # ITB hits +system.cpu1.itb.fetch_misses 13 # ITB misses +system.cpu1.itb.read_accesses 0 # DTB read accesses +system.cpu1.itb.read_acv 0 # DTB read access violations +system.cpu1.itb.read_hits 0 # DTB read hits +system.cpu1.itb.read_misses 0 # DTB read misses +system.cpu1.itb.write_accesses 0 # DTB write accesses +system.cpu1.itb.write_acv 0 # DTB write access violations +system.cpu1.itb.write_hits 0 # DTB write hits +system.cpu1.itb.write_misses 0 # DTB write misses system.cpu1.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu1.numCycles 1476774 # number of cpu cycles simulated system.cpu1.num_insts 499975 # Number of instructions executed @@ -347,10 +379,14 @@ system.cpu2.dcache.tagsinuse 272.921161 # Cy system.cpu2.dcache.total_refs 180312 # Total number of references to valid blocks. system.cpu2.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu2.dcache.writebacks 29 # number of writebacks -system.cpu2.dtb.accesses 180793 # DTB accesses -system.cpu2.dtb.acv 0 # DTB access violations -system.cpu2.dtb.hits 180775 # DTB hits -system.cpu2.dtb.misses 18 # DTB misses +system.cpu2.dtb.data_accesses 180793 # DTB accesses +system.cpu2.dtb.data_acv 0 # DTB access violations +system.cpu2.dtb.data_hits 180775 # DTB hits +system.cpu2.dtb.data_misses 18 # DTB misses +system.cpu2.dtb.fetch_accesses 0 # ITB accesses +system.cpu2.dtb.fetch_acv 0 # ITB acv +system.cpu2.dtb.fetch_hits 0 # ITB hits +system.cpu2.dtb.fetch_misses 0 # ITB misses system.cpu2.dtb.read_accesses 124443 # DTB read accesses system.cpu2.dtb.read_acv 0 # DTB read access violations system.cpu2.dtb.read_hits 124435 # DTB read hits @@ -413,10 +449,22 @@ system.cpu2.icache.total_refs 499557 # To system.cpu2.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu2.icache.writebacks 0 # number of writebacks system.cpu2.idle_fraction 0 # Percentage of idle cycles -system.cpu2.itb.accesses 500033 # ITB accesses -system.cpu2.itb.acv 0 # ITB acv -system.cpu2.itb.hits 500020 # ITB hits -system.cpu2.itb.misses 13 # ITB misses +system.cpu2.itb.data_accesses 0 # DTB accesses +system.cpu2.itb.data_acv 0 # DTB access violations +system.cpu2.itb.data_hits 0 # DTB hits +system.cpu2.itb.data_misses 0 # DTB misses +system.cpu2.itb.fetch_accesses 500033 # ITB accesses +system.cpu2.itb.fetch_acv 0 # ITB acv +system.cpu2.itb.fetch_hits 500020 # ITB hits +system.cpu2.itb.fetch_misses 13 # ITB misses +system.cpu2.itb.read_accesses 0 # DTB read accesses +system.cpu2.itb.read_acv 0 # DTB read access violations +system.cpu2.itb.read_hits 0 # DTB read hits +system.cpu2.itb.read_misses 0 # DTB read misses +system.cpu2.itb.write_accesses 0 # DTB write accesses +system.cpu2.itb.write_acv 0 # DTB write access violations +system.cpu2.itb.write_hits 0 # DTB write hits +system.cpu2.itb.write_misses 0 # DTB write misses system.cpu2.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu2.numCycles 1476774 # number of cpu cycles simulated system.cpu2.num_insts 500001 # Number of instructions executed @@ -485,10 +533,14 @@ system.cpu3.dcache.tagsinuse 272.916356 # Cy system.cpu3.dcache.total_refs 180309 # Total number of references to valid blocks. system.cpu3.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu3.dcache.writebacks 29 # number of writebacks -system.cpu3.dtb.accesses 180790 # DTB accesses -system.cpu3.dtb.acv 0 # DTB access violations -system.cpu3.dtb.hits 180772 # DTB hits -system.cpu3.dtb.misses 18 # DTB misses +system.cpu3.dtb.data_accesses 180790 # DTB accesses +system.cpu3.dtb.data_acv 0 # DTB access violations +system.cpu3.dtb.data_hits 180772 # DTB hits +system.cpu3.dtb.data_misses 18 # DTB misses +system.cpu3.dtb.fetch_accesses 0 # ITB accesses +system.cpu3.dtb.fetch_acv 0 # ITB acv +system.cpu3.dtb.fetch_hits 0 # ITB hits +system.cpu3.dtb.fetch_misses 0 # ITB misses system.cpu3.dtb.read_accesses 124441 # DTB read accesses system.cpu3.dtb.read_acv 0 # DTB read access violations system.cpu3.dtb.read_hits 124433 # DTB read hits @@ -551,10 +603,22 @@ system.cpu3.icache.total_refs 499540 # To system.cpu3.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu3.icache.writebacks 0 # number of writebacks system.cpu3.idle_fraction 0 # Percentage of idle cycles -system.cpu3.itb.accesses 500016 # ITB accesses -system.cpu3.itb.acv 0 # ITB acv -system.cpu3.itb.hits 500003 # ITB hits -system.cpu3.itb.misses 13 # ITB misses +system.cpu3.itb.data_accesses 0 # DTB accesses +system.cpu3.itb.data_acv 0 # DTB access violations +system.cpu3.itb.data_hits 0 # DTB hits +system.cpu3.itb.data_misses 0 # DTB misses +system.cpu3.itb.fetch_accesses 500016 # ITB accesses +system.cpu3.itb.fetch_acv 0 # ITB acv +system.cpu3.itb.fetch_hits 500003 # ITB hits +system.cpu3.itb.fetch_misses 13 # ITB misses +system.cpu3.itb.read_accesses 0 # DTB read accesses +system.cpu3.itb.read_acv 0 # DTB read access violations +system.cpu3.itb.read_hits 0 # DTB read hits +system.cpu3.itb.read_misses 0 # DTB read misses +system.cpu3.itb.write_accesses 0 # DTB write accesses +system.cpu3.itb.write_acv 0 # DTB write access violations +system.cpu3.itb.write_hits 0 # DTB write hits +system.cpu3.itb.write_misses 0 # DTB write misses system.cpu3.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu3.numCycles 1476774 # number of cpu cycles simulated system.cpu3.num_insts 499984 # Number of instructions executed |