diff options
Diffstat (limited to 'tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt')
| -rw-r--r-- | tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt | 170 |
1 files changed, 85 insertions, 85 deletions
diff --git a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt b/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt index 6e706304f..9d16d1421 100644 --- a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt +++ b/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1148641 # Simulator instruction rate (inst/s) -host_mem_usage 1126984 # Number of bytes of host memory used -host_seconds 0.59 # Real time elapsed on the host -host_tick_rate 148677785 # Simulator tick rate (ticks/s) +host_inst_rate 1712699 # Simulator instruction rate (inst/s) +host_mem_usage 1128716 # Number of bytes of host memory used +host_seconds 0.40 # Real time elapsed on the host +host_tick_rate 221634180 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 677340 # Number of instructions simulated sim_seconds 0.000088 # Number of seconds simulated @@ -20,17 +20,17 @@ system.cpu0.dcache.WriteReq_accesses 16107 # nu system.cpu0.dcache.WriteReq_hits 15998 # number of WriteReq hits system.cpu0.dcache.WriteReq_miss_rate 0.006767 # miss rate for WriteReq accesses system.cpu0.dcache.WriteReq_misses 109 # number of WriteReq misses -system.cpu0.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu0.dcache.avg_refs 1206.107143 # Average number of references to valid blocks. -system.cpu0.dcache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu0.dcache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.cache_copies 0 # number of cache copies performed system.cpu0.dcache.demand_accesses 58461 # number of demand (read+write) accesses system.cpu0.dcache.demand_avg_miss_latency 0 # average overall miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency system.cpu0.dcache.demand_hits 58190 # number of demand (read+write) hits system.cpu0.dcache.demand_miss_latency 0 # number of demand (read+write) miss cycles system.cpu0.dcache.demand_miss_rate 0.004636 # miss rate for demand accesses @@ -44,8 +44,8 @@ system.cpu0.dcache.mshr_cap_events 0 # nu system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.dcache.overall_accesses 58461 # number of overall (read+write) accesses system.cpu0.dcache.overall_avg_miss_latency 0 # average overall miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu0.dcache.overall_hits 58190 # number of overall hits system.cpu0.dcache.overall_miss_latency 0 # number of overall miss cycles system.cpu0.dcache.overall_miss_rate 0.004636 # miss rate for overall accesses @@ -67,17 +67,17 @@ system.cpu0.icache.ReadReq_accesses 167366 # nu system.cpu0.icache.ReadReq_hits 167008 # number of ReadReq hits system.cpu0.icache.ReadReq_miss_rate 0.002139 # miss rate for ReadReq accesses system.cpu0.icache.ReadReq_misses 358 # number of ReadReq misses -system.cpu0.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked -system.cpu0.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu0.icache.avg_refs 466.502793 # Average number of references to valid blocks. -system.cpu0.icache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu0.icache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu0.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.cache_copies 0 # number of cache copies performed system.cpu0.icache.demand_accesses 167366 # number of demand (read+write) accesses system.cpu0.icache.demand_avg_miss_latency 0 # average overall miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency system.cpu0.icache.demand_hits 167008 # number of demand (read+write) hits system.cpu0.icache.demand_miss_latency 0 # number of demand (read+write) miss cycles system.cpu0.icache.demand_miss_rate 0.002139 # miss rate for demand accesses @@ -91,8 +91,8 @@ system.cpu0.icache.mshr_cap_events 0 # nu system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.icache.overall_accesses 167366 # number of overall (read+write) accesses system.cpu0.icache.overall_avg_miss_latency 0 # average overall miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu0.icache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu0.icache.overall_hits 167008 # number of overall hits system.cpu0.icache.overall_miss_latency 0 # number of overall miss cycles system.cpu0.icache.overall_miss_rate 0.002139 # miss rate for overall accesses @@ -128,17 +128,17 @@ system.cpu1.dcache.WriteReq_accesses 14362 # nu system.cpu1.dcache.WriteReq_hits 14260 # number of WriteReq hits system.cpu1.dcache.WriteReq_miss_rate 0.007102 # miss rate for WriteReq accesses system.cpu1.dcache.WriteReq_misses 102 # number of WriteReq misses -system.cpu1.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked -system.cpu1.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu1.dcache.avg_refs 1045.137931 # Average number of references to valid blocks. -system.cpu1.dcache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu1.dcache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu1.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu1.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.cache_copies 0 # number of cache copies performed system.cpu1.dcache.demand_accesses 55820 # number of demand (read+write) accesses system.cpu1.dcache.demand_avg_miss_latency 0 # average overall miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency system.cpu1.dcache.demand_hits 55559 # number of demand (read+write) hits system.cpu1.dcache.demand_miss_latency 0 # number of demand (read+write) miss cycles system.cpu1.dcache.demand_miss_rate 0.004676 # miss rate for demand accesses @@ -152,8 +152,8 @@ system.cpu1.dcache.mshr_cap_events 0 # nu system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dcache.overall_accesses 55820 # number of overall (read+write) accesses system.cpu1.dcache.overall_avg_miss_latency 0 # average overall miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu1.dcache.overall_hits 55559 # number of overall hits system.cpu1.dcache.overall_miss_latency 0 # number of overall miss cycles system.cpu1.dcache.overall_miss_rate 0.004676 # miss rate for overall accesses @@ -175,17 +175,17 @@ system.cpu1.icache.ReadReq_accesses 167301 # nu system.cpu1.icache.ReadReq_hits 166942 # number of ReadReq hits system.cpu1.icache.ReadReq_miss_rate 0.002146 # miss rate for ReadReq accesses system.cpu1.icache.ReadReq_misses 359 # number of ReadReq misses -system.cpu1.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked -system.cpu1.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu1.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu1.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu1.icache.avg_refs 465.019499 # Average number of references to valid blocks. -system.cpu1.icache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu1.icache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu1.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu1.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.cache_copies 0 # number of cache copies performed system.cpu1.icache.demand_accesses 167301 # number of demand (read+write) accesses system.cpu1.icache.demand_avg_miss_latency 0 # average overall miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency system.cpu1.icache.demand_hits 166942 # number of demand (read+write) hits system.cpu1.icache.demand_miss_latency 0 # number of demand (read+write) miss cycles system.cpu1.icache.demand_miss_rate 0.002146 # miss rate for demand accesses @@ -199,8 +199,8 @@ system.cpu1.icache.mshr_cap_events 0 # nu system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.icache.overall_accesses 167301 # number of overall (read+write) accesses system.cpu1.icache.overall_avg_miss_latency 0 # average overall miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu1.icache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu1.icache.overall_hits 166942 # number of overall hits system.cpu1.icache.overall_miss_latency 0 # number of overall miss cycles system.cpu1.icache.overall_miss_rate 0.002146 # miss rate for overall accesses @@ -235,17 +235,17 @@ system.cpu2.dcache.WriteReq_accesses 27755 # nu system.cpu2.dcache.WriteReq_hits 27561 # number of WriteReq hits system.cpu2.dcache.WriteReq_miss_rate 0.006990 # miss rate for WriteReq accesses system.cpu2.dcache.WriteReq_misses 194 # number of WriteReq misses -system.cpu2.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked -system.cpu2.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu2.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu2.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu2.dcache.avg_refs 362.347059 # Average number of references to valid blocks. -system.cpu2.dcache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu2.dcache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu2.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu2.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu2.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu2.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu2.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu2.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu2.dcache.cache_copies 0 # number of cache copies performed system.cpu2.dcache.demand_accesses 82337 # number of demand (read+write) accesses system.cpu2.dcache.demand_avg_miss_latency 0 # average overall miss latency -system.cpu2.dcache.demand_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency +system.cpu2.dcache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency system.cpu2.dcache.demand_hits 81992 # number of demand (read+write) hits system.cpu2.dcache.demand_miss_latency 0 # number of demand (read+write) miss cycles system.cpu2.dcache.demand_miss_rate 0.004190 # miss rate for demand accesses @@ -259,8 +259,8 @@ system.cpu2.dcache.mshr_cap_events 0 # nu system.cpu2.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu2.dcache.overall_accesses 82337 # number of overall (read+write) accesses system.cpu2.dcache.overall_avg_miss_latency 0 # average overall miss latency -system.cpu2.dcache.overall_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency -system.cpu2.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu2.dcache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency +system.cpu2.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu2.dcache.overall_hits 81992 # number of overall hits system.cpu2.dcache.overall_miss_latency 0 # number of overall miss cycles system.cpu2.dcache.overall_miss_rate 0.004190 # miss rate for overall accesses @@ -282,17 +282,17 @@ system.cpu2.icache.ReadReq_accesses 175401 # nu system.cpu2.icache.ReadReq_hits 174934 # number of ReadReq hits system.cpu2.icache.ReadReq_miss_rate 0.002662 # miss rate for ReadReq accesses system.cpu2.icache.ReadReq_misses 467 # number of ReadReq misses -system.cpu2.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked -system.cpu2.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu2.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu2.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu2.icache.avg_refs 374.591006 # Average number of references to valid blocks. -system.cpu2.icache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu2.icache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu2.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu2.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu2.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu2.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu2.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu2.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu2.icache.cache_copies 0 # number of cache copies performed system.cpu2.icache.demand_accesses 175401 # number of demand (read+write) accesses system.cpu2.icache.demand_avg_miss_latency 0 # average overall miss latency -system.cpu2.icache.demand_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency +system.cpu2.icache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency system.cpu2.icache.demand_hits 174934 # number of demand (read+write) hits system.cpu2.icache.demand_miss_latency 0 # number of demand (read+write) miss cycles system.cpu2.icache.demand_miss_rate 0.002662 # miss rate for demand accesses @@ -306,8 +306,8 @@ system.cpu2.icache.mshr_cap_events 0 # nu system.cpu2.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu2.icache.overall_accesses 175401 # number of overall (read+write) accesses system.cpu2.icache.overall_avg_miss_latency 0 # average overall miss latency -system.cpu2.icache.overall_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency -system.cpu2.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu2.icache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency +system.cpu2.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu2.icache.overall_hits 174934 # number of overall hits system.cpu2.icache.overall_miss_latency 0 # number of overall miss cycles system.cpu2.icache.overall_miss_rate 0.002662 # miss rate for overall accesses @@ -342,17 +342,17 @@ system.cpu3.dcache.WriteReq_accesses 12669 # nu system.cpu3.dcache.WriteReq_hits 12563 # number of WriteReq hits system.cpu3.dcache.WriteReq_miss_rate 0.008367 # miss rate for WriteReq accesses system.cpu3.dcache.WriteReq_misses 106 # number of WriteReq misses -system.cpu3.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked -system.cpu3.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu3.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu3.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu3.dcache.avg_refs 960.321429 # Average number of references to valid blocks. -system.cpu3.dcache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu3.dcache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu3.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu3.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu3.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu3.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu3.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu3.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu3.dcache.cache_copies 0 # number of cache copies performed system.cpu3.dcache.demand_accesses 53313 # number of demand (read+write) accesses system.cpu3.dcache.demand_avg_miss_latency 0 # average overall miss latency -system.cpu3.dcache.demand_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency +system.cpu3.dcache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency system.cpu3.dcache.demand_hits 53031 # number of demand (read+write) hits system.cpu3.dcache.demand_miss_latency 0 # number of demand (read+write) miss cycles system.cpu3.dcache.demand_miss_rate 0.005290 # miss rate for demand accesses @@ -366,8 +366,8 @@ system.cpu3.dcache.mshr_cap_events 0 # nu system.cpu3.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu3.dcache.overall_accesses 53313 # number of overall (read+write) accesses system.cpu3.dcache.overall_avg_miss_latency 0 # average overall miss latency -system.cpu3.dcache.overall_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency -system.cpu3.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu3.dcache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency +system.cpu3.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu3.dcache.overall_hits 53031 # number of overall hits system.cpu3.dcache.overall_miss_latency 0 # number of overall miss cycles system.cpu3.dcache.overall_miss_rate 0.005290 # miss rate for overall accesses @@ -389,17 +389,17 @@ system.cpu3.icache.ReadReq_accesses 167430 # nu system.cpu3.icache.ReadReq_hits 167072 # number of ReadReq hits system.cpu3.icache.ReadReq_miss_rate 0.002138 # miss rate for ReadReq accesses system.cpu3.icache.ReadReq_misses 358 # number of ReadReq misses -system.cpu3.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked -system.cpu3.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu3.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu3.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu3.icache.avg_refs 466.681564 # Average number of references to valid blocks. -system.cpu3.icache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu3.icache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu3.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu3.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu3.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu3.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu3.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu3.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu3.icache.cache_copies 0 # number of cache copies performed system.cpu3.icache.demand_accesses 167430 # number of demand (read+write) accesses system.cpu3.icache.demand_avg_miss_latency 0 # average overall miss latency -system.cpu3.icache.demand_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency +system.cpu3.icache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency system.cpu3.icache.demand_hits 167072 # number of demand (read+write) hits system.cpu3.icache.demand_miss_latency 0 # number of demand (read+write) miss cycles system.cpu3.icache.demand_miss_rate 0.002138 # miss rate for demand accesses @@ -413,8 +413,8 @@ system.cpu3.icache.mshr_cap_events 0 # nu system.cpu3.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu3.icache.overall_accesses 167430 # number of overall (read+write) accesses system.cpu3.icache.overall_avg_miss_latency 0 # average overall miss latency -system.cpu3.icache.overall_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency -system.cpu3.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu3.icache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency +system.cpu3.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu3.icache.overall_hits 167072 # number of overall hits system.cpu3.icache.overall_miss_latency 0 # number of overall miss cycles system.cpu3.icache.overall_miss_rate 0.002138 # miss rate for overall accesses @@ -449,17 +449,17 @@ system.l2c.UpgradeReq_miss_rate 1 # mi system.l2c.UpgradeReq_misses 106 # number of UpgradeReq misses system.l2c.Writeback_accesses 9 # number of Writeback accesses(hits+misses) system.l2c.Writeback_hits 9 # number of Writeback hits -system.l2c.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked -system.l2c.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.l2c.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.l2c.avg_refs 2.968447 # Average number of references to valid blocks. -system.l2c.blocked_no_mshrs 0 # number of cycles access was blocked -system.l2c.blocked_no_targets 0 # number of cycles access was blocked -system.l2c.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.l2c.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked +system.l2c.blocked::no_targets 0 # number of cycles access was blocked +system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.cache_copies 0 # number of cache copies performed system.l2c.demand_accesses 1785 # number of demand (read+write) accesses system.l2c.demand_avg_miss_latency 0 # average overall miss latency -system.l2c.demand_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency system.l2c.demand_hits 1226 # number of demand (read+write) hits system.l2c.demand_miss_latency 0 # number of demand (read+write) miss cycles system.l2c.demand_miss_rate 0.313165 # miss rate for demand accesses @@ -473,8 +473,8 @@ system.l2c.mshr_cap_events 0 # nu system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate system.l2c.overall_accesses 1785 # number of overall (read+write) accesses system.l2c.overall_avg_miss_latency 0 # average overall miss latency -system.l2c.overall_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency -system.l2c.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency +system.l2c.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.l2c.overall_hits 1226 # number of overall hits system.l2c.overall_miss_latency 0 # number of overall miss cycles system.l2c.overall_miss_rate 0.313165 # miss rate for overall accesses |