summaryrefslogtreecommitdiff
path: root/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/config.ini
diff options
context:
space:
mode:
Diffstat (limited to 'tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/config.ini')
-rw-r--r--tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/config.ini9
1 files changed, 6 insertions, 3 deletions
diff --git a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/config.ini b/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/config.ini
index 2570db111..ae7e021b5 100644
--- a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/config.ini
+++ b/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/config.ini
@@ -9,6 +9,8 @@ time_sync_spin_threshold=100000000
type=System
children=cpu0 cpu1 cpu2 cpu3 l2c membus physmem toL2Bus
mem_mode=timing
+memories=system.physmem
+num_work_ids=16
physmem=system.physmem
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
@@ -17,6 +19,7 @@ work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
+system_port=system.membus.port[1]
[system.cpu0]
type=TimingSimpleCPU
@@ -127,7 +130,7 @@ egid=100
env=
errout=cerr
euid=100
-executable=/chips/pd/randd/dist/test-progs/m5threads/bin/sparc/linux/test_atomic
+executable=/dist/m5/regression/test-progs/m5threads/bin/sparc/linux/test_atomic
gid=100
input=cin
max_stack_size=67108864
@@ -481,7 +484,7 @@ clock=1000
header_cycles=1
use_default_range=false
width=64
-port=system.l2c.mem_side system.physmem.port[0]
+port=system.l2c.mem_side system.system_port system.physmem.port[0]
[system.physmem]
type=PhysicalMemory
@@ -491,7 +494,7 @@ latency_var=0
null=false
range=0:134217727
zero=false
-port=system.membus.port[1]
+port=system.membus.port[2]
[system.toL2Bus]
type=Bus