diff options
Diffstat (limited to 'tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp')
4 files changed, 188 insertions, 48 deletions
diff --git a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/config.ini b/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/config.ini index c778c454d..f3434ec9b 100644 --- a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/config.ini +++ b/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/config.ini @@ -45,7 +45,7 @@ hash_delay=1 latency=1000 max_miss_count=0 mshrs=4 -prefetch_cache_check_push=true +num_cpus=1 prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 @@ -80,7 +80,7 @@ hash_delay=1 latency=1000 max_miss_count=0 mshrs=4 -prefetch_cache_check_push=true +num_cpus=1 prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 @@ -116,7 +116,7 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/regression/test-progs/m5threads/bin/sparc/linux/test_atomic +executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/m5threads/bin/sparc/linux/test_atomic gid=100 input=cin max_stack_size=67108864 @@ -163,7 +163,7 @@ hash_delay=1 latency=1000 max_miss_count=0 mshrs=4 -prefetch_cache_check_push=true +num_cpus=1 prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 @@ -198,7 +198,7 @@ hash_delay=1 latency=1000 max_miss_count=0 mshrs=4 -prefetch_cache_check_push=true +num_cpus=1 prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 @@ -262,7 +262,7 @@ hash_delay=1 latency=1000 max_miss_count=0 mshrs=4 -prefetch_cache_check_push=true +num_cpus=1 prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 @@ -297,7 +297,7 @@ hash_delay=1 latency=1000 max_miss_count=0 mshrs=4 -prefetch_cache_check_push=true +num_cpus=1 prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 @@ -361,7 +361,7 @@ hash_delay=1 latency=1000 max_miss_count=0 mshrs=4 -prefetch_cache_check_push=true +num_cpus=1 prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 @@ -396,7 +396,7 @@ hash_delay=1 latency=1000 max_miss_count=0 mshrs=4 -prefetch_cache_check_push=true +num_cpus=1 prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 @@ -434,7 +434,7 @@ hash_delay=1 latency=10000 max_miss_count=0 mshrs=92 -prefetch_cache_check_push=true +num_cpus=4 prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=100000 diff --git a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/simerr b/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/simerr index eabe42249..eabe42249 100644..100755 --- a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/simerr +++ b/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/simerr diff --git a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/simout b/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/simout index 304f6e9bf..a76dcd8cb 100644..100755 --- a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/simout +++ b/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 22 2009 06:58:47 -M5 revision ce26a627c841 6126 default qtip tip stats_no_compat.diff -M5 started Apr 22 2009 07:32:59 -M5 executing on maize +M5 compiled Feb 25 2010 03:11:27 +M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip +M5 started Feb 25 2010 03:38:17 +M5 executing on SC2B0619 command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/40.m5threads-test-atomic/sparc/linux/simple-timing-mp -re tests/run.py build/SPARC_SE/tests/fast/quick/40.m5threads-test-atomic/sparc/linux/simple-timing-mp Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt b/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt index bfbb72508..a432347b0 100644 --- a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt +++ b/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1057647 # Simulator instruction rate (inst/s) -host_mem_usage 211204 # Number of bytes of host memory used -host_seconds 0.62 # Real time elapsed on the host -host_tick_rate 427981185 # Simulator tick rate (ticks/s) +host_inst_rate 920855 # Simulator instruction rate (inst/s) +host_mem_usage 198472 # Number of bytes of host memory used +host_seconds 0.71 # Real time elapsed on the host +host_tick_rate 372636983 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 650423 # Number of instructions simulated sim_seconds 0.000263 # Number of seconds simulated @@ -60,6 +60,8 @@ system.cpu0.dcache.demand_mshr_misses 262 # nu system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu0.dcache.occ_%::0 0.048480 # Average percentage of cache occupancy +system.cpu0.dcache.occ_blocks::0 24.821539 # Average occupied blocks per context system.cpu0.dcache.overall_accesses 56889 # number of overall (read+write) accesses system.cpu0.dcache.overall_avg_miss_latency 16950.381679 # average overall miss latency system.cpu0.dcache.overall_avg_mshr_miss_latency 13950.381679 # average overall mshr miss latency @@ -113,6 +115,8 @@ system.cpu0.icache.demand_mshr_misses 358 # nu system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu0.icache.occ_%::0 0.127582 # Average percentage of cache occupancy +system.cpu0.icache.occ_blocks::0 65.321793 # Average occupied blocks per context system.cpu0.icache.overall_accesses 161568 # number of overall (read+write) accesses system.cpu0.icache.overall_avg_miss_latency 14758.379888 # average overall miss latency system.cpu0.icache.overall_avg_mshr_miss_latency 11758.379888 # average overall mshr miss latency @@ -192,6 +196,8 @@ system.cpu1.dcache.demand_mshr_misses 262 # nu system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu1.dcache.occ_%::0 0.049924 # Average percentage of cache occupancy +system.cpu1.dcache.occ_blocks::0 25.561342 # Average occupied blocks per context system.cpu1.dcache.overall_accesses 56189 # number of overall (read+write) accesses system.cpu1.dcache.overall_avg_miss_latency 17095.419847 # average overall miss latency system.cpu1.dcache.overall_avg_mshr_miss_latency 14095.419847 # average overall mshr miss latency @@ -245,6 +251,8 @@ system.cpu1.icache.demand_mshr_misses 359 # nu system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu1.icache.occ_%::0 0.131739 # Average percentage of cache occupancy +system.cpu1.icache.occ_blocks::0 67.450287 # Average occupied blocks per context system.cpu1.icache.overall_accesses 162202 # number of overall (read+write) accesses system.cpu1.icache.overall_avg_miss_latency 14391.364903 # average overall miss latency system.cpu1.icache.overall_avg_mshr_miss_latency 11391.364903 # average overall mshr miss latency @@ -323,6 +331,8 @@ system.cpu2.dcache.demand_mshr_misses 362 # nu system.cpu2.dcache.fast_writes 0 # number of fast writes performed system.cpu2.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu2.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu2.dcache.occ_%::0 0.275555 # Average percentage of cache occupancy +system.cpu2.dcache.occ_blocks::0 141.084106 # Average occupied blocks per context system.cpu2.dcache.overall_accesses 73844 # number of overall (read+write) accesses system.cpu2.dcache.overall_avg_miss_latency 35787.292818 # average overall miss latency system.cpu2.dcache.overall_avg_mshr_miss_latency 32787.292818 # average overall mshr miss latency @@ -376,6 +386,8 @@ system.cpu2.icache.demand_mshr_misses 467 # nu system.cpu2.icache.fast_writes 0 # number of fast writes performed system.cpu2.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu2.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu2.icache.occ_%::0 0.414415 # Average percentage of cache occupancy +system.cpu2.icache.occ_blocks::0 212.180630 # Average occupied blocks per context system.cpu2.icache.overall_accesses 158416 # number of overall (read+write) accesses system.cpu2.icache.overall_avg_miss_latency 39665.952891 # average overall miss latency system.cpu2.icache.overall_avg_mshr_miss_latency 36665.952891 # average overall mshr miss latency @@ -454,6 +466,8 @@ system.cpu3.dcache.demand_mshr_misses 276 # nu system.cpu3.dcache.fast_writes 0 # number of fast writes performed system.cpu3.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu3.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu3.dcache.occ_%::0 0.051885 # Average percentage of cache occupancy +system.cpu3.dcache.occ_blocks::0 26.564950 # Average occupied blocks per context system.cpu3.dcache.overall_accesses 46826 # number of overall (read+write) accesses system.cpu3.dcache.overall_avg_miss_latency 19681.159420 # average overall miss latency system.cpu3.dcache.overall_avg_mshr_miss_latency 16681.159420 # average overall mshr miss latency @@ -507,6 +521,8 @@ system.cpu3.icache.demand_mshr_misses 358 # nu system.cpu3.icache.fast_writes 0 # number of fast writes performed system.cpu3.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu3.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu3.icache.occ_%::0 0.136289 # Average percentage of cache occupancy +system.cpu3.icache.occ_blocks::0 69.779720 # Average occupied blocks per context system.cpu3.icache.overall_accesses 168396 # number of overall (read+write) accesses system.cpu3.icache.overall_avg_miss_latency 21104.748603 # average overall miss latency system.cpu3.icache.overall_avg_mshr_miss_latency 18103.351955 # average overall mshr miss latency @@ -533,37 +549,103 @@ system.cpu3.not_idle_fraction 0.865927 # Pe system.cpu3.numCycles 515096 # number of cpu cycles simulated system.cpu3.num_insts 168364 # Number of instructions executed system.cpu3.num_refs 46919 # Number of memory references -system.l2c.ReadExReq_accesses 136 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency +system.l2c.ReadExReq_accesses::0 12 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::1 12 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::2 99 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::3 13 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 136 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_avg_miss_latency::0 589333.333333 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::1 589333.333333 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::2 71434.343434 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::3 544000 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 1794101.010101 # average ReadExReq miss latency system.l2c.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency system.l2c.ReadExReq_miss_latency 7072000 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_misses 136 # number of ReadExReq misses +system.l2c.ReadExReq_miss_rate::0 1 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::1 1 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::2 1 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::3 1 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 4 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_misses::0 12 # number of ReadExReq misses +system.l2c.ReadExReq_misses::1 12 # number of ReadExReq misses +system.l2c.ReadExReq_misses::2 99 # number of ReadExReq misses +system.l2c.ReadExReq_misses::3 13 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 136 # number of ReadExReq misses system.l2c.ReadExReq_mshr_miss_latency 5440000 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::0 11.333333 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::1 11.333333 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::2 1.373737 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::3 10.461538 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 34.501943 # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_misses 136 # number of ReadExReq MSHR misses -system.l2c.ReadReq_accesses 1649 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_avg_miss_latency 51941.724942 # average ReadReq miss latency +system.l2c.ReadReq_accesses::0 370 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::1 371 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::2 538 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::3 370 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 1649 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_avg_miss_latency::0 3183285.714286 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::1 5570750 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::2 63484.330484 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::3 332582.089552 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 9150102.134322 # average ReadReq miss latency system.l2c.ReadReq_avg_mshr_miss_latency 40007.092199 # average ReadReq mshr miss latency -system.l2c.ReadReq_hits 1220 # number of ReadReq hits +system.l2c.ReadReq_hits::0 363 # number of ReadReq hits +system.l2c.ReadReq_hits::1 367 # number of ReadReq hits +system.l2c.ReadReq_hits::2 187 # number of ReadReq hits +system.l2c.ReadReq_hits::3 303 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1220 # number of ReadReq hits system.l2c.ReadReq_miss_latency 22283000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_rate 0.260158 # miss rate for ReadReq accesses -system.l2c.ReadReq_misses 429 # number of ReadReq misses +system.l2c.ReadReq_miss_rate::0 0.018919 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::1 0.010782 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::2 0.652416 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::3 0.181081 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.863198 # miss rate for ReadReq accesses +system.l2c.ReadReq_misses::0 7 # number of ReadReq misses +system.l2c.ReadReq_misses::1 4 # number of ReadReq misses +system.l2c.ReadReq_misses::2 351 # number of ReadReq misses +system.l2c.ReadReq_misses::3 67 # number of ReadReq misses +system.l2c.ReadReq_misses::total 429 # number of ReadReq misses system.l2c.ReadReq_mshr_hits 6 # number of ReadReq MSHR hits system.l2c.ReadReq_mshr_miss_latency 16923000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_rate 0.256519 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::0 1.143243 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::1 1.140162 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::2 0.786245 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::3 1.143243 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 4.212894 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_misses 423 # number of ReadReq MSHR misses -system.l2c.UpgradeReq_accesses 91 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_avg_miss_latency 11428.571429 # average UpgradeReq miss latency +system.l2c.UpgradeReq_accesses::0 16 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::1 16 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::2 47 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::3 12 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 91 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_avg_miss_latency::0 65000 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::1 65000 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::2 22127.659574 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::3 86666.666667 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 238794.326241 # average UpgradeReq miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency system.l2c.UpgradeReq_miss_latency 1040000 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_misses 91 # number of UpgradeReq misses +system.l2c.UpgradeReq_miss_rate::0 1 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::1 1 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::2 1 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::3 1 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 4 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_misses::0 16 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::1 16 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::2 47 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::3 12 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 91 # number of UpgradeReq misses system.l2c.UpgradeReq_mshr_miss_latency 3640000 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::0 5.687500 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::1 5.687500 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::2 1.936170 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::3 7.583333 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 20.894504 # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_misses 91 # number of UpgradeReq MSHR misses -system.l2c.Writeback_accesses 9 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_hits 9 # number of Writeback hits +system.l2c.Writeback_accesses::0 9 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 9 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_hits::0 9 # number of Writeback hits +system.l2c.Writeback_hits::total 9 # number of Writeback hits system.l2c.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.l2c.avg_refs 2.953883 # Average number of references to valid blocks. @@ -572,31 +654,89 @@ system.l2c.blocked::no_targets 0 # nu system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.demand_accesses 1785 # number of demand (read+write) accesses -system.l2c.demand_avg_miss_latency 51955.752212 # average overall miss latency +system.l2c.demand_accesses::0 382 # number of demand (read+write) accesses +system.l2c.demand_accesses::1 383 # number of demand (read+write) accesses +system.l2c.demand_accesses::2 637 # number of demand (read+write) accesses +system.l2c.demand_accesses::3 383 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 1785 # number of demand (read+write) accesses +system.l2c.demand_avg_miss_latency::0 1545000 # average overall miss latency +system.l2c.demand_avg_miss_latency::1 1834687.500000 # average overall miss latency +system.l2c.demand_avg_miss_latency::2 65233.333333 # average overall miss latency +system.l2c.demand_avg_miss_latency::3 366937.500000 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 3811858.333333 # average overall miss latency system.l2c.demand_avg_mshr_miss_latency 40005.366726 # average overall mshr miss latency -system.l2c.demand_hits 1220 # number of demand (read+write) hits +system.l2c.demand_hits::0 363 # number of demand (read+write) hits +system.l2c.demand_hits::1 367 # number of demand (read+write) hits +system.l2c.demand_hits::2 187 # number of demand (read+write) hits +system.l2c.demand_hits::3 303 # number of demand (read+write) hits +system.l2c.demand_hits::total 1220 # number of demand (read+write) hits system.l2c.demand_miss_latency 29355000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_rate 0.316527 # miss rate for demand accesses -system.l2c.demand_misses 565 # number of demand (read+write) misses +system.l2c.demand_miss_rate::0 0.049738 # miss rate for demand accesses +system.l2c.demand_miss_rate::1 0.041775 # miss rate for demand accesses +system.l2c.demand_miss_rate::2 0.706436 # miss rate for demand accesses +system.l2c.demand_miss_rate::3 0.208877 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 1.006827 # miss rate for demand accesses +system.l2c.demand_misses::0 19 # number of demand (read+write) misses +system.l2c.demand_misses::1 16 # number of demand (read+write) misses +system.l2c.demand_misses::2 450 # number of demand (read+write) misses +system.l2c.demand_misses::3 80 # number of demand (read+write) misses +system.l2c.demand_misses::total 565 # number of demand (read+write) misses system.l2c.demand_mshr_hits 6 # number of demand (read+write) MSHR hits system.l2c.demand_mshr_miss_latency 22363000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_rate 0.313165 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::0 1.463351 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::1 1.459530 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::2 0.877551 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::3 1.459530 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 5.259962 # mshr miss rate for demand accesses system.l2c.demand_mshr_misses 559 # number of demand (read+write) MSHR misses system.l2c.fast_writes 0 # number of fast writes performed system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.overall_accesses 1785 # number of overall (read+write) accesses -system.l2c.overall_avg_miss_latency 51955.752212 # average overall miss latency +system.l2c.occ_%::0 0.000040 # Average percentage of cache occupancy +system.l2c.occ_%::1 0.000026 # Average percentage of cache occupancy +system.l2c.occ_%::2 0.004171 # Average percentage of cache occupancy +system.l2c.occ_%::3 0.000879 # Average percentage of cache occupancy +system.l2c.occ_%::4 0.000085 # Average percentage of cache occupancy +system.l2c.occ_blocks::0 2.602775 # Average occupied blocks per context +system.l2c.occ_blocks::1 1.727475 # Average occupied blocks per context +system.l2c.occ_blocks::2 273.330650 # Average occupied blocks per context +system.l2c.occ_blocks::3 57.582989 # Average occupied blocks per context +system.l2c.occ_blocks::4 5.583152 # Average occupied blocks per context +system.l2c.overall_accesses::0 382 # number of overall (read+write) accesses +system.l2c.overall_accesses::1 383 # number of overall (read+write) accesses +system.l2c.overall_accesses::2 637 # number of overall (read+write) accesses +system.l2c.overall_accesses::3 383 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 1785 # number of overall (read+write) accesses +system.l2c.overall_avg_miss_latency::0 1545000 # average overall miss latency +system.l2c.overall_avg_miss_latency::1 1834687.500000 # average overall miss latency +system.l2c.overall_avg_miss_latency::2 65233.333333 # average overall miss latency +system.l2c.overall_avg_miss_latency::3 366937.500000 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 3811858.333333 # average overall miss latency system.l2c.overall_avg_mshr_miss_latency 40005.366726 # average overall mshr miss latency system.l2c.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.l2c.overall_hits 1220 # number of overall hits +system.l2c.overall_hits::0 363 # number of overall hits +system.l2c.overall_hits::1 367 # number of overall hits +system.l2c.overall_hits::2 187 # number of overall hits +system.l2c.overall_hits::3 303 # number of overall hits +system.l2c.overall_hits::total 1220 # number of overall hits system.l2c.overall_miss_latency 29355000 # number of overall miss cycles -system.l2c.overall_miss_rate 0.316527 # miss rate for overall accesses -system.l2c.overall_misses 565 # number of overall misses +system.l2c.overall_miss_rate::0 0.049738 # miss rate for overall accesses +system.l2c.overall_miss_rate::1 0.041775 # miss rate for overall accesses +system.l2c.overall_miss_rate::2 0.706436 # miss rate for overall accesses +system.l2c.overall_miss_rate::3 0.208877 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 1.006827 # miss rate for overall accesses +system.l2c.overall_misses::0 19 # number of overall misses +system.l2c.overall_misses::1 16 # number of overall misses +system.l2c.overall_misses::2 450 # number of overall misses +system.l2c.overall_misses::3 80 # number of overall misses +system.l2c.overall_misses::total 565 # number of overall misses system.l2c.overall_mshr_hits 6 # number of overall MSHR hits system.l2c.overall_mshr_miss_latency 22363000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_rate 0.313165 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::0 1.463351 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::1 1.459530 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::2 0.877551 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::3 1.459530 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 5.259962 # mshr miss rate for overall accesses system.l2c.overall_mshr_misses 559 # number of overall MSHR misses system.l2c.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses |