diff options
Diffstat (limited to 'tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp')
4 files changed, 26 insertions, 18 deletions
diff --git a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/config.ini b/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/config.ini index 2570db111..ae7e021b5 100644 --- a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/config.ini +++ b/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/config.ini @@ -9,6 +9,8 @@ time_sync_spin_threshold=100000000 type=System children=cpu0 cpu1 cpu2 cpu3 l2c membus physmem toL2Bus mem_mode=timing +memories=system.physmem +num_work_ids=16 physmem=system.physmem work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 @@ -17,6 +19,7 @@ work_cpus_ckpt_count=0 work_end_ckpt_count=0 work_end_exit_count=0 work_item_id=-1 +system_port=system.membus.port[1] [system.cpu0] type=TimingSimpleCPU @@ -127,7 +130,7 @@ egid=100 env= errout=cerr euid=100 -executable=/chips/pd/randd/dist/test-progs/m5threads/bin/sparc/linux/test_atomic +executable=/dist/m5/regression/test-progs/m5threads/bin/sparc/linux/test_atomic gid=100 input=cin max_stack_size=67108864 @@ -481,7 +484,7 @@ clock=1000 header_cycles=1 use_default_range=false width=64 -port=system.l2c.mem_side system.physmem.port[0] +port=system.l2c.mem_side system.system_port system.physmem.port[0] [system.physmem] type=PhysicalMemory @@ -491,7 +494,7 @@ latency_var=0 null=false range=0:134217727 zero=false -port=system.membus.port[1] +port=system.membus.port[2] [system.toL2Bus] type=Bus diff --git a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/simerr b/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/simerr index eabe42249..e45cd058f 100755 --- a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/simerr +++ b/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/simerr @@ -1,3 +1,2 @@ warn: Sockets disabled, not accepting gdb connections -For more information see: http://www.m5sim.org/warn/d946bea6 hack: be nice to actually delete the event here diff --git a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/simout b/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/simout index 6949b715b..6f90c0dd1 100755 --- a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/simout +++ b/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/simout @@ -1,14 +1,10 @@ -M5 Simulator System +gem5 Simulator System. http://gem5.org +gem5 is copyrighted software; use the --copyright option for details. -Copyright (c) 2001-2008 -The Regents of The University of Michigan -All Rights Reserved - - -M5 compiled May 1 2011 16:25:10 -M5 started May 1 2011 16:26:16 -M5 executing on u200439-lin.austin.arm.com -command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/40.m5threads-test-atomic/sparc/linux/simple-timing-mp -re tests/run.py build/SPARC_SE/tests/fast/quick/40.m5threads-test-atomic/sparc/linux/simple-timing-mp +gem5 compiled Jan 23 2012 04:02:00 +gem5 started Jan 23 2012 04:24:33 +gem5 executing on zizzer +command line: build/SPARC_SE/gem5.opt -d build/SPARC_SE/tests/opt/quick/40.m5threads-test-atomic/sparc/linux/simple-timing-mp -re tests/run.py build/SPARC_SE/tests/opt/quick/40.m5threads-test-atomic/sparc/linux/simple-timing-mp Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... Init done diff --git a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt b/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt index e12a86eb8..0ce3fe3af 100644 --- a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt +++ b/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt @@ -2,12 +2,22 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000262 # Number of seconds simulated sim_ticks 262298000 # Number of ticks simulated +final_tick 262298000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 557035 # Simulator instruction rate (inst/s) -host_tick_rate 220601847 # Simulator tick rate (ticks/s) -host_mem_usage 235124 # Number of bytes of host memory used -host_seconds 1.19 # Real time elapsed on the host +host_inst_rate 1158712 # Simulator instruction rate (inst/s) +host_tick_rate 458877844 # Simulator tick rate (ticks/s) +host_mem_usage 222944 # Number of bytes of host memory used +host_seconds 0.57 # Real time elapsed on the host sim_insts 662307 # Number of instructions simulated +system.physmem.bytes_read 36608 # Number of bytes read from this memory +system.physmem.bytes_inst_read 22656 # Number of instructions bytes read from this memory +system.physmem.bytes_written 0 # Number of bytes written to this memory +system.physmem.num_reads 572 # Number of read requests responded to by this memory +system.physmem.num_writes 0 # Number of write requests responded to by this memory +system.physmem.num_other 0 # Number of other requests responded to by this memory +system.physmem.bw_read 139566447 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read 86375039 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total 139566447 # Total bandwidth to/from this memory (bytes/s) system.cpu0.workload.num_syscalls 89 # Number of system calls system.cpu0.numCycles 524596 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started |