diff options
Diffstat (limited to 'tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/stats.txt')
| -rw-r--r-- | tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/stats.txt | 42 |
1 files changed, 21 insertions, 21 deletions
diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/stats.txt b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/stats.txt index 977e6ebbe..9b0c24527 100644 --- a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/stats.txt +++ b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/stats.txt @@ -1,34 +1,34 @@ ---------- Begin Simulation Statistics ---------- -host_mem_usage 1501368 # Number of bytes of host memory used -host_seconds 892.41 # Real time elapsed on the host -host_tick_rate 35514 # Simulator tick rate (ticks/s) +host_mem_usage 2438776 # Number of bytes of host memory used +host_seconds 3924.24 # Real time elapsed on the host +host_tick_rate 15406 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_seconds 0.000032 # Number of seconds simulated -sim_ticks 31693010 # Number of ticks simulated +sim_seconds 0.000060 # Number of seconds simulated +sim_ticks 60455258 # Number of ticks simulated system.cpu0.num_copies 0 # number of copy accesses completed -system.cpu0.num_reads 99568 # number of read accesses completed -system.cpu0.num_writes 53636 # number of write accesses completed +system.cpu0.num_reads 99982 # number of read accesses completed +system.cpu0.num_writes 53168 # number of write accesses completed system.cpu1.num_copies 0 # number of copy accesses completed -system.cpu1.num_reads 99545 # number of read accesses completed -system.cpu1.num_writes 53439 # number of write accesses completed +system.cpu1.num_reads 100000 # number of read accesses completed +system.cpu1.num_writes 53657 # number of write accesses completed system.cpu2.num_copies 0 # number of copy accesses completed -system.cpu2.num_reads 99287 # number of read accesses completed -system.cpu2.num_writes 53468 # number of write accesses completed +system.cpu2.num_reads 99758 # number of read accesses completed +system.cpu2.num_writes 53630 # number of write accesses completed system.cpu3.num_copies 0 # number of copy accesses completed -system.cpu3.num_reads 100000 # number of read accesses completed -system.cpu3.num_writes 53560 # number of write accesses completed +system.cpu3.num_reads 99707 # number of read accesses completed +system.cpu3.num_writes 53628 # number of write accesses completed system.cpu4.num_copies 0 # number of copy accesses completed -system.cpu4.num_reads 99582 # number of read accesses completed -system.cpu4.num_writes 53929 # number of write accesses completed +system.cpu4.num_reads 99425 # number of read accesses completed +system.cpu4.num_writes 53969 # number of write accesses completed system.cpu5.num_copies 0 # number of copy accesses completed -system.cpu5.num_reads 99543 # number of read accesses completed -system.cpu5.num_writes 53703 # number of write accesses completed +system.cpu5.num_reads 99810 # number of read accesses completed +system.cpu5.num_writes 53444 # number of write accesses completed system.cpu6.num_copies 0 # number of copy accesses completed -system.cpu6.num_reads 99253 # number of read accesses completed -system.cpu6.num_writes 53497 # number of write accesses completed +system.cpu6.num_reads 99532 # number of read accesses completed +system.cpu6.num_writes 53907 # number of write accesses completed system.cpu7.num_copies 0 # number of copy accesses completed -system.cpu7.num_reads 99640 # number of read accesses completed -system.cpu7.num_writes 53676 # number of write accesses completed +system.cpu7.num_reads 99819 # number of read accesses completed +system.cpu7.num_writes 53668 # number of write accesses completed ---------- End Simulation Statistics ---------- |