summaryrefslogtreecommitdiff
path: root/tests/quick/50.memtest/ref
diff options
context:
space:
mode:
Diffstat (limited to 'tests/quick/50.memtest/ref')
-rw-r--r--tests/quick/50.memtest/ref/alpha/linux/memtest/config.ini29
-rw-r--r--tests/quick/50.memtest/ref/alpha/linux/memtest/config.out29
-rw-r--r--tests/quick/50.memtest/ref/alpha/linux/memtest/m5stats.txt1260
-rw-r--r--tests/quick/50.memtest/ref/alpha/linux/memtest/stderr146
-rw-r--r--tests/quick/50.memtest/ref/alpha/linux/memtest/stdout8
5 files changed, 729 insertions, 743 deletions
diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest/config.ini b/tests/quick/50.memtest/ref/alpha/linux/memtest/config.ini
index 363cb64d4..bf66a6947 100644
--- a/tests/quick/50.memtest/ref/alpha/linux/memtest/config.ini
+++ b/tests/quick/50.memtest/ref/alpha/linux/memtest/config.ini
@@ -34,8 +34,7 @@ block_size=64
compressed_bus=false
compression_latency=0
hash_delay=1
-hit_latency=1
-latency=1
+latency=1000
lifo=false
max_miss_count=0
mshrs=12
@@ -95,8 +94,7 @@ block_size=64
compressed_bus=false
compression_latency=0
hash_delay=1
-hit_latency=1
-latency=1
+latency=1000
lifo=false
max_miss_count=0
mshrs=12
@@ -156,8 +154,7 @@ block_size=64
compressed_bus=false
compression_latency=0
hash_delay=1
-hit_latency=1
-latency=1
+latency=1000
lifo=false
max_miss_count=0
mshrs=12
@@ -217,8 +214,7 @@ block_size=64
compressed_bus=false
compression_latency=0
hash_delay=1
-hit_latency=1
-latency=1
+latency=1000
lifo=false
max_miss_count=0
mshrs=12
@@ -278,8 +274,7 @@ block_size=64
compressed_bus=false
compression_latency=0
hash_delay=1
-hit_latency=1
-latency=1
+latency=1000
lifo=false
max_miss_count=0
mshrs=12
@@ -339,8 +334,7 @@ block_size=64
compressed_bus=false
compression_latency=0
hash_delay=1
-hit_latency=1
-latency=1
+latency=1000
lifo=false
max_miss_count=0
mshrs=12
@@ -400,8 +394,7 @@ block_size=64
compressed_bus=false
compression_latency=0
hash_delay=1
-hit_latency=1
-latency=1
+latency=1000
lifo=false
max_miss_count=0
mshrs=12
@@ -461,8 +454,7 @@ block_size=64
compressed_bus=false
compression_latency=0
hash_delay=1
-hit_latency=1
-latency=1
+latency=1000
lifo=false
max_miss_count=0
mshrs=12
@@ -514,8 +506,7 @@ block_size=64
compressed_bus=false
compression_latency=0
hash_delay=1
-hit_latency=1
-latency=10
+latency=10000
lifo=false
max_miss_count=0
mshrs=92
@@ -547,6 +538,7 @@ mem_side=system.membus.port[0]
[system.membus]
type=Bus
+block_size=64
bus_id=0
clock=2
responder_set=false
@@ -563,6 +555,7 @@ port=system.membus.port[1]
[system.toL2Bus]
type=Bus
+block_size=64
bus_id=0
clock=2
responder_set=false
diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest/config.out b/tests/quick/50.memtest/ref/alpha/linux/memtest/config.out
index b3f4ec871..53f718c0d 100644
--- a/tests/quick/50.memtest/ref/alpha/linux/memtest/config.out
+++ b/tests/quick/50.memtest/ref/alpha/linux/memtest/config.out
@@ -20,13 +20,14 @@ bus_id=0
clock=2
width=16
responder_set=false
+block_size=64
[system.l2c]
type=BaseCache
size=65536
assoc=8
block_size=64
-latency=10
+latency=10000
mshrs=92
tgts_per_mshr=16
write_buffers=8
@@ -57,7 +58,6 @@ prefetch_policy=none
prefetch_cache_check_push=true
prefetch_use_cpu_id=true
prefetch_data_accesses_only=false
-hit_latency=1
[system.cpu6]
type=MemTest
@@ -82,7 +82,7 @@ type=BaseCache
size=32768
assoc=4
block_size=64
-latency=1
+latency=1000
mshrs=12
tgts_per_mshr=8
write_buffers=8
@@ -113,7 +113,6 @@ prefetch_policy=none
prefetch_cache_check_push=true
prefetch_use_cpu_id=true
prefetch_data_accesses_only=false
-hit_latency=1
[system.cpu4]
type=MemTest
@@ -138,7 +137,7 @@ type=BaseCache
size=32768
assoc=4
block_size=64
-latency=1
+latency=1000
mshrs=12
tgts_per_mshr=8
write_buffers=8
@@ -169,7 +168,6 @@ prefetch_policy=none
prefetch_cache_check_push=true
prefetch_use_cpu_id=true
prefetch_data_accesses_only=false
-hit_latency=1
[system.cpu5]
type=MemTest
@@ -194,7 +192,7 @@ type=BaseCache
size=32768
assoc=4
block_size=64
-latency=1
+latency=1000
mshrs=12
tgts_per_mshr=8
write_buffers=8
@@ -225,7 +223,6 @@ prefetch_policy=none
prefetch_cache_check_push=true
prefetch_use_cpu_id=true
prefetch_data_accesses_only=false
-hit_latency=1
[system.cpu2]
type=MemTest
@@ -250,7 +247,7 @@ type=BaseCache
size=32768
assoc=4
block_size=64
-latency=1
+latency=1000
mshrs=12
tgts_per_mshr=8
write_buffers=8
@@ -281,7 +278,6 @@ prefetch_policy=none
prefetch_cache_check_push=true
prefetch_use_cpu_id=true
prefetch_data_accesses_only=false
-hit_latency=1
[system.cpu3]
type=MemTest
@@ -306,7 +302,7 @@ type=BaseCache
size=32768
assoc=4
block_size=64
-latency=1
+latency=1000
mshrs=12
tgts_per_mshr=8
write_buffers=8
@@ -337,7 +333,6 @@ prefetch_policy=none
prefetch_cache_check_push=true
prefetch_use_cpu_id=true
prefetch_data_accesses_only=false
-hit_latency=1
[system.cpu0]
type=MemTest
@@ -362,7 +357,7 @@ type=BaseCache
size=32768
assoc=4
block_size=64
-latency=1
+latency=1000
mshrs=12
tgts_per_mshr=8
write_buffers=8
@@ -393,7 +388,6 @@ prefetch_policy=none
prefetch_cache_check_push=true
prefetch_use_cpu_id=true
prefetch_data_accesses_only=false
-hit_latency=1
[system.cpu1]
type=MemTest
@@ -418,7 +412,7 @@ type=BaseCache
size=32768
assoc=4
block_size=64
-latency=1
+latency=1000
mshrs=12
tgts_per_mshr=8
write_buffers=8
@@ -449,7 +443,6 @@ prefetch_policy=none
prefetch_cache_check_push=true
prefetch_use_cpu_id=true
prefetch_data_accesses_only=false
-hit_latency=1
[system.funcmem]
type=PhysicalMemory
@@ -481,7 +474,7 @@ type=BaseCache
size=32768
assoc=4
block_size=64
-latency=1
+latency=1000
mshrs=12
tgts_per_mshr=8
write_buffers=8
@@ -512,7 +505,6 @@ prefetch_policy=none
prefetch_cache_check_push=true
prefetch_use_cpu_id=true
prefetch_data_accesses_only=false
-hit_latency=1
[system.toL2Bus]
type=Bus
@@ -520,4 +512,5 @@ bus_id=0
clock=2
width=16
responder_set=false
+block_size=64
diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest/m5stats.txt b/tests/quick/50.memtest/ref/alpha/linux/memtest/m5stats.txt
index 285ab3702..2617dd49e 100644
--- a/tests/quick/50.memtest/ref/alpha/linux/memtest/m5stats.txt
+++ b/tests/quick/50.memtest/ref/alpha/linux/memtest/m5stats.txt
@@ -1,73 +1,73 @@
---------- Begin Simulation Statistics ----------
-host_mem_usage 303680 # Number of bytes of host memory used
-host_seconds 32.50 # Real time elapsed on the host
-host_tick_rate 177110 # Simulator tick rate (ticks/s)
+host_mem_usage 1265676 # Number of bytes of host memory used
+host_seconds 390.60 # Real time elapsed on the host
+host_tick_rate 215953 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
-sim_seconds 0.000006 # Number of seconds simulated
-sim_ticks 5755736 # Number of ticks simulated
-system.cpu0.l1c.ReadReq_accesses 45048 # number of ReadReq accesses(hits+misses)
-system.cpu0.l1c.ReadReq_avg_miss_latency 959.688548 # average ReadReq miss latency
-system.cpu0.l1c.ReadReq_avg_mshr_miss_latency 884.132516 # average ReadReq mshr miss latency
-system.cpu0.l1c.ReadReq_hits 7543 # number of ReadReq hits
-system.cpu0.l1c.ReadReq_miss_latency 35993119 # number of ReadReq miss cycles
-system.cpu0.l1c.ReadReq_miss_rate 0.832556 # miss rate for ReadReq accesses
-system.cpu0.l1c.ReadReq_misses 37505 # number of ReadReq misses
-system.cpu0.l1c.ReadReq_mshr_miss_latency 33159390 # number of ReadReq MSHR miss cycles
-system.cpu0.l1c.ReadReq_mshr_miss_rate 0.832556 # mshr miss rate for ReadReq accesses
-system.cpu0.l1c.ReadReq_mshr_misses 37505 # number of ReadReq MSHR misses
-system.cpu0.l1c.ReadReq_mshr_uncacheable 9815 # number of ReadReq MSHR uncacheable
+sim_seconds 0.000084 # Number of seconds simulated
+sim_ticks 84350509 # Number of ticks simulated
+system.cpu0.l1c.ReadReq_accesses 44421 # number of ReadReq accesses(hits+misses)
+system.cpu0.l1c.ReadReq_avg_miss_latency 14010.391786 # average ReadReq miss latency
+system.cpu0.l1c.ReadReq_avg_mshr_miss_latency 12986.475734 # average ReadReq mshr miss latency
+system.cpu0.l1c.ReadReq_hits 7291 # number of ReadReq hits
+system.cpu0.l1c.ReadReq_miss_latency 520205847 # number of ReadReq miss cycles
+system.cpu0.l1c.ReadReq_miss_rate 0.835866 # miss rate for ReadReq accesses
+system.cpu0.l1c.ReadReq_misses 37130 # number of ReadReq misses
+system.cpu0.l1c.ReadReq_mshr_miss_latency 482187844 # number of ReadReq MSHR miss cycles
+system.cpu0.l1c.ReadReq_mshr_miss_rate 0.835866 # mshr miss rate for ReadReq accesses
+system.cpu0.l1c.ReadReq_mshr_misses 37130 # number of ReadReq MSHR misses
+system.cpu0.l1c.ReadReq_mshr_uncacheable 9916 # number of ReadReq MSHR uncacheable
system.cpu0.l1c.ReadResp_avg_mshr_uncacheable_latency inf # average ReadResp mshr uncacheable latency
-system.cpu0.l1c.ReadResp_mshr_uncacheable_latency 17521633 # number of ReadResp MSHR uncacheable cycles
-system.cpu0.l1c.WriteReq_accesses 24308 # number of WriteReq accesses(hits+misses)
-system.cpu0.l1c.WriteReq_avg_miss_latency 862.246942 # average WriteReq miss latency
-system.cpu0.l1c.WriteReq_avg_mshr_miss_latency 778.821396 # average WriteReq mshr miss latency
-system.cpu0.l1c.WriteReq_hits 1173 # number of WriteReq hits
-system.cpu0.l1c.WriteReq_miss_latency 19948083 # number of WriteReq miss cycles
-system.cpu0.l1c.WriteReq_miss_rate 0.951744 # miss rate for WriteReq accesses
-system.cpu0.l1c.WriteReq_misses 23135 # number of WriteReq misses
-system.cpu0.l1c.WriteReq_mshr_miss_latency 18018033 # number of WriteReq MSHR miss cycles
-system.cpu0.l1c.WriteReq_mshr_miss_rate 0.951744 # mshr miss rate for WriteReq accesses
-system.cpu0.l1c.WriteReq_mshr_misses 23135 # number of WriteReq MSHR misses
-system.cpu0.l1c.WriteReq_mshr_uncacheable 5428 # number of WriteReq MSHR uncacheable
+system.cpu0.l1c.ReadResp_mshr_uncacheable_latency 255520881 # number of ReadResp MSHR uncacheable cycles
+system.cpu0.l1c.WriteReq_accesses 23898 # number of WriteReq accesses(hits+misses)
+system.cpu0.l1c.WriteReq_avg_miss_latency 12904.605270 # average WriteReq miss latency
+system.cpu0.l1c.WriteReq_avg_mshr_miss_latency 11399.917485 # average WriteReq mshr miss latency
+system.cpu0.l1c.WriteReq_hits 1090 # number of WriteReq hits
+system.cpu0.l1c.WriteReq_miss_latency 294328237 # number of WriteReq miss cycles
+system.cpu0.l1c.WriteReq_miss_rate 0.954389 # miss rate for WriteReq accesses
+system.cpu0.l1c.WriteReq_misses 22808 # number of WriteReq misses
+system.cpu0.l1c.WriteReq_mshr_miss_latency 260009318 # number of WriteReq MSHR miss cycles
+system.cpu0.l1c.WriteReq_mshr_miss_rate 0.954389 # mshr miss rate for WriteReq accesses
+system.cpu0.l1c.WriteReq_mshr_misses 22808 # number of WriteReq MSHR misses
+system.cpu0.l1c.WriteReq_mshr_uncacheable 5184 # number of WriteReq MSHR uncacheable
system.cpu0.l1c.WriteResp_avg_mshr_uncacheable_latency inf # average WriteResp mshr uncacheable latency
-system.cpu0.l1c.WriteResp_mshr_uncacheable_latency 10755873 # number of WriteResp MSHR uncacheable cycles
-system.cpu0.l1c.avg_blocked_cycles_no_mshrs 81.366905 # average number of cycles each access was blocked
+system.cpu0.l1c.WriteResp_mshr_uncacheable_latency 154702333 # number of WriteResp MSHR uncacheable cycles
+system.cpu0.l1c.avg_blocked_cycles_no_mshrs 1194.948852 # average number of cycles each access was blocked
system.cpu0.l1c.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
-system.cpu0.l1c.avg_refs 0.417208 # Average number of references to valid blocks.
-system.cpu0.l1c.blocked_no_mshrs 69811 # number of cycles access was blocked
+system.cpu0.l1c.avg_refs 0.407238 # Average number of references to valid blocks.
+system.cpu0.l1c.blocked_no_mshrs 69093 # number of cycles access was blocked
system.cpu0.l1c.blocked_no_targets 0 # number of cycles access was blocked
-system.cpu0.l1c.blocked_cycles_no_mshrs 5680305 # number of cycles access was blocked
+system.cpu0.l1c.blocked_cycles_no_mshrs 82562601 # number of cycles access was blocked
system.cpu0.l1c.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu0.l1c.cache_copies 0 # number of cache copies performed
-system.cpu0.l1c.demand_accesses 69356 # number of demand (read+write) accesses
-system.cpu0.l1c.demand_avg_miss_latency 922.513226 # average overall miss latency
-system.cpu0.l1c.demand_avg_mshr_miss_latency 843.954865 # average overall mshr miss latency
-system.cpu0.l1c.demand_hits 8716 # number of demand (read+write) hits
-system.cpu0.l1c.demand_miss_latency 55941202 # number of demand (read+write) miss cycles
-system.cpu0.l1c.demand_miss_rate 0.874330 # miss rate for demand accesses
-system.cpu0.l1c.demand_misses 60640 # number of demand (read+write) misses
+system.cpu0.l1c.demand_accesses 68319 # number of demand (read+write) accesses
+system.cpu0.l1c.demand_avg_miss_latency 13589.610664 # average overall miss latency
+system.cpu0.l1c.demand_avg_mshr_miss_latency 12382.748206 # average overall mshr miss latency
+system.cpu0.l1c.demand_hits 8381 # number of demand (read+write) hits
+system.cpu0.l1c.demand_miss_latency 814534084 # number of demand (read+write) miss cycles
+system.cpu0.l1c.demand_miss_rate 0.877325 # miss rate for demand accesses
+system.cpu0.l1c.demand_misses 59938 # number of demand (read+write) misses
system.cpu0.l1c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu0.l1c.demand_mshr_miss_latency 51177423 # number of demand (read+write) MSHR miss cycles
-system.cpu0.l1c.demand_mshr_miss_rate 0.874330 # mshr miss rate for demand accesses
-system.cpu0.l1c.demand_mshr_misses 60640 # number of demand (read+write) MSHR misses
+system.cpu0.l1c.demand_mshr_miss_latency 742197162 # number of demand (read+write) MSHR miss cycles
+system.cpu0.l1c.demand_mshr_miss_rate 0.877325 # mshr miss rate for demand accesses
+system.cpu0.l1c.demand_mshr_misses 59938 # number of demand (read+write) MSHR misses
system.cpu0.l1c.fast_writes 0 # number of fast writes performed
system.cpu0.l1c.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu0.l1c.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu0.l1c.overall_accesses 69356 # number of overall (read+write) accesses
-system.cpu0.l1c.overall_avg_miss_latency 922.513226 # average overall miss latency
-system.cpu0.l1c.overall_avg_mshr_miss_latency 843.954865 # average overall mshr miss latency
+system.cpu0.l1c.overall_accesses 68319 # number of overall (read+write) accesses
+system.cpu0.l1c.overall_avg_miss_latency 13589.610664 # average overall miss latency
+system.cpu0.l1c.overall_avg_mshr_miss_latency 12382.748206 # average overall mshr miss latency
system.cpu0.l1c.overall_avg_mshr_uncacheable_latency 0 # average overall mshr uncacheable latency
-system.cpu0.l1c.overall_hits 8716 # number of overall hits
-system.cpu0.l1c.overall_miss_latency 55941202 # number of overall miss cycles
-system.cpu0.l1c.overall_miss_rate 0.874330 # miss rate for overall accesses
-system.cpu0.l1c.overall_misses 60640 # number of overall misses
+system.cpu0.l1c.overall_hits 8381 # number of overall hits
+system.cpu0.l1c.overall_miss_latency 814534084 # number of overall miss cycles
+system.cpu0.l1c.overall_miss_rate 0.877325 # miss rate for overall accesses
+system.cpu0.l1c.overall_misses 59938 # number of overall misses
system.cpu0.l1c.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu0.l1c.overall_mshr_miss_latency 51177423 # number of overall MSHR miss cycles
-system.cpu0.l1c.overall_mshr_miss_rate 0.874330 # mshr miss rate for overall accesses
-system.cpu0.l1c.overall_mshr_misses 60640 # number of overall MSHR misses
+system.cpu0.l1c.overall_mshr_miss_latency 742197162 # number of overall MSHR miss cycles
+system.cpu0.l1c.overall_mshr_miss_rate 0.877325 # mshr miss rate for overall accesses
+system.cpu0.l1c.overall_mshr_misses 59938 # number of overall MSHR misses
system.cpu0.l1c.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu0.l1c.overall_mshr_uncacheable_misses 15243 # number of overall MSHR uncacheable misses
+system.cpu0.l1c.overall_mshr_uncacheable_misses 15100 # number of overall MSHR uncacheable misses
system.cpu0.l1c.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
system.cpu0.l1c.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
system.cpu0.l1c.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
@@ -78,103 +78,103 @@ system.cpu0.l1c.prefetcher.num_hwpf_removed_MSHR_hit 0
system.cpu0.l1c.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu0.l1c.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
system.cpu0.l1c.protocol.hwpf_invalid 0 # hard prefetch misses to invalid blocks
-system.cpu0.l1c.protocol.read_invalid 109554 # read misses to invalid blocks
+system.cpu0.l1c.protocol.read_invalid 1761660 # read misses to invalid blocks
system.cpu0.l1c.protocol.snoop_inv_exclusive 0 # Invalidate snoops on exclusive blocks
system.cpu0.l1c.protocol.snoop_inv_invalid 0 # Invalidate snoops on invalid blocks
system.cpu0.l1c.protocol.snoop_inv_modified 0 # Invalidate snoops on modified blocks
system.cpu0.l1c.protocol.snoop_inv_owned 0 # Invalidate snoops on owned blocks
system.cpu0.l1c.protocol.snoop_inv_shared 0 # Invalidate snoops on shared blocks
-system.cpu0.l1c.protocol.snoop_read_exclusive 2807 # read snoops on exclusive blocks
-system.cpu0.l1c.protocol.snoop_read_modified 12380 # read snoops on modified blocks
-system.cpu0.l1c.protocol.snoop_read_owned 7157 # read snoops on owned blocks
-system.cpu0.l1c.protocol.snoop_read_shared 22767 # read snoops on shared blocks
-system.cpu0.l1c.protocol.snoop_readex_exclusive 1535 # readEx snoops on exclusive blocks
-system.cpu0.l1c.protocol.snoop_readex_modified 6851 # readEx snoops on modified blocks
-system.cpu0.l1c.protocol.snoop_readex_owned 3877 # readEx snoops on owned blocks
-system.cpu0.l1c.protocol.snoop_readex_shared 12465 # readEx snoops on shared blocks
-system.cpu0.l1c.protocol.snoop_upgrade_owned 887 # upgrade snoops on owned blocks
-system.cpu0.l1c.protocol.snoop_upgrade_shared 2994 # upgradee snoops on shared blocks
+system.cpu0.l1c.protocol.snoop_read_exclusive 2836 # read snoops on exclusive blocks
+system.cpu0.l1c.protocol.snoop_read_modified 12378 # read snoops on modified blocks
+system.cpu0.l1c.protocol.snoop_read_owned 7300 # read snoops on owned blocks
+system.cpu0.l1c.protocol.snoop_read_shared 1749577 # read snoops on shared blocks
+system.cpu0.l1c.protocol.snoop_readex_exclusive 1616 # readEx snoops on exclusive blocks
+system.cpu0.l1c.protocol.snoop_readex_modified 6692 # readEx snoops on modified blocks
+system.cpu0.l1c.protocol.snoop_readex_owned 4009 # readEx snoops on owned blocks
+system.cpu0.l1c.protocol.snoop_readex_shared 12550 # readEx snoops on shared blocks
+system.cpu0.l1c.protocol.snoop_upgrade_owned 790 # upgrade snoops on owned blocks
+system.cpu0.l1c.protocol.snoop_upgrade_shared 3004 # upgradee snoops on shared blocks
system.cpu0.l1c.protocol.snoop_writeinv_exclusive 0 # WriteInvalidate snoops on exclusive blocks
system.cpu0.l1c.protocol.snoop_writeinv_invalid 0 # WriteInvalidate snoops on invalid blocks
system.cpu0.l1c.protocol.snoop_writeinv_modified 0 # WriteInvalidate snoops on modified blocks
system.cpu0.l1c.protocol.snoop_writeinv_owned 0 # WriteInvalidate snoops on owned blocks
system.cpu0.l1c.protocol.snoop_writeinv_shared 0 # WriteInvalidate snoops on shared blocks
system.cpu0.l1c.protocol.swpf_invalid 0 # soft prefetch misses to invalid blocks
-system.cpu0.l1c.protocol.write_invalid 60706 # write misses to invalid blocks
-system.cpu0.l1c.protocol.write_owned 1361 # write misses to owned blocks
-system.cpu0.l1c.protocol.write_shared 4416 # write misses to shared blocks
-system.cpu0.l1c.replacements 27529 # number of replacements
-system.cpu0.l1c.sampled_refs 27883 # Sample count of references to valid blocks.
+system.cpu0.l1c.protocol.write_invalid 940728 # write misses to invalid blocks
+system.cpu0.l1c.protocol.write_owned 1344 # write misses to owned blocks
+system.cpu0.l1c.protocol.write_shared 4484 # write misses to shared blocks
+system.cpu0.l1c.replacements 27160 # number of replacements
+system.cpu0.l1c.sampled_refs 27495 # Sample count of references to valid blocks.
system.cpu0.l1c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu0.l1c.tagsinuse 342.460043 # Cycle average of tags in use
-system.cpu0.l1c.total_refs 11633 # Total number of references to valid blocks.
+system.cpu0.l1c.tagsinuse 342.709273 # Cycle average of tags in use
+system.cpu0.l1c.total_refs 11197 # Total number of references to valid blocks.
system.cpu0.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu0.l1c.writebacks 10915 # number of writebacks
+system.cpu0.l1c.writebacks 10716 # number of writebacks
system.cpu0.num_copies 0 # number of copy accesses completed
-system.cpu0.num_reads 99586 # number of read accesses completed
-system.cpu0.num_writes 53803 # number of write accesses completed
-system.cpu1.l1c.ReadReq_accesses 44416 # number of ReadReq accesses(hits+misses)
-system.cpu1.l1c.ReadReq_avg_miss_latency 969.343786 # average ReadReq miss latency
-system.cpu1.l1c.ReadReq_avg_mshr_miss_latency 893.327484 # average ReadReq mshr miss latency
-system.cpu1.l1c.ReadReq_hits 7486 # number of ReadReq hits
-system.cpu1.l1c.ReadReq_miss_latency 35797866 # number of ReadReq miss cycles
-system.cpu1.l1c.ReadReq_miss_rate 0.831457 # miss rate for ReadReq accesses
-system.cpu1.l1c.ReadReq_misses 36930 # number of ReadReq misses
-system.cpu1.l1c.ReadReq_mshr_miss_latency 32990584 # number of ReadReq MSHR miss cycles
-system.cpu1.l1c.ReadReq_mshr_miss_rate 0.831457 # mshr miss rate for ReadReq accesses
-system.cpu1.l1c.ReadReq_mshr_misses 36930 # number of ReadReq MSHR misses
-system.cpu1.l1c.ReadReq_mshr_uncacheable 9894 # number of ReadReq MSHR uncacheable
+system.cpu0.num_reads 98012 # number of read accesses completed
+system.cpu0.num_writes 53207 # number of write accesses completed
+system.cpu1.l1c.ReadReq_accesses 44893 # number of ReadReq accesses(hits+misses)
+system.cpu1.l1c.ReadReq_avg_miss_latency 13909.754864 # average ReadReq miss latency
+system.cpu1.l1c.ReadReq_avg_mshr_miss_latency 12900.185775 # average ReadReq mshr miss latency
+system.cpu1.l1c.ReadReq_hits 7579 # number of ReadReq hits
+system.cpu1.l1c.ReadReq_miss_latency 519028593 # number of ReadReq miss cycles
+system.cpu1.l1c.ReadReq_miss_rate 0.831176 # miss rate for ReadReq accesses
+system.cpu1.l1c.ReadReq_misses 37314 # number of ReadReq misses
+system.cpu1.l1c.ReadReq_mshr_miss_latency 481357532 # number of ReadReq MSHR miss cycles
+system.cpu1.l1c.ReadReq_mshr_miss_rate 0.831176 # mshr miss rate for ReadReq accesses
+system.cpu1.l1c.ReadReq_mshr_misses 37314 # number of ReadReq MSHR misses
+system.cpu1.l1c.ReadReq_mshr_uncacheable 9811 # number of ReadReq MSHR uncacheable
system.cpu1.l1c.ReadResp_avg_mshr_uncacheable_latency inf # average ReadResp mshr uncacheable latency
-system.cpu1.l1c.ReadResp_mshr_uncacheable_latency 17663360 # number of ReadResp MSHR uncacheable cycles
-system.cpu1.l1c.WriteReq_accesses 24084 # number of WriteReq accesses(hits+misses)
-system.cpu1.l1c.WriteReq_avg_miss_latency 871.179293 # average WriteReq miss latency
-system.cpu1.l1c.WriteReq_avg_mshr_miss_latency 786.258930 # average WriteReq mshr miss latency
-system.cpu1.l1c.WriteReq_hits 1155 # number of WriteReq hits
-system.cpu1.l1c.WriteReq_miss_latency 19975270 # number of WriteReq miss cycles
-system.cpu1.l1c.WriteReq_miss_rate 0.952043 # miss rate for WriteReq accesses
-system.cpu1.l1c.WriteReq_misses 22929 # number of WriteReq misses
-system.cpu1.l1c.WriteReq_mshr_miss_latency 18028131 # number of WriteReq MSHR miss cycles
-system.cpu1.l1c.WriteReq_mshr_miss_rate 0.952043 # mshr miss rate for WriteReq accesses
-system.cpu1.l1c.WriteReq_mshr_misses 22929 # number of WriteReq MSHR misses
-system.cpu1.l1c.WriteReq_mshr_uncacheable 5271 # number of WriteReq MSHR uncacheable
+system.cpu1.l1c.ReadResp_mshr_uncacheable_latency 251708747 # number of ReadResp MSHR uncacheable cycles
+system.cpu1.l1c.WriteReq_accesses 24614 # number of WriteReq accesses(hits+misses)
+system.cpu1.l1c.WriteReq_avg_miss_latency 12788.679753 # average WriteReq miss latency
+system.cpu1.l1c.WriteReq_avg_mshr_miss_latency 11344.205121 # average WriteReq mshr miss latency
+system.cpu1.l1c.WriteReq_hits 1257 # number of WriteReq hits
+system.cpu1.l1c.WriteReq_miss_latency 298705193 # number of WriteReq miss cycles
+system.cpu1.l1c.WriteReq_miss_rate 0.948932 # miss rate for WriteReq accesses
+system.cpu1.l1c.WriteReq_misses 23357 # number of WriteReq misses
+system.cpu1.l1c.WriteReq_mshr_miss_latency 264966599 # number of WriteReq MSHR miss cycles
+system.cpu1.l1c.WriteReq_mshr_miss_rate 0.948932 # mshr miss rate for WriteReq accesses
+system.cpu1.l1c.WriteReq_mshr_misses 23357 # number of WriteReq MSHR misses
+system.cpu1.l1c.WriteReq_mshr_uncacheable 5453 # number of WriteReq MSHR uncacheable
system.cpu1.l1c.WriteResp_avg_mshr_uncacheable_latency inf # average WriteResp mshr uncacheable latency
-system.cpu1.l1c.WriteResp_mshr_uncacheable_latency 10523322 # number of WriteResp MSHR uncacheable cycles
-system.cpu1.l1c.avg_blocked_cycles_no_mshrs 82.260179 # average number of cycles each access was blocked
+system.cpu1.l1c.WriteResp_mshr_uncacheable_latency 163813954 # number of WriteResp MSHR uncacheable cycles
+system.cpu1.l1c.avg_blocked_cycles_no_mshrs 1183.149435 # average number of cycles each access was blocked
system.cpu1.l1c.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
-system.cpu1.l1c.avg_refs 0.414867 # Average number of references to valid blocks.
-system.cpu1.l1c.blocked_no_mshrs 68941 # number of cycles access was blocked
+system.cpu1.l1c.avg_refs 0.414323 # Average number of references to valid blocks.
+system.cpu1.l1c.blocked_no_mshrs 69763 # number of cycles access was blocked
system.cpu1.l1c.blocked_no_targets 0 # number of cycles access was blocked
-system.cpu1.l1c.blocked_cycles_no_mshrs 5671099 # number of cycles access was blocked
+system.cpu1.l1c.blocked_cycles_no_mshrs 82540054 # number of cycles access was blocked
system.cpu1.l1c.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu1.l1c.cache_copies 0 # number of cache copies performed
-system.cpu1.l1c.demand_accesses 68500 # number of demand (read+write) accesses
-system.cpu1.l1c.demand_avg_miss_latency 931.741860 # average overall miss latency
-system.cpu1.l1c.demand_avg_mshr_miss_latency 852.314857 # average overall mshr miss latency
-system.cpu1.l1c.demand_hits 8641 # number of demand (read+write) hits
-system.cpu1.l1c.demand_miss_latency 55773136 # number of demand (read+write) miss cycles
-system.cpu1.l1c.demand_miss_rate 0.873854 # miss rate for demand accesses
-system.cpu1.l1c.demand_misses 59859 # number of demand (read+write) misses
+system.cpu1.l1c.demand_accesses 69507 # number of demand (read+write) accesses
+system.cpu1.l1c.demand_avg_miss_latency 13478.165615 # average overall miss latency
+system.cpu1.l1c.demand_avg_mshr_miss_latency 12301.167461 # average overall mshr miss latency
+system.cpu1.l1c.demand_hits 8836 # number of demand (read+write) hits
+system.cpu1.l1c.demand_miss_latency 817733786 # number of demand (read+write) miss cycles
+system.cpu1.l1c.demand_miss_rate 0.872876 # miss rate for demand accesses
+system.cpu1.l1c.demand_misses 60671 # number of demand (read+write) misses
system.cpu1.l1c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu1.l1c.demand_mshr_miss_latency 51018715 # number of demand (read+write) MSHR miss cycles
-system.cpu1.l1c.demand_mshr_miss_rate 0.873854 # mshr miss rate for demand accesses
-system.cpu1.l1c.demand_mshr_misses 59859 # number of demand (read+write) MSHR misses
+system.cpu1.l1c.demand_mshr_miss_latency 746324131 # number of demand (read+write) MSHR miss cycles
+system.cpu1.l1c.demand_mshr_miss_rate 0.872876 # mshr miss rate for demand accesses
+system.cpu1.l1c.demand_mshr_misses 60671 # number of demand (read+write) MSHR misses
system.cpu1.l1c.fast_writes 0 # number of fast writes performed
system.cpu1.l1c.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu1.l1c.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu1.l1c.overall_accesses 68500 # number of overall (read+write) accesses
-system.cpu1.l1c.overall_avg_miss_latency 931.741860 # average overall miss latency
-system.cpu1.l1c.overall_avg_mshr_miss_latency 852.314857 # average overall mshr miss latency
+system.cpu1.l1c.overall_accesses 69507 # number of overall (read+write) accesses
+system.cpu1.l1c.overall_avg_miss_latency 13478.165615 # average overall miss latency
+system.cpu1.l1c.overall_avg_mshr_miss_latency 12301.167461 # average overall mshr miss latency
system.cpu1.l1c.overall_avg_mshr_uncacheable_latency 0 # average overall mshr uncacheable latency
-system.cpu1.l1c.overall_hits 8641 # number of overall hits
-system.cpu1.l1c.overall_miss_latency 55773136 # number of overall miss cycles
-system.cpu1.l1c.overall_miss_rate 0.873854 # miss rate for overall accesses
-system.cpu1.l1c.overall_misses 59859 # number of overall misses
+system.cpu1.l1c.overall_hits 8836 # number of overall hits
+system.cpu1.l1c.overall_miss_latency 817733786 # number of overall miss cycles
+system.cpu1.l1c.overall_miss_rate 0.872876 # miss rate for overall accesses
+system.cpu1.l1c.overall_misses 60671 # number of overall misses
system.cpu1.l1c.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu1.l1c.overall_mshr_miss_latency 51018715 # number of overall MSHR miss cycles
-system.cpu1.l1c.overall_mshr_miss_rate 0.873854 # mshr miss rate for overall accesses
-system.cpu1.l1c.overall_mshr_misses 59859 # number of overall MSHR misses
+system.cpu1.l1c.overall_mshr_miss_latency 746324131 # number of overall MSHR miss cycles
+system.cpu1.l1c.overall_mshr_miss_rate 0.872876 # mshr miss rate for overall accesses
+system.cpu1.l1c.overall_mshr_misses 60671 # number of overall MSHR misses
system.cpu1.l1c.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu1.l1c.overall_mshr_uncacheable_misses 15165 # number of overall MSHR uncacheable misses
+system.cpu1.l1c.overall_mshr_uncacheable_misses 15264 # number of overall MSHR uncacheable misses
system.cpu1.l1c.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
system.cpu1.l1c.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
system.cpu1.l1c.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
@@ -185,103 +185,103 @@ system.cpu1.l1c.prefetcher.num_hwpf_removed_MSHR_hit 0
system.cpu1.l1c.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu1.l1c.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
system.cpu1.l1c.protocol.hwpf_invalid 0 # hard prefetch misses to invalid blocks
-system.cpu1.l1c.protocol.read_invalid 114228 # read misses to invalid blocks
+system.cpu1.l1c.protocol.read_invalid 1717891 # read misses to invalid blocks
system.cpu1.l1c.protocol.snoop_inv_exclusive 0 # Invalidate snoops on exclusive blocks
system.cpu1.l1c.protocol.snoop_inv_invalid 0 # Invalidate snoops on invalid blocks
system.cpu1.l1c.protocol.snoop_inv_modified 0 # Invalidate snoops on modified blocks
system.cpu1.l1c.protocol.snoop_inv_owned 0 # Invalidate snoops on owned blocks
system.cpu1.l1c.protocol.snoop_inv_shared 0 # Invalidate snoops on shared blocks
-system.cpu1.l1c.protocol.snoop_read_exclusive 2718 # read snoops on exclusive blocks
-system.cpu1.l1c.protocol.snoop_read_modified 12396 # read snoops on modified blocks
-system.cpu1.l1c.protocol.snoop_read_owned 7348 # read snoops on owned blocks
-system.cpu1.l1c.protocol.snoop_read_shared 23222 # read snoops on shared blocks
-system.cpu1.l1c.protocol.snoop_readex_exclusive 1497 # readEx snoops on exclusive blocks
-system.cpu1.l1c.protocol.snoop_readex_modified 6706 # readEx snoops on modified blocks
-system.cpu1.l1c.protocol.snoop_readex_owned 3865 # readEx snoops on owned blocks
-system.cpu1.l1c.protocol.snoop_readex_shared 12512 # readEx snoops on shared blocks
-system.cpu1.l1c.protocol.snoop_upgrade_owned 852 # upgrade snoops on owned blocks
-system.cpu1.l1c.protocol.snoop_upgrade_shared 2973 # upgradee snoops on shared blocks
+system.cpu1.l1c.protocol.snoop_read_exclusive 2925 # read snoops on exclusive blocks
+system.cpu1.l1c.protocol.snoop_read_modified 12701 # read snoops on modified blocks
+system.cpu1.l1c.protocol.snoop_read_owned 7436 # read snoops on owned blocks
+system.cpu1.l1c.protocol.snoop_read_shared 1669937 # read snoops on shared blocks
+system.cpu1.l1c.protocol.snoop_readex_exclusive 1611 # readEx snoops on exclusive blocks
+system.cpu1.l1c.protocol.snoop_readex_modified 6726 # readEx snoops on modified blocks
+system.cpu1.l1c.protocol.snoop_readex_owned 3965 # readEx snoops on owned blocks
+system.cpu1.l1c.protocol.snoop_readex_shared 12596 # readEx snoops on shared blocks
+system.cpu1.l1c.protocol.snoop_upgrade_owned 860 # upgrade snoops on owned blocks
+system.cpu1.l1c.protocol.snoop_upgrade_shared 2979 # upgradee snoops on shared blocks
system.cpu1.l1c.protocol.snoop_writeinv_exclusive 0 # WriteInvalidate snoops on exclusive blocks
system.cpu1.l1c.protocol.snoop_writeinv_invalid 0 # WriteInvalidate snoops on invalid blocks
system.cpu1.l1c.protocol.snoop_writeinv_modified 0 # WriteInvalidate snoops on modified blocks
system.cpu1.l1c.protocol.snoop_writeinv_owned 0 # WriteInvalidate snoops on owned blocks
system.cpu1.l1c.protocol.snoop_writeinv_shared 0 # WriteInvalidate snoops on shared blocks
system.cpu1.l1c.protocol.swpf_invalid 0 # soft prefetch misses to invalid blocks
-system.cpu1.l1c.protocol.write_invalid 61595 # write misses to invalid blocks
-system.cpu1.l1c.protocol.write_owned 1320 # write misses to owned blocks
-system.cpu1.l1c.protocol.write_shared 4183 # write misses to shared blocks
-system.cpu1.l1c.replacements 27139 # number of replacements
-system.cpu1.l1c.sampled_refs 27498 # Sample count of references to valid blocks.
+system.cpu1.l1c.protocol.write_invalid 914774 # write misses to invalid blocks
+system.cpu1.l1c.protocol.write_owned 1422 # write misses to owned blocks
+system.cpu1.l1c.protocol.write_shared 4382 # write misses to shared blocks
+system.cpu1.l1c.replacements 27806 # number of replacements
+system.cpu1.l1c.sampled_refs 28164 # Sample count of references to valid blocks.
system.cpu1.l1c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu1.l1c.tagsinuse 341.113569 # Cycle average of tags in use
-system.cpu1.l1c.total_refs 11408 # Total number of references to valid blocks.
+system.cpu1.l1c.tagsinuse 345.545872 # Cycle average of tags in use
+system.cpu1.l1c.total_refs 11669 # Total number of references to valid blocks.
system.cpu1.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu1.l1c.writebacks 10884 # number of writebacks
+system.cpu1.l1c.writebacks 11204 # number of writebacks
system.cpu1.num_copies 0 # number of copy accesses completed
-system.cpu1.num_reads 98821 # number of read accesses completed
-system.cpu1.num_writes 53366 # number of write accesses completed
-system.cpu2.l1c.ReadReq_accesses 45016 # number of ReadReq accesses(hits+misses)
-system.cpu2.l1c.ReadReq_avg_miss_latency 956.031371 # average ReadReq miss latency
-system.cpu2.l1c.ReadReq_avg_mshr_miss_latency 880.781951 # average ReadReq mshr miss latency
-system.cpu2.l1c.ReadReq_hits 7529 # number of ReadReq hits
-system.cpu2.l1c.ReadReq_miss_latency 35838748 # number of ReadReq miss cycles
-system.cpu2.l1c.ReadReq_miss_rate 0.832748 # miss rate for ReadReq accesses
-system.cpu2.l1c.ReadReq_misses 37487 # number of ReadReq misses
-system.cpu2.l1c.ReadReq_mshr_miss_latency 33017873 # number of ReadReq MSHR miss cycles
-system.cpu2.l1c.ReadReq_mshr_miss_rate 0.832748 # mshr miss rate for ReadReq accesses
-system.cpu2.l1c.ReadReq_mshr_misses 37487 # number of ReadReq MSHR misses
-system.cpu2.l1c.ReadReq_mshr_uncacheable 9887 # number of ReadReq MSHR uncacheable
+system.cpu1.num_reads 100000 # number of read accesses completed
+system.cpu1.num_writes 54335 # number of write accesses completed
+system.cpu2.l1c.ReadReq_accesses 44489 # number of ReadReq accesses(hits+misses)
+system.cpu2.l1c.ReadReq_avg_miss_latency 14018.031231 # average ReadReq miss latency
+system.cpu2.l1c.ReadReq_avg_mshr_miss_latency 12993.788573 # average ReadReq mshr miss latency
+system.cpu2.l1c.ReadReq_hits 7507 # number of ReadReq hits
+system.cpu2.l1c.ReadReq_miss_latency 518414831 # number of ReadReq miss cycles
+system.cpu2.l1c.ReadReq_miss_rate 0.831262 # miss rate for ReadReq accesses
+system.cpu2.l1c.ReadReq_misses 36982 # number of ReadReq misses
+system.cpu2.l1c.ReadReq_mshr_miss_latency 480536289 # number of ReadReq MSHR miss cycles
+system.cpu2.l1c.ReadReq_mshr_miss_rate 0.831262 # mshr miss rate for ReadReq accesses
+system.cpu2.l1c.ReadReq_mshr_misses 36982 # number of ReadReq MSHR misses
+system.cpu2.l1c.ReadReq_mshr_uncacheable 9861 # number of ReadReq MSHR uncacheable
system.cpu2.l1c.ReadResp_avg_mshr_uncacheable_latency inf # average ReadResp mshr uncacheable latency
-system.cpu2.l1c.ReadResp_mshr_uncacheable_latency 17582637 # number of ReadResp MSHR uncacheable cycles
-system.cpu2.l1c.WriteReq_accesses 24456 # number of WriteReq accesses(hits+misses)
-system.cpu2.l1c.WriteReq_avg_miss_latency 859.707355 # average WriteReq miss latency
-system.cpu2.l1c.WriteReq_avg_mshr_miss_latency 777.777296 # average WriteReq mshr miss latency
-system.cpu2.l1c.WriteReq_hits 1165 # number of WriteReq hits
-system.cpu2.l1c.WriteReq_miss_latency 20023444 # number of WriteReq miss cycles
-system.cpu2.l1c.WriteReq_miss_rate 0.952363 # miss rate for WriteReq accesses
-system.cpu2.l1c.WriteReq_misses 23291 # number of WriteReq misses
-system.cpu2.l1c.WriteReq_mshr_miss_latency 18115211 # number of WriteReq MSHR miss cycles
-system.cpu2.l1c.WriteReq_mshr_miss_rate 0.952363 # mshr miss rate for WriteReq accesses
-system.cpu2.l1c.WriteReq_mshr_misses 23291 # number of WriteReq MSHR misses
-system.cpu2.l1c.WriteReq_mshr_uncacheable 5362 # number of WriteReq MSHR uncacheable
+system.cpu2.l1c.ReadResp_mshr_uncacheable_latency 253484666 # number of ReadResp MSHR uncacheable cycles
+system.cpu2.l1c.WriteReq_accesses 24340 # number of WriteReq accesses(hits+misses)
+system.cpu2.l1c.WriteReq_avg_miss_latency 12765.385606 # average WriteReq miss latency
+system.cpu2.l1c.WriteReq_avg_mshr_miss_latency 11318.971789 # average WriteReq mshr miss latency
+system.cpu2.l1c.WriteReq_hits 1122 # number of WriteReq hits
+system.cpu2.l1c.WriteReq_miss_latency 296386723 # number of WriteReq miss cycles
+system.cpu2.l1c.WriteReq_miss_rate 0.953903 # miss rate for WriteReq accesses
+system.cpu2.l1c.WriteReq_misses 23218 # number of WriteReq misses
+system.cpu2.l1c.WriteReq_mshr_miss_latency 262803887 # number of WriteReq MSHR miss cycles
+system.cpu2.l1c.WriteReq_mshr_miss_rate 0.953903 # mshr miss rate for WriteReq accesses
+system.cpu2.l1c.WriteReq_mshr_misses 23218 # number of WriteReq MSHR misses
+system.cpu2.l1c.WriteReq_mshr_uncacheable 5480 # number of WriteReq MSHR uncacheable
system.cpu2.l1c.WriteResp_avg_mshr_uncacheable_latency inf # average WriteResp mshr uncacheable latency
-system.cpu2.l1c.WriteResp_mshr_uncacheable_latency 10583136 # number of WriteResp MSHR uncacheable cycles
-system.cpu2.l1c.avg_blocked_cycles_no_mshrs 81.152375 # average number of cycles each access was blocked
+system.cpu2.l1c.WriteResp_mshr_uncacheable_latency 165110755 # number of WriteResp MSHR uncacheable cycles
+system.cpu2.l1c.avg_blocked_cycles_no_mshrs 1190.317505 # average number of cycles each access was blocked
system.cpu2.l1c.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
-system.cpu2.l1c.avg_refs 0.404365 # Average number of references to valid blocks.
-system.cpu2.l1c.blocked_no_mshrs 69867 # number of cycles access was blocked
+system.cpu2.l1c.avg_refs 0.414721 # Average number of references to valid blocks.
+system.cpu2.l1c.blocked_no_mshrs 69202 # number of cycles access was blocked
system.cpu2.l1c.blocked_no_targets 0 # number of cycles access was blocked
-system.cpu2.l1c.blocked_cycles_no_mshrs 5669873 # number of cycles access was blocked
+system.cpu2.l1c.blocked_cycles_no_mshrs 82372352 # number of cycles access was blocked
system.cpu2.l1c.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu2.l1c.cache_copies 0 # number of cache copies performed
-system.cpu2.l1c.demand_accesses 69472 # number of demand (read+write) accesses
-system.cpu2.l1c.demand_avg_miss_latency 919.118628 # average overall miss latency
-system.cpu2.l1c.demand_avg_mshr_miss_latency 841.309092 # average overall mshr miss latency
-system.cpu2.l1c.demand_hits 8694 # number of demand (read+write) hits
-system.cpu2.l1c.demand_miss_latency 55862192 # number of demand (read+write) miss cycles
-system.cpu2.l1c.demand_miss_rate 0.874856 # miss rate for demand accesses
-system.cpu2.l1c.demand_misses 60778 # number of demand (read+write) misses
+system.cpu2.l1c.demand_accesses 68829 # number of demand (read+write) accesses
+system.cpu2.l1c.demand_avg_miss_latency 13534.909535 # average overall miss latency
+system.cpu2.l1c.demand_avg_mshr_miss_latency 12347.843455 # average overall mshr miss latency
+system.cpu2.l1c.demand_hits 8629 # number of demand (read+write) hits
+system.cpu2.l1c.demand_miss_latency 814801554 # number of demand (read+write) miss cycles
+system.cpu2.l1c.demand_miss_rate 0.874631 # miss rate for demand accesses
+system.cpu2.l1c.demand_misses 60200 # number of demand (read+write) misses
system.cpu2.l1c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu2.l1c.demand_mshr_miss_latency 51133084 # number of demand (read+write) MSHR miss cycles
-system.cpu2.l1c.demand_mshr_miss_rate 0.874856 # mshr miss rate for demand accesses
-system.cpu2.l1c.demand_mshr_misses 60778 # number of demand (read+write) MSHR misses
+system.cpu2.l1c.demand_mshr_miss_latency 743340176 # number of demand (read+write) MSHR miss cycles
+system.cpu2.l1c.demand_mshr_miss_rate 0.874631 # mshr miss rate for demand accesses
+system.cpu2.l1c.demand_mshr_misses 60200 # number of demand (read+write) MSHR misses
system.cpu2.l1c.fast_writes 0 # number of fast writes performed
system.cpu2.l1c.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu2.l1c.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu2.l1c.overall_accesses 69472 # number of overall (read+write) accesses
-system.cpu2.l1c.overall_avg_miss_latency 919.118628 # average overall miss latency
-system.cpu2.l1c.overall_avg_mshr_miss_latency 841.309092 # average overall mshr miss latency
+system.cpu2.l1c.overall_accesses 68829 # number of overall (read+write) accesses
+system.cpu2.l1c.overall_avg_miss_latency 13534.909535 # average overall miss latency
+system.cpu2.l1c.overall_avg_mshr_miss_latency 12347.843455 # average overall mshr miss latency
system.cpu2.l1c.overall_avg_mshr_uncacheable_latency 0 # average overall mshr uncacheable latency
-system.cpu2.l1c.overall_hits 8694 # number of overall hits
-system.cpu2.l1c.overall_miss_latency 55862192 # number of overall miss cycles
-system.cpu2.l1c.overall_miss_rate 0.874856 # miss rate for overall accesses
-system.cpu2.l1c.overall_misses 60778 # number of overall misses
+system.cpu2.l1c.overall_hits 8629 # number of overall hits
+system.cpu2.l1c.overall_miss_latency 814801554 # number of overall miss cycles
+system.cpu2.l1c.overall_miss_rate 0.874631 # miss rate for overall accesses
+system.cpu2.l1c.overall_misses 60200 # number of overall misses
system.cpu2.l1c.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu2.l1c.overall_mshr_miss_latency 51133084 # number of overall MSHR miss cycles
-system.cpu2.l1c.overall_mshr_miss_rate 0.874856 # mshr miss rate for overall accesses
-system.cpu2.l1c.overall_mshr_misses 60778 # number of overall MSHR misses
+system.cpu2.l1c.overall_mshr_miss_latency 743340176 # number of overall MSHR miss cycles
+system.cpu2.l1c.overall_mshr_miss_rate 0.874631 # mshr miss rate for overall accesses
+system.cpu2.l1c.overall_mshr_misses 60200 # number of overall MSHR misses
system.cpu2.l1c.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu2.l1c.overall_mshr_uncacheable_misses 15249 # number of overall MSHR uncacheable misses
+system.cpu2.l1c.overall_mshr_uncacheable_misses 15341 # number of overall MSHR uncacheable misses
system.cpu2.l1c.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
system.cpu2.l1c.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
system.cpu2.l1c.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
@@ -292,103 +292,103 @@ system.cpu2.l1c.prefetcher.num_hwpf_removed_MSHR_hit 0
system.cpu2.l1c.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu2.l1c.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
system.cpu2.l1c.protocol.hwpf_invalid 0 # hard prefetch misses to invalid blocks
-system.cpu2.l1c.protocol.read_invalid 111528 # read misses to invalid blocks
+system.cpu2.l1c.protocol.read_invalid 1818161 # read misses to invalid blocks
system.cpu2.l1c.protocol.snoop_inv_exclusive 0 # Invalidate snoops on exclusive blocks
system.cpu2.l1c.protocol.snoop_inv_invalid 0 # Invalidate snoops on invalid blocks
system.cpu2.l1c.protocol.snoop_inv_modified 0 # Invalidate snoops on modified blocks
system.cpu2.l1c.protocol.snoop_inv_owned 0 # Invalidate snoops on owned blocks
system.cpu2.l1c.protocol.snoop_inv_shared 0 # Invalidate snoops on shared blocks
-system.cpu2.l1c.protocol.snoop_read_exclusive 2757 # read snoops on exclusive blocks
-system.cpu2.l1c.protocol.snoop_read_modified 12587 # read snoops on modified blocks
-system.cpu2.l1c.protocol.snoop_read_owned 7252 # read snoops on owned blocks
-system.cpu2.l1c.protocol.snoop_read_shared 22967 # read snoops on shared blocks
-system.cpu2.l1c.protocol.snoop_readex_exclusive 1579 # readEx snoops on exclusive blocks
-system.cpu2.l1c.protocol.snoop_readex_modified 6680 # readEx snoops on modified blocks
-system.cpu2.l1c.protocol.snoop_readex_owned 3891 # readEx snoops on owned blocks
-system.cpu2.l1c.protocol.snoop_readex_shared 12468 # readEx snoops on shared blocks
-system.cpu2.l1c.protocol.snoop_upgrade_owned 850 # upgrade snoops on owned blocks
-system.cpu2.l1c.protocol.snoop_upgrade_shared 2951 # upgradee snoops on shared blocks
+system.cpu2.l1c.protocol.snoop_read_exclusive 2846 # read snoops on exclusive blocks
+system.cpu2.l1c.protocol.snoop_read_modified 12505 # read snoops on modified blocks
+system.cpu2.l1c.protocol.snoop_read_owned 7354 # read snoops on owned blocks
+system.cpu2.l1c.protocol.snoop_read_shared 1719896 # read snoops on shared blocks
+system.cpu2.l1c.protocol.snoop_readex_exclusive 1512 # readEx snoops on exclusive blocks
+system.cpu2.l1c.protocol.snoop_readex_modified 6836 # readEx snoops on modified blocks
+system.cpu2.l1c.protocol.snoop_readex_owned 4066 # readEx snoops on owned blocks
+system.cpu2.l1c.protocol.snoop_readex_shared 12494 # readEx snoops on shared blocks
+system.cpu2.l1c.protocol.snoop_upgrade_owned 828 # upgrade snoops on owned blocks
+system.cpu2.l1c.protocol.snoop_upgrade_shared 2975 # upgradee snoops on shared blocks
system.cpu2.l1c.protocol.snoop_writeinv_exclusive 0 # WriteInvalidate snoops on exclusive blocks
system.cpu2.l1c.protocol.snoop_writeinv_invalid 0 # WriteInvalidate snoops on invalid blocks
system.cpu2.l1c.protocol.snoop_writeinv_modified 0 # WriteInvalidate snoops on modified blocks
system.cpu2.l1c.protocol.snoop_writeinv_owned 0 # WriteInvalidate snoops on owned blocks
system.cpu2.l1c.protocol.snoop_writeinv_shared 0 # WriteInvalidate snoops on shared blocks
system.cpu2.l1c.protocol.swpf_invalid 0 # soft prefetch misses to invalid blocks
-system.cpu2.l1c.protocol.write_invalid 57618 # write misses to invalid blocks
-system.cpu2.l1c.protocol.write_owned 1263 # write misses to owned blocks
-system.cpu2.l1c.protocol.write_shared 4251 # write misses to shared blocks
-system.cpu2.l1c.replacements 28062 # number of replacements
-system.cpu2.l1c.sampled_refs 28405 # Sample count of references to valid blocks.
+system.cpu2.l1c.protocol.write_invalid 1061132 # write misses to invalid blocks
+system.cpu2.l1c.protocol.write_owned 1410 # write misses to owned blocks
+system.cpu2.l1c.protocol.write_shared 4436 # write misses to shared blocks
+system.cpu2.l1c.replacements 27337 # number of replacements
+system.cpu2.l1c.sampled_refs 27674 # Sample count of references to valid blocks.
system.cpu2.l1c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu2.l1c.tagsinuse 344.040679 # Cycle average of tags in use
-system.cpu2.l1c.total_refs 11486 # Total number of references to valid blocks.
+system.cpu2.l1c.tagsinuse 343.290844 # Cycle average of tags in use
+system.cpu2.l1c.total_refs 11477 # Total number of references to valid blocks.
system.cpu2.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu2.l1c.writebacks 11295 # number of writebacks
+system.cpu2.l1c.writebacks 10872 # number of writebacks
system.cpu2.num_copies 0 # number of copy accesses completed
-system.cpu2.num_reads 100000 # number of read accesses completed
-system.cpu2.num_writes 54133 # number of write accesses completed
-system.cpu3.l1c.ReadReq_accesses 44504 # number of ReadReq accesses(hits+misses)
-system.cpu3.l1c.ReadReq_avg_miss_latency 968.772953 # average ReadReq miss latency
-system.cpu3.l1c.ReadReq_avg_mshr_miss_latency 892.914985 # average ReadReq mshr miss latency
-system.cpu3.l1c.ReadReq_hits 7428 # number of ReadReq hits
-system.cpu3.l1c.ReadReq_miss_latency 35918226 # number of ReadReq miss cycles
-system.cpu3.l1c.ReadReq_miss_rate 0.833094 # miss rate for ReadReq accesses
-system.cpu3.l1c.ReadReq_misses 37076 # number of ReadReq misses
-system.cpu3.l1c.ReadReq_mshr_miss_latency 33105716 # number of ReadReq MSHR miss cycles
-system.cpu3.l1c.ReadReq_mshr_miss_rate 0.833094 # mshr miss rate for ReadReq accesses
-system.cpu3.l1c.ReadReq_mshr_misses 37076 # number of ReadReq MSHR misses
-system.cpu3.l1c.ReadReq_mshr_uncacheable 9876 # number of ReadReq MSHR uncacheable
+system.cpu2.num_reads 98887 # number of read accesses completed
+system.cpu2.num_writes 53640 # number of write accesses completed
+system.cpu3.l1c.ReadReq_accesses 44566 # number of ReadReq accesses(hits+misses)
+system.cpu3.l1c.ReadReq_avg_miss_latency 14066.553951 # average ReadReq miss latency
+system.cpu3.l1c.ReadReq_avg_mshr_miss_latency 13052.525235 # average ReadReq mshr miss latency
+system.cpu3.l1c.ReadReq_hits 7375 # number of ReadReq hits
+system.cpu3.l1c.ReadReq_miss_latency 523149208 # number of ReadReq miss cycles
+system.cpu3.l1c.ReadReq_miss_rate 0.834515 # miss rate for ReadReq accesses
+system.cpu3.l1c.ReadReq_misses 37191 # number of ReadReq misses
+system.cpu3.l1c.ReadReq_mshr_miss_latency 485436466 # number of ReadReq MSHR miss cycles
+system.cpu3.l1c.ReadReq_mshr_miss_rate 0.834515 # mshr miss rate for ReadReq accesses
+system.cpu3.l1c.ReadReq_mshr_misses 37191 # number of ReadReq MSHR misses
+system.cpu3.l1c.ReadReq_mshr_uncacheable 9820 # number of ReadReq MSHR uncacheable
system.cpu3.l1c.ReadResp_avg_mshr_uncacheable_latency inf # average ReadResp mshr uncacheable latency
-system.cpu3.l1c.ReadResp_mshr_uncacheable_latency 17594905 # number of ReadResp MSHR uncacheable cycles
-system.cpu3.l1c.WriteReq_accesses 24087 # number of WriteReq accesses(hits+misses)
-system.cpu3.l1c.WriteReq_avg_miss_latency 868.499565 # average WriteReq miss latency
-system.cpu3.l1c.WriteReq_avg_mshr_miss_latency 784.537397 # average WriteReq mshr miss latency
-system.cpu3.l1c.WriteReq_hits 1117 # number of WriteReq hits
-system.cpu3.l1c.WriteReq_miss_latency 19949435 # number of WriteReq miss cycles
-system.cpu3.l1c.WriteReq_miss_rate 0.953626 # miss rate for WriteReq accesses
-system.cpu3.l1c.WriteReq_misses 22970 # number of WriteReq misses
-system.cpu3.l1c.WriteReq_mshr_miss_latency 18020824 # number of WriteReq MSHR miss cycles
-system.cpu3.l1c.WriteReq_mshr_miss_rate 0.953626 # mshr miss rate for WriteReq accesses
-system.cpu3.l1c.WriteReq_mshr_misses 22970 # number of WriteReq MSHR misses
-system.cpu3.l1c.WriteReq_mshr_uncacheable 5355 # number of WriteReq MSHR uncacheable
+system.cpu3.l1c.ReadResp_mshr_uncacheable_latency 252799971 # number of ReadResp MSHR uncacheable cycles
+system.cpu3.l1c.WriteReq_accesses 24030 # number of WriteReq accesses(hits+misses)
+system.cpu3.l1c.WriteReq_avg_miss_latency 12807.474484 # average WriteReq miss latency
+system.cpu3.l1c.WriteReq_avg_mshr_miss_latency 11345.837164 # average WriteReq mshr miss latency
+system.cpu3.l1c.WriteReq_hits 1142 # number of WriteReq hits
+system.cpu3.l1c.WriteReq_miss_latency 293137476 # number of WriteReq miss cycles
+system.cpu3.l1c.WriteReq_miss_rate 0.952476 # miss rate for WriteReq accesses
+system.cpu3.l1c.WriteReq_misses 22888 # number of WriteReq misses
+system.cpu3.l1c.WriteReq_mshr_miss_latency 259683521 # number of WriteReq MSHR miss cycles
+system.cpu3.l1c.WriteReq_mshr_miss_rate 0.952476 # mshr miss rate for WriteReq accesses
+system.cpu3.l1c.WriteReq_mshr_misses 22888 # number of WriteReq MSHR misses
+system.cpu3.l1c.WriteReq_mshr_uncacheable 5294 # number of WriteReq MSHR uncacheable
system.cpu3.l1c.WriteResp_avg_mshr_uncacheable_latency inf # average WriteResp mshr uncacheable latency
-system.cpu3.l1c.WriteResp_mshr_uncacheable_latency 10637792 # number of WriteResp MSHR uncacheable cycles
-system.cpu3.l1c.avg_blocked_cycles_no_mshrs 82.097897 # average number of cycles each access was blocked
+system.cpu3.l1c.WriteResp_mshr_uncacheable_latency 159218905 # number of WriteResp MSHR uncacheable cycles
+system.cpu3.l1c.avg_blocked_cycles_no_mshrs 1193.729049 # average number of cycles each access was blocked
system.cpu3.l1c.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
-system.cpu3.l1c.avg_refs 0.411489 # Average number of references to valid blocks.
-system.cpu3.l1c.blocked_no_mshrs 69124 # number of cycles access was blocked
+system.cpu3.l1c.avg_refs 0.411345 # Average number of references to valid blocks.
+system.cpu3.l1c.blocked_no_mshrs 69160 # number of cycles access was blocked
system.cpu3.l1c.blocked_no_targets 0 # number of cycles access was blocked
-system.cpu3.l1c.blocked_cycles_no_mshrs 5674935 # number of cycles access was blocked
+system.cpu3.l1c.blocked_cycles_no_mshrs 82558301 # number of cycles access was blocked
system.cpu3.l1c.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu3.l1c.cache_copies 0 # number of cache copies performed
-system.cpu3.l1c.demand_accesses 68591 # number of demand (read+write) accesses
-system.cpu3.l1c.demand_avg_miss_latency 930.414366 # average overall miss latency
-system.cpu3.l1c.demand_avg_mshr_miss_latency 851.456217 # average overall mshr miss latency
-system.cpu3.l1c.demand_hits 8545 # number of demand (read+write) hits
-system.cpu3.l1c.demand_miss_latency 55867661 # number of demand (read+write) miss cycles
-system.cpu3.l1c.demand_miss_rate 0.875421 # miss rate for demand accesses
-system.cpu3.l1c.demand_misses 60046 # number of demand (read+write) misses
+system.cpu3.l1c.demand_accesses 68596 # number of demand (read+write) accesses
+system.cpu3.l1c.demand_avg_miss_latency 13586.888663 # average overall miss latency
+system.cpu3.l1c.demand_avg_mshr_miss_latency 12402.336707 # average overall mshr miss latency
+system.cpu3.l1c.demand_hits 8517 # number of demand (read+write) hits
+system.cpu3.l1c.demand_miss_latency 816286684 # number of demand (read+write) miss cycles
+system.cpu3.l1c.demand_miss_rate 0.875838 # miss rate for demand accesses
+system.cpu3.l1c.demand_misses 60079 # number of demand (read+write) misses
system.cpu3.l1c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu3.l1c.demand_mshr_miss_latency 51126540 # number of demand (read+write) MSHR miss cycles
-system.cpu3.l1c.demand_mshr_miss_rate 0.875421 # mshr miss rate for demand accesses
-system.cpu3.l1c.demand_mshr_misses 60046 # number of demand (read+write) MSHR misses
+system.cpu3.l1c.demand_mshr_miss_latency 745119987 # number of demand (read+write) MSHR miss cycles
+system.cpu3.l1c.demand_mshr_miss_rate 0.875838 # mshr miss rate for demand accesses
+system.cpu3.l1c.demand_mshr_misses 60079 # number of demand (read+write) MSHR misses
system.cpu3.l1c.fast_writes 0 # number of fast writes performed
system.cpu3.l1c.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu3.l1c.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu3.l1c.overall_accesses 68591 # number of overall (read+write) accesses
-system.cpu3.l1c.overall_avg_miss_latency 930.414366 # average overall miss latency
-system.cpu3.l1c.overall_avg_mshr_miss_latency 851.456217 # average overall mshr miss latency
+system.cpu3.l1c.overall_accesses 68596 # number of overall (read+write) accesses
+system.cpu3.l1c.overall_avg_miss_latency 13586.888663 # average overall miss latency
+system.cpu3.l1c.overall_avg_mshr_miss_latency 12402.336707 # average overall mshr miss latency
system.cpu3.l1c.overall_avg_mshr_uncacheable_latency 0 # average overall mshr uncacheable latency
-system.cpu3.l1c.overall_hits 8545 # number of overall hits
-system.cpu3.l1c.overall_miss_latency 55867661 # number of overall miss cycles
-system.cpu3.l1c.overall_miss_rate 0.875421 # miss rate for overall accesses
-system.cpu3.l1c.overall_misses 60046 # number of overall misses
+system.cpu3.l1c.overall_hits 8517 # number of overall hits
+system.cpu3.l1c.overall_miss_latency 816286684 # number of overall miss cycles
+system.cpu3.l1c.overall_miss_rate 0.875838 # miss rate for overall accesses
+system.cpu3.l1c.overall_misses 60079 # number of overall misses
system.cpu3.l1c.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu3.l1c.overall_mshr_miss_latency 51126540 # number of overall MSHR miss cycles
-system.cpu3.l1c.overall_mshr_miss_rate 0.875421 # mshr miss rate for overall accesses
-system.cpu3.l1c.overall_mshr_misses 60046 # number of overall MSHR misses
+system.cpu3.l1c.overall_mshr_miss_latency 745119987 # number of overall MSHR miss cycles
+system.cpu3.l1c.overall_mshr_miss_rate 0.875838 # mshr miss rate for overall accesses
+system.cpu3.l1c.overall_mshr_misses 60079 # number of overall MSHR misses
system.cpu3.l1c.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu3.l1c.overall_mshr_uncacheable_misses 15231 # number of overall MSHR uncacheable misses
+system.cpu3.l1c.overall_mshr_uncacheable_misses 15114 # number of overall MSHR uncacheable misses
system.cpu3.l1c.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
system.cpu3.l1c.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
system.cpu3.l1c.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
@@ -399,103 +399,103 @@ system.cpu3.l1c.prefetcher.num_hwpf_removed_MSHR_hit 0
system.cpu3.l1c.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu3.l1c.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
system.cpu3.l1c.protocol.hwpf_invalid 0 # hard prefetch misses to invalid blocks
-system.cpu3.l1c.protocol.read_invalid 110901 # read misses to invalid blocks
+system.cpu3.l1c.protocol.read_invalid 1894373 # read misses to invalid blocks
system.cpu3.l1c.protocol.snoop_inv_exclusive 0 # Invalidate snoops on exclusive blocks
system.cpu3.l1c.protocol.snoop_inv_invalid 0 # Invalidate snoops on invalid blocks
system.cpu3.l1c.protocol.snoop_inv_modified 0 # Invalidate snoops on modified blocks
system.cpu3.l1c.protocol.snoop_inv_owned 0 # Invalidate snoops on owned blocks
system.cpu3.l1c.protocol.snoop_inv_shared 0 # Invalidate snoops on shared blocks
-system.cpu3.l1c.protocol.snoop_read_exclusive 2843 # read snoops on exclusive blocks
-system.cpu3.l1c.protocol.snoop_read_modified 12490 # read snoops on modified blocks
-system.cpu3.l1c.protocol.snoop_read_owned 7235 # read snoops on owned blocks
-system.cpu3.l1c.protocol.snoop_read_shared 23011 # read snoops on shared blocks
-system.cpu3.l1c.protocol.snoop_readex_exclusive 1535 # readEx snoops on exclusive blocks
-system.cpu3.l1c.protocol.snoop_readex_modified 6732 # readEx snoops on modified blocks
-system.cpu3.l1c.protocol.snoop_readex_owned 3954 # readEx snoops on owned blocks
-system.cpu3.l1c.protocol.snoop_readex_shared 12354 # readEx snoops on shared blocks
-system.cpu3.l1c.protocol.snoop_upgrade_owned 858 # upgrade snoops on owned blocks
-system.cpu3.l1c.protocol.snoop_upgrade_shared 3087 # upgradee snoops on shared blocks
+system.cpu3.l1c.protocol.snoop_read_exclusive 2902 # read snoops on exclusive blocks
+system.cpu3.l1c.protocol.snoop_read_modified 12291 # read snoops on modified blocks
+system.cpu3.l1c.protocol.snoop_read_owned 7221 # read snoops on owned blocks
+system.cpu3.l1c.protocol.snoop_read_shared 1743434 # read snoops on shared blocks
+system.cpu3.l1c.protocol.snoop_readex_exclusive 1553 # readEx snoops on exclusive blocks
+system.cpu3.l1c.protocol.snoop_readex_modified 6822 # readEx snoops on modified blocks
+system.cpu3.l1c.protocol.snoop_readex_owned 3914 # readEx snoops on owned blocks
+system.cpu3.l1c.protocol.snoop_readex_shared 12477 # readEx snoops on shared blocks
+system.cpu3.l1c.protocol.snoop_upgrade_owned 867 # upgrade snoops on owned blocks
+system.cpu3.l1c.protocol.snoop_upgrade_shared 3008 # upgradee snoops on shared blocks
system.cpu3.l1c.protocol.snoop_writeinv_exclusive 0 # WriteInvalidate snoops on exclusive blocks
system.cpu3.l1c.protocol.snoop_writeinv_invalid 0 # WriteInvalidate snoops on invalid blocks
system.cpu3.l1c.protocol.snoop_writeinv_modified 0 # WriteInvalidate snoops on modified blocks
system.cpu3.l1c.protocol.snoop_writeinv_owned 0 # WriteInvalidate snoops on owned blocks
system.cpu3.l1c.protocol.snoop_writeinv_shared 0 # WriteInvalidate snoops on shared blocks
system.cpu3.l1c.protocol.swpf_invalid 0 # soft prefetch misses to invalid blocks
-system.cpu3.l1c.protocol.write_invalid 59061 # write misses to invalid blocks
-system.cpu3.l1c.protocol.write_owned 1261 # write misses to owned blocks
-system.cpu3.l1c.protocol.write_shared 4235 # write misses to shared blocks
-system.cpu3.l1c.replacements 27216 # number of replacements
-system.cpu3.l1c.sampled_refs 27556 # Sample count of references to valid blocks.
+system.cpu3.l1c.protocol.write_invalid 1046634 # write misses to invalid blocks
+system.cpu3.l1c.protocol.write_owned 1364 # write misses to owned blocks
+system.cpu3.l1c.protocol.write_shared 4484 # write misses to shared blocks
+system.cpu3.l1c.replacements 27286 # number of replacements
+system.cpu3.l1c.sampled_refs 27624 # Sample count of references to valid blocks.
system.cpu3.l1c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu3.l1c.tagsinuse 341.602377 # Cycle average of tags in use
-system.cpu3.l1c.total_refs 11339 # Total number of references to valid blocks.
+system.cpu3.l1c.tagsinuse 342.290575 # Cycle average of tags in use
+system.cpu3.l1c.total_refs 11363 # Total number of references to valid blocks.
system.cpu3.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu3.l1c.writebacks 10831 # number of writebacks
+system.cpu3.l1c.writebacks 10681 # number of writebacks
system.cpu3.num_copies 0 # number of copy accesses completed
-system.cpu3.num_reads 98893 # number of read accesses completed
-system.cpu3.num_writes 53654 # number of write accesses completed
-system.cpu4.l1c.ReadReq_accesses 44272 # number of ReadReq accesses(hits+misses)
-system.cpu4.l1c.ReadReq_avg_miss_latency 976.655364 # average ReadReq miss latency
-system.cpu4.l1c.ReadReq_avg_mshr_miss_latency 901.292278 # average ReadReq mshr miss latency
-system.cpu4.l1c.ReadReq_hits 7468 # number of ReadReq hits
-system.cpu4.l1c.ReadReq_miss_latency 35944824 # number of ReadReq miss cycles
-system.cpu4.l1c.ReadReq_miss_rate 0.831316 # miss rate for ReadReq accesses
-system.cpu4.l1c.ReadReq_misses 36804 # number of ReadReq misses
-system.cpu4.l1c.ReadReq_mshr_miss_latency 33171161 # number of ReadReq MSHR miss cycles
-system.cpu4.l1c.ReadReq_mshr_miss_rate 0.831316 # mshr miss rate for ReadReq accesses
-system.cpu4.l1c.ReadReq_mshr_misses 36804 # number of ReadReq MSHR misses
-system.cpu4.l1c.ReadReq_mshr_uncacheable 9822 # number of ReadReq MSHR uncacheable
+system.cpu3.num_reads 99322 # number of read accesses completed
+system.cpu3.num_writes 53280 # number of write accesses completed
+system.cpu4.l1c.ReadReq_accesses 44971 # number of ReadReq accesses(hits+misses)
+system.cpu4.l1c.ReadReq_avg_miss_latency 13943.186039 # average ReadReq miss latency
+system.cpu4.l1c.ReadReq_avg_mshr_miss_latency 12937.718615 # average ReadReq mshr miss latency
+system.cpu4.l1c.ReadReq_hits 7581 # number of ReadReq hits
+system.cpu4.l1c.ReadReq_miss_latency 521335726 # number of ReadReq miss cycles
+system.cpu4.l1c.ReadReq_miss_rate 0.831425 # miss rate for ReadReq accesses
+system.cpu4.l1c.ReadReq_misses 37390 # number of ReadReq misses
+system.cpu4.l1c.ReadReq_mshr_miss_latency 483741299 # number of ReadReq MSHR miss cycles
+system.cpu4.l1c.ReadReq_mshr_miss_rate 0.831425 # mshr miss rate for ReadReq accesses
+system.cpu4.l1c.ReadReq_mshr_misses 37390 # number of ReadReq MSHR misses
+system.cpu4.l1c.ReadReq_mshr_uncacheable 9931 # number of ReadReq MSHR uncacheable
system.cpu4.l1c.ReadResp_avg_mshr_uncacheable_latency inf # average ReadResp mshr uncacheable latency
-system.cpu4.l1c.ReadResp_mshr_uncacheable_latency 17532387 # number of ReadResp MSHR uncacheable cycles
-system.cpu4.l1c.WriteReq_accesses 23994 # number of WriteReq accesses(hits+misses)
-system.cpu4.l1c.WriteReq_avg_miss_latency 874.063859 # average WriteReq miss latency
-system.cpu4.l1c.WriteReq_avg_mshr_miss_latency 788.017488 # average WriteReq mshr miss latency
-system.cpu4.l1c.WriteReq_hits 1178 # number of WriteReq hits
-system.cpu4.l1c.WriteReq_miss_latency 19942641 # number of WriteReq miss cycles
-system.cpu4.l1c.WriteReq_miss_rate 0.950904 # miss rate for WriteReq accesses
-system.cpu4.l1c.WriteReq_misses 22816 # number of WriteReq misses
-system.cpu4.l1c.WriteReq_mshr_miss_latency 17979407 # number of WriteReq MSHR miss cycles
-system.cpu4.l1c.WriteReq_mshr_miss_rate 0.950904 # mshr miss rate for WriteReq accesses
-system.cpu4.l1c.WriteReq_mshr_misses 22816 # number of WriteReq MSHR misses
-system.cpu4.l1c.WriteReq_mshr_uncacheable 5315 # number of WriteReq MSHR uncacheable
+system.cpu4.l1c.ReadResp_mshr_uncacheable_latency 254015216 # number of ReadResp MSHR uncacheable cycles
+system.cpu4.l1c.WriteReq_accesses 24134 # number of WriteReq accesses(hits+misses)
+system.cpu4.l1c.WriteReq_avg_miss_latency 12764.573629 # average WriteReq miss latency
+system.cpu4.l1c.WriteReq_avg_mshr_miss_latency 11273.971841 # average WriteReq mshr miss latency
+system.cpu4.l1c.WriteReq_hits 1086 # number of WriteReq hits
+system.cpu4.l1c.WriteReq_miss_latency 294197893 # number of WriteReq miss cycles
+system.cpu4.l1c.WriteReq_miss_rate 0.955001 # miss rate for WriteReq accesses
+system.cpu4.l1c.WriteReq_misses 23048 # number of WriteReq misses
+system.cpu4.l1c.WriteReq_mshr_miss_latency 259842503 # number of WriteReq MSHR miss cycles
+system.cpu4.l1c.WriteReq_mshr_miss_rate 0.955001 # mshr miss rate for WriteReq accesses
+system.cpu4.l1c.WriteReq_mshr_misses 23048 # number of WriteReq MSHR misses
+system.cpu4.l1c.WriteReq_mshr_uncacheable 5390 # number of WriteReq MSHR uncacheable
system.cpu4.l1c.WriteResp_avg_mshr_uncacheable_latency inf # average WriteResp mshr uncacheable latency
-system.cpu4.l1c.WriteResp_mshr_uncacheable_latency 10563676 # number of WriteResp MSHR uncacheable cycles
-system.cpu4.l1c.avg_blocked_cycles_no_mshrs 82.703233 # average number of cycles each access was blocked
+system.cpu4.l1c.WriteResp_mshr_uncacheable_latency 161643344 # number of WriteResp MSHR uncacheable cycles
+system.cpu4.l1c.avg_blocked_cycles_no_mshrs 1186.636056 # average number of cycles each access was blocked
system.cpu4.l1c.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
-system.cpu4.l1c.avg_refs 0.416368 # Average number of references to valid blocks.
-system.cpu4.l1c.blocked_no_mshrs 68707 # number of cycles access was blocked
+system.cpu4.l1c.avg_refs 0.410931 # Average number of references to valid blocks.
+system.cpu4.l1c.blocked_no_mshrs 69637 # number of cycles access was blocked
system.cpu4.l1c.blocked_no_targets 0 # number of cycles access was blocked
-system.cpu4.l1c.blocked_cycles_no_mshrs 5682291 # number of cycles access was blocked
+system.cpu4.l1c.blocked_cycles_no_mshrs 82633775 # number of cycles access was blocked
system.cpu4.l1c.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu4.l1c.cache_copies 0 # number of cache copies performed
-system.cpu4.l1c.demand_accesses 68266 # number of demand (read+write) accesses
-system.cpu4.l1c.demand_avg_miss_latency 937.394582 # average overall miss latency
-system.cpu4.l1c.demand_avg_mshr_miss_latency 857.943106 # average overall mshr miss latency
-system.cpu4.l1c.demand_hits 8646 # number of demand (read+write) hits
-system.cpu4.l1c.demand_miss_latency 55887465 # number of demand (read+write) miss cycles
-system.cpu4.l1c.demand_miss_rate 0.873348 # miss rate for demand accesses
-system.cpu4.l1c.demand_misses 59620 # number of demand (read+write) misses
+system.cpu4.l1c.demand_accesses 69105 # number of demand (read+write) accesses
+system.cpu4.l1c.demand_avg_miss_latency 13493.722807 # average overall miss latency
+system.cpu4.l1c.demand_avg_mshr_miss_latency 12303.249644 # average overall mshr miss latency
+system.cpu4.l1c.demand_hits 8667 # number of demand (read+write) hits
+system.cpu4.l1c.demand_miss_latency 815533619 # number of demand (read+write) miss cycles
+system.cpu4.l1c.demand_miss_rate 0.874582 # miss rate for demand accesses
+system.cpu4.l1c.demand_misses 60438 # number of demand (read+write) misses
system.cpu4.l1c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu4.l1c.demand_mshr_miss_latency 51150568 # number of demand (read+write) MSHR miss cycles
-system.cpu4.l1c.demand_mshr_miss_rate 0.873348 # mshr miss rate for demand accesses
-system.cpu4.l1c.demand_mshr_misses 59620 # number of demand (read+write) MSHR misses
+system.cpu4.l1c.demand_mshr_miss_latency 743583802 # number of demand (read+write) MSHR miss cycles
+system.cpu4.l1c.demand_mshr_miss_rate 0.874582 # mshr miss rate for demand accesses
+system.cpu4.l1c.demand_mshr_misses 60438 # number of demand (read+write) MSHR misses
system.cpu4.l1c.fast_writes 0 # number of fast writes performed
system.cpu4.l1c.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu4.l1c.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu4.l1c.overall_accesses 68266 # number of overall (read+write) accesses
-system.cpu4.l1c.overall_avg_miss_latency 937.394582 # average overall miss latency
-system.cpu4.l1c.overall_avg_mshr_miss_latency 857.943106 # average overall mshr miss latency
+system.cpu4.l1c.overall_accesses 69105 # number of overall (read+write) accesses
+system.cpu4.l1c.overall_avg_miss_latency 13493.722807 # average overall miss latency
+system.cpu4.l1c.overall_avg_mshr_miss_latency 12303.249644 # average overall mshr miss latency
system.cpu4.l1c.overall_avg_mshr_uncacheable_latency 0 # average overall mshr uncacheable latency
-system.cpu4.l1c.overall_hits 8646 # number of overall hits
-system.cpu4.l1c.overall_miss_latency 55887465 # number of overall miss cycles
-system.cpu4.l1c.overall_miss_rate 0.873348 # miss rate for overall accesses
-system.cpu4.l1c.overall_misses 59620 # number of overall misses
+system.cpu4.l1c.overall_hits 8667 # number of overall hits
+system.cpu4.l1c.overall_miss_latency 815533619 # number of overall miss cycles
+system.cpu4.l1c.overall_miss_rate 0.874582 # miss rate for overall accesses
+system.cpu4.l1c.overall_misses 60438 # number of overall misses
system.cpu4.l1c.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu4.l1c.overall_mshr_miss_latency 51150568 # number of overall MSHR miss cycles
-system.cpu4.l1c.overall_mshr_miss_rate 0.873348 # mshr miss rate for overall accesses
-system.cpu4.l1c.overall_mshr_misses 59620 # number of overall MSHR misses
+system.cpu4.l1c.overall_mshr_miss_latency 743583802 # number of overall MSHR miss cycles
+system.cpu4.l1c.overall_mshr_miss_rate 0.874582 # mshr miss rate for overall accesses
+system.cpu4.l1c.overall_mshr_misses 60438 # number of overall MSHR misses
system.cpu4.l1c.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu4.l1c.overall_mshr_uncacheable_misses 15137 # number of overall MSHR uncacheable misses
+system.cpu4.l1c.overall_mshr_uncacheable_misses 15321 # number of overall MSHR uncacheable misses
system.cpu4.l1c.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
system.cpu4.l1c.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
system.cpu4.l1c.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
@@ -506,103 +506,103 @@ system.cpu4.l1c.prefetcher.num_hwpf_removed_MSHR_hit 0
system.cpu4.l1c.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu4.l1c.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
system.cpu4.l1c.protocol.hwpf_invalid 0 # hard prefetch misses to invalid blocks
-system.cpu4.l1c.protocol.read_invalid 113154 # read misses to invalid blocks
+system.cpu4.l1c.protocol.read_invalid 1830675 # read misses to invalid blocks
system.cpu4.l1c.protocol.snoop_inv_exclusive 0 # Invalidate snoops on exclusive blocks
system.cpu4.l1c.protocol.snoop_inv_invalid 0 # Invalidate snoops on invalid blocks
system.cpu4.l1c.protocol.snoop_inv_modified 0 # Invalidate snoops on modified blocks
system.cpu4.l1c.protocol.snoop_inv_owned 0 # Invalidate snoops on owned blocks
system.cpu4.l1c.protocol.snoop_inv_shared 0 # Invalidate snoops on shared blocks
-system.cpu4.l1c.protocol.snoop_read_exclusive 2804 # read snoops on exclusive blocks
-system.cpu4.l1c.protocol.snoop_read_modified 12453 # read snoops on modified blocks
-system.cpu4.l1c.protocol.snoop_read_owned 7418 # read snoops on owned blocks
-system.cpu4.l1c.protocol.snoop_read_shared 23136 # read snoops on shared blocks
-system.cpu4.l1c.protocol.snoop_readex_exclusive 1528 # readEx snoops on exclusive blocks
-system.cpu4.l1c.protocol.snoop_readex_modified 6607 # readEx snoops on modified blocks
-system.cpu4.l1c.protocol.snoop_readex_owned 3922 # readEx snoops on owned blocks
-system.cpu4.l1c.protocol.snoop_readex_shared 12524 # readEx snoops on shared blocks
-system.cpu4.l1c.protocol.snoop_upgrade_owned 843 # upgrade snoops on owned blocks
-system.cpu4.l1c.protocol.snoop_upgrade_shared 2904 # upgradee snoops on shared blocks
+system.cpu4.l1c.protocol.snoop_read_exclusive 2847 # read snoops on exclusive blocks
+system.cpu4.l1c.protocol.snoop_read_modified 12499 # read snoops on modified blocks
+system.cpu4.l1c.protocol.snoop_read_owned 7458 # read snoops on owned blocks
+system.cpu4.l1c.protocol.snoop_read_shared 1765770 # read snoops on shared blocks
+system.cpu4.l1c.protocol.snoop_readex_exclusive 1560 # readEx snoops on exclusive blocks
+system.cpu4.l1c.protocol.snoop_readex_modified 6711 # readEx snoops on modified blocks
+system.cpu4.l1c.protocol.snoop_readex_owned 3919 # readEx snoops on owned blocks
+system.cpu4.l1c.protocol.snoop_readex_shared 12526 # readEx snoops on shared blocks
+system.cpu4.l1c.protocol.snoop_upgrade_owned 902 # upgrade snoops on owned blocks
+system.cpu4.l1c.protocol.snoop_upgrade_shared 3023 # upgradee snoops on shared blocks
system.cpu4.l1c.protocol.snoop_writeinv_exclusive 0 # WriteInvalidate snoops on exclusive blocks
system.cpu4.l1c.protocol.snoop_writeinv_invalid 0 # WriteInvalidate snoops on invalid blocks
system.cpu4.l1c.protocol.snoop_writeinv_modified 0 # WriteInvalidate snoops on modified blocks
system.cpu4.l1c.protocol.snoop_writeinv_owned 0 # WriteInvalidate snoops on owned blocks
system.cpu4.l1c.protocol.snoop_writeinv_shared 0 # WriteInvalidate snoops on shared blocks
system.cpu4.l1c.protocol.swpf_invalid 0 # soft prefetch misses to invalid blocks
-system.cpu4.l1c.protocol.write_invalid 59622 # write misses to invalid blocks
-system.cpu4.l1c.protocol.write_owned 1265 # write misses to owned blocks
-system.cpu4.l1c.protocol.write_shared 4187 # write misses to shared blocks
-system.cpu4.l1c.replacements 27000 # number of replacements
-system.cpu4.l1c.sampled_refs 27346 # Sample count of references to valid blocks.
+system.cpu4.l1c.protocol.write_invalid 854606 # write misses to invalid blocks
+system.cpu4.l1c.protocol.write_owned 1318 # write misses to owned blocks
+system.cpu4.l1c.protocol.write_shared 4519 # write misses to shared blocks
+system.cpu4.l1c.replacements 27664 # number of replacements
+system.cpu4.l1c.sampled_refs 28012 # Sample count of references to valid blocks.
system.cpu4.l1c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu4.l1c.tagsinuse 342.121323 # Cycle average of tags in use
-system.cpu4.l1c.total_refs 11386 # Total number of references to valid blocks.
+system.cpu4.l1c.tagsinuse 344.185288 # Cycle average of tags in use
+system.cpu4.l1c.total_refs 11511 # Total number of references to valid blocks.
system.cpu4.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu4.l1c.writebacks 10847 # number of writebacks
+system.cpu4.l1c.writebacks 10935 # number of writebacks
system.cpu4.num_copies 0 # number of copy accesses completed
-system.cpu4.num_reads 98882 # number of read accesses completed
-system.cpu4.num_writes 53288 # number of write accesses completed
-system.cpu5.l1c.ReadReq_accesses 44218 # number of ReadReq accesses(hits+misses)
-system.cpu5.l1c.ReadReq_avg_miss_latency 975.652027 # average ReadReq miss latency
-system.cpu5.l1c.ReadReq_avg_mshr_miss_latency 898.818359 # average ReadReq mshr miss latency
-system.cpu5.l1c.ReadReq_hits 7310 # number of ReadReq hits
-system.cpu5.l1c.ReadReq_miss_latency 36009365 # number of ReadReq miss cycles
-system.cpu5.l1c.ReadReq_miss_rate 0.834683 # miss rate for ReadReq accesses
-system.cpu5.l1c.ReadReq_misses 36908 # number of ReadReq misses
-system.cpu5.l1c.ReadReq_mshr_miss_latency 33173588 # number of ReadReq MSHR miss cycles
-system.cpu5.l1c.ReadReq_mshr_miss_rate 0.834683 # mshr miss rate for ReadReq accesses
-system.cpu5.l1c.ReadReq_mshr_misses 36908 # number of ReadReq MSHR misses
-system.cpu5.l1c.ReadReq_mshr_uncacheable 9866 # number of ReadReq MSHR uncacheable
+system.cpu4.num_reads 99841 # number of read accesses completed
+system.cpu4.num_writes 54005 # number of write accesses completed
+system.cpu5.l1c.ReadReq_accesses 45075 # number of ReadReq accesses(hits+misses)
+system.cpu5.l1c.ReadReq_avg_miss_latency 13980.675167 # average ReadReq miss latency
+system.cpu5.l1c.ReadReq_avg_mshr_miss_latency 12974.186518 # average ReadReq mshr miss latency
+system.cpu5.l1c.ReadReq_hits 7588 # number of ReadReq hits
+system.cpu5.l1c.ReadReq_miss_latency 524093570 # number of ReadReq miss cycles
+system.cpu5.l1c.ReadReq_miss_rate 0.831658 # miss rate for ReadReq accesses
+system.cpu5.l1c.ReadReq_misses 37487 # number of ReadReq misses
+system.cpu5.l1c.ReadReq_mshr_miss_latency 486363330 # number of ReadReq MSHR miss cycles
+system.cpu5.l1c.ReadReq_mshr_miss_rate 0.831658 # mshr miss rate for ReadReq accesses
+system.cpu5.l1c.ReadReq_mshr_misses 37487 # number of ReadReq MSHR misses
+system.cpu5.l1c.ReadReq_mshr_uncacheable 9769 # number of ReadReq MSHR uncacheable
system.cpu5.l1c.ReadResp_avg_mshr_uncacheable_latency inf # average ReadResp mshr uncacheable latency
-system.cpu5.l1c.ReadResp_mshr_uncacheable_latency 17625443 # number of ReadResp MSHR uncacheable cycles
-system.cpu5.l1c.WriteReq_accesses 23923 # number of WriteReq accesses(hits+misses)
-system.cpu5.l1c.WriteReq_avg_miss_latency 873.308611 # average WriteReq miss latency
-system.cpu5.l1c.WriteReq_avg_mshr_miss_latency 788.173188 # average WriteReq mshr miss latency
-system.cpu5.l1c.WriteReq_hits 1150 # number of WriteReq hits
-system.cpu5.l1c.WriteReq_miss_latency 19887857 # number of WriteReq miss cycles
-system.cpu5.l1c.WriteReq_miss_rate 0.951929 # miss rate for WriteReq accesses
-system.cpu5.l1c.WriteReq_misses 22773 # number of WriteReq misses
-system.cpu5.l1c.WriteReq_mshr_miss_latency 17949068 # number of WriteReq MSHR miss cycles
-system.cpu5.l1c.WriteReq_mshr_miss_rate 0.951929 # mshr miss rate for WriteReq accesses
-system.cpu5.l1c.WriteReq_mshr_misses 22773 # number of WriteReq MSHR misses
-system.cpu5.l1c.WriteReq_mshr_uncacheable 5207 # number of WriteReq MSHR uncacheable
+system.cpu5.l1c.ReadResp_mshr_uncacheable_latency 252483534 # number of ReadResp MSHR uncacheable cycles
+system.cpu5.l1c.WriteReq_accesses 24120 # number of WriteReq accesses(hits+misses)
+system.cpu5.l1c.WriteReq_avg_miss_latency 12733.111936 # average WriteReq miss latency
+system.cpu5.l1c.WriteReq_avg_mshr_miss_latency 11249.826210 # average WriteReq mshr miss latency
+system.cpu5.l1c.WriteReq_hits 1098 # number of WriteReq hits
+system.cpu5.l1c.WriteReq_miss_latency 293141703 # number of WriteReq miss cycles
+system.cpu5.l1c.WriteReq_miss_rate 0.954478 # miss rate for WriteReq accesses
+system.cpu5.l1c.WriteReq_misses 23022 # number of WriteReq misses
+system.cpu5.l1c.WriteReq_mshr_miss_latency 258993499 # number of WriteReq MSHR miss cycles
+system.cpu5.l1c.WriteReq_mshr_miss_rate 0.954478 # mshr miss rate for WriteReq accesses
+system.cpu5.l1c.WriteReq_mshr_misses 23022 # number of WriteReq MSHR misses
+system.cpu5.l1c.WriteReq_mshr_uncacheable 5232 # number of WriteReq MSHR uncacheable
system.cpu5.l1c.WriteResp_avg_mshr_uncacheable_latency inf # average WriteResp mshr uncacheable latency
-system.cpu5.l1c.WriteResp_mshr_uncacheable_latency 10374807 # number of WriteResp MSHR uncacheable cycles
-system.cpu5.l1c.avg_blocked_cycles_no_mshrs 82.590363 # average number of cycles each access was blocked
+system.cpu5.l1c.WriteResp_mshr_uncacheable_latency 155064988 # number of WriteResp MSHR uncacheable cycles
+system.cpu5.l1c.avg_blocked_cycles_no_mshrs 1188.349008 # average number of cycles each access was blocked
system.cpu5.l1c.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
-system.cpu5.l1c.avg_refs 0.413664 # Average number of references to valid blocks.
-system.cpu5.l1c.blocked_no_mshrs 68944 # number of cycles access was blocked
+system.cpu5.l1c.avg_refs 0.414917 # Average number of references to valid blocks.
+system.cpu5.l1c.blocked_no_mshrs 69537 # number of cycles access was blocked
system.cpu5.l1c.blocked_no_targets 0 # number of cycles access was blocked
-system.cpu5.l1c.blocked_cycles_no_mshrs 5694110 # number of cycles access was blocked
+system.cpu5.l1c.blocked_cycles_no_mshrs 82634225 # number of cycles access was blocked
system.cpu5.l1c.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu5.l1c.cache_copies 0 # number of cache copies performed
-system.cpu5.l1c.demand_accesses 68141 # number of demand (read+write) accesses
-system.cpu5.l1c.demand_avg_miss_latency 936.599956 # average overall miss latency
-system.cpu5.l1c.demand_avg_mshr_miss_latency 856.598515 # average overall mshr miss latency
-system.cpu5.l1c.demand_hits 8460 # number of demand (read+write) hits
-system.cpu5.l1c.demand_miss_latency 55897222 # number of demand (read+write) miss cycles
-system.cpu5.l1c.demand_miss_rate 0.875846 # miss rate for demand accesses
-system.cpu5.l1c.demand_misses 59681 # number of demand (read+write) misses
+system.cpu5.l1c.demand_accesses 69195 # number of demand (read+write) accesses
+system.cpu5.l1c.demand_avg_miss_latency 13506.011883 # average overall miss latency
+system.cpu5.l1c.demand_avg_mshr_miss_latency 12318.115140 # average overall mshr miss latency
+system.cpu5.l1c.demand_hits 8686 # number of demand (read+write) hits
+system.cpu5.l1c.demand_miss_latency 817235273 # number of demand (read+write) miss cycles
+system.cpu5.l1c.demand_miss_rate 0.874471 # miss rate for demand accesses
+system.cpu5.l1c.demand_misses 60509 # number of demand (read+write) misses
system.cpu5.l1c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu5.l1c.demand_mshr_miss_latency 51122656 # number of demand (read+write) MSHR miss cycles
-system.cpu5.l1c.demand_mshr_miss_rate 0.875846 # mshr miss rate for demand accesses
-system.cpu5.l1c.demand_mshr_misses 59681 # number of demand (read+write) MSHR misses
+system.cpu5.l1c.demand_mshr_miss_latency 745356829 # number of demand (read+write) MSHR miss cycles
+system.cpu5.l1c.demand_mshr_miss_rate 0.874471 # mshr miss rate for demand accesses
+system.cpu5.l1c.demand_mshr_misses 60509 # number of demand (read+write) MSHR misses
system.cpu5.l1c.fast_writes 0 # number of fast writes performed
system.cpu5.l1c.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu5.l1c.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu5.l1c.overall_accesses 68141 # number of overall (read+write) accesses
-system.cpu5.l1c.overall_avg_miss_latency 936.599956 # average overall miss latency
-system.cpu5.l1c.overall_avg_mshr_miss_latency 856.598515 # average overall mshr miss latency
+system.cpu5.l1c.overall_accesses 69195 # number of overall (read+write) accesses
+system.cpu5.l1c.overall_avg_miss_latency 13506.011883 # average overall miss latency
+system.cpu5.l1c.overall_avg_mshr_miss_latency 12318.115140 # average overall mshr miss latency
system.cpu5.l1c.overall_avg_mshr_uncacheable_latency 0 # average overall mshr uncacheable latency
-system.cpu5.l1c.overall_hits 8460 # number of overall hits
-system.cpu5.l1c.overall_miss_latency 55897222 # number of overall miss cycles
-system.cpu5.l1c.overall_miss_rate 0.875846 # miss rate for overall accesses
-system.cpu5.l1c.overall_misses 59681 # number of overall misses
+system.cpu5.l1c.overall_hits 8686 # number of overall hits
+system.cpu5.l1c.overall_miss_latency 817235273 # number of overall miss cycles
+system.cpu5.l1c.overall_miss_rate 0.874471 # miss rate for overall accesses
+system.cpu5.l1c.overall_misses 60509 # number of overall misses
system.cpu5.l1c.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu5.l1c.overall_mshr_miss_latency 51122656 # number of overall MSHR miss cycles
-system.cpu5.l1c.overall_mshr_miss_rate 0.875846 # mshr miss rate for overall accesses
-system.cpu5.l1c.overall_mshr_misses 59681 # number of overall MSHR misses
+system.cpu5.l1c.overall_mshr_miss_latency 745356829 # number of overall MSHR miss cycles
+system.cpu5.l1c.overall_mshr_miss_rate 0.874471 # mshr miss rate for overall accesses
+system.cpu5.l1c.overall_mshr_misses 60509 # number of overall MSHR misses
system.cpu5.l1c.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu5.l1c.overall_mshr_uncacheable_misses 15073 # number of overall MSHR uncacheable misses
+system.cpu5.l1c.overall_mshr_uncacheable_misses 15001 # number of overall MSHR uncacheable misses
system.cpu5.l1c.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
system.cpu5.l1c.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
system.cpu5.l1c.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
@@ -613,103 +613,103 @@ system.cpu5.l1c.prefetcher.num_hwpf_removed_MSHR_hit 0
system.cpu5.l1c.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu5.l1c.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
system.cpu5.l1c.protocol.hwpf_invalid 0 # hard prefetch misses to invalid blocks
-system.cpu5.l1c.protocol.read_invalid 114279 # read misses to invalid blocks
+system.cpu5.l1c.protocol.read_invalid 1718821 # read misses to invalid blocks
system.cpu5.l1c.protocol.snoop_inv_exclusive 0 # Invalidate snoops on exclusive blocks
system.cpu5.l1c.protocol.snoop_inv_invalid 0 # Invalidate snoops on invalid blocks
system.cpu5.l1c.protocol.snoop_inv_modified 0 # Invalidate snoops on modified blocks
system.cpu5.l1c.protocol.snoop_inv_owned 0 # Invalidate snoops on owned blocks
system.cpu5.l1c.protocol.snoop_inv_shared 0 # Invalidate snoops on shared blocks
-system.cpu5.l1c.protocol.snoop_read_exclusive 2860 # read snoops on exclusive blocks
-system.cpu5.l1c.protocol.snoop_read_modified 12253 # read snoops on modified blocks
-system.cpu5.l1c.protocol.snoop_read_owned 7231 # read snoops on owned blocks
-system.cpu5.l1c.protocol.snoop_read_shared 23182 # read snoops on shared blocks
-system.cpu5.l1c.protocol.snoop_readex_exclusive 1499 # readEx snoops on exclusive blocks
-system.cpu5.l1c.protocol.snoop_readex_modified 6757 # readEx snoops on modified blocks
-system.cpu5.l1c.protocol.snoop_readex_owned 3896 # readEx snoops on owned blocks
-system.cpu5.l1c.protocol.snoop_readex_shared 12461 # readEx snoops on shared blocks
-system.cpu5.l1c.protocol.snoop_upgrade_owned 887 # upgrade snoops on owned blocks
-system.cpu5.l1c.protocol.snoop_upgrade_shared 3020 # upgradee snoops on shared blocks
+system.cpu5.l1c.protocol.snoop_read_exclusive 2926 # read snoops on exclusive blocks
+system.cpu5.l1c.protocol.snoop_read_modified 12465 # read snoops on modified blocks
+system.cpu5.l1c.protocol.snoop_read_owned 7201 # read snoops on owned blocks
+system.cpu5.l1c.protocol.snoop_read_shared 1810557 # read snoops on shared blocks
+system.cpu5.l1c.protocol.snoop_readex_exclusive 1622 # readEx snoops on exclusive blocks
+system.cpu5.l1c.protocol.snoop_readex_modified 6690 # readEx snoops on modified blocks
+system.cpu5.l1c.protocol.snoop_readex_owned 3947 # readEx snoops on owned blocks
+system.cpu5.l1c.protocol.snoop_readex_shared 12574 # readEx snoops on shared blocks
+system.cpu5.l1c.protocol.snoop_upgrade_owned 818 # upgrade snoops on owned blocks
+system.cpu5.l1c.protocol.snoop_upgrade_shared 3092 # upgradee snoops on shared blocks
system.cpu5.l1c.protocol.snoop_writeinv_exclusive 0 # WriteInvalidate snoops on exclusive blocks
system.cpu5.l1c.protocol.snoop_writeinv_invalid 0 # WriteInvalidate snoops on invalid blocks
system.cpu5.l1c.protocol.snoop_writeinv_modified 0 # WriteInvalidate snoops on modified blocks
system.cpu5.l1c.protocol.snoop_writeinv_owned 0 # WriteInvalidate snoops on owned blocks
system.cpu5.l1c.protocol.snoop_writeinv_shared 0 # WriteInvalidate snoops on shared blocks
system.cpu5.l1c.protocol.swpf_invalid 0 # soft prefetch misses to invalid blocks
-system.cpu5.l1c.protocol.write_invalid 60969 # write misses to invalid blocks
-system.cpu5.l1c.protocol.write_owned 1349 # write misses to owned blocks
-system.cpu5.l1c.protocol.write_shared 4191 # write misses to shared blocks
-system.cpu5.l1c.replacements 26828 # number of replacements
-system.cpu5.l1c.sampled_refs 27196 # Sample count of references to valid blocks.
+system.cpu5.l1c.protocol.write_invalid 914561 # write misses to invalid blocks
+system.cpu5.l1c.protocol.write_owned 1422 # write misses to owned blocks
+system.cpu5.l1c.protocol.write_shared 4534 # write misses to shared blocks
+system.cpu5.l1c.replacements 27551 # number of replacements
+system.cpu5.l1c.sampled_refs 27914 # Sample count of references to valid blocks.
system.cpu5.l1c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu5.l1c.tagsinuse 340.865502 # Cycle average of tags in use
-system.cpu5.l1c.total_refs 11250 # Total number of references to valid blocks.
+system.cpu5.l1c.tagsinuse 344.440637 # Cycle average of tags in use
+system.cpu5.l1c.total_refs 11582 # Total number of references to valid blocks.
system.cpu5.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu5.l1c.writebacks 10567 # number of writebacks
+system.cpu5.l1c.writebacks 10931 # number of writebacks
system.cpu5.num_copies 0 # number of copy accesses completed
-system.cpu5.num_reads 97882 # number of read accesses completed
-system.cpu5.num_writes 52965 # number of write accesses completed
-system.cpu6.l1c.ReadReq_accesses 44971 # number of ReadReq accesses(hits+misses)
-system.cpu6.l1c.ReadReq_avg_miss_latency 967.006541 # average ReadReq miss latency
-system.cpu6.l1c.ReadReq_avg_mshr_miss_latency 890.563660 # average ReadReq mshr miss latency
-system.cpu6.l1c.ReadReq_hits 7514 # number of ReadReq hits
-system.cpu6.l1c.ReadReq_miss_latency 36221164 # number of ReadReq miss cycles
-system.cpu6.l1c.ReadReq_miss_rate 0.832915 # miss rate for ReadReq accesses
-system.cpu6.l1c.ReadReq_misses 37457 # number of ReadReq misses
-system.cpu6.l1c.ReadReq_mshr_miss_latency 33357843 # number of ReadReq MSHR miss cycles
-system.cpu6.l1c.ReadReq_mshr_miss_rate 0.832915 # mshr miss rate for ReadReq accesses
-system.cpu6.l1c.ReadReq_mshr_misses 37457 # number of ReadReq MSHR misses
-system.cpu6.l1c.ReadReq_mshr_uncacheable 9684 # number of ReadReq MSHR uncacheable
+system.cpu5.num_reads 99674 # number of read accesses completed
+system.cpu5.num_writes 53393 # number of write accesses completed
+system.cpu6.l1c.ReadReq_accesses 44595 # number of ReadReq accesses(hits+misses)
+system.cpu6.l1c.ReadReq_avg_miss_latency 14001.082353 # average ReadReq miss latency
+system.cpu6.l1c.ReadReq_avg_mshr_miss_latency 12995.526917 # average ReadReq mshr miss latency
+system.cpu6.l1c.ReadReq_hits 7462 # number of ReadReq hits
+system.cpu6.l1c.ReadReq_miss_latency 519902191 # number of ReadReq miss cycles
+system.cpu6.l1c.ReadReq_miss_rate 0.832672 # miss rate for ReadReq accesses
+system.cpu6.l1c.ReadReq_misses 37133 # number of ReadReq misses
+system.cpu6.l1c.ReadReq_mshr_miss_latency 482562901 # number of ReadReq MSHR miss cycles
+system.cpu6.l1c.ReadReq_mshr_miss_rate 0.832672 # mshr miss rate for ReadReq accesses
+system.cpu6.l1c.ReadReq_mshr_misses 37133 # number of ReadReq MSHR misses
+system.cpu6.l1c.ReadReq_mshr_uncacheable 9820 # number of ReadReq MSHR uncacheable
system.cpu6.l1c.ReadResp_avg_mshr_uncacheable_latency inf # average ReadResp mshr uncacheable latency
-system.cpu6.l1c.ReadResp_mshr_uncacheable_latency 17275344 # number of ReadResp MSHR uncacheable cycles
-system.cpu6.l1c.WriteReq_accesses 23996 # number of WriteReq accesses(hits+misses)
-system.cpu6.l1c.WriteReq_avg_miss_latency 873.777515 # average WriteReq miss latency
-system.cpu6.l1c.WriteReq_avg_mshr_miss_latency 790.631514 # average WriteReq mshr miss latency
-system.cpu6.l1c.WriteReq_hits 1181 # number of WriteReq hits
-system.cpu6.l1c.WriteReq_miss_latency 19935234 # number of WriteReq miss cycles
-system.cpu6.l1c.WriteReq_miss_rate 0.950783 # miss rate for WriteReq accesses
-system.cpu6.l1c.WriteReq_misses 22815 # number of WriteReq misses
-system.cpu6.l1c.WriteReq_mshr_miss_latency 18038258 # number of WriteReq MSHR miss cycles
-system.cpu6.l1c.WriteReq_mshr_miss_rate 0.950783 # mshr miss rate for WriteReq accesses
-system.cpu6.l1c.WriteReq_mshr_misses 22815 # number of WriteReq MSHR misses
-system.cpu6.l1c.WriteReq_mshr_uncacheable 5345 # number of WriteReq MSHR uncacheable
+system.cpu6.l1c.ReadResp_mshr_uncacheable_latency 251671127 # number of ReadResp MSHR uncacheable cycles
+system.cpu6.l1c.WriteReq_accesses 24364 # number of WriteReq accesses(hits+misses)
+system.cpu6.l1c.WriteReq_avg_miss_latency 12854.640783 # average WriteReq miss latency
+system.cpu6.l1c.WriteReq_avg_mshr_miss_latency 11385.598176 # average WriteReq mshr miss latency
+system.cpu6.l1c.WriteReq_hits 1222 # number of WriteReq hits
+system.cpu6.l1c.WriteReq_miss_latency 297482097 # number of WriteReq miss cycles
+system.cpu6.l1c.WriteReq_miss_rate 0.949844 # miss rate for WriteReq accesses
+system.cpu6.l1c.WriteReq_misses 23142 # number of WriteReq misses
+system.cpu6.l1c.WriteReq_mshr_miss_latency 263485513 # number of WriteReq MSHR miss cycles
+system.cpu6.l1c.WriteReq_mshr_miss_rate 0.949844 # mshr miss rate for WriteReq accesses
+system.cpu6.l1c.WriteReq_mshr_misses 23142 # number of WriteReq MSHR misses
+system.cpu6.l1c.WriteReq_mshr_uncacheable 5447 # number of WriteReq MSHR uncacheable
system.cpu6.l1c.WriteResp_avg_mshr_uncacheable_latency inf # average WriteResp mshr uncacheable latency
-system.cpu6.l1c.WriteResp_mshr_uncacheable_latency 10602140 # number of WriteResp MSHR uncacheable cycles
-system.cpu6.l1c.avg_blocked_cycles_no_mshrs 82.071085 # average number of cycles each access was blocked
+system.cpu6.l1c.WriteResp_mshr_uncacheable_latency 163399316 # number of WriteResp MSHR uncacheable cycles
+system.cpu6.l1c.avg_blocked_cycles_no_mshrs 1189.328084 # average number of cycles each access was blocked
system.cpu6.l1c.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
-system.cpu6.l1c.avg_refs 0.412251 # Average number of references to valid blocks.
-system.cpu6.l1c.blocked_no_mshrs 69157 # number of cycles access was blocked
+system.cpu6.l1c.avg_refs 0.411043 # Average number of references to valid blocks.
+system.cpu6.l1c.blocked_no_mshrs 69345 # number of cycles access was blocked
system.cpu6.l1c.blocked_no_targets 0 # number of cycles access was blocked
-system.cpu6.l1c.blocked_cycles_no_mshrs 5675790 # number of cycles access was blocked
+system.cpu6.l1c.blocked_cycles_no_mshrs 82473956 # number of cycles access was blocked
system.cpu6.l1c.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu6.l1c.cache_copies 0 # number of cache copies performed
-system.cpu6.l1c.demand_accesses 68967 # number of demand (read+write) accesses
-system.cpu6.l1c.demand_avg_miss_latency 931.716187 # average overall miss latency
-system.cpu6.l1c.demand_avg_mshr_miss_latency 852.735947 # average overall mshr miss latency
-system.cpu6.l1c.demand_hits 8695 # number of demand (read+write) hits
-system.cpu6.l1c.demand_miss_latency 56156398 # number of demand (read+write) miss cycles
-system.cpu6.l1c.demand_miss_rate 0.873925 # miss rate for demand accesses
-system.cpu6.l1c.demand_misses 60272 # number of demand (read+write) misses
+system.cpu6.l1c.demand_accesses 68959 # number of demand (read+write) accesses
+system.cpu6.l1c.demand_avg_miss_latency 13560.917263 # average overall miss latency
+system.cpu6.l1c.demand_avg_mshr_miss_latency 12377.410436 # average overall mshr miss latency
+system.cpu6.l1c.demand_hits 8684 # number of demand (read+write) hits
+system.cpu6.l1c.demand_miss_latency 817384288 # number of demand (read+write) miss cycles
+system.cpu6.l1c.demand_miss_rate 0.874070 # miss rate for demand accesses
+system.cpu6.l1c.demand_misses 60275 # number of demand (read+write) misses
system.cpu6.l1c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu6.l1c.demand_mshr_miss_latency 51396101 # number of demand (read+write) MSHR miss cycles
-system.cpu6.l1c.demand_mshr_miss_rate 0.873925 # mshr miss rate for demand accesses
-system.cpu6.l1c.demand_mshr_misses 60272 # number of demand (read+write) MSHR misses
+system.cpu6.l1c.demand_mshr_miss_latency 746048414 # number of demand (read+write) MSHR miss cycles
+system.cpu6.l1c.demand_mshr_miss_rate 0.874070 # mshr miss rate for demand accesses
+system.cpu6.l1c.demand_mshr_misses 60275 # number of demand (read+write) MSHR misses
system.cpu6.l1c.fast_writes 0 # number of fast writes performed
system.cpu6.l1c.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu6.l1c.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu6.l1c.overall_accesses 68967 # number of overall (read+write) accesses
-system.cpu6.l1c.overall_avg_miss_latency 931.716187 # average overall miss latency
-system.cpu6.l1c.overall_avg_mshr_miss_latency 852.735947 # average overall mshr miss latency
+system.cpu6.l1c.overall_accesses 68959 # number of overall (read+write) accesses
+system.cpu6.l1c.overall_avg_miss_latency 13560.917263 # average overall miss latency
+system.cpu6.l1c.overall_avg_mshr_miss_latency 12377.410436 # average overall mshr miss latency
system.cpu6.l1c.overall_avg_mshr_uncacheable_latency 0 # average overall mshr uncacheable latency
-system.cpu6.l1c.overall_hits 8695 # number of overall hits
-system.cpu6.l1c.overall_miss_latency 56156398 # number of overall miss cycles
-system.cpu6.l1c.overall_miss_rate 0.873925 # miss rate for overall accesses
-system.cpu6.l1c.overall_misses 60272 # number of overall misses
+system.cpu6.l1c.overall_hits 8684 # number of overall hits
+system.cpu6.l1c.overall_miss_latency 817384288 # number of overall miss cycles
+system.cpu6.l1c.overall_miss_rate 0.874070 # miss rate for overall accesses
+system.cpu6.l1c.overall_misses 60275 # number of overall misses
system.cpu6.l1c.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu6.l1c.overall_mshr_miss_latency 51396101 # number of overall MSHR miss cycles
-system.cpu6.l1c.overall_mshr_miss_rate 0.873925 # mshr miss rate for overall accesses
-system.cpu6.l1c.overall_mshr_misses 60272 # number of overall MSHR misses
+system.cpu6.l1c.overall_mshr_miss_latency 746048414 # number of overall MSHR miss cycles
+system.cpu6.l1c.overall_mshr_miss_rate 0.874070 # mshr miss rate for overall accesses
+system.cpu6.l1c.overall_mshr_misses 60275 # number of overall MSHR misses
system.cpu6.l1c.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu6.l1c.overall_mshr_uncacheable_misses 15029 # number of overall MSHR uncacheable misses
+system.cpu6.l1c.overall_mshr_uncacheable_misses 15267 # number of overall MSHR uncacheable misses
system.cpu6.l1c.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
system.cpu6.l1c.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
system.cpu6.l1c.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
@@ -720,103 +720,103 @@ system.cpu6.l1c.prefetcher.num_hwpf_removed_MSHR_hit 0
system.cpu6.l1c.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu6.l1c.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
system.cpu6.l1c.protocol.hwpf_invalid 0 # hard prefetch misses to invalid blocks
-system.cpu6.l1c.protocol.read_invalid 114488 # read misses to invalid blocks
+system.cpu6.l1c.protocol.read_invalid 1894590 # read misses to invalid blocks
system.cpu6.l1c.protocol.snoop_inv_exclusive 0 # Invalidate snoops on exclusive blocks
system.cpu6.l1c.protocol.snoop_inv_invalid 0 # Invalidate snoops on invalid blocks
system.cpu6.l1c.protocol.snoop_inv_modified 0 # Invalidate snoops on modified blocks
system.cpu6.l1c.protocol.snoop_inv_owned 0 # Invalidate snoops on owned blocks
system.cpu6.l1c.protocol.snoop_inv_shared 0 # Invalidate snoops on shared blocks
-system.cpu6.l1c.protocol.snoop_read_exclusive 2876 # read snoops on exclusive blocks
-system.cpu6.l1c.protocol.snoop_read_modified 12371 # read snoops on modified blocks
-system.cpu6.l1c.protocol.snoop_read_owned 7223 # read snoops on owned blocks
-system.cpu6.l1c.protocol.snoop_read_shared 23305 # read snoops on shared blocks
-system.cpu6.l1c.protocol.snoop_readex_exclusive 1616 # readEx snoops on exclusive blocks
-system.cpu6.l1c.protocol.snoop_readex_modified 6693 # readEx snoops on modified blocks
-system.cpu6.l1c.protocol.snoop_readex_owned 3909 # readEx snoops on owned blocks
-system.cpu6.l1c.protocol.snoop_readex_shared 12446 # readEx snoops on shared blocks
-system.cpu6.l1c.protocol.snoop_upgrade_owned 833 # upgrade snoops on owned blocks
-system.cpu6.l1c.protocol.snoop_upgrade_shared 2948 # upgradee snoops on shared blocks
+system.cpu6.l1c.protocol.snoop_read_exclusive 2887 # read snoops on exclusive blocks
+system.cpu6.l1c.protocol.snoop_read_modified 12551 # read snoops on modified blocks
+system.cpu6.l1c.protocol.snoop_read_owned 7188 # read snoops on owned blocks
+system.cpu6.l1c.protocol.snoop_read_shared 1703425 # read snoops on shared blocks
+system.cpu6.l1c.protocol.snoop_readex_exclusive 1550 # readEx snoops on exclusive blocks
+system.cpu6.l1c.protocol.snoop_readex_modified 6733 # readEx snoops on modified blocks
+system.cpu6.l1c.protocol.snoop_readex_owned 3926 # readEx snoops on owned blocks
+system.cpu6.l1c.protocol.snoop_readex_shared 12456 # readEx snoops on shared blocks
+system.cpu6.l1c.protocol.snoop_upgrade_owned 800 # upgrade snoops on owned blocks
+system.cpu6.l1c.protocol.snoop_upgrade_shared 3156 # upgradee snoops on shared blocks
system.cpu6.l1c.protocol.snoop_writeinv_exclusive 0 # WriteInvalidate snoops on exclusive blocks
system.cpu6.l1c.protocol.snoop_writeinv_invalid 0 # WriteInvalidate snoops on invalid blocks
system.cpu6.l1c.protocol.snoop_writeinv_modified 0 # WriteInvalidate snoops on modified blocks
system.cpu6.l1c.protocol.snoop_writeinv_owned 0 # WriteInvalidate snoops on owned blocks
system.cpu6.l1c.protocol.snoop_writeinv_shared 0 # WriteInvalidate snoops on shared blocks
system.cpu6.l1c.protocol.swpf_invalid 0 # soft prefetch misses to invalid blocks
-system.cpu6.l1c.protocol.write_invalid 58413 # write misses to invalid blocks
-system.cpu6.l1c.protocol.write_owned 1374 # write misses to owned blocks
-system.cpu6.l1c.protocol.write_shared 4109 # write misses to shared blocks
-system.cpu6.l1c.replacements 27477 # number of replacements
-system.cpu6.l1c.sampled_refs 27835 # Sample count of references to valid blocks.
+system.cpu6.l1c.protocol.write_invalid 987928 # write misses to invalid blocks
+system.cpu6.l1c.protocol.write_owned 1405 # write misses to owned blocks
+system.cpu6.l1c.protocol.write_shared 4406 # write misses to shared blocks
+system.cpu6.l1c.replacements 27613 # number of replacements
+system.cpu6.l1c.sampled_refs 27946 # Sample count of references to valid blocks.
system.cpu6.l1c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu6.l1c.tagsinuse 342.134742 # Cycle average of tags in use
-system.cpu6.l1c.total_refs 11475 # Total number of references to valid blocks.
+system.cpu6.l1c.tagsinuse 344.860122 # Cycle average of tags in use
+system.cpu6.l1c.total_refs 11487 # Total number of references to valid blocks.
system.cpu6.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu6.l1c.writebacks 10759 # number of writebacks
+system.cpu6.l1c.writebacks 11073 # number of writebacks
system.cpu6.num_copies 0 # number of copy accesses completed
-system.cpu6.num_reads 99303 # number of read accesses completed
-system.cpu6.num_writes 53385 # number of write accesses completed
-system.cpu7.l1c.ReadReq_accesses 44438 # number of ReadReq accesses(hits+misses)
-system.cpu7.l1c.ReadReq_avg_miss_latency 975.306986 # average ReadReq miss latency
-system.cpu7.l1c.ReadReq_avg_mshr_miss_latency 899.340271 # average ReadReq mshr miss latency
-system.cpu7.l1c.ReadReq_hits 7394 # number of ReadReq hits
-system.cpu7.l1c.ReadReq_miss_latency 36129272 # number of ReadReq miss cycles
-system.cpu7.l1c.ReadReq_miss_rate 0.833611 # miss rate for ReadReq accesses
-system.cpu7.l1c.ReadReq_misses 37044 # number of ReadReq misses
-system.cpu7.l1c.ReadReq_mshr_miss_latency 33315161 # number of ReadReq MSHR miss cycles
-system.cpu7.l1c.ReadReq_mshr_miss_rate 0.833611 # mshr miss rate for ReadReq accesses
-system.cpu7.l1c.ReadReq_mshr_misses 37044 # number of ReadReq MSHR misses
-system.cpu7.l1c.ReadReq_mshr_uncacheable 9861 # number of ReadReq MSHR uncacheable
+system.cpu6.num_reads 98723 # number of read accesses completed
+system.cpu6.num_writes 53876 # number of write accesses completed
+system.cpu7.l1c.ReadReq_accesses 44990 # number of ReadReq accesses(hits+misses)
+system.cpu7.l1c.ReadReq_avg_miss_latency 13952.283047 # average ReadReq miss latency
+system.cpu7.l1c.ReadReq_avg_mshr_miss_latency 12937.789329 # average ReadReq mshr miss latency
+system.cpu7.l1c.ReadReq_hits 7505 # number of ReadReq hits
+system.cpu7.l1c.ReadReq_miss_latency 523001330 # number of ReadReq miss cycles
+system.cpu7.l1c.ReadReq_miss_rate 0.833185 # miss rate for ReadReq accesses
+system.cpu7.l1c.ReadReq_misses 37485 # number of ReadReq misses
+system.cpu7.l1c.ReadReq_mshr_miss_latency 484973033 # number of ReadReq MSHR miss cycles
+system.cpu7.l1c.ReadReq_mshr_miss_rate 0.833185 # mshr miss rate for ReadReq accesses
+system.cpu7.l1c.ReadReq_mshr_misses 37485 # number of ReadReq MSHR misses
+system.cpu7.l1c.ReadReq_mshr_uncacheable 10001 # number of ReadReq MSHR uncacheable
system.cpu7.l1c.ReadResp_avg_mshr_uncacheable_latency inf # average ReadResp mshr uncacheable latency
-system.cpu7.l1c.ReadResp_mshr_uncacheable_latency 17576395 # number of ReadResp MSHR uncacheable cycles
-system.cpu7.l1c.WriteReq_accesses 23999 # number of WriteReq accesses(hits+misses)
-system.cpu7.l1c.WriteReq_avg_miss_latency 861.568979 # average WriteReq miss latency
-system.cpu7.l1c.WriteReq_avg_mshr_miss_latency 776.580264 # average WriteReq mshr miss latency
-system.cpu7.l1c.WriteReq_hits 1137 # number of WriteReq hits
-system.cpu7.l1c.WriteReq_miss_latency 19697190 # number of WriteReq miss cycles
-system.cpu7.l1c.WriteReq_miss_rate 0.952623 # miss rate for WriteReq accesses
-system.cpu7.l1c.WriteReq_misses 22862 # number of WriteReq misses
-system.cpu7.l1c.WriteReq_mshr_miss_latency 17754178 # number of WriteReq MSHR miss cycles
-system.cpu7.l1c.WriteReq_mshr_miss_rate 0.952623 # mshr miss rate for WriteReq accesses
-system.cpu7.l1c.WriteReq_mshr_misses 22862 # number of WriteReq MSHR misses
-system.cpu7.l1c.WriteReq_mshr_uncacheable 5386 # number of WriteReq MSHR uncacheable
+system.cpu7.l1c.ReadResp_mshr_uncacheable_latency 257188342 # number of ReadResp MSHR uncacheable cycles
+system.cpu7.l1c.WriteReq_accesses 24083 # number of WriteReq accesses(hits+misses)
+system.cpu7.l1c.WriteReq_avg_miss_latency 12615.682417 # average WriteReq miss latency
+system.cpu7.l1c.WriteReq_avg_mshr_miss_latency 11155.458639 # average WriteReq mshr miss latency
+system.cpu7.l1c.WriteReq_hits 1163 # number of WriteReq hits
+system.cpu7.l1c.WriteReq_miss_latency 289151441 # number of WriteReq miss cycles
+system.cpu7.l1c.WriteReq_miss_rate 0.951709 # miss rate for WriteReq accesses
+system.cpu7.l1c.WriteReq_misses 22920 # number of WriteReq misses
+system.cpu7.l1c.WriteReq_mshr_miss_latency 255683112 # number of WriteReq MSHR miss cycles
+system.cpu7.l1c.WriteReq_mshr_miss_rate 0.951709 # mshr miss rate for WriteReq accesses
+system.cpu7.l1c.WriteReq_mshr_misses 22920 # number of WriteReq MSHR misses
+system.cpu7.l1c.WriteReq_mshr_uncacheable 5323 # number of WriteReq MSHR uncacheable
system.cpu7.l1c.WriteResp_avg_mshr_uncacheable_latency inf # average WriteResp mshr uncacheable latency
-system.cpu7.l1c.WriteResp_mshr_uncacheable_latency 10720857 # number of WriteResp MSHR uncacheable cycles
-system.cpu7.l1c.avg_blocked_cycles_no_mshrs 82.167211 # average number of cycles each access was blocked
+system.cpu7.l1c.WriteResp_mshr_uncacheable_latency 159397105 # number of WriteResp MSHR uncacheable cycles
+system.cpu7.l1c.avg_blocked_cycles_no_mshrs 1185.864523 # average number of cycles each access was blocked
system.cpu7.l1c.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
-system.cpu7.l1c.avg_refs 0.419292 # Average number of references to valid blocks.
-system.cpu7.l1c.blocked_no_mshrs 68907 # number of cycles access was blocked
+system.cpu7.l1c.avg_refs 0.413879 # Average number of references to valid blocks.
+system.cpu7.l1c.blocked_no_mshrs 69665 # number of cycles access was blocked
system.cpu7.l1c.blocked_no_targets 0 # number of cycles access was blocked
-system.cpu7.l1c.blocked_cycles_no_mshrs 5661896 # number of cycles access was blocked
+system.cpu7.l1c.blocked_cycles_no_mshrs 82613252 # number of cycles access was blocked
system.cpu7.l1c.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu7.l1c.cache_copies 0 # number of cache copies performed
-system.cpu7.l1c.demand_accesses 68437 # number of demand (read+write) accesses
-system.cpu7.l1c.demand_avg_miss_latency 931.901012 # average overall miss latency
-system.cpu7.l1c.demand_avg_mshr_miss_latency 852.491220 # average overall mshr miss latency
-system.cpu7.l1c.demand_hits 8531 # number of demand (read+write) hits
-system.cpu7.l1c.demand_miss_latency 55826462 # number of demand (read+write) miss cycles
-system.cpu7.l1c.demand_miss_rate 0.875345 # miss rate for demand accesses
-system.cpu7.l1c.demand_misses 59906 # number of demand (read+write) misses
+system.cpu7.l1c.demand_accesses 69073 # number of demand (read+write) accesses
+system.cpu7.l1c.demand_avg_miss_latency 13445.124923 # average overall miss latency
+system.cpu7.l1c.demand_avg_mshr_miss_latency 12261.503932 # average overall mshr miss latency
+system.cpu7.l1c.demand_hits 8668 # number of demand (read+write) hits
+system.cpu7.l1c.demand_miss_latency 812152771 # number of demand (read+write) miss cycles
+system.cpu7.l1c.demand_miss_rate 0.874510 # miss rate for demand accesses
+system.cpu7.l1c.demand_misses 60405 # number of demand (read+write) misses
system.cpu7.l1c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu7.l1c.demand_mshr_miss_latency 51069339 # number of demand (read+write) MSHR miss cycles
-system.cpu7.l1c.demand_mshr_miss_rate 0.875345 # mshr miss rate for demand accesses
-system.cpu7.l1c.demand_mshr_misses 59906 # number of demand (read+write) MSHR misses
+system.cpu7.l1c.demand_mshr_miss_latency 740656145 # number of demand (read+write) MSHR miss cycles
+system.cpu7.l1c.demand_mshr_miss_rate 0.874510 # mshr miss rate for demand accesses
+system.cpu7.l1c.demand_mshr_misses 60405 # number of demand (read+write) MSHR misses
system.cpu7.l1c.fast_writes 0 # number of fast writes performed
system.cpu7.l1c.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu7.l1c.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu7.l1c.overall_accesses 68437 # number of overall (read+write) accesses
-system.cpu7.l1c.overall_avg_miss_latency 931.901012 # average overall miss latency
-system.cpu7.l1c.overall_avg_mshr_miss_latency 852.491220 # average overall mshr miss latency
+system.cpu7.l1c.overall_accesses 69073 # number of overall (read+write) accesses
+system.cpu7.l1c.overall_avg_miss_latency 13445.124923 # average overall miss latency
+system.cpu7.l1c.overall_avg_mshr_miss_latency 12261.503932 # average overall mshr miss latency
system.cpu7.l1c.overall_avg_mshr_uncacheable_latency 0 # average overall mshr uncacheable latency
-system.cpu7.l1c.overall_hits 8531 # number of overall hits
-system.cpu7.l1c.overall_miss_latency 55826462 # number of overall miss cycles
-system.cpu7.l1c.overall_miss_rate 0.875345 # miss rate for overall accesses
-system.cpu7.l1c.overall_misses 59906 # number of overall misses
+system.cpu7.l1c.overall_hits 8668 # number of overall hits
+system.cpu7.l1c.overall_miss_latency 812152771 # number of overall miss cycles
+system.cpu7.l1c.overall_miss_rate 0.874510 # miss rate for overall accesses
+system.cpu7.l1c.overall_misses 60405 # number of overall misses
system.cpu7.l1c.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu7.l1c.overall_mshr_miss_latency 51069339 # number of overall MSHR miss cycles
-system.cpu7.l1c.overall_mshr_miss_rate 0.875345 # mshr miss rate for overall accesses
-system.cpu7.l1c.overall_mshr_misses 59906 # number of overall MSHR misses
+system.cpu7.l1c.overall_mshr_miss_latency 740656145 # number of overall MSHR miss cycles
+system.cpu7.l1c.overall_mshr_miss_rate 0.874510 # mshr miss rate for overall accesses
+system.cpu7.l1c.overall_mshr_misses 60405 # number of overall MSHR misses
system.cpu7.l1c.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu7.l1c.overall_mshr_uncacheable_misses 15247 # number of overall MSHR uncacheable misses
+system.cpu7.l1c.overall_mshr_uncacheable_misses 15324 # number of overall MSHR uncacheable misses
system.cpu7.l1c.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
system.cpu7.l1c.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
system.cpu7.l1c.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
@@ -827,111 +827,111 @@ system.cpu7.l1c.prefetcher.num_hwpf_removed_MSHR_hit 0
system.cpu7.l1c.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu7.l1c.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
system.cpu7.l1c.protocol.hwpf_invalid 0 # hard prefetch misses to invalid blocks
-system.cpu7.l1c.protocol.read_invalid 115064 # read misses to invalid blocks
+system.cpu7.l1c.protocol.read_invalid 1929884 # read misses to invalid blocks
system.cpu7.l1c.protocol.snoop_inv_exclusive 0 # Invalidate snoops on exclusive blocks
system.cpu7.l1c.protocol.snoop_inv_invalid 0 # Invalidate snoops on invalid blocks
system.cpu7.l1c.protocol.snoop_inv_modified 0 # Invalidate snoops on modified blocks
system.cpu7.l1c.protocol.snoop_inv_owned 0 # Invalidate snoops on owned blocks
system.cpu7.l1c.protocol.snoop_inv_shared 0 # Invalidate snoops on shared blocks
-system.cpu7.l1c.protocol.snoop_read_exclusive 2793 # read snoops on exclusive blocks
-system.cpu7.l1c.protocol.snoop_read_modified 12588 # read snoops on modified blocks
-system.cpu7.l1c.protocol.snoop_read_owned 7412 # read snoops on owned blocks
-system.cpu7.l1c.protocol.snoop_read_shared 23048 # read snoops on shared blocks
-system.cpu7.l1c.protocol.snoop_readex_exclusive 1548 # readEx snoops on exclusive blocks
-system.cpu7.l1c.protocol.snoop_readex_modified 6593 # readEx snoops on modified blocks
-system.cpu7.l1c.protocol.snoop_readex_owned 3944 # readEx snoops on owned blocks
-system.cpu7.l1c.protocol.snoop_readex_shared 12404 # readEx snoops on shared blocks
-system.cpu7.l1c.protocol.snoop_upgrade_owned 919 # upgrade snoops on owned blocks
-system.cpu7.l1c.protocol.snoop_upgrade_shared 2959 # upgradee snoops on shared blocks
+system.cpu7.l1c.protocol.snoop_read_exclusive 2904 # read snoops on exclusive blocks
+system.cpu7.l1c.protocol.snoop_read_modified 12387 # read snoops on modified blocks
+system.cpu7.l1c.protocol.snoop_read_owned 7174 # read snoops on owned blocks
+system.cpu7.l1c.protocol.snoop_read_shared 1782059 # read snoops on shared blocks
+system.cpu7.l1c.protocol.snoop_readex_exclusive 1587 # readEx snoops on exclusive blocks
+system.cpu7.l1c.protocol.snoop_readex_modified 6687 # readEx snoops on modified blocks
+system.cpu7.l1c.protocol.snoop_readex_owned 3842 # readEx snoops on owned blocks
+system.cpu7.l1c.protocol.snoop_readex_shared 12759 # readEx snoops on shared blocks
+system.cpu7.l1c.protocol.snoop_upgrade_owned 792 # upgrade snoops on owned blocks
+system.cpu7.l1c.protocol.snoop_upgrade_shared 3085 # upgradee snoops on shared blocks
system.cpu7.l1c.protocol.snoop_writeinv_exclusive 0 # WriteInvalidate snoops on exclusive blocks
system.cpu7.l1c.protocol.snoop_writeinv_invalid 0 # WriteInvalidate snoops on invalid blocks
system.cpu7.l1c.protocol.snoop_writeinv_modified 0 # WriteInvalidate snoops on modified blocks
system.cpu7.l1c.protocol.snoop_writeinv_owned 0 # WriteInvalidate snoops on owned blocks
system.cpu7.l1c.protocol.snoop_writeinv_shared 0 # WriteInvalidate snoops on shared blocks
system.cpu7.l1c.protocol.swpf_invalid 0 # soft prefetch misses to invalid blocks
-system.cpu7.l1c.protocol.write_invalid 58173 # write misses to invalid blocks
-system.cpu7.l1c.protocol.write_owned 1351 # write misses to owned blocks
-system.cpu7.l1c.protocol.write_shared 4494 # write misses to shared blocks
-system.cpu7.l1c.replacements 27080 # number of replacements
-system.cpu7.l1c.sampled_refs 27420 # Sample count of references to valid blocks.
+system.cpu7.l1c.protocol.write_invalid 930930 # write misses to invalid blocks
+system.cpu7.l1c.protocol.write_owned 1422 # write misses to owned blocks
+system.cpu7.l1c.protocol.write_shared 4465 # write misses to shared blocks
+system.cpu7.l1c.replacements 27486 # number of replacements
+system.cpu7.l1c.sampled_refs 27827 # Sample count of references to valid blocks.
system.cpu7.l1c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu7.l1c.tagsinuse 342.061742 # Cycle average of tags in use
-system.cpu7.l1c.total_refs 11497 # Total number of references to valid blocks.
+system.cpu7.l1c.tagsinuse 344.310963 # Cycle average of tags in use
+system.cpu7.l1c.total_refs 11517 # Total number of references to valid blocks.
system.cpu7.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu7.l1c.writebacks 10789 # number of writebacks
+system.cpu7.l1c.writebacks 10979 # number of writebacks
system.cpu7.num_copies 0 # number of copy accesses completed
-system.cpu7.num_reads 98350 # number of read accesses completed
-system.cpu7.num_writes 53282 # number of write accesses completed
-system.l2c.ReadExReq_accesses 75399 # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_avg_miss_latency 89.483714 # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency 6.467886 # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_hits 39632 # number of ReadExReq hits
-system.l2c.ReadExReq_miss_latency 3200564 # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_rate 0.474370 # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_misses 35767 # number of ReadExReq misses
-system.l2c.ReadExReq_mshr_hits 4 # number of ReadExReq MSHR hits
-system.l2c.ReadExReq_mshr_miss_latency 231311 # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_rate 0.474317 # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_misses 35763 # number of ReadExReq MSHR misses
-system.l2c.ReadReq_accesses 138997 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_avg_miss_latency 89.683271 # average ReadReq miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency 6.196645 # average ReadReq mshr miss latency
-system.l2c.ReadReq_hits 72568 # number of ReadReq hits
-system.l2c.ReadReq_miss_latency 5957570 # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_rate 0.477917 # miss rate for ReadReq accesses
-system.l2c.ReadReq_misses 66429 # number of ReadReq misses
-system.l2c.ReadReq_mshr_hits 15 # number of ReadReq MSHR hits
-system.l2c.ReadReq_mshr_miss_latency 411544 # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_rate 0.477809 # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_misses 66414 # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_uncacheable 78703 # number of ReadReq MSHR uncacheable
+system.cpu7.num_reads 99734 # number of read accesses completed
+system.cpu7.num_writes 53652 # number of write accesses completed
+system.l2c.ReadExReq_accesses 75160 # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_avg_miss_latency 10115.633652 # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency 6085.503709 # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_hits 39620 # number of ReadExReq hits
+system.l2c.ReadExReq_miss_latency 359509620 # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_rate 0.472858 # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_misses 35540 # number of ReadExReq misses
+system.l2c.ReadExReq_mshr_hits 220 # number of ReadExReq MSHR hits
+system.l2c.ReadExReq_mshr_miss_latency 214939991 # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_rate 0.469931 # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_misses 35320 # number of ReadExReq MSHR misses
+system.l2c.ReadReq_accesses 138762 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_avg_miss_latency 10150.344064 # average ReadReq miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency 6129.500996 # average ReadReq mshr miss latency
+system.l2c.ReadReq_hits 72597 # number of ReadReq hits
+system.l2c.ReadReq_miss_latency 671597515 # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_rate 0.476824 # miss rate for ReadReq accesses
+system.l2c.ReadReq_misses 66165 # number of ReadReq misses
+system.l2c.ReadReq_mshr_hits 406 # number of ReadReq MSHR hits
+system.l2c.ReadReq_mshr_miss_latency 403069856 # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_rate 0.473898 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_misses 65759 # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_uncacheable 78927 # number of ReadReq MSHR uncacheable
system.l2c.ReadResp_avg_mshr_uncacheable_latency inf # average ReadResp mshr uncacheable latency
-system.l2c.ReadResp_mshr_uncacheable_latency 420484 # number of ReadResp MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable 42661 # number of WriteReq MSHR uncacheable
+system.l2c.ReadResp_mshr_uncacheable_latency 484683934 # number of ReadResp MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable 42802 # number of WriteReq MSHR uncacheable
system.l2c.WriteResp_avg_mshr_uncacheable_latency inf # average WriteResp mshr uncacheable latency
-system.l2c.WriteResp_mshr_uncacheable_latency 298282 # number of WriteResp MSHR uncacheable cycles
-system.l2c.Writeback_accesses 86614 # number of Writeback accesses(hits+misses)
-system.l2c.Writeback_hits 18299 # number of Writeback hits
-system.l2c.Writeback_miss_rate 0.788729 # miss rate for Writeback accesses
-system.l2c.Writeback_misses 68315 # number of Writeback misses
-system.l2c.Writeback_mshr_miss_rate 0.788729 # mshr miss rate for Writeback accesses
-system.l2c.Writeback_mshr_misses 68315 # number of Writeback MSHR misses
-system.l2c.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
+system.l2c.WriteResp_mshr_uncacheable_latency 248118294 # number of WriteResp MSHR uncacheable cycles
+system.l2c.Writeback_accesses 86706 # number of Writeback accesses(hits+misses)
+system.l2c.Writeback_hits 18948 # number of Writeback hits
+system.l2c.Writeback_miss_rate 0.781468 # miss rate for Writeback accesses
+system.l2c.Writeback_misses 67758 # number of Writeback misses
+system.l2c.Writeback_mshr_miss_rate 0.781468 # mshr miss rate for Writeback accesses
+system.l2c.Writeback_mshr_misses 67758 # number of Writeback MSHR misses
+system.l2c.avg_blocked_cycles_no_mshrs 3278 # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
-system.l2c.avg_refs 1.277186 # Average number of references to valid blocks.
-system.l2c.blocked_no_mshrs 0 # number of cycles access was blocked
+system.l2c.avg_refs 1.297661 # Average number of references to valid blocks.
+system.l2c.blocked_no_mshrs 3 # number of cycles access was blocked
system.l2c.blocked_no_targets 0 # number of cycles access was blocked
-system.l2c.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
+system.l2c.blocked_cycles_no_mshrs 9834 # number of cycles access was blocked
system.l2c.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.l2c.cache_copies 0 # number of cache copies performed
-system.l2c.demand_accesses 138997 # number of demand (read+write) accesses
-system.l2c.demand_avg_miss_latency 89.683271 # average overall miss latency
-system.l2c.demand_avg_mshr_miss_latency 6.196645 # average overall mshr miss latency
-system.l2c.demand_hits 72568 # number of demand (read+write) hits
-system.l2c.demand_miss_latency 5957570 # number of demand (read+write) miss cycles
-system.l2c.demand_miss_rate 0.477917 # miss rate for demand accesses
-system.l2c.demand_misses 66429 # number of demand (read+write) misses
-system.l2c.demand_mshr_hits 15 # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_miss_latency 411544 # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_rate 0.477809 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_misses 66414 # number of demand (read+write) MSHR misses
+system.l2c.demand_accesses 138762 # number of demand (read+write) accesses
+system.l2c.demand_avg_miss_latency 10150.344064 # average overall miss latency
+system.l2c.demand_avg_mshr_miss_latency 6129.500996 # average overall mshr miss latency
+system.l2c.demand_hits 72597 # number of demand (read+write) hits
+system.l2c.demand_miss_latency 671597515 # number of demand (read+write) miss cycles
+system.l2c.demand_miss_rate 0.476824 # miss rate for demand accesses
+system.l2c.demand_misses 66165 # number of demand (read+write) misses
+system.l2c.demand_mshr_hits 406 # number of demand (read+write) MSHR hits
+system.l2c.demand_mshr_miss_latency 403069856 # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_rate 0.473898 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_misses 65759 # number of demand (read+write) MSHR misses
system.l2c.fast_writes 0 # number of fast writes performed
system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
-system.l2c.overall_accesses 225611 # number of overall (read+write) accesses
-system.l2c.overall_avg_miss_latency 44.213991 # average overall miss latency
-system.l2c.overall_avg_mshr_miss_latency 6.196645 # average overall mshr miss latency
+system.l2c.overall_accesses 225468 # number of overall (read+write) accesses
+system.l2c.overall_avg_miss_latency 5014.803394 # average overall miss latency
+system.l2c.overall_avg_mshr_miss_latency 6129.500996 # average overall mshr miss latency
system.l2c.overall_avg_mshr_uncacheable_latency 0 # average overall mshr uncacheable latency
-system.l2c.overall_hits 90867 # number of overall hits
-system.l2c.overall_miss_latency 5957570 # number of overall miss cycles
-system.l2c.overall_miss_rate 0.597240 # miss rate for overall accesses
-system.l2c.overall_misses 134744 # number of overall misses
-system.l2c.overall_mshr_hits 15 # number of overall MSHR hits
-system.l2c.overall_mshr_miss_latency 411544 # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_rate 0.294374 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_misses 66414 # number of overall MSHR misses
+system.l2c.overall_hits 91545 # number of overall hits
+system.l2c.overall_miss_latency 671597515 # number of overall miss cycles
+system.l2c.overall_miss_rate 0.593978 # miss rate for overall accesses
+system.l2c.overall_misses 133923 # number of overall misses
+system.l2c.overall_mshr_hits 406 # number of overall MSHR hits
+system.l2c.overall_mshr_miss_latency 403069856 # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_rate 0.291656 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_misses 65759 # number of overall MSHR misses
system.l2c.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_misses 121364 # number of overall MSHR uncacheable misses
+system.l2c.overall_mshr_uncacheable_misses 121729 # number of overall MSHR uncacheable misses
system.l2c.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
system.l2c.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
system.l2c.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
@@ -941,12 +941,12 @@ system.l2c.prefetcher.num_hwpf_issued 0 # nu
system.l2c.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
system.l2c.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.l2c.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
-system.l2c.replacements 101153 # number of replacements
-system.l2c.sampled_refs 102177 # Sample count of references to valid blocks.
+system.l2c.replacements 100054 # number of replacements
+system.l2c.sampled_refs 101078 # Sample count of references to valid blocks.
system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.l2c.tagsinuse 1022.647312 # Cycle average of tags in use
-system.l2c.total_refs 130499 # Total number of references to valid blocks.
-system.l2c.warmup_cycle 31838 # Cycle when the warmup percentage was hit.
-system.l2c.writebacks 15786 # number of writebacks
+system.l2c.tagsinuse 1023.099242 # Cycle average of tags in use
+system.l2c.total_refs 131165 # Total number of references to valid blocks.
+system.l2c.warmup_cycle 296156 # Cycle when the warmup percentage was hit.
+system.l2c.writebacks 16243 # number of writebacks
---------- End Simulation Statistics ----------
diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest/stderr b/tests/quick/50.memtest/ref/alpha/linux/memtest/stderr
index 16580296b..d45294bbb 100644
--- a/tests/quick/50.memtest/ref/alpha/linux/memtest/stderr
+++ b/tests/quick/50.memtest/ref/alpha/linux/memtest/stderr
@@ -1,74 +1,74 @@
warn: Entering event queue @ 0. Starting simulation...
-system.cpu2: completed 10000 read accesses @573559
-system.cpu1: completed 10000 read accesses @574452
-system.cpu4: completed 10000 read accesses @578704
-system.cpu6: completed 10000 read accesses @579414
-system.cpu0: completed 10000 read accesses @588706
-system.cpu5: completed 10000 read accesses @590846
-system.cpu7: completed 10000 read accesses @592958
-system.cpu3: completed 10000 read accesses @604807
-system.cpu2: completed 20000 read accesses @1142209
-system.cpu1: completed 20000 read accesses @1143294
-system.cpu6: completed 20000 read accesses @1150506
-system.cpu4: completed 20000 read accesses @1152288
-system.cpu0: completed 20000 read accesses @1160537
-system.cpu3: completed 20000 read accesses @1175338
-system.cpu5: completed 20000 read accesses @1175648
-system.cpu7: completed 20000 read accesses @1180960
-system.cpu6: completed 30000 read accesses @1716218
-system.cpu3: completed 30000 read accesses @1728281
-system.cpu1: completed 30000 read accesses @1735983
-system.cpu0: completed 30000 read accesses @1736422
-system.cpu2: completed 30000 read accesses @1739692
-system.cpu4: completed 30000 read accesses @1746362
-system.cpu5: completed 30000 read accesses @1766199
-system.cpu7: completed 30000 read accesses @1783424
-system.cpu6: completed 40000 read accesses @2281651
-system.cpu0: completed 40000 read accesses @2300760
-system.cpu3: completed 40000 read accesses @2312993
-system.cpu2: completed 40000 read accesses @2314026
-system.cpu4: completed 40000 read accesses @2332178
-system.cpu1: completed 40000 read accesses @2336380
-system.cpu5: completed 40000 read accesses @2349370
-system.cpu7: completed 40000 read accesses @2365352
-system.cpu6: completed 50000 read accesses @2863317
-system.cpu0: completed 50000 read accesses @2878182
-system.cpu2: completed 50000 read accesses @2884989
-system.cpu3: completed 50000 read accesses @2897940
-system.cpu4: completed 50000 read accesses @2918842
-system.cpu1: completed 50000 read accesses @2929102
-system.cpu5: completed 50000 read accesses @2938269
-system.cpu7: completed 50000 read accesses @2944872
-system.cpu6: completed 60000 read accesses @3435715
-system.cpu2: completed 60000 read accesses @3454809
-system.cpu0: completed 60000 read accesses @3462986
-system.cpu3: completed 60000 read accesses @3485243
-system.cpu4: completed 60000 read accesses @3498361
-system.cpu1: completed 60000 read accesses @3501000
-system.cpu5: completed 60000 read accesses @3516984
-system.cpu7: completed 60000 read accesses @3517323
-system.cpu6: completed 70000 read accesses @4032530
-system.cpu0: completed 70000 read accesses @4041457
-system.cpu2: completed 70000 read accesses @4043695
-system.cpu7: completed 70000 read accesses @4070977
-system.cpu1: completed 70000 read accesses @4075964
-system.cpu4: completed 70000 read accesses @4076518
-system.cpu3: completed 70000 read accesses @4082470
-system.cpu5: completed 70000 read accesses @4104778
-system.cpu0: completed 80000 read accesses @4610101
-system.cpu2: completed 80000 read accesses @4622528
-system.cpu6: completed 80000 read accesses @4627690
-system.cpu1: completed 80000 read accesses @4654033
-system.cpu4: completed 80000 read accesses @4661016
-system.cpu3: completed 80000 read accesses @4662752
-system.cpu7: completed 80000 read accesses @4668924
-system.cpu5: completed 80000 read accesses @4689767
-system.cpu2: completed 90000 read accesses @5186824
-system.cpu0: completed 90000 read accesses @5189006
-system.cpu6: completed 90000 read accesses @5214829
-system.cpu1: completed 90000 read accesses @5229787
-system.cpu3: completed 90000 read accesses @5235400
-system.cpu4: completed 90000 read accesses @5240445
-system.cpu7: completed 90000 read accesses @5254426
-system.cpu5: completed 90000 read accesses @5292462
-system.cpu2: completed 100000 read accesses @5755736
+system.cpu7: completed 10000 read accesses @8253930
+system.cpu1: completed 10000 read accesses @8325085
+system.cpu6: completed 10000 read accesses @8427313
+system.cpu4: completed 10000 read accesses @8438233
+system.cpu2: completed 10000 read accesses @8458126
+system.cpu5: completed 10000 read accesses @8549800
+system.cpu3: completed 10000 read accesses @8559995
+system.cpu0: completed 10000 read accesses @8593654
+system.cpu7: completed 20000 read accesses @16744182
+system.cpu1: completed 20000 read accesses @16774744
+system.cpu4: completed 20000 read accesses @16786220
+system.cpu3: completed 20000 read accesses @16787358
+system.cpu5: completed 20000 read accesses @16795808
+system.cpu6: completed 20000 read accesses @16836913
+system.cpu2: completed 20000 read accesses @17031052
+system.cpu0: completed 20000 read accesses @17126654
+system.cpu5: completed 30000 read accesses @24892576
+system.cpu6: completed 30000 read accesses @24903300
+system.cpu3: completed 30000 read accesses @24935860
+system.cpu4: completed 30000 read accesses @25020642
+system.cpu1: completed 30000 read accesses @25031726
+system.cpu7: completed 30000 read accesses @25112091
+system.cpu2: completed 30000 read accesses @25235960
+system.cpu0: completed 30000 read accesses @25505209
+system.cpu5: completed 40000 read accesses @33191203
+system.cpu6: completed 40000 read accesses @33273684
+system.cpu4: completed 40000 read accesses @33345526
+system.cpu3: completed 40000 read accesses @33406412
+system.cpu7: completed 40000 read accesses @33509130
+system.cpu1: completed 40000 read accesses @33509218
+system.cpu2: completed 40000 read accesses @33664822
+system.cpu0: completed 40000 read accesses @33869626
+system.cpu5: completed 50000 read accesses @41488848
+system.cpu4: completed 50000 read accesses @41582702
+system.cpu7: completed 50000 read accesses @41828988
+system.cpu3: completed 50000 read accesses @41829496
+system.cpu1: completed 50000 read accesses @41849534
+system.cpu6: completed 50000 read accesses @41982608
+system.cpu2: completed 50000 read accesses @42197798
+system.cpu0: completed 50000 read accesses @42443468
+system.cpu5: completed 60000 read accesses @49751344
+system.cpu4: completed 60000 read accesses @49783100
+system.cpu1: completed 60000 read accesses @49918062
+system.cpu7: completed 60000 read accesses @49929008
+system.cpu3: completed 60000 read accesses @50173996
+system.cpu6: completed 60000 read accesses @50351766
+system.cpu2: completed 60000 read accesses @50352657
+system.cpu0: completed 60000 read accesses @50789771
+system.cpu4: completed 70000 read accesses @58352386
+system.cpu5: completed 70000 read accesses @58394758
+system.cpu7: completed 70000 read accesses @58570698
+system.cpu1: completed 70000 read accesses @58764169
+system.cpu3: completed 70000 read accesses @58764648
+system.cpu2: completed 70000 read accesses @58921714
+system.cpu6: completed 70000 read accesses @58929984
+system.cpu0: completed 70000 read accesses @59567320
+system.cpu1: completed 80000 read accesses @67092786
+system.cpu5: completed 80000 read accesses @67153667
+system.cpu4: completed 80000 read accesses @67153760
+system.cpu7: completed 80000 read accesses @67207042
+system.cpu3: completed 80000 read accesses @67238507
+system.cpu2: completed 80000 read accesses @67633112
+system.cpu6: completed 80000 read accesses @67664637
+system.cpu0: completed 80000 read accesses @68437288
+system.cpu1: completed 90000 read accesses @75679048
+system.cpu4: completed 90000 read accesses @75680280
+system.cpu7: completed 90000 read accesses @75751053
+system.cpu5: completed 90000 read accesses @75781514
+system.cpu3: completed 90000 read accesses @75844118
+system.cpu2: completed 90000 read accesses @76346671
+system.cpu6: completed 90000 read accesses @76491728
+system.cpu0: completed 90000 read accesses @77376872
+system.cpu1: completed 100000 read accesses @84350509
diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest/stdout b/tests/quick/50.memtest/ref/alpha/linux/memtest/stdout
index ea4812a6d..fb8e47d20 100644
--- a/tests/quick/50.memtest/ref/alpha/linux/memtest/stdout
+++ b/tests/quick/50.memtest/ref/alpha/linux/memtest/stdout
@@ -5,9 +5,9 @@ The Regents of The University of Michigan
All Rights Reserved
-M5 compiled Apr 21 2007 21:50:58
-M5 started Sat Apr 21 21:51:15 2007
-M5 executing on zamp.eecs.umich.edu
+M5 compiled May 14 2007 16:35:50
+M5 started Tue May 15 12:18:46 2007
+M5 executing on zizzer.eecs.umich.edu
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/50.memtest/alpha/linux/memtest tests/run.py quick/50.memtest/alpha/linux/memtest
warning: overwriting port funcmem.functional value cpu1.functional with cpu2.functional
warning: overwriting port funcmem.functional value cpu2.functional with cpu3.functional
@@ -16,4 +16,4 @@ warning: overwriting port funcmem.functional value cpu4.functional with cpu5.fun
warning: overwriting port funcmem.functional value cpu5.functional with cpu6.functional
warning: overwriting port funcmem.functional value cpu6.functional with cpu7.functional
Global frequency set at 1000000000000 ticks per second
-Exiting @ tick 5755736 because Maximum number of loads reached!
+Exiting @ tick 84350509 because Maximum number of loads reached!