diff options
Diffstat (limited to 'tests/quick/50.memtest/ref')
3 files changed, 573 insertions, 576 deletions
diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest/m5stats.txt b/tests/quick/50.memtest/ref/alpha/linux/memtest/m5stats.txt index 19f13b80b..8a8c21ab1 100644 --- a/tests/quick/50.memtest/ref/alpha/linux/memtest/m5stats.txt +++ b/tests/quick/50.memtest/ref/alpha/linux/memtest/m5stats.txt @@ -1,70 +1,70 @@ ---------- Begin Simulation Statistics ---------- -host_mem_usage 368552 # Number of bytes of host memory used -host_seconds 153.46 # Real time elapsed on the host -host_tick_rate 1061945 # Simulator tick rate (ticks/s) +host_mem_usage 323008 # Number of bytes of host memory used +host_seconds 186.85 # Real time elapsed on the host +host_tick_rate 602387 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_seconds 0.000163 # Number of seconds simulated -sim_ticks 162969030 # Number of ticks simulated -system.cpu0.l1c.ReadReq_accesses 44649 # number of ReadReq accesses(hits+misses) -system.cpu0.l1c.ReadReq_avg_miss_latency 23666.382848 # average ReadReq miss latency -system.cpu0.l1c.ReadReq_avg_mshr_miss_latency 22664.543419 # average ReadReq mshr miss latency +sim_seconds 0.000113 # Number of seconds simulated +sim_ticks 112555067 # Number of ticks simulated +system.cpu0.l1c.ReadReq_accesses 44584 # number of ReadReq accesses(hits+misses) +system.cpu0.l1c.ReadReq_avg_miss_latency 16791.681399 # average ReadReq miss latency +system.cpu0.l1c.ReadReq_avg_mshr_miss_latency 15789.838066 # average ReadReq mshr miss latency system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.cpu0.l1c.ReadReq_hits 7488 # number of ReadReq hits -system.cpu0.l1c.ReadReq_miss_latency 879466453 # number of ReadReq miss cycles -system.cpu0.l1c.ReadReq_miss_rate 0.832292 # miss rate for ReadReq accesses -system.cpu0.l1c.ReadReq_misses 37161 # number of ReadReq misses -system.cpu0.l1c.ReadReq_mshr_miss_latency 842237098 # number of ReadReq MSHR miss cycles -system.cpu0.l1c.ReadReq_mshr_miss_rate 0.832292 # mshr miss rate for ReadReq accesses -system.cpu0.l1c.ReadReq_mshr_misses 37161 # number of ReadReq MSHR misses -system.cpu0.l1c.ReadReq_mshr_uncacheable_latency 472367401 # number of ReadReq MSHR uncacheable cycles -system.cpu0.l1c.WriteReq_accesses 24088 # number of WriteReq accesses(hits+misses) -system.cpu0.l1c.WriteReq_avg_miss_latency 28277.359652 # average WriteReq miss latency -system.cpu0.l1c.WriteReq_avg_mshr_miss_latency 27275.445460 # average WriteReq mshr miss latency +system.cpu0.l1c.ReadReq_hits 7569 # number of ReadReq hits +system.cpu0.l1c.ReadReq_miss_latency 621544087 # number of ReadReq miss cycles +system.cpu0.l1c.ReadReq_miss_rate 0.830231 # miss rate for ReadReq accesses +system.cpu0.l1c.ReadReq_misses 37015 # number of ReadReq misses +system.cpu0.l1c.ReadReq_mshr_miss_latency 584460856 # number of ReadReq MSHR miss cycles +system.cpu0.l1c.ReadReq_mshr_miss_rate 0.830231 # mshr miss rate for ReadReq accesses +system.cpu0.l1c.ReadReq_mshr_misses 37015 # number of ReadReq MSHR misses +system.cpu0.l1c.ReadReq_mshr_uncacheable_latency 311047382 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l1c.WriteReq_accesses 24314 # number of WriteReq accesses(hits+misses) +system.cpu0.l1c.WriteReq_avg_miss_latency 20326.593908 # average WriteReq miss latency +system.cpu0.l1c.WriteReq_avg_mshr_miss_latency 19324.632455 # average WriteReq mshr miss latency system.cpu0.l1c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency -system.cpu0.l1c.WriteReq_hits 885 # number of WriteReq hits -system.cpu0.l1c.WriteReq_miss_latency 656119576 # number of WriteReq miss cycles -system.cpu0.l1c.WriteReq_miss_rate 0.963260 # miss rate for WriteReq accesses -system.cpu0.l1c.WriteReq_misses 23203 # number of WriteReq misses -system.cpu0.l1c.WriteReq_mshr_miss_latency 632872161 # number of WriteReq MSHR miss cycles -system.cpu0.l1c.WriteReq_mshr_miss_rate 0.963260 # mshr miss rate for WriteReq accesses -system.cpu0.l1c.WriteReq_mshr_misses 23203 # number of WriteReq MSHR misses -system.cpu0.l1c.WriteReq_mshr_uncacheable_latency 285830278 # number of WriteReq MSHR uncacheable cycles -system.cpu0.l1c.avg_blocked_cycles_no_mshrs 2295.113017 # average number of cycles each access was blocked +system.cpu0.l1c.WriteReq_hits 940 # number of WriteReq hits +system.cpu0.l1c.WriteReq_miss_latency 475113806 # number of WriteReq miss cycles +system.cpu0.l1c.WriteReq_miss_rate 0.961339 # miss rate for WriteReq accesses +system.cpu0.l1c.WriteReq_misses 23374 # number of WriteReq misses +system.cpu0.l1c.WriteReq_mshr_miss_latency 451693959 # number of WriteReq MSHR miss cycles +system.cpu0.l1c.WriteReq_mshr_miss_rate 0.961339 # mshr miss rate for WriteReq accesses +system.cpu0.l1c.WriteReq_mshr_misses 23374 # number of WriteReq MSHR misses +system.cpu0.l1c.WriteReq_mshr_uncacheable_latency 197852033 # number of WriteReq MSHR uncacheable cycles +system.cpu0.l1c.avg_blocked_cycles_no_mshrs 1596.131819 # average number of cycles each access was blocked system.cpu0.l1c.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu0.l1c.avg_refs 0.412189 # Average number of references to valid blocks. -system.cpu0.l1c.blocked_no_mshrs 69538 # number of cycles access was blocked +system.cpu0.l1c.avg_refs 0.411842 # Average number of references to valid blocks. +system.cpu0.l1c.blocked_no_mshrs 69641 # number of cycles access was blocked system.cpu0.l1c.blocked_no_targets 0 # number of cycles access was blocked -system.cpu0.l1c.blocked_cycles_no_mshrs 159597569 # number of cycles access was blocked +system.cpu0.l1c.blocked_cycles_no_mshrs 111156216 # number of cycles access was blocked system.cpu0.l1c.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu0.l1c.cache_copies 0 # number of cache copies performed -system.cpu0.l1c.demand_accesses 68737 # number of demand (read+write) accesses -system.cpu0.l1c.demand_avg_miss_latency 25438.771934 # average overall miss latency -system.cpu0.l1c.demand_avg_mshr_miss_latency 24436.903767 # average overall mshr miss latency -system.cpu0.l1c.demand_hits 8373 # number of demand (read+write) hits -system.cpu0.l1c.demand_miss_latency 1535586029 # number of demand (read+write) miss cycles -system.cpu0.l1c.demand_miss_rate 0.878188 # miss rate for demand accesses -system.cpu0.l1c.demand_misses 60364 # number of demand (read+write) misses +system.cpu0.l1c.demand_accesses 68898 # number of demand (read+write) accesses +system.cpu0.l1c.demand_avg_miss_latency 18159.894898 # average overall miss latency +system.cpu0.l1c.demand_avg_mshr_miss_latency 17158.005845 # average overall mshr miss latency +system.cpu0.l1c.demand_hits 8509 # number of demand (read+write) hits +system.cpu0.l1c.demand_miss_latency 1096657893 # number of demand (read+write) miss cycles +system.cpu0.l1c.demand_miss_rate 0.876499 # miss rate for demand accesses +system.cpu0.l1c.demand_misses 60389 # number of demand (read+write) misses system.cpu0.l1c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu0.l1c.demand_mshr_miss_latency 1475109259 # number of demand (read+write) MSHR miss cycles -system.cpu0.l1c.demand_mshr_miss_rate 0.878188 # mshr miss rate for demand accesses -system.cpu0.l1c.demand_mshr_misses 60364 # number of demand (read+write) MSHR misses +system.cpu0.l1c.demand_mshr_miss_latency 1036154815 # number of demand (read+write) MSHR miss cycles +system.cpu0.l1c.demand_mshr_miss_rate 0.876499 # mshr miss rate for demand accesses +system.cpu0.l1c.demand_mshr_misses 60389 # number of demand (read+write) MSHR misses system.cpu0.l1c.fast_writes 0 # number of fast writes performed system.cpu0.l1c.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu0.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.l1c.overall_accesses 68737 # number of overall (read+write) accesses -system.cpu0.l1c.overall_avg_miss_latency 25438.771934 # average overall miss latency -system.cpu0.l1c.overall_avg_mshr_miss_latency 24436.903767 # average overall mshr miss latency +system.cpu0.l1c.overall_accesses 68898 # number of overall (read+write) accesses +system.cpu0.l1c.overall_avg_miss_latency 18159.894898 # average overall miss latency +system.cpu0.l1c.overall_avg_mshr_miss_latency 17158.005845 # average overall mshr miss latency system.cpu0.l1c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.cpu0.l1c.overall_hits 8373 # number of overall hits -system.cpu0.l1c.overall_miss_latency 1535586029 # number of overall miss cycles -system.cpu0.l1c.overall_miss_rate 0.878188 # miss rate for overall accesses -system.cpu0.l1c.overall_misses 60364 # number of overall misses +system.cpu0.l1c.overall_hits 8509 # number of overall hits +system.cpu0.l1c.overall_miss_latency 1096657893 # number of overall miss cycles +system.cpu0.l1c.overall_miss_rate 0.876499 # miss rate for overall accesses +system.cpu0.l1c.overall_misses 60389 # number of overall misses system.cpu0.l1c.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu0.l1c.overall_mshr_miss_latency 1475109259 # number of overall MSHR miss cycles -system.cpu0.l1c.overall_mshr_miss_rate 0.878188 # mshr miss rate for overall accesses -system.cpu0.l1c.overall_mshr_misses 60364 # number of overall MSHR misses -system.cpu0.l1c.overall_mshr_uncacheable_latency 758197679 # number of overall MSHR uncacheable cycles +system.cpu0.l1c.overall_mshr_miss_latency 1036154815 # number of overall MSHR miss cycles +system.cpu0.l1c.overall_mshr_miss_rate 0.876499 # mshr miss rate for overall accesses +system.cpu0.l1c.overall_mshr_misses 60389 # number of overall MSHR misses +system.cpu0.l1c.overall_mshr_uncacheable_latency 508899415 # number of overall MSHR uncacheable cycles system.cpu0.l1c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu0.l1c.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache system.cpu0.l1c.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr @@ -75,75 +75,75 @@ system.cpu0.l1c.prefetcher.num_hwpf_issued 0 # system.cpu0.l1c.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu0.l1c.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu0.l1c.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu0.l1c.replacements 27517 # number of replacements -system.cpu0.l1c.sampled_refs 27861 # Sample count of references to valid blocks. +system.cpu0.l1c.replacements 27835 # number of replacements +system.cpu0.l1c.sampled_refs 28188 # Sample count of references to valid blocks. system.cpu0.l1c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu0.l1c.tagsinuse 345.121888 # Cycle average of tags in use -system.cpu0.l1c.total_refs 11484 # Total number of references to valid blocks. +system.cpu0.l1c.tagsinuse 346.302314 # Cycle average of tags in use +system.cpu0.l1c.total_refs 11609 # Total number of references to valid blocks. system.cpu0.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.l1c.writebacks 10876 # number of writebacks +system.cpu0.l1c.writebacks 10966 # number of writebacks system.cpu0.num_copies 0 # number of copy accesses completed -system.cpu0.num_reads 99133 # number of read accesses completed -system.cpu0.num_writes 53626 # number of write accesses completed -system.cpu1.l1c.ReadReq_accesses 44934 # number of ReadReq accesses(hits+misses) -system.cpu1.l1c.ReadReq_avg_miss_latency 23743.367678 # average ReadReq miss latency -system.cpu1.l1c.ReadReq_avg_mshr_miss_latency 22741.526988 # average ReadReq mshr miss latency +system.cpu0.num_reads 98907 # number of read accesses completed +system.cpu0.num_writes 53498 # number of write accesses completed +system.cpu1.l1c.ReadReq_accesses 44625 # number of ReadReq accesses(hits+misses) +system.cpu1.l1c.ReadReq_avg_miss_latency 16739.803812 # average ReadReq miss latency +system.cpu1.l1c.ReadReq_avg_mshr_miss_latency 15737.959508 # average ReadReq mshr miss latency system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.cpu1.l1c.ReadReq_hits 7510 # number of ReadReq hits -system.cpu1.l1c.ReadReq_miss_latency 888571792 # number of ReadReq miss cycles -system.cpu1.l1c.ReadReq_miss_rate 0.832866 # miss rate for ReadReq accesses -system.cpu1.l1c.ReadReq_misses 37424 # number of ReadReq misses -system.cpu1.l1c.ReadReq_mshr_miss_latency 851078906 # number of ReadReq MSHR miss cycles -system.cpu1.l1c.ReadReq_mshr_miss_rate 0.832866 # mshr miss rate for ReadReq accesses -system.cpu1.l1c.ReadReq_mshr_misses 37424 # number of ReadReq MSHR misses -system.cpu1.l1c.ReadReq_mshr_uncacheable_latency 461314055 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l1c.WriteReq_accesses 24224 # number of WriteReq accesses(hits+misses) -system.cpu1.l1c.WriteReq_avg_miss_latency 28268.157373 # average WriteReq miss latency -system.cpu1.l1c.WriteReq_avg_mshr_miss_latency 27266.371925 # average WriteReq mshr miss latency +system.cpu1.l1c.ReadReq_hits 7482 # number of ReadReq hits +system.cpu1.l1c.ReadReq_miss_latency 621766533 # number of ReadReq miss cycles +system.cpu1.l1c.ReadReq_miss_rate 0.832336 # miss rate for ReadReq accesses +system.cpu1.l1c.ReadReq_misses 37143 # number of ReadReq misses +system.cpu1.l1c.ReadReq_mshr_miss_latency 584555030 # number of ReadReq MSHR miss cycles +system.cpu1.l1c.ReadReq_mshr_miss_rate 0.832336 # mshr miss rate for ReadReq accesses +system.cpu1.l1c.ReadReq_mshr_misses 37143 # number of ReadReq MSHR misses +system.cpu1.l1c.ReadReq_mshr_uncacheable_latency 314667115 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l1c.WriteReq_accesses 24302 # number of WriteReq accesses(hits+misses) +system.cpu1.l1c.WriteReq_avg_miss_latency 20215.551692 # average WriteReq miss latency +system.cpu1.l1c.WriteReq_avg_mshr_miss_latency 19213.676756 # average WriteReq mshr miss latency system.cpu1.l1c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency -system.cpu1.l1c.WriteReq_hits 929 # number of WriteReq hits -system.cpu1.l1c.WriteReq_miss_latency 658506726 # number of WriteReq miss cycles -system.cpu1.l1c.WriteReq_miss_rate 0.961650 # miss rate for WriteReq accesses -system.cpu1.l1c.WriteReq_misses 23295 # number of WriteReq misses -system.cpu1.l1c.WriteReq_mshr_miss_latency 635170134 # number of WriteReq MSHR miss cycles -system.cpu1.l1c.WriteReq_mshr_miss_rate 0.961650 # mshr miss rate for WriteReq accesses -system.cpu1.l1c.WriteReq_mshr_misses 23295 # number of WriteReq MSHR misses -system.cpu1.l1c.WriteReq_mshr_uncacheable_latency 280215693 # number of WriteReq MSHR uncacheable cycles -system.cpu1.l1c.avg_blocked_cycles_no_mshrs 2295.300422 # average number of cycles each access was blocked +system.cpu1.l1c.WriteReq_hits 1010 # number of WriteReq hits +system.cpu1.l1c.WriteReq_miss_latency 470860630 # number of WriteReq miss cycles +system.cpu1.l1c.WriteReq_miss_rate 0.958440 # miss rate for WriteReq accesses +system.cpu1.l1c.WriteReq_misses 23292 # number of WriteReq misses +system.cpu1.l1c.WriteReq_mshr_miss_latency 447524959 # number of WriteReq MSHR miss cycles +system.cpu1.l1c.WriteReq_mshr_miss_rate 0.958440 # mshr miss rate for WriteReq accesses +system.cpu1.l1c.WriteReq_mshr_misses 23292 # number of WriteReq MSHR misses +system.cpu1.l1c.WriteReq_mshr_uncacheable_latency 196094106 # number of WriteReq MSHR uncacheable cycles +system.cpu1.l1c.avg_blocked_cycles_no_mshrs 1590.812213 # average number of cycles each access was blocked system.cpu1.l1c.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu1.l1c.avg_refs 0.407660 # Average number of references to valid blocks. -system.cpu1.l1c.blocked_no_mshrs 69592 # number of cycles access was blocked +system.cpu1.l1c.avg_refs 0.412303 # Average number of references to valid blocks. +system.cpu1.l1c.blocked_no_mshrs 69797 # number of cycles access was blocked system.cpu1.l1c.blocked_no_targets 0 # number of cycles access was blocked -system.cpu1.l1c.blocked_cycles_no_mshrs 159734547 # number of cycles access was blocked +system.cpu1.l1c.blocked_cycles_no_mshrs 111033920 # number of cycles access was blocked system.cpu1.l1c.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu1.l1c.cache_copies 0 # number of cache copies performed -system.cpu1.l1c.demand_accesses 69158 # number of demand (read+write) accesses -system.cpu1.l1c.demand_avg_miss_latency 25479.314844 # average overall miss latency -system.cpu1.l1c.demand_avg_mshr_miss_latency 24477.495347 # average overall mshr miss latency -system.cpu1.l1c.demand_hits 8439 # number of demand (read+write) hits -system.cpu1.l1c.demand_miss_latency 1547078518 # number of demand (read+write) miss cycles -system.cpu1.l1c.demand_miss_rate 0.877975 # miss rate for demand accesses -system.cpu1.l1c.demand_misses 60719 # number of demand (read+write) misses +system.cpu1.l1c.demand_accesses 68927 # number of demand (read+write) accesses +system.cpu1.l1c.demand_avg_miss_latency 18079.377232 # average overall miss latency +system.cpu1.l1c.demand_avg_mshr_miss_latency 17077.521122 # average overall mshr miss latency +system.cpu1.l1c.demand_hits 8492 # number of demand (read+write) hits +system.cpu1.l1c.demand_miss_latency 1092627163 # number of demand (read+write) miss cycles +system.cpu1.l1c.demand_miss_rate 0.876797 # miss rate for demand accesses +system.cpu1.l1c.demand_misses 60435 # number of demand (read+write) misses system.cpu1.l1c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu1.l1c.demand_mshr_miss_latency 1486249040 # number of demand (read+write) MSHR miss cycles -system.cpu1.l1c.demand_mshr_miss_rate 0.877975 # mshr miss rate for demand accesses -system.cpu1.l1c.demand_mshr_misses 60719 # number of demand (read+write) MSHR misses +system.cpu1.l1c.demand_mshr_miss_latency 1032079989 # number of demand (read+write) MSHR miss cycles +system.cpu1.l1c.demand_mshr_miss_rate 0.876797 # mshr miss rate for demand accesses +system.cpu1.l1c.demand_mshr_misses 60435 # number of demand (read+write) MSHR misses system.cpu1.l1c.fast_writes 0 # number of fast writes performed system.cpu1.l1c.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu1.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.l1c.overall_accesses 69158 # number of overall (read+write) accesses -system.cpu1.l1c.overall_avg_miss_latency 25479.314844 # average overall miss latency -system.cpu1.l1c.overall_avg_mshr_miss_latency 24477.495347 # average overall mshr miss latency +system.cpu1.l1c.overall_accesses 68927 # number of overall (read+write) accesses +system.cpu1.l1c.overall_avg_miss_latency 18079.377232 # average overall miss latency +system.cpu1.l1c.overall_avg_mshr_miss_latency 17077.521122 # average overall mshr miss latency system.cpu1.l1c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.cpu1.l1c.overall_hits 8439 # number of overall hits -system.cpu1.l1c.overall_miss_latency 1547078518 # number of overall miss cycles -system.cpu1.l1c.overall_miss_rate 0.877975 # miss rate for overall accesses -system.cpu1.l1c.overall_misses 60719 # number of overall misses +system.cpu1.l1c.overall_hits 8492 # number of overall hits +system.cpu1.l1c.overall_miss_latency 1092627163 # number of overall miss cycles +system.cpu1.l1c.overall_miss_rate 0.876797 # miss rate for overall accesses +system.cpu1.l1c.overall_misses 60435 # number of overall misses system.cpu1.l1c.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu1.l1c.overall_mshr_miss_latency 1486249040 # number of overall MSHR miss cycles -system.cpu1.l1c.overall_mshr_miss_rate 0.877975 # mshr miss rate for overall accesses -system.cpu1.l1c.overall_mshr_misses 60719 # number of overall MSHR misses -system.cpu1.l1c.overall_mshr_uncacheable_latency 741529748 # number of overall MSHR uncacheable cycles +system.cpu1.l1c.overall_mshr_miss_latency 1032079989 # number of overall MSHR miss cycles +system.cpu1.l1c.overall_mshr_miss_rate 0.876797 # mshr miss rate for overall accesses +system.cpu1.l1c.overall_mshr_misses 60435 # number of overall MSHR misses +system.cpu1.l1c.overall_mshr_uncacheable_latency 510761221 # number of overall MSHR uncacheable cycles system.cpu1.l1c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu1.l1c.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache system.cpu1.l1c.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr @@ -154,75 +154,75 @@ system.cpu1.l1c.prefetcher.num_hwpf_issued 0 # system.cpu1.l1c.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu1.l1c.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu1.l1c.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu1.l1c.replacements 27839 # number of replacements -system.cpu1.l1c.sampled_refs 28200 # Sample count of references to valid blocks. +system.cpu1.l1c.replacements 27754 # number of replacements +system.cpu1.l1c.sampled_refs 28108 # Sample count of references to valid blocks. system.cpu1.l1c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu1.l1c.tagsinuse 344.387684 # Cycle average of tags in use -system.cpu1.l1c.total_refs 11496 # Total number of references to valid blocks. +system.cpu1.l1c.tagsinuse 346.756421 # Cycle average of tags in use +system.cpu1.l1c.total_refs 11589 # Total number of references to valid blocks. system.cpu1.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.l1c.writebacks 10966 # number of writebacks +system.cpu1.l1c.writebacks 11009 # number of writebacks system.cpu1.num_copies 0 # number of copy accesses completed -system.cpu1.num_reads 99887 # number of read accesses completed -system.cpu1.num_writes 53581 # number of write accesses completed -system.cpu2.l1c.ReadReq_accesses 44676 # number of ReadReq accesses(hits+misses) -system.cpu2.l1c.ReadReq_avg_miss_latency 23702.165485 # average ReadReq miss latency -system.cpu2.l1c.ReadReq_avg_mshr_miss_latency 22700.326495 # average ReadReq mshr miss latency +system.cpu1.num_reads 99307 # number of read accesses completed +system.cpu1.num_writes 53968 # number of write accesses completed +system.cpu2.l1c.ReadReq_accesses 44798 # number of ReadReq accesses(hits+misses) +system.cpu2.l1c.ReadReq_avg_miss_latency 16757.356387 # average ReadReq miss latency +system.cpu2.l1c.ReadReq_avg_mshr_miss_latency 15755.538278 # average ReadReq mshr miss latency system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.cpu2.l1c.ReadReq_hits 7579 # number of ReadReq hits -system.cpu2.l1c.ReadReq_miss_latency 879279233 # number of ReadReq miss cycles -system.cpu2.l1c.ReadReq_miss_rate 0.830356 # miss rate for ReadReq accesses -system.cpu2.l1c.ReadReq_misses 37097 # number of ReadReq misses -system.cpu2.l1c.ReadReq_mshr_miss_latency 842114012 # number of ReadReq MSHR miss cycles -system.cpu2.l1c.ReadReq_mshr_miss_rate 0.830356 # mshr miss rate for ReadReq accesses -system.cpu2.l1c.ReadReq_mshr_misses 37097 # number of ReadReq MSHR misses -system.cpu2.l1c.ReadReq_mshr_uncacheable_latency 463945660 # number of ReadReq MSHR uncacheable cycles -system.cpu2.l1c.WriteReq_accesses 24311 # number of WriteReq accesses(hits+misses) -system.cpu2.l1c.WriteReq_avg_miss_latency 28427.205208 # average WriteReq miss latency -system.cpu2.l1c.WriteReq_avg_mshr_miss_latency 27425.376280 # average WriteReq mshr miss latency +system.cpu2.l1c.ReadReq_hits 7479 # number of ReadReq hits +system.cpu2.l1c.ReadReq_miss_latency 625367783 # number of ReadReq miss cycles +system.cpu2.l1c.ReadReq_miss_rate 0.833051 # miss rate for ReadReq accesses +system.cpu2.l1c.ReadReq_misses 37319 # number of ReadReq misses +system.cpu2.l1c.ReadReq_mshr_miss_latency 587980933 # number of ReadReq MSHR miss cycles +system.cpu2.l1c.ReadReq_mshr_miss_rate 0.833051 # mshr miss rate for ReadReq accesses +system.cpu2.l1c.ReadReq_mshr_misses 37319 # number of ReadReq MSHR misses +system.cpu2.l1c.ReadReq_mshr_uncacheable_latency 312913561 # number of ReadReq MSHR uncacheable cycles +system.cpu2.l1c.WriteReq_accesses 24115 # number of WriteReq accesses(hits+misses) +system.cpu2.l1c.WriteReq_avg_miss_latency 20248.523869 # average WriteReq miss latency +system.cpu2.l1c.WriteReq_avg_mshr_miss_latency 19246.649160 # average WriteReq mshr miss latency system.cpu2.l1c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency -system.cpu2.l1c.WriteReq_hits 964 # number of WriteReq hits -system.cpu2.l1c.WriteReq_miss_latency 663689960 # number of WriteReq miss cycles -system.cpu2.l1c.WriteReq_miss_rate 0.960347 # miss rate for WriteReq accesses -system.cpu2.l1c.WriteReq_misses 23347 # number of WriteReq misses -system.cpu2.l1c.WriteReq_mshr_miss_latency 640300260 # number of WriteReq MSHR miss cycles -system.cpu2.l1c.WriteReq_mshr_miss_rate 0.960347 # mshr miss rate for WriteReq accesses -system.cpu2.l1c.WriteReq_mshr_misses 23347 # number of WriteReq MSHR misses -system.cpu2.l1c.WriteReq_mshr_uncacheable_latency 293541767 # number of WriteReq MSHR uncacheable cycles -system.cpu2.l1c.avg_blocked_cycles_no_mshrs 2298.353100 # average number of cycles each access was blocked +system.cpu2.l1c.WriteReq_hits 905 # number of WriteReq hits +system.cpu2.l1c.WriteReq_miss_latency 469968239 # number of WriteReq miss cycles +system.cpu2.l1c.WriteReq_miss_rate 0.962471 # miss rate for WriteReq accesses +system.cpu2.l1c.WriteReq_misses 23210 # number of WriteReq misses +system.cpu2.l1c.WriteReq_mshr_miss_latency 446714727 # number of WriteReq MSHR miss cycles +system.cpu2.l1c.WriteReq_mshr_miss_rate 0.962471 # mshr miss rate for WriteReq accesses +system.cpu2.l1c.WriteReq_mshr_misses 23210 # number of WriteReq MSHR misses +system.cpu2.l1c.WriteReq_mshr_uncacheable_latency 194813468 # number of WriteReq MSHR uncacheable cycles +system.cpu2.l1c.avg_blocked_cycles_no_mshrs 1594.588395 # average number of cycles each access was blocked system.cpu2.l1c.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu2.l1c.avg_refs 0.415183 # Average number of references to valid blocks. -system.cpu2.l1c.blocked_no_mshrs 69275 # number of cycles access was blocked +system.cpu2.l1c.avg_refs 0.408059 # Average number of references to valid blocks. +system.cpu2.l1c.blocked_no_mshrs 69812 # number of cycles access was blocked system.cpu2.l1c.blocked_no_targets 0 # number of cycles access was blocked -system.cpu2.l1c.blocked_cycles_no_mshrs 159218411 # number of cycles access was blocked +system.cpu2.l1c.blocked_cycles_no_mshrs 111321405 # number of cycles access was blocked system.cpu2.l1c.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu2.l1c.cache_copies 0 # number of cache copies performed -system.cpu2.l1c.demand_accesses 68987 # number of demand (read+write) accesses -system.cpu2.l1c.demand_avg_miss_latency 25527.251555 # average overall miss latency -system.cpu2.l1c.demand_avg_mshr_miss_latency 24525.416452 # average overall mshr miss latency -system.cpu2.l1c.demand_hits 8543 # number of demand (read+write) hits -system.cpu2.l1c.demand_miss_latency 1542969193 # number of demand (read+write) miss cycles -system.cpu2.l1c.demand_miss_rate 0.876165 # miss rate for demand accesses -system.cpu2.l1c.demand_misses 60444 # number of demand (read+write) misses +system.cpu2.l1c.demand_accesses 68913 # number of demand (read+write) accesses +system.cpu2.l1c.demand_avg_miss_latency 18096.053495 # average overall miss latency +system.cpu2.l1c.demand_avg_mshr_miss_latency 17094.213683 # average overall mshr miss latency +system.cpu2.l1c.demand_hits 8384 # number of demand (read+write) hits +system.cpu2.l1c.demand_miss_latency 1095336022 # number of demand (read+write) miss cycles +system.cpu2.l1c.demand_miss_rate 0.878339 # miss rate for demand accesses +system.cpu2.l1c.demand_misses 60529 # number of demand (read+write) misses system.cpu2.l1c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu2.l1c.demand_mshr_miss_latency 1482414272 # number of demand (read+write) MSHR miss cycles -system.cpu2.l1c.demand_mshr_miss_rate 0.876165 # mshr miss rate for demand accesses -system.cpu2.l1c.demand_mshr_misses 60444 # number of demand (read+write) MSHR misses +system.cpu2.l1c.demand_mshr_miss_latency 1034695660 # number of demand (read+write) MSHR miss cycles +system.cpu2.l1c.demand_mshr_miss_rate 0.878339 # mshr miss rate for demand accesses +system.cpu2.l1c.demand_mshr_misses 60529 # number of demand (read+write) MSHR misses system.cpu2.l1c.fast_writes 0 # number of fast writes performed system.cpu2.l1c.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu2.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu2.l1c.overall_accesses 68987 # number of overall (read+write) accesses -system.cpu2.l1c.overall_avg_miss_latency 25527.251555 # average overall miss latency -system.cpu2.l1c.overall_avg_mshr_miss_latency 24525.416452 # average overall mshr miss latency +system.cpu2.l1c.overall_accesses 68913 # number of overall (read+write) accesses +system.cpu2.l1c.overall_avg_miss_latency 18096.053495 # average overall miss latency +system.cpu2.l1c.overall_avg_mshr_miss_latency 17094.213683 # average overall mshr miss latency system.cpu2.l1c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.cpu2.l1c.overall_hits 8543 # number of overall hits -system.cpu2.l1c.overall_miss_latency 1542969193 # number of overall miss cycles -system.cpu2.l1c.overall_miss_rate 0.876165 # miss rate for overall accesses -system.cpu2.l1c.overall_misses 60444 # number of overall misses +system.cpu2.l1c.overall_hits 8384 # number of overall hits +system.cpu2.l1c.overall_miss_latency 1095336022 # number of overall miss cycles +system.cpu2.l1c.overall_miss_rate 0.878339 # miss rate for overall accesses +system.cpu2.l1c.overall_misses 60529 # number of overall misses system.cpu2.l1c.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu2.l1c.overall_mshr_miss_latency 1482414272 # number of overall MSHR miss cycles -system.cpu2.l1c.overall_mshr_miss_rate 0.876165 # mshr miss rate for overall accesses -system.cpu2.l1c.overall_mshr_misses 60444 # number of overall MSHR misses -system.cpu2.l1c.overall_mshr_uncacheable_latency 757487427 # number of overall MSHR uncacheable cycles +system.cpu2.l1c.overall_mshr_miss_latency 1034695660 # number of overall MSHR miss cycles +system.cpu2.l1c.overall_mshr_miss_rate 0.878339 # mshr miss rate for overall accesses +system.cpu2.l1c.overall_mshr_misses 60529 # number of overall MSHR misses +system.cpu2.l1c.overall_mshr_uncacheable_latency 507727029 # number of overall MSHR uncacheable cycles system.cpu2.l1c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu2.l1c.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache system.cpu2.l1c.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr @@ -233,75 +233,75 @@ system.cpu2.l1c.prefetcher.num_hwpf_issued 0 # system.cpu2.l1c.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu2.l1c.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu2.l1c.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu2.l1c.replacements 27813 # number of replacements -system.cpu2.l1c.sampled_refs 28149 # Sample count of references to valid blocks. +system.cpu2.l1c.replacements 27701 # number of replacements +system.cpu2.l1c.sampled_refs 28067 # Sample count of references to valid blocks. system.cpu2.l1c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu2.l1c.tagsinuse 346.292399 # Cycle average of tags in use -system.cpu2.l1c.total_refs 11687 # Total number of references to valid blocks. +system.cpu2.l1c.tagsinuse 345.217009 # Cycle average of tags in use +system.cpu2.l1c.total_refs 11453 # Total number of references to valid blocks. system.cpu2.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu2.l1c.writebacks 11045 # number of writebacks +system.cpu2.l1c.writebacks 10945 # number of writebacks system.cpu2.num_copies 0 # number of copy accesses completed -system.cpu2.num_reads 99140 # number of read accesses completed -system.cpu2.num_writes 54118 # number of write accesses completed -system.cpu3.l1c.ReadReq_accesses 44967 # number of ReadReq accesses(hits+misses) -system.cpu3.l1c.ReadReq_avg_miss_latency 23556.282690 # average ReadReq miss latency -system.cpu3.l1c.ReadReq_avg_mshr_miss_latency 22554.335004 # average ReadReq mshr miss latency +system.cpu2.num_reads 99465 # number of read accesses completed +system.cpu2.num_writes 53678 # number of write accesses completed +system.cpu3.l1c.ReadReq_accesses 44738 # number of ReadReq accesses(hits+misses) +system.cpu3.l1c.ReadReq_avg_miss_latency 16807.406146 # average ReadReq miss latency +system.cpu3.l1c.ReadReq_avg_mshr_miss_latency 15805.508175 # average ReadReq mshr miss latency system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.cpu3.l1c.ReadReq_hits 7463 # number of ReadReq hits -system.cpu3.l1c.ReadReq_miss_latency 883454826 # number of ReadReq miss cycles -system.cpu3.l1c.ReadReq_miss_rate 0.834034 # miss rate for ReadReq accesses -system.cpu3.l1c.ReadReq_misses 37504 # number of ReadReq misses -system.cpu3.l1c.ReadReq_mshr_miss_latency 845877780 # number of ReadReq MSHR miss cycles -system.cpu3.l1c.ReadReq_mshr_miss_rate 0.834034 # mshr miss rate for ReadReq accesses -system.cpu3.l1c.ReadReq_mshr_misses 37504 # number of ReadReq MSHR misses -system.cpu3.l1c.ReadReq_mshr_uncacheable_latency 463016288 # number of ReadReq MSHR uncacheable cycles -system.cpu3.l1c.WriteReq_accesses 24252 # number of WriteReq accesses(hits+misses) -system.cpu3.l1c.WriteReq_avg_miss_latency 28359.679643 # average WriteReq miss latency -system.cpu3.l1c.WriteReq_avg_mshr_miss_latency 27357.936889 # average WriteReq mshr miss latency +system.cpu3.l1c.ReadReq_hits 7611 # number of ReadReq hits +system.cpu3.l1c.ReadReq_miss_latency 624008568 # number of ReadReq miss cycles +system.cpu3.l1c.ReadReq_miss_rate 0.829876 # miss rate for ReadReq accesses +system.cpu3.l1c.ReadReq_misses 37127 # number of ReadReq misses +system.cpu3.l1c.ReadReq_mshr_miss_latency 586811102 # number of ReadReq MSHR miss cycles +system.cpu3.l1c.ReadReq_mshr_miss_rate 0.829876 # mshr miss rate for ReadReq accesses +system.cpu3.l1c.ReadReq_mshr_misses 37127 # number of ReadReq MSHR misses +system.cpu3.l1c.ReadReq_mshr_uncacheable_latency 311781129 # number of ReadReq MSHR uncacheable cycles +system.cpu3.l1c.WriteReq_accesses 24234 # number of WriteReq accesses(hits+misses) +system.cpu3.l1c.WriteReq_avg_miss_latency 20220.683790 # average WriteReq miss latency +system.cpu3.l1c.WriteReq_avg_mshr_miss_latency 19218.851594 # average WriteReq mshr miss latency system.cpu3.l1c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency -system.cpu3.l1c.WriteReq_hits 928 # number of WriteReq hits -system.cpu3.l1c.WriteReq_miss_latency 661461168 # number of WriteReq miss cycles -system.cpu3.l1c.WriteReq_miss_rate 0.961735 # miss rate for WriteReq accesses -system.cpu3.l1c.WriteReq_misses 23324 # number of WriteReq misses -system.cpu3.l1c.WriteReq_mshr_miss_latency 638096520 # number of WriteReq MSHR miss cycles -system.cpu3.l1c.WriteReq_mshr_miss_rate 0.961735 # mshr miss rate for WriteReq accesses -system.cpu3.l1c.WriteReq_mshr_misses 23324 # number of WriteReq MSHR misses -system.cpu3.l1c.WriteReq_mshr_uncacheable_latency 286853981 # number of WriteReq MSHR uncacheable cycles -system.cpu3.l1c.avg_blocked_cycles_no_mshrs 2284.842199 # average number of cycles each access was blocked +system.cpu3.l1c.WriteReq_hits 933 # number of WriteReq hits +system.cpu3.l1c.WriteReq_miss_latency 471162153 # number of WriteReq miss cycles +system.cpu3.l1c.WriteReq_miss_rate 0.961500 # miss rate for WriteReq accesses +system.cpu3.l1c.WriteReq_misses 23301 # number of WriteReq misses +system.cpu3.l1c.WriteReq_mshr_miss_latency 447818461 # number of WriteReq MSHR miss cycles +system.cpu3.l1c.WriteReq_mshr_miss_rate 0.961500 # mshr miss rate for WriteReq accesses +system.cpu3.l1c.WriteReq_mshr_misses 23301 # number of WriteReq MSHR misses +system.cpu3.l1c.WriteReq_mshr_uncacheable_latency 199047765 # number of WriteReq MSHR uncacheable cycles +system.cpu3.l1c.avg_blocked_cycles_no_mshrs 1592.177624 # average number of cycles each access was blocked system.cpu3.l1c.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu3.l1c.avg_refs 0.401096 # Average number of references to valid blocks. -system.cpu3.l1c.blocked_no_mshrs 69803 # number of cycles access was blocked +system.cpu3.l1c.avg_refs 0.416452 # Average number of references to valid blocks. +system.cpu3.l1c.blocked_no_mshrs 69619 # number of cycles access was blocked system.cpu3.l1c.blocked_no_targets 0 # number of cycles access was blocked -system.cpu3.l1c.blocked_cycles_no_mshrs 159488840 # number of cycles access was blocked +system.cpu3.l1c.blocked_cycles_no_mshrs 110845814 # number of cycles access was blocked system.cpu3.l1c.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu3.l1c.cache_copies 0 # number of cache copies performed -system.cpu3.l1c.demand_accesses 69219 # number of demand (read+write) accesses -system.cpu3.l1c.demand_avg_miss_latency 25398.106037 # average overall miss latency -system.cpu3.l1c.demand_avg_mshr_miss_latency 24396.236930 # average overall mshr miss latency -system.cpu3.l1c.demand_hits 8391 # number of demand (read+write) hits -system.cpu3.l1c.demand_miss_latency 1544915994 # number of demand (read+write) miss cycles -system.cpu3.l1c.demand_miss_rate 0.878776 # miss rate for demand accesses -system.cpu3.l1c.demand_misses 60828 # number of demand (read+write) misses +system.cpu3.l1c.demand_accesses 68972 # number of demand (read+write) accesses +system.cpu3.l1c.demand_avg_miss_latency 18123.563927 # average overall miss latency +system.cpu3.l1c.demand_avg_mshr_miss_latency 17121.691319 # average overall mshr miss latency +system.cpu3.l1c.demand_hits 8544 # number of demand (read+write) hits +system.cpu3.l1c.demand_miss_latency 1095170721 # number of demand (read+write) miss cycles +system.cpu3.l1c.demand_miss_rate 0.876124 # miss rate for demand accesses +system.cpu3.l1c.demand_misses 60428 # number of demand (read+write) misses system.cpu3.l1c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu3.l1c.demand_mshr_miss_latency 1483974300 # number of demand (read+write) MSHR miss cycles -system.cpu3.l1c.demand_mshr_miss_rate 0.878776 # mshr miss rate for demand accesses -system.cpu3.l1c.demand_mshr_misses 60828 # number of demand (read+write) MSHR misses +system.cpu3.l1c.demand_mshr_miss_latency 1034629563 # number of demand (read+write) MSHR miss cycles +system.cpu3.l1c.demand_mshr_miss_rate 0.876124 # mshr miss rate for demand accesses +system.cpu3.l1c.demand_mshr_misses 60428 # number of demand (read+write) MSHR misses system.cpu3.l1c.fast_writes 0 # number of fast writes performed system.cpu3.l1c.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu3.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu3.l1c.overall_accesses 69219 # number of overall (read+write) accesses -system.cpu3.l1c.overall_avg_miss_latency 25398.106037 # average overall miss latency -system.cpu3.l1c.overall_avg_mshr_miss_latency 24396.236930 # average overall mshr miss latency +system.cpu3.l1c.overall_accesses 68972 # number of overall (read+write) accesses +system.cpu3.l1c.overall_avg_miss_latency 18123.563927 # average overall miss latency +system.cpu3.l1c.overall_avg_mshr_miss_latency 17121.691319 # average overall mshr miss latency system.cpu3.l1c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.cpu3.l1c.overall_hits 8391 # number of overall hits -system.cpu3.l1c.overall_miss_latency 1544915994 # number of overall miss cycles -system.cpu3.l1c.overall_miss_rate 0.878776 # miss rate for overall accesses -system.cpu3.l1c.overall_misses 60828 # number of overall misses +system.cpu3.l1c.overall_hits 8544 # number of overall hits +system.cpu3.l1c.overall_miss_latency 1095170721 # number of overall miss cycles +system.cpu3.l1c.overall_miss_rate 0.876124 # miss rate for overall accesses +system.cpu3.l1c.overall_misses 60428 # number of overall misses system.cpu3.l1c.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu3.l1c.overall_mshr_miss_latency 1483974300 # number of overall MSHR miss cycles -system.cpu3.l1c.overall_mshr_miss_rate 0.878776 # mshr miss rate for overall accesses -system.cpu3.l1c.overall_mshr_misses 60828 # number of overall MSHR misses -system.cpu3.l1c.overall_mshr_uncacheable_latency 749870269 # number of overall MSHR uncacheable cycles +system.cpu3.l1c.overall_mshr_miss_latency 1034629563 # number of overall MSHR miss cycles +system.cpu3.l1c.overall_mshr_miss_rate 0.876124 # mshr miss rate for overall accesses +system.cpu3.l1c.overall_mshr_misses 60428 # number of overall MSHR misses +system.cpu3.l1c.overall_mshr_uncacheable_latency 510828894 # number of overall MSHR uncacheable cycles system.cpu3.l1c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu3.l1c.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache system.cpu3.l1c.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr @@ -312,75 +312,75 @@ system.cpu3.l1c.prefetcher.num_hwpf_issued 0 # system.cpu3.l1c.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu3.l1c.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu3.l1c.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu3.l1c.replacements 28133 # number of replacements -system.cpu3.l1c.sampled_refs 28477 # Sample count of references to valid blocks. +system.cpu3.l1c.replacements 27578 # number of replacements +system.cpu3.l1c.sampled_refs 27936 # Sample count of references to valid blocks. system.cpu3.l1c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu3.l1c.tagsinuse 347.262699 # Cycle average of tags in use -system.cpu3.l1c.total_refs 11422 # Total number of references to valid blocks. +system.cpu3.l1c.tagsinuse 346.223352 # Cycle average of tags in use +system.cpu3.l1c.total_refs 11634 # Total number of references to valid blocks. system.cpu3.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu3.l1c.writebacks 11005 # number of writebacks +system.cpu3.l1c.writebacks 10930 # number of writebacks system.cpu3.num_copies 0 # number of copy accesses completed -system.cpu3.num_reads 99592 # number of read accesses completed -system.cpu3.num_writes 53713 # number of write accesses completed -system.cpu4.l1c.ReadReq_accesses 44752 # number of ReadReq accesses(hits+misses) -system.cpu4.l1c.ReadReq_avg_miss_latency 23804.358655 # average ReadReq miss latency -system.cpu4.l1c.ReadReq_avg_mshr_miss_latency 22802.626506 # average ReadReq mshr miss latency +system.cpu3.num_reads 99191 # number of read accesses completed +system.cpu3.num_writes 53892 # number of write accesses completed +system.cpu4.l1c.ReadReq_accesses 44699 # number of ReadReq accesses(hits+misses) +system.cpu4.l1c.ReadReq_avg_miss_latency 16730.870402 # average ReadReq miss latency +system.cpu4.l1c.ReadReq_avg_mshr_miss_latency 15728.971431 # average ReadReq mshr miss latency system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.cpu4.l1c.ReadReq_hits 7485 # number of ReadReq hits -system.cpu4.l1c.ReadReq_miss_latency 887117034 # number of ReadReq miss cycles -system.cpu4.l1c.ReadReq_miss_rate 0.832745 # miss rate for ReadReq accesses -system.cpu4.l1c.ReadReq_misses 37267 # number of ReadReq misses -system.cpu4.l1c.ReadReq_mshr_miss_latency 849785482 # number of ReadReq MSHR miss cycles -system.cpu4.l1c.ReadReq_mshr_miss_rate 0.832745 # mshr miss rate for ReadReq accesses -system.cpu4.l1c.ReadReq_mshr_misses 37267 # number of ReadReq MSHR misses -system.cpu4.l1c.ReadReq_mshr_uncacheable_latency 460944695 # number of ReadReq MSHR uncacheable cycles -system.cpu4.l1c.WriteReq_accesses 24051 # number of WriteReq accesses(hits+misses) -system.cpu4.l1c.WriteReq_avg_miss_latency 28478.181673 # average WriteReq miss latency -system.cpu4.l1c.WriteReq_avg_mshr_miss_latency 27476.224597 # average WriteReq mshr miss latency +system.cpu4.l1c.ReadReq_hits 7561 # number of ReadReq hits +system.cpu4.l1c.ReadReq_miss_latency 621351065 # number of ReadReq miss cycles +system.cpu4.l1c.ReadReq_miss_rate 0.830846 # miss rate for ReadReq accesses +system.cpu4.l1c.ReadReq_misses 37138 # number of ReadReq misses +system.cpu4.l1c.ReadReq_mshr_miss_latency 584142541 # number of ReadReq MSHR miss cycles +system.cpu4.l1c.ReadReq_mshr_miss_rate 0.830846 # mshr miss rate for ReadReq accesses +system.cpu4.l1c.ReadReq_mshr_misses 37138 # number of ReadReq MSHR misses +system.cpu4.l1c.ReadReq_mshr_uncacheable_latency 311544934 # number of ReadReq MSHR uncacheable cycles +system.cpu4.l1c.WriteReq_accesses 24149 # number of WriteReq accesses(hits+misses) +system.cpu4.l1c.WriteReq_avg_miss_latency 20416.974602 # average WriteReq miss latency +system.cpu4.l1c.WriteReq_avg_mshr_miss_latency 19415.143220 # average WriteReq mshr miss latency system.cpu4.l1c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency -system.cpu4.l1c.WriteReq_hits 894 # number of WriteReq hits -system.cpu4.l1c.WriteReq_miss_latency 659469253 # number of WriteReq miss cycles -system.cpu4.l1c.WriteReq_miss_rate 0.962829 # miss rate for WriteReq accesses -system.cpu4.l1c.WriteReq_misses 23157 # number of WriteReq misses -system.cpu4.l1c.WriteReq_mshr_miss_latency 636266933 # number of WriteReq MSHR miss cycles -system.cpu4.l1c.WriteReq_mshr_miss_rate 0.962829 # mshr miss rate for WriteReq accesses -system.cpu4.l1c.WriteReq_mshr_misses 23157 # number of WriteReq MSHR misses -system.cpu4.l1c.WriteReq_mshr_uncacheable_latency 290316641 # number of WriteReq MSHR uncacheable cycles -system.cpu4.l1c.avg_blocked_cycles_no_mshrs 2303.542545 # average number of cycles each access was blocked +system.cpu4.l1c.WriteReq_hits 919 # number of WriteReq hits +system.cpu4.l1c.WriteReq_miss_latency 474286320 # number of WriteReq miss cycles +system.cpu4.l1c.WriteReq_miss_rate 0.961945 # miss rate for WriteReq accesses +system.cpu4.l1c.WriteReq_misses 23230 # number of WriteReq misses +system.cpu4.l1c.WriteReq_mshr_miss_latency 451013777 # number of WriteReq MSHR miss cycles +system.cpu4.l1c.WriteReq_mshr_miss_rate 0.961945 # mshr miss rate for WriteReq accesses +system.cpu4.l1c.WriteReq_mshr_misses 23230 # number of WriteReq MSHR misses +system.cpu4.l1c.WriteReq_mshr_uncacheable_latency 197320845 # number of WriteReq MSHR uncacheable cycles +system.cpu4.l1c.avg_blocked_cycles_no_mshrs 1595.899195 # average number of cycles each access was blocked system.cpu4.l1c.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu4.l1c.avg_refs 0.410509 # Average number of references to valid blocks. -system.cpu4.l1c.blocked_no_mshrs 69338 # number of cycles access was blocked +system.cpu4.l1c.avg_refs 0.415693 # Average number of references to valid blocks. +system.cpu4.l1c.blocked_no_mshrs 69580 # number of cycles access was blocked system.cpu4.l1c.blocked_no_targets 0 # number of cycles access was blocked -system.cpu4.l1c.blocked_cycles_no_mshrs 159723033 # number of cycles access was blocked +system.cpu4.l1c.blocked_cycles_no_mshrs 111042666 # number of cycles access was blocked system.cpu4.l1c.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu4.l1c.cache_copies 0 # number of cache copies performed -system.cpu4.l1c.demand_accesses 68803 # number of demand (read+write) accesses -system.cpu4.l1c.demand_avg_miss_latency 25595.562806 # average overall miss latency -system.cpu4.l1c.demand_avg_mshr_miss_latency 24593.744456 # average overall mshr miss latency -system.cpu4.l1c.demand_hits 8379 # number of demand (read+write) hits -system.cpu4.l1c.demand_miss_latency 1546586287 # number of demand (read+write) miss cycles -system.cpu4.l1c.demand_miss_rate 0.878218 # miss rate for demand accesses -system.cpu4.l1c.demand_misses 60424 # number of demand (read+write) misses +system.cpu4.l1c.demand_accesses 68848 # number of demand (read+write) accesses +system.cpu4.l1c.demand_avg_miss_latency 18149.307332 # average overall miss latency +system.cpu4.l1c.demand_avg_mshr_miss_latency 17147.434369 # average overall mshr miss latency +system.cpu4.l1c.demand_hits 8480 # number of demand (read+write) hits +system.cpu4.l1c.demand_miss_latency 1095637385 # number of demand (read+write) miss cycles +system.cpu4.l1c.demand_miss_rate 0.876830 # miss rate for demand accesses +system.cpu4.l1c.demand_misses 60368 # number of demand (read+write) misses system.cpu4.l1c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu4.l1c.demand_mshr_miss_latency 1486052415 # number of demand (read+write) MSHR miss cycles -system.cpu4.l1c.demand_mshr_miss_rate 0.878218 # mshr miss rate for demand accesses -system.cpu4.l1c.demand_mshr_misses 60424 # number of demand (read+write) MSHR misses +system.cpu4.l1c.demand_mshr_miss_latency 1035156318 # number of demand (read+write) MSHR miss cycles +system.cpu4.l1c.demand_mshr_miss_rate 0.876830 # mshr miss rate for demand accesses +system.cpu4.l1c.demand_mshr_misses 60368 # number of demand (read+write) MSHR misses system.cpu4.l1c.fast_writes 0 # number of fast writes performed system.cpu4.l1c.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu4.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu4.l1c.overall_accesses 68803 # number of overall (read+write) accesses -system.cpu4.l1c.overall_avg_miss_latency 25595.562806 # average overall miss latency -system.cpu4.l1c.overall_avg_mshr_miss_latency 24593.744456 # average overall mshr miss latency +system.cpu4.l1c.overall_accesses 68848 # number of overall (read+write) accesses +system.cpu4.l1c.overall_avg_miss_latency 18149.307332 # average overall miss latency +system.cpu4.l1c.overall_avg_mshr_miss_latency 17147.434369 # average overall mshr miss latency system.cpu4.l1c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.cpu4.l1c.overall_hits 8379 # number of overall hits -system.cpu4.l1c.overall_miss_latency 1546586287 # number of overall miss cycles -system.cpu4.l1c.overall_miss_rate 0.878218 # miss rate for overall accesses -system.cpu4.l1c.overall_misses 60424 # number of overall misses +system.cpu4.l1c.overall_hits 8480 # number of overall hits +system.cpu4.l1c.overall_miss_latency 1095637385 # number of overall miss cycles +system.cpu4.l1c.overall_miss_rate 0.876830 # miss rate for overall accesses +system.cpu4.l1c.overall_misses 60368 # number of overall misses system.cpu4.l1c.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu4.l1c.overall_mshr_miss_latency 1486052415 # number of overall MSHR miss cycles -system.cpu4.l1c.overall_mshr_miss_rate 0.878218 # mshr miss rate for overall accesses -system.cpu4.l1c.overall_mshr_misses 60424 # number of overall MSHR misses -system.cpu4.l1c.overall_mshr_uncacheable_latency 751261336 # number of overall MSHR uncacheable cycles +system.cpu4.l1c.overall_mshr_miss_latency 1035156318 # number of overall MSHR miss cycles +system.cpu4.l1c.overall_mshr_miss_rate 0.876830 # mshr miss rate for overall accesses +system.cpu4.l1c.overall_mshr_misses 60368 # number of overall MSHR misses +system.cpu4.l1c.overall_mshr_uncacheable_latency 508865779 # number of overall MSHR uncacheable cycles system.cpu4.l1c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu4.l1c.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache system.cpu4.l1c.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr @@ -391,75 +391,75 @@ system.cpu4.l1c.prefetcher.num_hwpf_issued 0 # system.cpu4.l1c.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu4.l1c.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu4.l1c.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu4.l1c.replacements 27694 # number of replacements -system.cpu4.l1c.sampled_refs 28053 # Sample count of references to valid blocks. +system.cpu4.l1c.replacements 27387 # number of replacements +system.cpu4.l1c.sampled_refs 27744 # Sample count of references to valid blocks. system.cpu4.l1c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu4.l1c.tagsinuse 346.576888 # Cycle average of tags in use -system.cpu4.l1c.total_refs 11516 # Total number of references to valid blocks. +system.cpu4.l1c.tagsinuse 342.465450 # Cycle average of tags in use +system.cpu4.l1c.total_refs 11533 # Total number of references to valid blocks. system.cpu4.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu4.l1c.writebacks 10817 # number of writebacks +system.cpu4.l1c.writebacks 10754 # number of writebacks system.cpu4.num_copies 0 # number of copy accesses completed -system.cpu4.num_reads 98799 # number of read accesses completed -system.cpu4.num_writes 53431 # number of write accesses completed -system.cpu5.l1c.ReadReq_accesses 44885 # number of ReadReq accesses(hits+misses) -system.cpu5.l1c.ReadReq_avg_miss_latency 23518.665421 # average ReadReq miss latency -system.cpu5.l1c.ReadReq_avg_mshr_miss_latency 22516.852786 # average ReadReq mshr miss latency +system.cpu4.num_reads 98875 # number of read accesses completed +system.cpu4.num_writes 53476 # number of write accesses completed +system.cpu5.l1c.ReadReq_accesses 45145 # number of ReadReq accesses(hits+misses) +system.cpu5.l1c.ReadReq_avg_miss_latency 16695.250027 # average ReadReq miss latency +system.cpu5.l1c.ReadReq_avg_mshr_miss_latency 15693.270526 # average ReadReq mshr miss latency system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.cpu5.l1c.ReadReq_hits 7701 # number of ReadReq hits -system.cpu5.l1c.ReadReq_miss_latency 874518055 # number of ReadReq miss cycles -system.cpu5.l1c.ReadReq_miss_rate 0.828428 # miss rate for ReadReq accesses -system.cpu5.l1c.ReadReq_misses 37184 # number of ReadReq misses -system.cpu5.l1c.ReadReq_mshr_miss_latency 837266654 # number of ReadReq MSHR miss cycles -system.cpu5.l1c.ReadReq_mshr_miss_rate 0.828428 # mshr miss rate for ReadReq accesses -system.cpu5.l1c.ReadReq_mshr_misses 37184 # number of ReadReq MSHR misses -system.cpu5.l1c.ReadReq_mshr_uncacheable_latency 472519207 # number of ReadReq MSHR uncacheable cycles -system.cpu5.l1c.WriteReq_accesses 24343 # number of WriteReq accesses(hits+misses) -system.cpu5.l1c.WriteReq_avg_miss_latency 28185.897903 # average WriteReq miss latency -system.cpu5.l1c.WriteReq_avg_mshr_miss_latency 27184.111666 # average WriteReq mshr miss latency +system.cpu5.l1c.ReadReq_hits 7729 # number of ReadReq hits +system.cpu5.l1c.ReadReq_miss_latency 624669475 # number of ReadReq miss cycles +system.cpu5.l1c.ReadReq_miss_rate 0.828796 # miss rate for ReadReq accesses +system.cpu5.l1c.ReadReq_misses 37416 # number of ReadReq misses +system.cpu5.l1c.ReadReq_mshr_miss_latency 587179410 # number of ReadReq MSHR miss cycles +system.cpu5.l1c.ReadReq_mshr_miss_rate 0.828796 # mshr miss rate for ReadReq accesses +system.cpu5.l1c.ReadReq_mshr_misses 37416 # number of ReadReq MSHR misses +system.cpu5.l1c.ReadReq_mshr_uncacheable_latency 307088107 # number of ReadReq MSHR uncacheable cycles +system.cpu5.l1c.WriteReq_accesses 24354 # number of WriteReq accesses(hits+misses) +system.cpu5.l1c.WriteReq_avg_miss_latency 20311.644445 # average WriteReq miss latency +system.cpu5.l1c.WriteReq_avg_mshr_miss_latency 19309.896163 # average WriteReq mshr miss latency system.cpu5.l1c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency -system.cpu5.l1c.WriteReq_hits 934 # number of WriteReq hits -system.cpu5.l1c.WriteReq_miss_latency 659803684 # number of WriteReq miss cycles -system.cpu5.l1c.WriteReq_miss_rate 0.961632 # miss rate for WriteReq accesses -system.cpu5.l1c.WriteReq_misses 23409 # number of WriteReq misses -system.cpu5.l1c.WriteReq_mshr_miss_latency 636352870 # number of WriteReq MSHR miss cycles -system.cpu5.l1c.WriteReq_mshr_miss_rate 0.961632 # mshr miss rate for WriteReq accesses -system.cpu5.l1c.WriteReq_mshr_misses 23409 # number of WriteReq MSHR misses -system.cpu5.l1c.WriteReq_mshr_uncacheable_latency 285116672 # number of WriteReq MSHR uncacheable cycles -system.cpu5.l1c.avg_blocked_cycles_no_mshrs 2289.516557 # average number of cycles each access was blocked +system.cpu5.l1c.WriteReq_hits 923 # number of WriteReq hits +system.cpu5.l1c.WriteReq_miss_latency 475922141 # number of WriteReq miss cycles +system.cpu5.l1c.WriteReq_miss_rate 0.962101 # miss rate for WriteReq accesses +system.cpu5.l1c.WriteReq_misses 23431 # number of WriteReq misses +system.cpu5.l1c.WriteReq_mshr_miss_latency 452450177 # number of WriteReq MSHR miss cycles +system.cpu5.l1c.WriteReq_mshr_miss_rate 0.962101 # mshr miss rate for WriteReq accesses +system.cpu5.l1c.WriteReq_mshr_misses 23431 # number of WriteReq MSHR misses +system.cpu5.l1c.WriteReq_mshr_uncacheable_latency 201036456 # number of WriteReq MSHR uncacheable cycles +system.cpu5.l1c.avg_blocked_cycles_no_mshrs 1589.108090 # average number of cycles each access was blocked system.cpu5.l1c.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu5.l1c.avg_refs 0.417638 # Average number of references to valid blocks. -system.cpu5.l1c.blocked_no_mshrs 69638 # number of cycles access was blocked +system.cpu5.l1c.avg_refs 0.411131 # Average number of references to valid blocks. +system.cpu5.l1c.blocked_no_mshrs 69923 # number of cycles access was blocked system.cpu5.l1c.blocked_no_targets 0 # number of cycles access was blocked -system.cpu5.l1c.blocked_cycles_no_mshrs 159437354 # number of cycles access was blocked +system.cpu5.l1c.blocked_cycles_no_mshrs 111115205 # number of cycles access was blocked system.cpu5.l1c.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu5.l1c.cache_copies 0 # number of cache copies performed -system.cpu5.l1c.demand_accesses 69228 # number of demand (read+write) accesses -system.cpu5.l1c.demand_avg_miss_latency 25321.765534 # average overall miss latency -system.cpu5.l1c.demand_avg_mshr_miss_latency 24319.963098 # average overall mshr miss latency -system.cpu5.l1c.demand_hits 8635 # number of demand (read+write) hits -system.cpu5.l1c.demand_miss_latency 1534321739 # number of demand (read+write) miss cycles -system.cpu5.l1c.demand_miss_rate 0.875267 # miss rate for demand accesses -system.cpu5.l1c.demand_misses 60593 # number of demand (read+write) misses +system.cpu5.l1c.demand_accesses 69499 # number of demand (read+write) accesses +system.cpu5.l1c.demand_avg_miss_latency 18087.853403 # average overall miss latency +system.cpu5.l1c.demand_avg_mshr_miss_latency 17085.962940 # average overall mshr miss latency +system.cpu5.l1c.demand_hits 8652 # number of demand (read+write) hits +system.cpu5.l1c.demand_miss_latency 1100591616 # number of demand (read+write) miss cycles +system.cpu5.l1c.demand_miss_rate 0.875509 # miss rate for demand accesses +system.cpu5.l1c.demand_misses 60847 # number of demand (read+write) misses system.cpu5.l1c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu5.l1c.demand_mshr_miss_latency 1473619524 # number of demand (read+write) MSHR miss cycles -system.cpu5.l1c.demand_mshr_miss_rate 0.875267 # mshr miss rate for demand accesses -system.cpu5.l1c.demand_mshr_misses 60593 # number of demand (read+write) MSHR misses +system.cpu5.l1c.demand_mshr_miss_latency 1039629587 # number of demand (read+write) MSHR miss cycles +system.cpu5.l1c.demand_mshr_miss_rate 0.875509 # mshr miss rate for demand accesses +system.cpu5.l1c.demand_mshr_misses 60847 # number of demand (read+write) MSHR misses system.cpu5.l1c.fast_writes 0 # number of fast writes performed system.cpu5.l1c.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu5.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu5.l1c.overall_accesses 69228 # number of overall (read+write) accesses -system.cpu5.l1c.overall_avg_miss_latency 25321.765534 # average overall miss latency -system.cpu5.l1c.overall_avg_mshr_miss_latency 24319.963098 # average overall mshr miss latency +system.cpu5.l1c.overall_accesses 69499 # number of overall (read+write) accesses +system.cpu5.l1c.overall_avg_miss_latency 18087.853403 # average overall miss latency +system.cpu5.l1c.overall_avg_mshr_miss_latency 17085.962940 # average overall mshr miss latency system.cpu5.l1c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.cpu5.l1c.overall_hits 8635 # number of overall hits -system.cpu5.l1c.overall_miss_latency 1534321739 # number of overall miss cycles -system.cpu5.l1c.overall_miss_rate 0.875267 # miss rate for overall accesses -system.cpu5.l1c.overall_misses 60593 # number of overall misses +system.cpu5.l1c.overall_hits 8652 # number of overall hits +system.cpu5.l1c.overall_miss_latency 1100591616 # number of overall miss cycles +system.cpu5.l1c.overall_miss_rate 0.875509 # miss rate for overall accesses +system.cpu5.l1c.overall_misses 60847 # number of overall misses system.cpu5.l1c.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu5.l1c.overall_mshr_miss_latency 1473619524 # number of overall MSHR miss cycles -system.cpu5.l1c.overall_mshr_miss_rate 0.875267 # mshr miss rate for overall accesses -system.cpu5.l1c.overall_mshr_misses 60593 # number of overall MSHR misses -system.cpu5.l1c.overall_mshr_uncacheable_latency 757635879 # number of overall MSHR uncacheable cycles +system.cpu5.l1c.overall_mshr_miss_latency 1039629587 # number of overall MSHR miss cycles +system.cpu5.l1c.overall_mshr_miss_rate 0.875509 # mshr miss rate for overall accesses +system.cpu5.l1c.overall_mshr_misses 60847 # number of overall MSHR misses +system.cpu5.l1c.overall_mshr_uncacheable_latency 508124563 # number of overall MSHR uncacheable cycles system.cpu5.l1c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu5.l1c.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache system.cpu5.l1c.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr @@ -470,75 +470,75 @@ system.cpu5.l1c.prefetcher.num_hwpf_issued 0 # system.cpu5.l1c.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu5.l1c.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu5.l1c.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu5.l1c.replacements 27880 # number of replacements -system.cpu5.l1c.sampled_refs 28223 # Sample count of references to valid blocks. +system.cpu5.l1c.replacements 28136 # number of replacements +system.cpu5.l1c.sampled_refs 28497 # Sample count of references to valid blocks. system.cpu5.l1c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu5.l1c.tagsinuse 348.223192 # Cycle average of tags in use -system.cpu5.l1c.total_refs 11787 # Total number of references to valid blocks. +system.cpu5.l1c.tagsinuse 345.800641 # Cycle average of tags in use +system.cpu5.l1c.total_refs 11716 # Total number of references to valid blocks. system.cpu5.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu5.l1c.writebacks 11039 # number of writebacks +system.cpu5.l1c.writebacks 11040 # number of writebacks system.cpu5.num_copies 0 # number of copy accesses completed system.cpu5.num_reads 100000 # number of read accesses completed -system.cpu5.num_writes 53951 # number of write accesses completed -system.cpu6.l1c.ReadReq_accesses 44452 # number of ReadReq accesses(hits+misses) -system.cpu6.l1c.ReadReq_avg_miss_latency 23599.078540 # average ReadReq miss latency -system.cpu6.l1c.ReadReq_avg_mshr_miss_latency 22597.239994 # average ReadReq mshr miss latency +system.cpu5.num_writes 53687 # number of write accesses completed +system.cpu6.l1c.ReadReq_accesses 45027 # number of ReadReq accesses(hits+misses) +system.cpu6.l1c.ReadReq_avg_miss_latency 16617.118087 # average ReadReq miss latency +system.cpu6.l1c.ReadReq_avg_mshr_miss_latency 15615.219316 # average ReadReq mshr miss latency system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.cpu6.l1c.ReadReq_hits 7401 # number of ReadReq hits -system.cpu6.l1c.ReadReq_miss_latency 874369459 # number of ReadReq miss cycles -system.cpu6.l1c.ReadReq_miss_rate 0.833506 # miss rate for ReadReq accesses -system.cpu6.l1c.ReadReq_misses 37051 # number of ReadReq misses -system.cpu6.l1c.ReadReq_mshr_miss_latency 837250339 # number of ReadReq MSHR miss cycles -system.cpu6.l1c.ReadReq_mshr_miss_rate 0.833506 # mshr miss rate for ReadReq accesses -system.cpu6.l1c.ReadReq_mshr_misses 37051 # number of ReadReq MSHR misses -system.cpu6.l1c.ReadReq_mshr_uncacheable_latency 468398074 # number of ReadReq MSHR uncacheable cycles -system.cpu6.l1c.WriteReq_accesses 24180 # number of WriteReq accesses(hits+misses) -system.cpu6.l1c.WriteReq_avg_miss_latency 28689.725113 # average WriteReq miss latency -system.cpu6.l1c.WriteReq_avg_mshr_miss_latency 27687.897435 # average WriteReq mshr miss latency +system.cpu6.l1c.ReadReq_hits 7597 # number of ReadReq hits +system.cpu6.l1c.ReadReq_miss_latency 621978730 # number of ReadReq miss cycles +system.cpu6.l1c.ReadReq_miss_rate 0.831279 # miss rate for ReadReq accesses +system.cpu6.l1c.ReadReq_misses 37430 # number of ReadReq misses +system.cpu6.l1c.ReadReq_mshr_miss_latency 584477659 # number of ReadReq MSHR miss cycles +system.cpu6.l1c.ReadReq_mshr_miss_rate 0.831279 # mshr miss rate for ReadReq accesses +system.cpu6.l1c.ReadReq_mshr_misses 37430 # number of ReadReq MSHR misses +system.cpu6.l1c.ReadReq_mshr_uncacheable_latency 320096620 # number of ReadReq MSHR uncacheable cycles +system.cpu6.l1c.WriteReq_accesses 23941 # number of WriteReq accesses(hits+misses) +system.cpu6.l1c.WriteReq_avg_miss_latency 20221.380036 # average WriteReq miss latency +system.cpu6.l1c.WriteReq_avg_mshr_miss_latency 19219.637304 # average WriteReq mshr miss latency system.cpu6.l1c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency -system.cpu6.l1c.WriteReq_hits 985 # number of WriteReq hits -system.cpu6.l1c.WriteReq_miss_latency 665458174 # number of WriteReq miss cycles -system.cpu6.l1c.WriteReq_miss_rate 0.959264 # miss rate for WriteReq accesses -system.cpu6.l1c.WriteReq_misses 23195 # number of WriteReq misses -system.cpu6.l1c.WriteReq_mshr_miss_latency 642220781 # number of WriteReq MSHR miss cycles -system.cpu6.l1c.WriteReq_mshr_miss_rate 0.959264 # mshr miss rate for WriteReq accesses -system.cpu6.l1c.WriteReq_mshr_misses 23195 # number of WriteReq MSHR misses -system.cpu6.l1c.WriteReq_mshr_uncacheable_latency 283288804 # number of WriteReq MSHR uncacheable cycles -system.cpu6.l1c.avg_blocked_cycles_no_mshrs 2306.135407 # average number of cycles each access was blocked +system.cpu6.l1c.WriteReq_hits 930 # number of WriteReq hits +system.cpu6.l1c.WriteReq_miss_latency 465314176 # number of WriteReq miss cycles +system.cpu6.l1c.WriteReq_miss_rate 0.961155 # miss rate for WriteReq accesses +system.cpu6.l1c.WriteReq_misses 23011 # number of WriteReq misses +system.cpu6.l1c.WriteReq_mshr_miss_latency 442263074 # number of WriteReq MSHR miss cycles +system.cpu6.l1c.WriteReq_mshr_miss_rate 0.961155 # mshr miss rate for WriteReq accesses +system.cpu6.l1c.WriteReq_mshr_misses 23011 # number of WriteReq MSHR misses +system.cpu6.l1c.WriteReq_mshr_uncacheable_latency 197754604 # number of WriteReq MSHR uncacheable cycles +system.cpu6.l1c.avg_blocked_cycles_no_mshrs 1586.699742 # average number of cycles each access was blocked system.cpu6.l1c.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu6.l1c.avg_refs 0.410866 # Average number of references to valid blocks. -system.cpu6.l1c.blocked_no_mshrs 69302 # number of cycles access was blocked +system.cpu6.l1c.avg_refs 0.414524 # Average number of references to valid blocks. +system.cpu6.l1c.blocked_no_mshrs 70023 # number of cycles access was blocked system.cpu6.l1c.blocked_no_targets 0 # number of cycles access was blocked -system.cpu6.l1c.blocked_cycles_no_mshrs 159819796 # number of cycles access was blocked +system.cpu6.l1c.blocked_cycles_no_mshrs 111105476 # number of cycles access was blocked system.cpu6.l1c.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu6.l1c.cache_copies 0 # number of cache copies performed -system.cpu6.l1c.demand_accesses 68632 # number of demand (read+write) accesses -system.cpu6.l1c.demand_avg_miss_latency 25559.001975 # average overall miss latency -system.cpu6.l1c.demand_avg_mshr_miss_latency 24557.167613 # average overall mshr miss latency -system.cpu6.l1c.demand_hits 8386 # number of demand (read+write) hits -system.cpu6.l1c.demand_miss_latency 1539827633 # number of demand (read+write) miss cycles -system.cpu6.l1c.demand_miss_rate 0.877812 # miss rate for demand accesses -system.cpu6.l1c.demand_misses 60246 # number of demand (read+write) misses +system.cpu6.l1c.demand_accesses 68968 # number of demand (read+write) accesses +system.cpu6.l1c.demand_avg_miss_latency 17989.326881 # average overall miss latency +system.cpu6.l1c.demand_avg_mshr_miss_latency 16987.487517 # average overall mshr miss latency +system.cpu6.l1c.demand_hits 8527 # number of demand (read+write) hits +system.cpu6.l1c.demand_miss_latency 1087292906 # number of demand (read+write) miss cycles +system.cpu6.l1c.demand_miss_rate 0.876363 # miss rate for demand accesses +system.cpu6.l1c.demand_misses 60441 # number of demand (read+write) misses system.cpu6.l1c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu6.l1c.demand_mshr_miss_latency 1479471120 # number of demand (read+write) MSHR miss cycles -system.cpu6.l1c.demand_mshr_miss_rate 0.877812 # mshr miss rate for demand accesses -system.cpu6.l1c.demand_mshr_misses 60246 # number of demand (read+write) MSHR misses +system.cpu6.l1c.demand_mshr_miss_latency 1026740733 # number of demand (read+write) MSHR miss cycles +system.cpu6.l1c.demand_mshr_miss_rate 0.876363 # mshr miss rate for demand accesses +system.cpu6.l1c.demand_mshr_misses 60441 # number of demand (read+write) MSHR misses system.cpu6.l1c.fast_writes 0 # number of fast writes performed system.cpu6.l1c.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu6.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu6.l1c.overall_accesses 68632 # number of overall (read+write) accesses -system.cpu6.l1c.overall_avg_miss_latency 25559.001975 # average overall miss latency -system.cpu6.l1c.overall_avg_mshr_miss_latency 24557.167613 # average overall mshr miss latency +system.cpu6.l1c.overall_accesses 68968 # number of overall (read+write) accesses +system.cpu6.l1c.overall_avg_miss_latency 17989.326881 # average overall miss latency +system.cpu6.l1c.overall_avg_mshr_miss_latency 16987.487517 # average overall mshr miss latency system.cpu6.l1c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.cpu6.l1c.overall_hits 8386 # number of overall hits -system.cpu6.l1c.overall_miss_latency 1539827633 # number of overall miss cycles -system.cpu6.l1c.overall_miss_rate 0.877812 # miss rate for overall accesses -system.cpu6.l1c.overall_misses 60246 # number of overall misses +system.cpu6.l1c.overall_hits 8527 # number of overall hits +system.cpu6.l1c.overall_miss_latency 1087292906 # number of overall miss cycles +system.cpu6.l1c.overall_miss_rate 0.876363 # miss rate for overall accesses +system.cpu6.l1c.overall_misses 60441 # number of overall misses system.cpu6.l1c.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu6.l1c.overall_mshr_miss_latency 1479471120 # number of overall MSHR miss cycles -system.cpu6.l1c.overall_mshr_miss_rate 0.877812 # mshr miss rate for overall accesses -system.cpu6.l1c.overall_mshr_misses 60246 # number of overall MSHR misses -system.cpu6.l1c.overall_mshr_uncacheable_latency 751686878 # number of overall MSHR uncacheable cycles +system.cpu6.l1c.overall_mshr_miss_latency 1026740733 # number of overall MSHR miss cycles +system.cpu6.l1c.overall_mshr_miss_rate 0.876363 # mshr miss rate for overall accesses +system.cpu6.l1c.overall_mshr_misses 60441 # number of overall MSHR misses +system.cpu6.l1c.overall_mshr_uncacheable_latency 517851224 # number of overall MSHR uncacheable cycles system.cpu6.l1c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu6.l1c.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache system.cpu6.l1c.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr @@ -549,75 +549,75 @@ system.cpu6.l1c.prefetcher.num_hwpf_issued 0 # system.cpu6.l1c.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu6.l1c.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu6.l1c.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu6.l1c.replacements 27468 # number of replacements -system.cpu6.l1c.sampled_refs 27829 # Sample count of references to valid blocks. +system.cpu6.l1c.replacements 27646 # number of replacements +system.cpu6.l1c.sampled_refs 27996 # Sample count of references to valid blocks. system.cpu6.l1c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu6.l1c.tagsinuse 345.245640 # Cycle average of tags in use -system.cpu6.l1c.total_refs 11434 # Total number of references to valid blocks. +system.cpu6.l1c.tagsinuse 344.481018 # Cycle average of tags in use +system.cpu6.l1c.total_refs 11605 # Total number of references to valid blocks. system.cpu6.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu6.l1c.writebacks 10779 # number of writebacks +system.cpu6.l1c.writebacks 10854 # number of writebacks system.cpu6.num_copies 0 # number of copy accesses completed -system.cpu6.num_reads 98631 # number of read accesses completed -system.cpu6.num_writes 53473 # number of write accesses completed -system.cpu7.l1c.ReadReq_accesses 45026 # number of ReadReq accesses(hits+misses) -system.cpu7.l1c.ReadReq_avg_miss_latency 23566.694007 # average ReadReq miss latency -system.cpu7.l1c.ReadReq_avg_mshr_miss_latency 22564.854082 # average ReadReq mshr miss latency +system.cpu6.num_reads 99885 # number of read accesses completed +system.cpu6.num_writes 53649 # number of write accesses completed +system.cpu7.l1c.ReadReq_accesses 44691 # number of ReadReq accesses(hits+misses) +system.cpu7.l1c.ReadReq_avg_miss_latency 16751.059693 # average ReadReq miss latency +system.cpu7.l1c.ReadReq_avg_mshr_miss_latency 15749.134660 # average ReadReq mshr miss latency system.cpu7.l1c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.cpu7.l1c.ReadReq_hits 7731 # number of ReadReq hits -system.cpu7.l1c.ReadReq_miss_latency 878919853 # number of ReadReq miss cycles -system.cpu7.l1c.ReadReq_miss_rate 0.828299 # miss rate for ReadReq accesses -system.cpu7.l1c.ReadReq_misses 37295 # number of ReadReq misses -system.cpu7.l1c.ReadReq_mshr_miss_latency 841556233 # number of ReadReq MSHR miss cycles -system.cpu7.l1c.ReadReq_mshr_miss_rate 0.828299 # mshr miss rate for ReadReq accesses -system.cpu7.l1c.ReadReq_mshr_misses 37295 # number of ReadReq MSHR misses -system.cpu7.l1c.ReadReq_mshr_uncacheable_latency 464511482 # number of ReadReq MSHR uncacheable cycles -system.cpu7.l1c.WriteReq_accesses 24312 # number of WriteReq accesses(hits+misses) -system.cpu7.l1c.WriteReq_avg_miss_latency 28334.071468 # average WriteReq miss latency -system.cpu7.l1c.WriteReq_avg_mshr_miss_latency 27332.156470 # average WriteReq mshr miss latency +system.cpu7.l1c.ReadReq_hits 7568 # number of ReadReq hits +system.cpu7.l1c.ReadReq_miss_latency 621849589 # number of ReadReq miss cycles +system.cpu7.l1c.ReadReq_miss_rate 0.830659 # miss rate for ReadReq accesses +system.cpu7.l1c.ReadReq_misses 37123 # number of ReadReq misses +system.cpu7.l1c.ReadReq_mshr_miss_latency 584655126 # number of ReadReq MSHR miss cycles +system.cpu7.l1c.ReadReq_mshr_miss_rate 0.830659 # mshr miss rate for ReadReq accesses +system.cpu7.l1c.ReadReq_mshr_misses 37123 # number of ReadReq MSHR misses +system.cpu7.l1c.ReadReq_mshr_uncacheable_latency 309541021 # number of ReadReq MSHR uncacheable cycles +system.cpu7.l1c.WriteReq_accesses 24304 # number of WriteReq accesses(hits+misses) +system.cpu7.l1c.WriteReq_avg_miss_latency 20320.041471 # average WriteReq miss latency +system.cpu7.l1c.WriteReq_avg_mshr_miss_latency 19318.250661 # average WriteReq mshr miss latency system.cpu7.l1c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency -system.cpu7.l1c.WriteReq_hits 889 # number of WriteReq hits -system.cpu7.l1c.WriteReq_miss_latency 663668956 # number of WriteReq miss cycles -system.cpu7.l1c.WriteReq_miss_rate 0.963434 # miss rate for WriteReq accesses -system.cpu7.l1c.WriteReq_misses 23423 # number of WriteReq misses -system.cpu7.l1c.WriteReq_mshr_miss_latency 640201101 # number of WriteReq MSHR miss cycles -system.cpu7.l1c.WriteReq_mshr_miss_rate 0.963434 # mshr miss rate for WriteReq accesses -system.cpu7.l1c.WriteReq_mshr_misses 23423 # number of WriteReq MSHR misses -system.cpu7.l1c.WriteReq_mshr_uncacheable_latency 287294687 # number of WriteReq MSHR uncacheable cycles -system.cpu7.l1c.avg_blocked_cycles_no_mshrs 2290.551288 # average number of cycles each access was blocked +system.cpu7.l1c.WriteReq_hits 866 # number of WriteReq hits +system.cpu7.l1c.WriteReq_miss_latency 476261132 # number of WriteReq miss cycles +system.cpu7.l1c.WriteReq_miss_rate 0.964368 # miss rate for WriteReq accesses +system.cpu7.l1c.WriteReq_misses 23438 # number of WriteReq misses +system.cpu7.l1c.WriteReq_mshr_miss_latency 452781159 # number of WriteReq MSHR miss cycles +system.cpu7.l1c.WriteReq_mshr_miss_rate 0.964368 # mshr miss rate for WriteReq accesses +system.cpu7.l1c.WriteReq_mshr_misses 23438 # number of WriteReq MSHR misses +system.cpu7.l1c.WriteReq_mshr_uncacheable_latency 195853343 # number of WriteReq MSHR uncacheable cycles +system.cpu7.l1c.avg_blocked_cycles_no_mshrs 1592.201934 # average number of cycles each access was blocked system.cpu7.l1c.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu7.l1c.avg_refs 0.413973 # Average number of references to valid blocks. -system.cpu7.l1c.blocked_no_mshrs 69548 # number of cycles access was blocked +system.cpu7.l1c.avg_refs 0.409635 # Average number of references to valid blocks. +system.cpu7.l1c.blocked_no_mshrs 69815 # number of cycles access was blocked system.cpu7.l1c.blocked_no_targets 0 # number of cycles access was blocked -system.cpu7.l1c.blocked_cycles_no_mshrs 159303261 # number of cycles access was blocked +system.cpu7.l1c.blocked_cycles_no_mshrs 111159578 # number of cycles access was blocked system.cpu7.l1c.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu7.l1c.cache_copies 0 # number of cache copies performed -system.cpu7.l1c.demand_accesses 69338 # number of demand (read+write) accesses -system.cpu7.l1c.demand_avg_miss_latency 25405.790853 # average overall miss latency -system.cpu7.l1c.demand_avg_mshr_miss_latency 24403.921967 # average overall mshr miss latency -system.cpu7.l1c.demand_hits 8620 # number of demand (read+write) hits -system.cpu7.l1c.demand_miss_latency 1542588809 # number of demand (read+write) miss cycles -system.cpu7.l1c.demand_miss_rate 0.875681 # miss rate for demand accesses -system.cpu7.l1c.demand_misses 60718 # number of demand (read+write) misses +system.cpu7.l1c.demand_accesses 68995 # number of demand (read+write) accesses +system.cpu7.l1c.demand_avg_miss_latency 18132.308268 # average overall miss latency +system.cpu7.l1c.demand_avg_mshr_miss_latency 17130.435181 # average overall mshr miss latency +system.cpu7.l1c.demand_hits 8434 # number of demand (read+write) hits +system.cpu7.l1c.demand_miss_latency 1098110721 # number of demand (read+write) miss cycles +system.cpu7.l1c.demand_miss_rate 0.877759 # miss rate for demand accesses +system.cpu7.l1c.demand_misses 60561 # number of demand (read+write) misses system.cpu7.l1c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu7.l1c.demand_mshr_miss_latency 1481757334 # number of demand (read+write) MSHR miss cycles -system.cpu7.l1c.demand_mshr_miss_rate 0.875681 # mshr miss rate for demand accesses -system.cpu7.l1c.demand_mshr_misses 60718 # number of demand (read+write) MSHR misses +system.cpu7.l1c.demand_mshr_miss_latency 1037436285 # number of demand (read+write) MSHR miss cycles +system.cpu7.l1c.demand_mshr_miss_rate 0.877759 # mshr miss rate for demand accesses +system.cpu7.l1c.demand_mshr_misses 60561 # number of demand (read+write) MSHR misses system.cpu7.l1c.fast_writes 0 # number of fast writes performed system.cpu7.l1c.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu7.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu7.l1c.overall_accesses 69338 # number of overall (read+write) accesses -system.cpu7.l1c.overall_avg_miss_latency 25405.790853 # average overall miss latency -system.cpu7.l1c.overall_avg_mshr_miss_latency 24403.921967 # average overall mshr miss latency +system.cpu7.l1c.overall_accesses 68995 # number of overall (read+write) accesses +system.cpu7.l1c.overall_avg_miss_latency 18132.308268 # average overall miss latency +system.cpu7.l1c.overall_avg_mshr_miss_latency 17130.435181 # average overall mshr miss latency system.cpu7.l1c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.cpu7.l1c.overall_hits 8620 # number of overall hits -system.cpu7.l1c.overall_miss_latency 1542588809 # number of overall miss cycles -system.cpu7.l1c.overall_miss_rate 0.875681 # miss rate for overall accesses -system.cpu7.l1c.overall_misses 60718 # number of overall misses +system.cpu7.l1c.overall_hits 8434 # number of overall hits +system.cpu7.l1c.overall_miss_latency 1098110721 # number of overall miss cycles +system.cpu7.l1c.overall_miss_rate 0.877759 # miss rate for overall accesses +system.cpu7.l1c.overall_misses 60561 # number of overall misses system.cpu7.l1c.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu7.l1c.overall_mshr_miss_latency 1481757334 # number of overall MSHR miss cycles -system.cpu7.l1c.overall_mshr_miss_rate 0.875681 # mshr miss rate for overall accesses -system.cpu7.l1c.overall_mshr_misses 60718 # number of overall MSHR misses -system.cpu7.l1c.overall_mshr_uncacheable_latency 751806169 # number of overall MSHR uncacheable cycles +system.cpu7.l1c.overall_mshr_miss_latency 1037436285 # number of overall MSHR miss cycles +system.cpu7.l1c.overall_mshr_miss_rate 0.877759 # mshr miss rate for overall accesses +system.cpu7.l1c.overall_mshr_misses 60561 # number of overall MSHR misses +system.cpu7.l1c.overall_mshr_uncacheable_latency 505394364 # number of overall MSHR uncacheable cycles system.cpu7.l1c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu7.l1c.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache system.cpu7.l1c.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr @@ -628,91 +628,88 @@ system.cpu7.l1c.prefetcher.num_hwpf_issued 0 # system.cpu7.l1c.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu7.l1c.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu7.l1c.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu7.l1c.replacements 27895 # number of replacements -system.cpu7.l1c.sampled_refs 28241 # Sample count of references to valid blocks. +system.cpu7.l1c.replacements 27888 # number of replacements +system.cpu7.l1c.sampled_refs 28230 # Sample count of references to valid blocks. system.cpu7.l1c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu7.l1c.tagsinuse 346.417041 # Cycle average of tags in use -system.cpu7.l1c.total_refs 11691 # Total number of references to valid blocks. +system.cpu7.l1c.tagsinuse 344.969892 # Cycle average of tags in use +system.cpu7.l1c.total_refs 11564 # Total number of references to valid blocks. system.cpu7.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu7.l1c.writebacks 10935 # number of writebacks +system.cpu7.l1c.writebacks 10925 # number of writebacks system.cpu7.num_copies 0 # number of copy accesses completed -system.cpu7.num_reads 99923 # number of read accesses completed -system.cpu7.num_writes 53956 # number of write accesses completed -system.l2c.ReadExReq_accesses 74537 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_avg_miss_latency 20115.263386 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency 10011.845848 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_miss_latency 1499331387 # number of ReadExReq miss cycles +system.cpu7.num_reads 99393 # number of read accesses completed +system.cpu7.num_writes 53943 # number of write accesses completed +system.l2c.ReadExReq_accesses 74841 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_avg_miss_latency 20077.258829 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency 10005.440708 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_miss_latency 1502602128 # number of ReadExReq miss cycles system.l2c.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_misses 74537 # number of ReadExReq misses -system.l2c.ReadExReq_mshr_hits 461 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_miss_latency 746252954 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_misses 74841 # number of ReadExReq misses +system.l2c.ReadExReq_mshr_hits 333 # number of ReadExReq MSHR hits +system.l2c.ReadExReq_mshr_miss_latency 748817188 # number of ReadExReq MSHR miss cycles system.l2c.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_misses 74537 # number of ReadExReq MSHR misses -system.l2c.ReadReq_accesses 137370 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_avg_miss_latency 20204.368124 # average ReadReq miss latency -system.l2c.ReadReq_avg_mshr_miss_latency 10010.792670 # average ReadReq mshr miss latency +system.l2c.ReadExReq_mshr_misses 74841 # number of ReadExReq MSHR misses +system.l2c.ReadReq_accesses 137840 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_avg_miss_latency 20218.016376 # average ReadReq miss latency +system.l2c.ReadReq_avg_mshr_miss_latency 10005.490618 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_hits 62417 # number of ReadReq hits -system.l2c.ReadReq_miss_latency 1514378004 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_rate 0.545629 # miss rate for ReadReq accesses -system.l2c.ReadReq_misses 74953 # number of ReadReq misses -system.l2c.ReadReq_mshr_hits 884 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_miss_latency 750338943 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_rate 0.545629 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_misses 74953 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_uncacheable_latency 791888060 # number of ReadReq MSHR uncacheable cycles -system.l2c.UpgradeReq_accesses 18325 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_avg_miss_latency 10129.887094 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency 10011.324093 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_miss_latency 185630181 # number of UpgradeReq miss cycles +system.l2c.ReadReq_hits 90514 # number of ReadReq hits +system.l2c.ReadReq_miss_latency 956837843 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_rate 0.343340 # miss rate for ReadReq accesses +system.l2c.ReadReq_misses 47326 # number of ReadReq misses +system.l2c.ReadReq_mshr_hits 619 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_miss_latency 473519849 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_rate 0.343340 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_misses 47326 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_uncacheable_latency 791100325 # number of ReadReq MSHR uncacheable cycles +system.l2c.UpgradeReq_accesses 18299 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_avg_miss_latency 11082.248210 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency 10005.327832 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_miss_latency 202794060 # number of UpgradeReq miss cycles system.l2c.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_misses 18325 # number of UpgradeReq misses -system.l2c.UpgradeReq_mshr_hits 24 # number of UpgradeReq MSHR hits -system.l2c.UpgradeReq_mshr_miss_latency 183457514 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_misses 18299 # number of UpgradeReq misses +system.l2c.UpgradeReq_mshr_hits 30 # number of UpgradeReq MSHR hits +system.l2c.UpgradeReq_mshr_miss_latency 183087494 # number of UpgradeReq MSHR miss cycles system.l2c.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_misses 18325 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses 18299 # number of UpgradeReq MSHR misses system.l2c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_mshr_uncacheable_latency 429360910 # number of WriteReq MSHR uncacheable cycles -system.l2c.Writeback_accesses 86629 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_miss_rate 1 # miss rate for Writeback accesses -system.l2c.Writeback_misses 86629 # number of Writeback misses -system.l2c.Writeback_mshr_miss_rate 1 # mshr miss rate for Writeback accesses -system.l2c.Writeback_mshr_misses 86629 # number of Writeback MSHR misses +system.l2c.WriteReq_mshr_uncacheable_latency 429380546 # number of WriteReq MSHR uncacheable cycles +system.l2c.Writeback_accesses 86810 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_hits 86810 # number of Writeback hits system.l2c.avg_blocked_cycles_no_mshrs 2919.500000 # average number of cycles each access was blocked system.l2c.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.l2c.avg_refs 3.325063 # Average number of references to valid blocks. +system.l2c.avg_refs 2.008302 # Average number of references to valid blocks. system.l2c.blocked_no_mshrs 6 # number of cycles access was blocked system.l2c.blocked_no_targets 0 # number of cycles access was blocked system.l2c.blocked_cycles_no_mshrs 17517 # number of cycles access was blocked system.l2c.blocked_cycles_no_targets 0 # number of cycles access was blocked system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.demand_accesses 211907 # number of demand (read+write) accesses -system.l2c.demand_avg_miss_latency 20159.939735 # average overall miss latency -system.l2c.demand_avg_mshr_miss_latency 10011.317794 # average overall mshr miss latency -system.l2c.demand_hits 62417 # number of demand (read+write) hits -system.l2c.demand_miss_latency 3013709391 # number of demand (read+write) miss cycles -system.l2c.demand_miss_rate 0.705451 # miss rate for demand accesses -system.l2c.demand_misses 149490 # number of demand (read+write) misses -system.l2c.demand_mshr_hits 1345 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_miss_latency 1496591897 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_rate 0.705451 # mshr miss rate for demand accesses -system.l2c.demand_mshr_misses 149490 # number of demand (read+write) MSHR misses +system.l2c.demand_accesses 212681 # number of demand (read+write) accesses +system.l2c.demand_avg_miss_latency 20131.786579 # average overall miss latency +system.l2c.demand_avg_mshr_miss_latency 10005.460042 # average overall mshr miss latency +system.l2c.demand_hits 90514 # number of demand (read+write) hits +system.l2c.demand_miss_latency 2459439971 # number of demand (read+write) miss cycles +system.l2c.demand_miss_rate 0.574414 # miss rate for demand accesses +system.l2c.demand_misses 122167 # number of demand (read+write) misses +system.l2c.demand_mshr_hits 952 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_miss_latency 1222337037 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_rate 0.574414 # mshr miss rate for demand accesses +system.l2c.demand_mshr_misses 122167 # number of demand (read+write) MSHR misses system.l2c.fast_writes 0 # number of fast writes performed system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.overall_accesses 211907 # number of overall (read+write) accesses -system.l2c.overall_avg_miss_latency 20159.939735 # average overall miss latency -system.l2c.overall_avg_mshr_miss_latency 10011.317794 # average overall mshr miss latency +system.l2c.overall_accesses 212681 # number of overall (read+write) accesses +system.l2c.overall_avg_miss_latency 20131.786579 # average overall miss latency +system.l2c.overall_avg_mshr_miss_latency 10005.460042 # average overall mshr miss latency system.l2c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.l2c.overall_hits 62417 # number of overall hits -system.l2c.overall_miss_latency 3013709391 # number of overall miss cycles -system.l2c.overall_miss_rate 0.705451 # miss rate for overall accesses -system.l2c.overall_misses 149490 # number of overall misses -system.l2c.overall_mshr_hits 1345 # number of overall MSHR hits -system.l2c.overall_mshr_miss_latency 1496591897 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_rate 0.705451 # mshr miss rate for overall accesses -system.l2c.overall_mshr_misses 149490 # number of overall MSHR misses -system.l2c.overall_mshr_uncacheable_latency 1221248970 # number of overall MSHR uncacheable cycles +system.l2c.overall_hits 90514 # number of overall hits +system.l2c.overall_miss_latency 2459439971 # number of overall miss cycles +system.l2c.overall_miss_rate 0.574414 # miss rate for overall accesses +system.l2c.overall_misses 122167 # number of overall misses +system.l2c.overall_mshr_hits 952 # number of overall MSHR hits +system.l2c.overall_mshr_miss_latency 1222337037 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_rate 0.574414 # mshr miss rate for overall accesses +system.l2c.overall_mshr_misses 122167 # number of overall MSHR misses +system.l2c.overall_mshr_uncacheable_latency 1220480871 # number of overall MSHR uncacheable cycles system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.l2c.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache system.l2c.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr @@ -723,12 +720,12 @@ system.l2c.prefetcher.num_hwpf_issued 0 # nu system.l2c.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.l2c.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.l2c.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.l2c.replacements 30719 # number of replacements -system.l2c.sampled_refs 31154 # Sample count of references to valid blocks. +system.l2c.replacements 73609 # number of replacements +system.l2c.sampled_refs 74198 # Sample count of references to valid blocks. system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.l2c.tagsinuse 460.327226 # Cycle average of tags in use -system.l2c.total_refs 103589 # Total number of references to valid blocks. +system.l2c.tagsinuse 631.450089 # Cycle average of tags in use +system.l2c.total_refs 149012 # Total number of references to valid blocks. system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.writebacks 0 # number of writebacks +system.l2c.writebacks 47009 # number of writebacks ---------- End Simulation Statistics ---------- diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest/stderr b/tests/quick/50.memtest/ref/alpha/linux/memtest/stderr index 6aaad2045..6e067280a 100644 --- a/tests/quick/50.memtest/ref/alpha/linux/memtest/stderr +++ b/tests/quick/50.memtest/ref/alpha/linux/memtest/stderr @@ -1,74 +1,74 @@ warn: Entering event queue @ 0. Starting simulation... -system.cpu7: completed 10000 read accesses @15573567 -system.cpu3: completed 10000 read accesses @15845087 -system.cpu6: completed 10000 read accesses @15845510 -system.cpu2: completed 10000 read accesses @15899346 -system.cpu0: completed 10000 read accesses @15988699 -system.cpu5: completed 10000 read accesses @15997024 -system.cpu1: completed 10000 read accesses @16210356 -system.cpu4: completed 10000 read accesses @16435221 -system.cpu7: completed 20000 read accesses @31796453 -system.cpu2: completed 20000 read accesses @32128661 -system.cpu5: completed 20000 read accesses @32234396 -system.cpu6: completed 20000 read accesses @32294014 -system.cpu0: completed 20000 read accesses @32471317 -system.cpu3: completed 20000 read accesses @32570615 -system.cpu1: completed 20000 read accesses @32640091 -system.cpu4: completed 20000 read accesses @32877562 -system.cpu5: completed 30000 read accesses @48207622 -system.cpu2: completed 30000 read accesses @48440845 -system.cpu7: completed 30000 read accesses @48459290 -system.cpu3: completed 30000 read accesses @48710826 -system.cpu0: completed 30000 read accesses @48923796 -system.cpu1: completed 30000 read accesses @48961602 -system.cpu6: completed 30000 read accesses @49000253 -system.cpu4: completed 30000 read accesses @49456834 -system.cpu5: completed 40000 read accesses @64830509 -system.cpu7: completed 40000 read accesses @64831406 -system.cpu2: completed 40000 read accesses @64990686 -system.cpu0: completed 40000 read accesses @65126336 -system.cpu3: completed 40000 read accesses @65216672 -system.cpu1: completed 40000 read accesses @65233718 -system.cpu6: completed 40000 read accesses @65544034 -system.cpu4: completed 40000 read accesses @65878034 -system.cpu5: completed 50000 read accesses @81060957 -system.cpu7: completed 50000 read accesses @81212197 -system.cpu2: completed 50000 read accesses @81437704 -system.cpu3: completed 50000 read accesses @81544353 -system.cpu0: completed 50000 read accesses @81653617 -system.cpu4: completed 50000 read accesses @81787398 -system.cpu1: completed 50000 read accesses @81868780 -system.cpu6: completed 50000 read accesses @82227342 -system.cpu7: completed 60000 read accesses @97291732 -system.cpu5: completed 60000 read accesses @97361345 -system.cpu2: completed 60000 read accesses @97621191 -system.cpu3: completed 60000 read accesses @97673986 -system.cpu1: completed 60000 read accesses @97950396 -system.cpu0: completed 60000 read accesses @98086520 -system.cpu4: completed 60000 read accesses @98139060 -system.cpu6: completed 60000 read accesses @98866267 -system.cpu7: completed 70000 read accesses @113775234 -system.cpu5: completed 70000 read accesses @114027734 -system.cpu3: completed 70000 read accesses @114107654 -system.cpu2: completed 70000 read accesses @114287447 -system.cpu1: completed 70000 read accesses @114429712 -system.cpu0: completed 70000 read accesses @114626666 -system.cpu4: completed 70000 read accesses @115046863 -system.cpu6: completed 70000 read accesses @115625699 -system.cpu7: completed 80000 read accesses @130114471 -system.cpu5: completed 80000 read accesses @130239115 -system.cpu3: completed 80000 read accesses @130679996 -system.cpu1: completed 80000 read accesses @130860729 -system.cpu0: completed 80000 read accesses @131170286 -system.cpu2: completed 80000 read accesses @131219347 -system.cpu4: completed 80000 read accesses @131694972 -system.cpu6: completed 80000 read accesses @132127278 -system.cpu7: completed 90000 read accesses @146355152 -system.cpu5: completed 90000 read accesses @146631518 -system.cpu3: completed 90000 read accesses @146856424 -system.cpu1: completed 90000 read accesses @147217275 -system.cpu0: completed 90000 read accesses @147658368 -system.cpu2: completed 90000 read accesses @147775118 -system.cpu4: completed 90000 read accesses @148157312 -system.cpu6: completed 90000 read accesses @148500053 -system.cpu5: completed 100000 read accesses @162969030 +system.cpu2: completed 10000 read accesses @10737200 +system.cpu5: completed 10000 read accesses @10933125 +system.cpu6: completed 10000 read accesses @10968295 +system.cpu4: completed 10000 read accesses @11004110 +system.cpu0: completed 10000 read accesses @11034624 +system.cpu1: completed 10000 read accesses @11079796 +system.cpu7: completed 10000 read accesses @11098893 +system.cpu3: completed 10000 read accesses @11305149 +system.cpu5: completed 20000 read accesses @22247478 +system.cpu0: completed 20000 read accesses @22286441 +system.cpu2: completed 20000 read accesses @22412370 +system.cpu6: completed 20000 read accesses @22412546 +system.cpu7: completed 20000 read accesses @22443360 +system.cpu4: completed 20000 read accesses @22571774 +system.cpu3: completed 20000 read accesses @22684521 +system.cpu1: completed 20000 read accesses @22854803 +system.cpu6: completed 30000 read accesses @33383823 +system.cpu5: completed 30000 read accesses @33433409 +system.cpu2: completed 30000 read accesses @33567039 +system.cpu0: completed 30000 read accesses @33772397 +system.cpu7: completed 30000 read accesses @33863963 +system.cpu4: completed 30000 read accesses @34085859 +system.cpu1: completed 30000 read accesses @34145159 +system.cpu3: completed 30000 read accesses @34287598 +system.cpu5: completed 40000 read accesses @44537930 +system.cpu6: completed 40000 read accesses @44682656 +system.cpu2: completed 40000 read accesses @45063291 +system.cpu7: completed 40000 read accesses @45207960 +system.cpu4: completed 40000 read accesses @45307242 +system.cpu0: completed 40000 read accesses @45322044 +system.cpu1: completed 40000 read accesses @45703462 +system.cpu3: completed 40000 read accesses @45764765 +system.cpu5: completed 50000 read accesses @55736175 +system.cpu6: completed 50000 read accesses @55796558 +system.cpu2: completed 50000 read accesses @56140676 +system.cpu7: completed 50000 read accesses @56614131 +system.cpu1: completed 50000 read accesses @56649016 +system.cpu0: completed 50000 read accesses @56658259 +system.cpu4: completed 50000 read accesses @56697374 +system.cpu3: completed 50000 read accesses @56853901 +system.cpu5: completed 60000 read accesses @66922971 +system.cpu6: completed 60000 read accesses @67166318 +system.cpu2: completed 60000 read accesses @67391190 +system.cpu4: completed 60000 read accesses @67879872 +system.cpu1: completed 60000 read accesses @67932570 +system.cpu7: completed 60000 read accesses @68061664 +system.cpu0: completed 60000 read accesses @68084935 +system.cpu3: completed 60000 read accesses @68091555 +system.cpu6: completed 70000 read accesses @78400269 +system.cpu5: completed 70000 read accesses @78438516 +system.cpu2: completed 70000 read accesses @78758205 +system.cpu3: completed 70000 read accesses @79263647 +system.cpu4: completed 70000 read accesses @79315746 +system.cpu7: completed 70000 read accesses @79346909 +system.cpu0: completed 70000 read accesses @79354333 +system.cpu1: completed 70000 read accesses @79387143 +system.cpu5: completed 80000 read accesses @89714934 +system.cpu6: completed 80000 read accesses @89763887 +system.cpu2: completed 80000 read accesses @90325410 +system.cpu7: completed 80000 read accesses @90552338 +system.cpu4: completed 80000 read accesses @90699585 +system.cpu1: completed 80000 read accesses @90703570 +system.cpu3: completed 80000 read accesses @90734586 +system.cpu0: completed 80000 read accesses @90833170 +system.cpu5: completed 90000 read accesses @100989582 +system.cpu6: completed 90000 read accesses @101209540 +system.cpu7: completed 90000 read accesses @101654330 +system.cpu2: completed 90000 read accesses @101680284 +system.cpu1: completed 90000 read accesses @101964609 +system.cpu3: completed 90000 read accesses @101974763 +system.cpu0: completed 90000 read accesses @102286151 +system.cpu4: completed 90000 read accesses @102328481 +system.cpu5: completed 100000 read accesses @112555067 diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest/stdout b/tests/quick/50.memtest/ref/alpha/linux/memtest/stdout index a0a2b76f8..9edc3918b 100644 --- a/tests/quick/50.memtest/ref/alpha/linux/memtest/stdout +++ b/tests/quick/50.memtest/ref/alpha/linux/memtest/stdout @@ -5,9 +5,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Jan 2 2008 15:26:07 -M5 started Wed Jan 2 15:26:09 2008 -M5 executing on vm1 +M5 compiled Feb 13 2008 00:33:15 +M5 started Wed Feb 13 00:34:33 2008 +M5 executing on zizzer command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/50.memtest/alpha/linux/memtest tests/run.py quick/50.memtest/alpha/linux/memtest Global frequency set at 1000000000000 ticks per second -Exiting @ tick 162969030 because maximum number of loads reached +Exiting @ tick 112555067 because maximum number of loads reached |