diff options
Diffstat (limited to 'tests/quick/50.memtest')
4 files changed, 450 insertions, 444 deletions
diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/ruby.stats b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/ruby.stats index b919c5ac9..824e957e9 100644 --- a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/ruby.stats +++ b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/ruby.stats @@ -15,17 +15,19 @@ DMA_Controller config: DMAController_0 buffer_size: 32 dma_sequencer: DMASequencer_0 number_of_TBEs: 256 + recycle_latency: 10 + request_latency: 6 transitions_per_cycle: 32 Directory_Controller config: DirectoryController_0 version: 0 buffer_size: 32 directory_latency: 6 directory_name: DirectoryMemory_0 + dma_select_low_bit: 6 + dma_select_num_bits: 0 memory_controller_name: MemoryControl_0 - memory_latency: 158 number_of_TBEs: 256 recycle_latency: 10 - to_mem_ctrl_latency: 1 transitions_per_cycle: 32 L1Cache_Controller config: L1CacheController_0 version: 0 @@ -34,6 +36,7 @@ L1Cache_Controller config: L1CacheController_0 cache_response_latency: 12 issue_latency: 2 number_of_TBEs: 256 + recycle_latency: 10 sequencer: Sequencer_0 transitions_per_cycle: 32 L1Cache_Controller config: L1CacheController_1 @@ -43,6 +46,7 @@ L1Cache_Controller config: L1CacheController_1 cache_response_latency: 12 issue_latency: 2 number_of_TBEs: 256 + recycle_latency: 10 sequencer: Sequencer_1 transitions_per_cycle: 32 L1Cache_Controller config: L1CacheController_2 @@ -52,6 +56,7 @@ L1Cache_Controller config: L1CacheController_2 cache_response_latency: 12 issue_latency: 2 number_of_TBEs: 256 + recycle_latency: 10 sequencer: Sequencer_2 transitions_per_cycle: 32 L1Cache_Controller config: L1CacheController_3 @@ -61,6 +66,7 @@ L1Cache_Controller config: L1CacheController_3 cache_response_latency: 12 issue_latency: 2 number_of_TBEs: 256 + recycle_latency: 10 sequencer: Sequencer_3 transitions_per_cycle: 32 L1Cache_Controller config: L1CacheController_4 @@ -70,6 +76,7 @@ L1Cache_Controller config: L1CacheController_4 cache_response_latency: 12 issue_latency: 2 number_of_TBEs: 256 + recycle_latency: 10 sequencer: Sequencer_4 transitions_per_cycle: 32 L1Cache_Controller config: L1CacheController_5 @@ -79,6 +86,7 @@ L1Cache_Controller config: L1CacheController_5 cache_response_latency: 12 issue_latency: 2 number_of_TBEs: 256 + recycle_latency: 10 sequencer: Sequencer_5 transitions_per_cycle: 32 L1Cache_Controller config: L1CacheController_6 @@ -88,6 +96,7 @@ L1Cache_Controller config: L1CacheController_6 cache_response_latency: 12 issue_latency: 2 number_of_TBEs: 256 + recycle_latency: 10 sequencer: Sequencer_6 transitions_per_cycle: 32 L1Cache_Controller config: L1CacheController_7 @@ -97,6 +106,7 @@ L1Cache_Controller config: L1CacheController_7 cache_response_latency: 12 issue_latency: 2 number_of_TBEs: 256 + recycle_latency: 10 sequencer: Sequencer_7 transitions_per_cycle: 32 Cache config: l1u_0 @@ -376,34 +386,34 @@ periodic_stats_period: 1000000 ================ End RubySystem Configuration Print ================ -Real time: Aug/07/2009 12:01:26 +Real time: Aug/05/2009 14:05:27 Profiler Stats -------------- -Elapsed_time_in_seconds: 3347 -Elapsed_time_in_minutes: 55.7833 -Elapsed_time_in_hours: 0.929722 -Elapsed_time_in_days: 0.0387384 +Elapsed_time_in_seconds: 1657 +Elapsed_time_in_minutes: 27.6167 +Elapsed_time_in_hours: 0.460278 +Elapsed_time_in_days: 0.0191782 -Virtual_time_in_seconds: 3329.08 -Virtual_time_in_minutes: 55.4847 -Virtual_time_in_hours: 0.924744 -Virtual_time_in_days: 0.038531 +Virtual_time_in_seconds: 1574.85 +Virtual_time_in_minutes: 26.2475 +Virtual_time_in_hours: 0.437458 +Virtual_time_in_days: 0.0182274 -Ruby_current_time: 31633981 +Ruby_current_time: 31871403 Ruby_start_time: 1 -Ruby_cycles: 31633980 +Ruby_cycles: 31871402 -mbytes_resident: 151.66 -mbytes_total: 151.863 -resident_ratio: 0.998688 +mbytes_resident: 150.73 +mbytes_total: 1502.58 +resident_ratio: 0.10032 Total_misses: 0 total_misses: 0 [ 0 0 0 0 0 0 0 0 ] user_misses: 0 [ 0 0 0 0 0 0 0 0 ] supervisor_misses: 0 [ 0 0 0 0 0 0 0 0 ] -ruby_cycles_executed: 253071848 [ 31633981 31633981 31633981 31633981 31633981 31633981 31633981 31633981 ] +ruby_cycles_executed: 254971224 [ 31871403 31871403 31871403 31871403 31871403 31871403 31871403 31871403 ] transactions_started: 0 [ 0 0 0 0 0 0 0 0 ] transactions_ended: 0 [ 0 0 0 0 0 0 0 0 ] @@ -412,40 +422,40 @@ misses_per_transaction: 0 [ 0 0 0 0 0 0 0 0 ] Memory control MemoryControl_0: - memory_total_requests: 1381183 - memory_reads: 690629 - memory_writes: 690370 - memory_refreshes: 65905 - memory_total_request_delays: 425134489 - memory_delays_per_request: 307.805 - memory_delays_in_input_queue: 85388326 - memory_delays_behind_head_of_bank_queue: 259618821 - memory_delays_stalled_at_head_of_bank_queue: 80127342 - memory_stalls_for_bank_busy: 12107712 + memory_total_requests: 1389969 + memory_reads: 695049 + memory_writes: 694795 + memory_refreshes: 66399 + memory_total_request_delays: 426018769 + memory_delays_per_request: 306.495 + memory_delays_in_input_queue: 90894877 + memory_delays_behind_head_of_bank_queue: 255108229 + memory_delays_stalled_at_head_of_bank_queue: 80015663 + memory_stalls_for_bank_busy: 12108953 memory_stalls_for_random_busy: 0 - memory_stalls_for_anti_starvation: 24583282 - memory_stalls_for_arbitration: 15571597 - memory_stalls_for_bus: 20455254 + memory_stalls_for_anti_starvation: 24487499 + memory_stalls_for_arbitration: 15539710 + memory_stalls_for_bus: 20434932 memory_stalls_for_tfaw: 0 - memory_stalls_for_read_write_turnaround: 5974044 - memory_stalls_for_read_read_turnaround: 1435453 - accesses_per_bank: 43198 43576 43674 43623 43552 43499 43522 43400 43189 43089 43029 43295 43259 42950 42944 43270 43014 42965 42891 43226 43304 43241 42901 42927 43003 43106 43026 42962 43021 42658 43000 42869 + memory_stalls_for_read_write_turnaround: 6003845 + memory_stalls_for_read_read_turnaround: 1440724 + accesses_per_bank: 43357 44015 43781 43810 43753 43615 43533 43621 43760 43473 43392 43592 43408 43516 43431 43583 43408 43238 43387 43265 43461 43404 43268 43371 43341 43146 43143 43177 43023 43329 42971 43397 Busy Controller Counts: -L1Cache-0:0 L1Cache-1:0 L1Cache-2:0 L1Cache-3:0 L1Cache-4:0 L1Cache-5:0 L1Cache-6:1 L1Cache-7:0 +L1Cache-0:0 L1Cache-1:0 L1Cache-2:0 L1Cache-3:0 L1Cache-4:0 L1Cache-5:0 L1Cache-6:0 L1Cache-7:2 Directory-0:0 DMA-0:0 Busy Bank Count:0 -sequencer_requests_outstanding: [binsize: 1 max: 16 count: 743833 average: 11.8447 | standard deviation: 3.39349 | 0 943 2667 5349 9593 15307 22977 32917 43740 53757 62743 69014 72318 72533 69768 66143 144064 ] +sequencer_requests_outstanding: [binsize: 1 max: 16 count: 749091 average: 11.7606 | standard deviation: 3.43055 | 0 1195 3094 5987 10211 16213 24379 33889 44818 55183 63828 70245 72985 71727 68120 64568 142649 ] All Non-Zero Cycle Demand Cache Accesses ---------------------------------------- -miss_latency: [binsize: 128 max: 21269 count: 743718 average: 3882.73 | standard deviation: 2361.17 | 20935 1943 3780 6806 8904 8370 7627 8570 10319 12006 13483 13514 11790 13310 16096 16962 16002 15761 17003 16692 16533 17939 18701 16373 15889 17333 17781 16095 15411 16614 15745 14254 14833 15352 13463 11917 12872 13439 11539 10770 11452 11195 9408 9387 10317 9075 7694 7872 8636 7254 6430 6775 6940 5641 5328 5550 5435 4531 4349 4584 4075 3471 3441 3653 3072 2649 2810 2659 2185 1958 2077 1909 1504 1493 1541 1308 1077 1063 1096 918 743 747 782 615 518 534 514 346 372 395 327 254 274 271 197 190 215 194 141 128 129 127 99 99 91 81 43 77 64 58 41 38 46 37 37 28 22 29 24 25 26 22 28 19 8 6 17 6 5 6 6 4 10 4 6 7 4 7 3 6 2 2 2 4 2 4 1 0 1 2 0 1 1 2 1 0 0 0 2 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] -miss_latency_2: [binsize: 128 max: 21269 count: 484136 average: 3881.42 | standard deviation: 2362.22 | 13661 1286 2387 4560 5765 5398 4995 5652 6728 7847 8759 8868 7728 8608 10415 10986 10369 10337 11083 10801 10779 11680 12129 10591 10467 11199 11639 10456 10072 10836 10211 9273 9627 9921 8839 7777 8381 8847 7500 7022 7473 7216 6112 6157 6741 5967 4898 5154 5599 4763 4200 4401 4458 3653 3479 3625 3466 2908 2754 3023 2653 2266 2215 2373 2005 1752 1808 1699 1430 1282 1356 1235 990 976 1011 849 703 692 729 571 475 484 500 386 339 349 353 237 236 251 229 180 192 184 128 118 130 130 93 77 87 83 64 65 60 51 29 51 44 40 26 24 25 26 24 21 16 22 15 17 19 13 20 15 4 4 14 6 2 6 4 2 7 3 4 4 3 5 0 3 1 0 1 3 1 3 1 0 1 1 0 0 0 1 0 0 0 0 2 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] -miss_latency_3: [binsize: 128 max: 19761 count: 259582 average: 3885.19 | standard deviation: 2359.2 | 7274 657 1393 2246 3139 2972 2632 2918 3591 4159 4724 4646 4062 4702 5681 5976 5633 5424 5920 5891 5754 6259 6572 5782 5422 6134 6142 5639 5339 5778 5534 4981 5206 5431 4624 4140 4491 4592 4039 3748 3979 3979 3296 3230 3576 3108 2796 2718 3037 2491 2230 2374 2482 1988 1849 1925 1969 1623 1595 1561 1422 1205 1226 1280 1067 897 1002 960 755 676 721 674 514 517 530 459 374 371 367 347 268 263 282 229 179 185 161 109 136 144 98 74 82 87 69 72 85 64 48 51 42 44 35 34 31 30 14 26 20 18 15 14 21 11 13 7 6 7 9 8 7 9 8 4 4 2 3 0 3 0 2 2 3 1 2 3 1 2 3 3 1 2 1 1 1 1 0 0 0 1 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency: [binsize: 128 max: 21143 count: 748999 average: 3853.8 | standard deviation: 2347.14 | 21685 2046 3724 6754 8786 8411 7788 8757 10178 12006 13478 13800 12395 13185 16353 16995 16436 16328 17286 17295 16892 18651 19670 16684 16291 17758 18049 16416 15965 16404 15524 14164 14431 15506 13589 12027 13053 13566 11578 10619 11289 11140 9536 9219 10023 9112 7727 7948 8409 7483 6331 6838 6701 5601 5153 5461 5371 4328 4243 4405 4068 3507 3548 3405 3002 2597 2725 2712 2106 1961 2002 1909 1487 1417 1536 1278 1012 1084 1058 904 709 736 738 545 501 536 472 397 337 357 316 252 267 271 202 195 179 183 140 124 136 106 74 91 89 65 54 61 55 60 60 45 33 31 24 39 28 23 30 31 14 20 14 16 22 12 6 10 21 6 9 8 6 4 6 11 7 9 5 2 4 2 3 6 3 2 0 2 2 2 1 1 2 1 1 4 0 0 0 1 1 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_2: [binsize: 128 max: 21143 count: 486326 average: 3852.66 | standard deviation: 2347.25 | 14072 1327 2443 4342 5729 5496 5083 5762 6663 7790 8820 8935 8050 8477 10578 11081 10605 10643 11287 11230 10992 12105 12745 10874 10606 11424 11647 10600 10427 10676 10079 9205 9306 10079 8868 7739 8487 8814 7465 6849 7339 7219 6182 6042 6453 5924 4980 5095 5515 4905 4170 4487 4307 3622 3327 3554 3511 2838 2751 2831 2713 2289 2261 2177 1939 1693 1757 1749 1388 1246 1314 1278 984 907 995 845 687 693 691 577 445 486 462 351 310 350 295 258 213 235 213 163 184 180 128 131 111 118 88 90 95 65 46 53 54 46 30 38 30 35 44 29 22 17 15 25 18 17 25 20 8 13 11 12 16 6 5 5 12 4 6 5 1 2 5 6 4 5 4 2 3 2 1 4 2 1 0 2 1 0 0 0 1 1 1 2 0 0 0 1 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_3: [binsize: 128 max: 21029 count: 262673 average: 3855.92 | standard deviation: 2346.94 | 7613 719 1281 2412 3057 2915 2705 2995 3515 4216 4658 4865 4345 4708 5775 5914 5831 5685 5999 6065 5900 6546 6925 5810 5685 6334 6402 5816 5538 5728 5445 4959 5125 5427 4721 4288 4566 4752 4113 3770 3950 3921 3354 3177 3570 3188 2747 2853 2894 2578 2161 2351 2394 1979 1826 1907 1860 1490 1492 1574 1355 1218 1287 1228 1063 904 968 963 718 715 688 631 503 510 541 433 325 391 367 327 264 250 276 194 191 186 177 139 124 122 103 89 83 91 74 64 68 65 52 34 41 41 28 38 35 19 24 23 25 25 16 16 11 14 9 14 10 6 5 11 6 7 3 4 6 6 1 5 9 2 3 3 5 2 1 5 3 4 1 0 1 0 2 2 1 1 0 0 1 2 1 1 1 0 0 2 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] All Non-Zero Cycle SW Prefetch Requests ------------------------------------ @@ -459,11 +469,11 @@ filter_action: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN Message Delayed Cycles ---------------------- -Total_delay_cycles: [binsize: 1 max: 18 count: 1487608 average: 0.00181365 | standard deviation: 0.163453 | 1487416 0 1 0 2 0 2 0 2 0 24 0 34 0 48 0 41 0 38 ] -Total_nonPF_delay_cycles: [binsize: 1 max: 18 count: 1487608 average: 0.00181365 | standard deviation: 0.163453 | 1487416 0 1 0 2 0 2 0 2 0 24 0 34 0 48 0 41 0 38 ] +Total_delay_cycles: [binsize: 1 max: 34 count: 1498140 average: 0.00218137 | standard deviation: 0.184029 | 1497918 0 1 0 2 0 3 0 5 0 13 0 27 0 56 0 72 0 40 0 0 0 0 0 0 0 0 0 2 0 0 0 0 0 1 ] +Total_nonPF_delay_cycles: [binsize: 1 max: 34 count: 1498140 average: 0.00218137 | standard deviation: 0.184029 | 1497918 0 1 0 2 0 3 0 5 0 13 0 27 0 56 0 72 0 40 0 0 0 0 0 0 0 0 0 2 0 0 0 0 0 1 ] virtual_network_0_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] - virtual_network_1_delay_cycles: [binsize: 1 max: 0 count: 743718 average: 0 | standard deviation: 0 | 743718 ] - virtual_network_2_delay_cycles: [binsize: 1 max: 18 count: 743890 average: 0.00362688 | standard deviation: 0.231129 | 743698 0 1 0 2 0 2 0 2 0 24 0 34 0 48 0 41 0 38 ] + virtual_network_1_delay_cycles: [binsize: 1 max: 0 count: 748999 average: 0 | standard deviation: 0 | 748999 ] + virtual_network_2_delay_cycles: [binsize: 1 max: 34 count: 749141 average: 0.00436233 | standard deviation: 0.260226 | 748919 0 1 0 2 0 3 0 5 0 13 0 27 0 56 0 72 0 40 0 0 0 0 0 0 0 0 0 2 0 0 0 0 0 1 ] virtual_network_3_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] virtual_network_4_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] virtual_network_5_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] @@ -471,10 +481,10 @@ Total_nonPF_delay_cycles: [binsize: 1 max: 18 count: 1487608 average: 0.00181365 Resource Usage -------------- page_size: 4096 -user_time: 3328 -system_time: 0 -page_reclaims: 38225 -page_faults: 1919 +user_time: 1568 +system_time: 6 +page_reclaims: 39818 +page_faults: 0 swaps: 0 block_inputs: 0 block_outputs: 0 @@ -484,110 +494,110 @@ Network Stats switch_0_inlinks: 2 switch_0_outlinks: 2 -links_utilized_percent_switch_0: 0.0918399 - links_utilized_percent_switch_0_link_0: 0.0367288 bw: 640000 base_latency: 1 - links_utilized_percent_switch_0_link_1: 0.146951 bw: 160000 base_latency: 1 +links_utilized_percent_switch_0: 0.0183566 + links_utilized_percent_switch_0_link_0: 0.00734197 bw: 640000 base_latency: 1 + links_utilized_percent_switch_0_link_1: 0.0293713 bw: 160000 base_latency: 1 - outgoing_messages_switch_0_link_0_Response_Data: 92948 6692256 [ 0 92948 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_0_Writeback_Control: 92970 743760 [ 0 0 92970 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_1_Control: 92954 743632 [ 92954 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_1_Data: 86451 6224472 [ 86451 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_1_Response_Data: 6524 469728 [ 0 6524 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_0_Response_Data: 93592 748736 [ 0 93592 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_0_Writeback_Control: 93607 748856 [ 0 0 93607 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_1_Control: 93601 748808 [ 93601 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_1_Data: 86982 695856 [ 86982 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_1_Response_Data: 6638 53104 [ 0 6638 0 0 0 0 ] base_latency: 1 switch_1_inlinks: 2 switch_1_outlinks: 2 -links_utilized_percent_switch_1: 0.0918541 - links_utilized_percent_switch_1_link_0: 0.0367308 bw: 640000 base_latency: 1 - links_utilized_percent_switch_1_link_1: 0.146977 bw: 160000 base_latency: 1 +links_utilized_percent_switch_1: 0.0183583 + links_utilized_percent_switch_1_link_0: 0.0073431 bw: 640000 base_latency: 1 + links_utilized_percent_switch_1_link_1: 0.0293735 bw: 160000 base_latency: 1 - outgoing_messages_switch_1_link_0_Response_Data: 92953 6692616 [ 0 92953 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_0_Writeback_Control: 92975 743800 [ 0 0 92975 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_1_Control: 92968 743744 [ 92968 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_1_Data: 86377 6219144 [ 86377 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_1_Response_Data: 6615 476280 [ 0 6615 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_0_Response_Data: 93606 748848 [ 0 93606 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_0_Writeback_Control: 93622 748976 [ 0 0 93622 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_1_Control: 93610 748880 [ 93610 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_1_Data: 86850 694800 [ 86850 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_1_Response_Data: 6775 54200 [ 0 6775 0 0 0 0 ] base_latency: 1 switch_2_inlinks: 2 switch_2_outlinks: 2 -links_utilized_percent_switch_2: 0.0918578 - links_utilized_percent_switch_2_link_0: 0.0367345 bw: 640000 base_latency: 1 - links_utilized_percent_switch_2_link_1: 0.146981 bw: 160000 base_latency: 1 +links_utilized_percent_switch_2: 0.0183623 + links_utilized_percent_switch_2_link_0: 0.00734448 bw: 640000 base_latency: 1 + links_utilized_percent_switch_2_link_1: 0.0293801 bw: 160000 base_latency: 1 - outgoing_messages_switch_2_link_0_Response_Data: 92963 6693336 [ 0 92963 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_0_Writeback_Control: 92979 743832 [ 0 0 92979 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_1_Control: 92974 743792 [ 92974 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_1_Data: 86365 6218280 [ 86365 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_1_Response_Data: 6629 477288 [ 0 6629 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_0_Response_Data: 93626 749008 [ 0 93626 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_0_Writeback_Control: 93637 749096 [ 0 0 93637 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_1_Control: 93632 749056 [ 93632 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_1_Data: 86768 694144 [ 86768 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_1_Response_Data: 6877 55016 [ 0 6877 0 0 0 0 ] base_latency: 1 switch_3_inlinks: 2 switch_3_outlinks: 2 -links_utilized_percent_switch_3: 0.0918754 - links_utilized_percent_switch_3_link_0: 0.0367403 bw: 640000 base_latency: 1 - links_utilized_percent_switch_3_link_1: 0.14701 bw: 160000 base_latency: 1 +links_utilized_percent_switch_3: 0.0183636 + links_utilized_percent_switch_3_link_0: 0.00734471 bw: 640000 base_latency: 1 + links_utilized_percent_switch_3_link_1: 0.0293825 bw: 160000 base_latency: 1 - outgoing_messages_switch_3_link_0_Response_Data: 92977 6694344 [ 0 92977 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_3_link_0_Writeback_Control: 93000 744000 [ 0 0 93000 0 0 0 ] base_latency: 1 - outgoing_messages_switch_3_link_1_Control: 92988 743904 [ 92988 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_3_link_1_Data: 86345 6216840 [ 86345 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_3_link_1_Response_Data: 6668 480096 [ 0 6668 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_0_Response_Data: 93633 749064 [ 0 93633 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_0_Writeback_Control: 93636 749088 [ 0 0 93636 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_1_Control: 93645 749160 [ 93645 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_1_Data: 86943 695544 [ 86943 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_1_Response_Data: 6704 53632 [ 0 6704 0 0 0 0 ] base_latency: 1 switch_4_inlinks: 2 switch_4_outlinks: 2 -links_utilized_percent_switch_4: 0.0918515 - links_utilized_percent_switch_4_link_0: 0.0367294 bw: 640000 base_latency: 1 - links_utilized_percent_switch_4_link_1: 0.146974 bw: 160000 base_latency: 1 +links_utilized_percent_switch_4: 0.0183624 + links_utilized_percent_switch_4_link_0: 0.00734432 bw: 640000 base_latency: 1 + links_utilized_percent_switch_4_link_1: 0.0293806 bw: 160000 base_latency: 1 - outgoing_messages_switch_4_link_0_Response_Data: 92949 6692328 [ 0 92949 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_4_link_0_Writeback_Control: 92976 743808 [ 0 0 92976 0 0 0 ] base_latency: 1 - outgoing_messages_switch_4_link_1_Control: 92962 743696 [ 92962 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_4_link_1_Data: 86218 6207696 [ 86218 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_4_link_1_Response_Data: 6772 487584 [ 0 6772 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_4_link_0_Response_Data: 93622 748976 [ 0 93622 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_4_link_0_Writeback_Control: 93637 749096 [ 0 0 93637 0 0 0 ] base_latency: 1 + outgoing_messages_switch_4_link_1_Control: 93631 749048 [ 93631 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_4_link_1_Data: 86839 694712 [ 86839 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_4_link_1_Response_Data: 6810 54480 [ 0 6810 0 0 0 0 ] base_latency: 1 switch_5_inlinks: 2 switch_5_outlinks: 2 -links_utilized_percent_switch_5: 0.0918873 - links_utilized_percent_switch_5_link_0: 0.0367455 bw: 640000 base_latency: 1 - links_utilized_percent_switch_5_link_1: 0.147029 bw: 160000 base_latency: 1 +links_utilized_percent_switch_5: 0.0183663 + links_utilized_percent_switch_5_link_0: 0.00734561 bw: 640000 base_latency: 1 + links_utilized_percent_switch_5_link_1: 0.029387 bw: 160000 base_latency: 1 - outgoing_messages_switch_5_link_0_Response_Data: 92991 6695352 [ 0 92991 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_5_link_0_Writeback_Control: 93006 744048 [ 0 0 93006 0 0 0 ] base_latency: 1 - outgoing_messages_switch_5_link_1_Control: 93007 744056 [ 93007 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_5_link_1_Data: 86410 6221520 [ 86410 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_5_link_1_Response_Data: 6614 476208 [ 0 6614 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_5_link_0_Response_Data: 93632 749056 [ 0 93632 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_5_link_0_Writeback_Control: 93660 749280 [ 0 0 93660 0 0 0 ] base_latency: 1 + outgoing_messages_switch_5_link_1_Control: 93647 749176 [ 93647 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_5_link_1_Data: 87074 696592 [ 87074 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_5_link_1_Response_Data: 6600 52800 [ 0 6600 0 0 0 0 ] base_latency: 1 switch_6_inlinks: 2 switch_6_outlinks: 2 -links_utilized_percent_switch_6: 0.0918695 - links_utilized_percent_switch_6_link_0: 0.0367379 bw: 640000 base_latency: 1 - links_utilized_percent_switch_6_link_1: 0.147001 bw: 160000 base_latency: 1 +links_utilized_percent_switch_6: 0.0183699 + links_utilized_percent_switch_6_link_0: 0.00734765 bw: 640000 base_latency: 1 + links_utilized_percent_switch_6_link_1: 0.0293922 bw: 160000 base_latency: 1 - outgoing_messages_switch_6_link_0_Response_Data: 92971 6693912 [ 0 92971 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_6_link_0_Writeback_Control: 92995 743960 [ 0 0 92995 0 0 0 ] base_latency: 1 - outgoing_messages_switch_6_link_1_Control: 92983 743864 [ 92983 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_6_link_1_Data: 86390 6220080 [ 86390 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_6_link_1_Response_Data: 6617 476424 [ 0 6617 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_6_link_0_Response_Data: 93657 749256 [ 0 93657 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_6_link_0_Writeback_Control: 93687 749496 [ 0 0 93687 0 0 0 ] base_latency: 1 + outgoing_messages_switch_6_link_1_Control: 93662 749296 [ 93662 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_6_link_1_Data: 86788 694304 [ 86788 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_6_link_1_Response_Data: 6904 55232 [ 0 6904 0 0 0 0 ] base_latency: 1 switch_7_inlinks: 2 switch_7_outlinks: 2 -links_utilized_percent_switch_7: 0.0918606 - links_utilized_percent_switch_7_link_0: 0.0367359 bw: 640000 base_latency: 1 - links_utilized_percent_switch_7_link_1: 0.146985 bw: 160000 base_latency: 1 +links_utilized_percent_switch_7: 0.018364 + links_utilized_percent_switch_7_link_0: 0.00734538 bw: 640000 base_latency: 1 + links_utilized_percent_switch_7_link_1: 0.0293826 bw: 160000 base_latency: 1 - outgoing_messages_switch_7_link_0_Response_Data: 92966 6693552 [ 0 92966 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_7_link_0_Writeback_Control: 92989 743912 [ 0 0 92989 0 0 0 ] base_latency: 1 - outgoing_messages_switch_7_link_1_Control: 92973 743784 [ 92973 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_7_link_1_Data: 86344 6216768 [ 86344 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_7_link_1_Response_Data: 6653 479016 [ 0 6653 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_7_link_0_Response_Data: 93631 749048 [ 0 93631 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_7_link_0_Writeback_Control: 93655 749240 [ 0 0 93655 0 0 0 ] base_latency: 1 + outgoing_messages_switch_7_link_1_Control: 93635 749080 [ 93635 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_7_link_1_Data: 87012 696096 [ 87012 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_7_link_1_Response_Data: 6646 53168 [ 0 6646 0 0 0 0 ] base_latency: 1 switch_8_inlinks: 2 switch_8_outlinks: 2 -links_utilized_percent_switch_8: 0.687552 - links_utilized_percent_switch_8_link_0: 0.275096 bw: 640000 base_latency: 1 - links_utilized_percent_switch_8_link_1: 1.10001 bw: 160000 base_latency: 1 +links_utilized_percent_switch_8: 0.141605 + links_utilized_percent_switch_8_link_0: 0.0566464 bw: 640000 base_latency: 1 + links_utilized_percent_switch_8_link_1: 0.226565 bw: 160000 base_latency: 1 - outgoing_messages_switch_8_link_0_Control: 743809 5950472 [ 743809 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_8_link_0_Data: 690900 49744800 [ 690900 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_8_link_1_Response_Data: 690626 49725072 [ 0 690626 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_8_link_1_Writeback_Control: 743890 5951120 [ 0 0 743890 0 0 0 ] base_latency: 1 + outgoing_messages_switch_8_link_0_Control: 749063 5992504 [ 749063 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_8_link_0_Data: 695256 5562048 [ 695256 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_8_link_1_Response_Data: 695045 5560360 [ 0 695045 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_8_link_1_Writeback_Control: 749141 5993128 [ 0 0 749141 0 0 0 ] base_latency: 1 switch_9_inlinks: 2 switch_9_outlinks: 2 @@ -598,148 +608,148 @@ links_utilized_percent_switch_9: 0 switch_10_inlinks: 10 switch_10_outlinks: 10 -links_utilized_percent_switch_10: 0.227592 - links_utilized_percent_switch_10_link_0: 0.146915 bw: 160000 base_latency: 1 - links_utilized_percent_switch_10_link_1: 0.146923 bw: 160000 base_latency: 1 - links_utilized_percent_switch_10_link_2: 0.146938 bw: 160000 base_latency: 1 - links_utilized_percent_switch_10_link_3: 0.146961 bw: 160000 base_latency: 1 - links_utilized_percent_switch_10_link_4: 0.146917 bw: 160000 base_latency: 1 - links_utilized_percent_switch_10_link_5: 0.146982 bw: 160000 base_latency: 1 - links_utilized_percent_switch_10_link_6: 0.146952 bw: 160000 base_latency: 1 - links_utilized_percent_switch_10_link_7: 0.146944 bw: 160000 base_latency: 1 - links_utilized_percent_switch_10_link_8: 1.10038 bw: 160000 base_latency: 1 +links_utilized_percent_switch_10: 0.0461614 + links_utilized_percent_switch_10_link_0: 0.0293679 bw: 160000 base_latency: 1 + links_utilized_percent_switch_10_link_1: 0.0293724 bw: 160000 base_latency: 1 + links_utilized_percent_switch_10_link_2: 0.0293779 bw: 160000 base_latency: 1 + links_utilized_percent_switch_10_link_3: 0.0293788 bw: 160000 base_latency: 1 + links_utilized_percent_switch_10_link_4: 0.0293773 bw: 160000 base_latency: 1 + links_utilized_percent_switch_10_link_5: 0.0293825 bw: 160000 base_latency: 1 + links_utilized_percent_switch_10_link_6: 0.0293906 bw: 160000 base_latency: 1 + links_utilized_percent_switch_10_link_7: 0.0293815 bw: 160000 base_latency: 1 + links_utilized_percent_switch_10_link_8: 0.226585 bw: 160000 base_latency: 1 links_utilized_percent_switch_10_link_9: 0 bw: 160000 base_latency: 1 - outgoing_messages_switch_10_link_0_Response_Data: 92948 6692256 [ 0 92948 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_0_Writeback_Control: 92970 743760 [ 0 0 92970 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_1_Response_Data: 92953 6692616 [ 0 92953 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_1_Writeback_Control: 92975 743800 [ 0 0 92975 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_2_Response_Data: 92963 6693336 [ 0 92963 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_2_Writeback_Control: 92979 743832 [ 0 0 92979 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_3_Response_Data: 92977 6694344 [ 0 92977 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_3_Writeback_Control: 93000 744000 [ 0 0 93000 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_4_Response_Data: 92949 6692328 [ 0 92949 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_4_Writeback_Control: 92976 743808 [ 0 0 92976 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_5_Response_Data: 92991 6695352 [ 0 92991 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_5_Writeback_Control: 93006 744048 [ 0 0 93006 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_6_Response_Data: 92971 6693912 [ 0 92971 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_6_Writeback_Control: 92995 743960 [ 0 0 92995 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_7_Response_Data: 92966 6693552 [ 0 92966 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_7_Writeback_Control: 92989 743912 [ 0 0 92989 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_8_Control: 743809 5950472 [ 743809 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_8_Data: 690900 49744800 [ 690900 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_0_Response_Data: 93592 748736 [ 0 93592 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_0_Writeback_Control: 93607 748856 [ 0 0 93607 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_1_Response_Data: 93606 748848 [ 0 93606 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_1_Writeback_Control: 93622 748976 [ 0 0 93622 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_2_Response_Data: 93626 749008 [ 0 93626 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_2_Writeback_Control: 93637 749096 [ 0 0 93637 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_3_Response_Data: 93633 749064 [ 0 93633 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_3_Writeback_Control: 93636 749088 [ 0 0 93636 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_4_Response_Data: 93622 748976 [ 0 93622 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_4_Writeback_Control: 93637 749096 [ 0 0 93637 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_5_Response_Data: 93632 749056 [ 0 93632 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_5_Writeback_Control: 93660 749280 [ 0 0 93660 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_6_Response_Data: 93657 749256 [ 0 93657 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_6_Writeback_Control: 93687 749496 [ 0 0 93687 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_7_Response_Data: 93631 749048 [ 0 93631 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_7_Writeback_Control: 93655 749240 [ 0 0 93655 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_8_Control: 749063 5992504 [ 749063 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_8_Data: 695256 5562048 [ 695256 0 0 0 0 0 ] base_latency: 1 l1u_0 cache stats: - l1u_0_total_misses: 92954 - l1u_0_total_demand_misses: 92954 + l1u_0_total_misses: 93601 + l1u_0_total_demand_misses: 93601 l1u_0_total_prefetches: 0 l1u_0_total_sw_prefetches: 0 l1u_0_total_hw_prefetches: 0 l1u_0_misses_per_transaction: inf - l1u_0_request_type_LD: 64.9547% - l1u_0_request_type_ST: 35.0453% + l1u_0_request_type_LD: 64.9138% + l1u_0_request_type_ST: 35.0862% - l1u_0_access_mode_type_SupervisorMode: 92954 100% - l1u_0_request_size: [binsize: log2 max: 1 count: 92954 average: 1 | standard deviation: 0 | 0 92954 ] + l1u_0_access_mode_type_SupervisorMode: 93601 100% + l1u_0_request_size: [binsize: log2 max: 1 count: 93601 average: 1 | standard deviation: 0 | 0 93601 ] l1u_1 cache stats: - l1u_1_total_misses: 92968 - l1u_1_total_demand_misses: 92968 + l1u_1_total_misses: 93610 + l1u_1_total_demand_misses: 93610 l1u_1_total_prefetches: 0 l1u_1_total_sw_prefetches: 0 l1u_1_total_hw_prefetches: 0 l1u_1_misses_per_transaction: inf - l1u_1_request_type_LD: 64.8438% - l1u_1_request_type_ST: 35.1562% + l1u_1_request_type_LD: 64.9364% + l1u_1_request_type_ST: 35.0636% - l1u_1_access_mode_type_SupervisorMode: 92968 100% - l1u_1_request_size: [binsize: log2 max: 1 count: 92968 average: 1 | standard deviation: 0 | 0 92968 ] + l1u_1_access_mode_type_SupervisorMode: 93610 100% + l1u_1_request_size: [binsize: log2 max: 1 count: 93610 average: 1 | standard deviation: 0 | 0 93610 ] l1u_2 cache stats: - l1u_2_total_misses: 92974 - l1u_2_total_demand_misses: 92974 + l1u_2_total_misses: 93632 + l1u_2_total_demand_misses: 93632 l1u_2_total_prefetches: 0 l1u_2_total_sw_prefetches: 0 l1u_2_total_hw_prefetches: 0 l1u_2_misses_per_transaction: inf - l1u_2_request_type_LD: 65.0203% - l1u_2_request_type_ST: 34.9797% + l1u_2_request_type_LD: 65.0301% + l1u_2_request_type_ST: 34.9699% - l1u_2_access_mode_type_SupervisorMode: 92974 100% - l1u_2_request_size: [binsize: log2 max: 1 count: 92974 average: 1 | standard deviation: 0 | 0 92974 ] + l1u_2_access_mode_type_SupervisorMode: 93632 100% + l1u_2_request_size: [binsize: log2 max: 1 count: 93632 average: 1 | standard deviation: 0 | 0 93632 ] l1u_3 cache stats: - l1u_3_total_misses: 92988 - l1u_3_total_demand_misses: 92988 + l1u_3_total_misses: 93645 + l1u_3_total_demand_misses: 93645 l1u_3_total_prefetches: 0 l1u_3_total_sw_prefetches: 0 l1u_3_total_hw_prefetches: 0 l1u_3_misses_per_transaction: inf - l1u_3_request_type_LD: 65.0751% - l1u_3_request_type_ST: 34.9249% + l1u_3_request_type_LD: 64.768% + l1u_3_request_type_ST: 35.232% - l1u_3_access_mode_type_SupervisorMode: 92988 100% - l1u_3_request_size: [binsize: log2 max: 1 count: 92988 average: 1 | standard deviation: 0 | 0 92988 ] + l1u_3_access_mode_type_SupervisorMode: 93645 100% + l1u_3_request_size: [binsize: log2 max: 1 count: 93645 average: 1 | standard deviation: 0 | 0 93645 ] l1u_4 cache stats: - l1u_4_total_misses: 92962 - l1u_4_total_demand_misses: 92962 + l1u_4_total_misses: 93631 + l1u_4_total_demand_misses: 93631 l1u_4_total_prefetches: 0 l1u_4_total_sw_prefetches: 0 l1u_4_total_hw_prefetches: 0 l1u_4_misses_per_transaction: inf - l1u_4_request_type_LD: 65.1503% - l1u_4_request_type_ST: 34.8497% + l1u_4_request_type_LD: 65.1579% + l1u_4_request_type_ST: 34.8421% - l1u_4_access_mode_type_SupervisorMode: 92962 100% - l1u_4_request_size: [binsize: log2 max: 1 count: 92962 average: 1 | standard deviation: 0 | 0 92962 ] + l1u_4_access_mode_type_SupervisorMode: 93631 100% + l1u_4_request_size: [binsize: log2 max: 1 count: 93631 average: 1 | standard deviation: 0 | 0 93631 ] l1u_5 cache stats: - l1u_5_total_misses: 93007 - l1u_5_total_demand_misses: 93007 + l1u_5_total_misses: 93647 + l1u_5_total_demand_misses: 93647 l1u_5_total_prefetches: 0 l1u_5_total_sw_prefetches: 0 l1u_5_total_hw_prefetches: 0 l1u_5_misses_per_transaction: inf - l1u_5_request_type_LD: 65.3338% - l1u_5_request_type_ST: 34.6662% + l1u_5_request_type_LD: 64.9086% + l1u_5_request_type_ST: 35.0914% - l1u_5_access_mode_type_SupervisorMode: 93007 100% - l1u_5_request_size: [binsize: log2 max: 1 count: 93007 average: 1 | standard deviation: 0 | 0 93007 ] + l1u_5_access_mode_type_SupervisorMode: 93647 100% + l1u_5_request_size: [binsize: log2 max: 1 count: 93647 average: 1 | standard deviation: 0 | 0 93647 ] l1u_6 cache stats: - l1u_6_total_misses: 92983 - l1u_6_total_demand_misses: 92983 + l1u_6_total_misses: 93662 + l1u_6_total_demand_misses: 93662 l1u_6_total_prefetches: 0 l1u_6_total_sw_prefetches: 0 l1u_6_total_hw_prefetches: 0 l1u_6_misses_per_transaction: inf - l1u_6_request_type_LD: 65.2474% - l1u_6_request_type_ST: 34.7526% + l1u_6_request_type_LD: 64.8353% + l1u_6_request_type_ST: 35.1647% - l1u_6_access_mode_type_SupervisorMode: 92983 100% - l1u_6_request_size: [binsize: log2 max: 1 count: 92983 average: 1 | standard deviation: 0 | 0 92983 ] + l1u_6_access_mode_type_SupervisorMode: 93662 100% + l1u_6_request_size: [binsize: log2 max: 1 count: 93662 average: 1 | standard deviation: 0 | 0 93662 ] l1u_7 cache stats: - l1u_7_total_misses: 92973 - l1u_7_total_demand_misses: 92973 + l1u_7_total_misses: 93635 + l1u_7_total_demand_misses: 93635 l1u_7_total_prefetches: 0 l1u_7_total_sw_prefetches: 0 l1u_7_total_hw_prefetches: 0 l1u_7_misses_per_transaction: inf - l1u_7_request_type_LD: 65.1544% - l1u_7_request_type_ST: 34.8456% + l1u_7_request_type_LD: 64.8881% + l1u_7_request_type_ST: 35.1119% - l1u_7_access_mode_type_SupervisorMode: 92973 100% - l1u_7_request_size: [binsize: log2 max: 1 count: 92973 average: 1 | standard deviation: 0 | 0 92973 ] + l1u_7_access_mode_type_SupervisorMode: 93635 100% + l1u_7_request_size: [binsize: log2 max: 1 count: 93635 average: 1 | standard deviation: 0 | 0 93635 ] --- DMA 0 --- - Event Counts - @@ -758,24 +768,24 @@ BUSY_WR Ack 0 <-- --- Directory 0 --- - Event Counts - -GETX 7305866 +GETX 7426933 GETS 0 -PUTX 690470 -PUTX_NotOwner 430 +PUTX 694863 +PUTX_NotOwner 393 DMA_READ 0 DMA_WRITE 0 -Memory_Data 690626 -Memory_Ack 690368 +Memory_Data 695045 +Memory_Ack 694794 - Transitions - -I GETX 690713 +I GETX 695106 I PUTX_NotOwner 0 <-- I DMA_READ 0 <-- I DMA_WRITE 0 <-- -M GETX 53092 -M PUTX 690470 -M PUTX_NotOwner 430 +M GETX 53954 +M PUTX 694863 +M PUTX_NotOwner 393 M DMA_READ 0 <-- M DMA_WRITE 0 <-- @@ -787,21 +797,21 @@ M_DWR PUTX 0 <-- M_DWRI Memory_Ack 0 <-- -IM GETX 3136382 +IM GETX 3188108 IM GETS 0 <-- IM PUTX 0 <-- IM PUTX_NotOwner 0 <-- IM DMA_READ 0 <-- IM DMA_WRITE 0 <-- -IM Memory_Data 690626 +IM Memory_Data 695045 -MI GETX 3425679 +MI GETX 3489765 MI GETS 0 <-- MI PUTX 0 <-- MI PUTX_NotOwner 0 <-- MI DMA_READ 0 <-- MI DMA_WRITE 0 <-- -MI Memory_Ack 690368 +MI Memory_Ack 694794 ID GETX 0 <-- ID GETS 0 <-- @@ -821,289 +831,289 @@ ID_W Memory_Ack 0 <-- --- L1Cache 0 --- - Event Counts - -Load 60378 +Load 60760 Ifetch 0 -Store 32576 -Data 92948 -Fwd_GETX 6524 +Store 32841 +Data 93592 +Fwd_GETX 6638 Inv 0 -Replacement 92922 -Writeback_Ack 86396 -Writeback_Nack 50 +Replacement 93569 +Writeback_Ack 86918 +Writeback_Nack 51 - Transitions - -I Load 60378 +I Load 60760 I Ifetch 0 <-- -I Store 32576 +I Store 32841 I Inv 0 <-- -I Replacement 6471 +I Replacement 6587 -II Writeback_Nack 50 +II Writeback_Nack 51 M Load 0 <-- M Ifetch 0 <-- M Store 0 <-- -M Fwd_GETX 6474 +M Fwd_GETX 6587 M Inv 0 <-- -M Replacement 86451 +M Replacement 86982 -MI Fwd_GETX 50 +MI Fwd_GETX 51 MI Inv 0 <-- -MI Writeback_Ack 86396 +MI Writeback_Ack 86918 -IS Data 60374 +IS Data 60754 -IM Data 32574 +IM Data 32838 --- L1Cache 1 --- - Event Counts - -Load 60284 +Load 60787 Ifetch 0 -Store 32684 -Data 92953 -Fwd_GETX 6615 +Store 32823 +Data 93606 +Fwd_GETX 6775 Inv 0 -Replacement 92936 -Writeback_Ack 86304 -Writeback_Nack 56 +Replacement 93578 +Writeback_Ack 86801 +Writeback_Nack 46 - Transitions - -I Load 60284 +I Load 60787 I Ifetch 0 <-- -I Store 32684 +I Store 32823 I Inv 0 <-- -I Replacement 6559 +I Replacement 6728 -II Writeback_Nack 56 +II Writeback_Nack 46 M Load 0 <-- M Ifetch 0 <-- M Store 0 <-- -M Fwd_GETX 6559 +M Fwd_GETX 6729 M Inv 0 <-- -M Replacement 86377 +M Replacement 86850 -MI Fwd_GETX 56 +MI Fwd_GETX 46 MI Inv 0 <-- -MI Writeback_Ack 86304 +MI Writeback_Ack 86801 -IS Data 60277 +IS Data 60784 -IM Data 32676 +IM Data 32822 --- L1Cache 2 --- - Event Counts - -Load 60452 +Load 60889 Ifetch 0 -Store 32522 -Data 92963 -Fwd_GETX 6629 +Store 32743 +Data 93626 +Fwd_GETX 6877 Inv 0 -Replacement 92942 -Writeback_Ack 86299 -Writeback_Nack 51 +Replacement 93600 +Writeback_Ack 86717 +Writeback_Nack 43 - Transitions - -I Load 60452 +I Load 60889 I Ifetch 0 <-- -I Store 32522 +I Store 32743 I Inv 0 <-- -I Replacement 6577 +I Replacement 6832 -II Writeback_Nack 51 +II Writeback_Nack 43 M Load 0 <-- M Ifetch 0 <-- M Store 0 <-- -M Fwd_GETX 6578 +M Fwd_GETX 6834 M Inv 0 <-- -M Replacement 86365 +M Replacement 86768 -MI Fwd_GETX 51 +MI Fwd_GETX 43 MI Inv 0 <-- -MI Writeback_Ack 86299 +MI Writeback_Ack 86717 -IS Data 60442 +IS Data 60884 -IM Data 32521 +IM Data 32742 --- L1Cache 3 --- - Event Counts - -Load 60512 +Load 60652 Ifetch 0 -Store 32476 -Data 92977 -Fwd_GETX 6668 +Store 32993 +Data 93633 +Fwd_GETX 6704 Inv 0 -Replacement 92956 -Writeback_Ack 86276 -Writeback_Nack 56 +Replacement 93613 +Writeback_Ack 86899 +Writeback_Nack 33 - Transitions - -I Load 60512 +I Load 60652 I Ifetch 0 <-- -I Store 32476 +I Store 32993 I Inv 0 <-- -I Replacement 6611 +I Replacement 6670 -II Writeback_Nack 56 +II Writeback_Nack 33 M Load 0 <-- M Ifetch 0 <-- M Store 0 <-- -M Fwd_GETX 6612 +M Fwd_GETX 6671 M Inv 0 <-- -M Replacement 86345 +M Replacement 86943 -MI Fwd_GETX 56 +MI Fwd_GETX 33 MI Inv 0 <-- -MI Writeback_Ack 86276 +MI Writeback_Ack 86899 -IS Data 60504 +IS Data 60644 -IM Data 32473 +IM Data 32989 --- L1Cache 4 --- - Event Counts - -Load 60565 +Load 61008 Ifetch 0 -Store 32397 -Data 92949 -Fwd_GETX 6772 +Store 32623 +Data 93622 +Fwd_GETX 6810 Inv 0 -Replacement 92930 -Writeback_Ack 86145 -Writeback_Nack 59 +Replacement 93599 +Writeback_Ack 86779 +Writeback_Nack 48 - Transitions - -I Load 60565 +I Load 61008 I Ifetch 0 <-- -I Store 32397 +I Store 32623 I Inv 0 <-- -I Replacement 6712 +I Replacement 6760 -II Writeback_Nack 59 +II Writeback_Nack 48 M Load 0 <-- M Ifetch 0 <-- M Store 0 <-- -M Fwd_GETX 6713 +M Fwd_GETX 6762 M Inv 0 <-- -M Replacement 86218 +M Replacement 86839 -MI Fwd_GETX 59 +MI Fwd_GETX 48 MI Inv 0 <-- -MI Writeback_Ack 86145 +MI Writeback_Ack 86779 -IS Data 60555 +IS Data 61004 -IM Data 32394 +IM Data 32618 --- L1Cache 5 --- - Event Counts - -Load 60765 +Load 60785 Ifetch 0 -Store 32242 -Data 92991 -Fwd_GETX 6614 +Store 32862 +Data 93632 +Fwd_GETX 6600 Inv 0 -Replacement 92975 -Writeback_Ack 86343 -Writeback_Nack 49 +Replacement 93615 +Writeback_Ack 87003 +Writeback_Nack 57 - Transitions - -I Load 60765 +I Load 60785 I Ifetch 0 <-- -I Store 32242 +I Store 32862 I Inv 0 <-- -I Replacement 6565 +I Replacement 6541 -II Writeback_Nack 49 +II Writeback_Nack 57 M Load 0 <-- M Ifetch 0 <-- M Store 0 <-- -M Fwd_GETX 6565 +M Fwd_GETX 6543 M Inv 0 <-- -M Replacement 86410 +M Replacement 87074 -MI Fwd_GETX 49 +MI Fwd_GETX 57 MI Inv 0 <-- -MI Writeback_Ack 86343 +MI Writeback_Ack 87003 -IS Data 60751 +IS Data 60776 -IM Data 32240 +IM Data 32856 --- L1Cache 6 --- - Event Counts - -Load 60669 +Load 60726 Ifetch 0 -Store 32314 -Data 92971 -Fwd_GETX 6617 +Store 32936 +Data 93657 +Fwd_GETX 6904 Inv 0 -Replacement 92951 -Writeback_Ack 86323 -Writeback_Nack 55 +Replacement 93630 +Writeback_Ack 86721 +Writeback_Nack 62 - Transitions - -I Load 60669 +I Load 60726 I Ifetch 0 <-- -I Store 32314 +I Store 32936 I Inv 0 <-- -I Replacement 6561 +I Replacement 6842 -II Writeback_Nack 55 +II Writeback_Nack 62 M Load 0 <-- M Ifetch 0 <-- M Store 0 <-- -M Fwd_GETX 6562 +M Fwd_GETX 6842 M Inv 0 <-- -M Replacement 86390 +M Replacement 86788 -MI Fwd_GETX 55 +MI Fwd_GETX 62 MI Inv 0 <-- -MI Writeback_Ack 86323 +MI Writeback_Ack 86721 -IS Data 60661 +IS Data 60724 -IM Data 32310 +IM Data 32933 --- L1Cache 7 --- - Event Counts - -Load 60576 +Load 60758 Ifetch 0 -Store 32397 -Data 92966 -Fwd_GETX 6653 +Store 32877 +Data 93631 +Fwd_GETX 6646 Inv 0 -Replacement 92941 -Writeback_Ack 86282 -Writeback_Nack 54 +Replacement 93603 +Writeback_Ack 86956 +Writeback_Nack 53 - Transitions - -I Load 60576 +I Load 60758 I Ifetch 0 <-- -I Store 32397 +I Store 32877 I Inv 0 <-- -I Replacement 6597 +I Replacement 6591 -II Writeback_Nack 54 +II Writeback_Nack 53 M Load 0 <-- M Ifetch 0 <-- M Store 0 <-- -M Fwd_GETX 6599 +M Fwd_GETX 6593 M Inv 0 <-- -M Replacement 86344 +M Replacement 87012 -MI Fwd_GETX 54 +MI Fwd_GETX 53 MI Inv 0 <-- -MI Writeback_Ack 86282 +MI Writeback_Ack 86956 -IS Data 60572 +IS Data 60756 -IM Data 32394 +IM Data 32875 diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/simerr b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/simerr index 9182a7f96..dd896132a 100755 --- a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/simerr +++ b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/simerr @@ -1,78 +1,76 @@ ["-r", "tests/configs/../../src/mem/ruby/config/MI_example-homogeneous.rb", "-p", "8", "-m", "1", "-s", "1024"] -Error: User specified set of debug components, but the RUBY_DEBUG compile-time flag is false. -Solution: Re-compile with RUBY_DEBUG set to true. print config: 1 -system.cpu1: completed 10000 read accesses @3663630 -system.cpu2: completed 10000 read accesses @3663638 -system.cpu5: completed 10000 read accesses @3680002 -system.cpu7: completed 10000 read accesses @3691164 -system.cpu3: completed 10000 read accesses @3698130 -system.cpu4: completed 10000 read accesses @3701748 -system.cpu6: completed 10000 read accesses @3704092 -system.cpu0: completed 10000 read accesses @3742302 -system.cpu2: completed 20000 read accesses @6778081 -system.cpu7: completed 20000 read accesses @6787708 -system.cpu3: completed 20000 read accesses @6819995 -system.cpu6: completed 20000 read accesses @6825022 -system.cpu5: completed 20000 read accesses @6833343 -system.cpu4: completed 20000 read accesses @6836578 -system.cpu1: completed 20000 read accesses @6842472 -system.cpu0: completed 20000 read accesses @6879216 -system.cpu6: completed 30000 read accesses @9933568 -system.cpu7: completed 30000 read accesses @9937112 -system.cpu2: completed 30000 read accesses @9954336 -system.cpu3: completed 30000 read accesses @9954652 -system.cpu4: completed 30000 read accesses @9954804 -system.cpu0: completed 30000 read accesses @9956400 -system.cpu1: completed 30000 read accesses @9969148 -system.cpu5: completed 30000 read accesses @9971642 -system.cpu4: completed 40000 read accesses @13043407 -system.cpu2: completed 40000 read accesses @13067576 -system.cpu0: completed 40000 read accesses @13084396 -system.cpu7: completed 40000 read accesses @13093378 -system.cpu6: completed 40000 read accesses @13094121 -system.cpu3: completed 40000 read accesses @13100062 -system.cpu5: completed 40000 read accesses @13106812 -system.cpu1: completed 40000 read accesses @13156070 -system.cpu7: completed 50000 read accesses @16206554 -system.cpu2: completed 50000 read accesses @16208768 -system.cpu0: completed 50000 read accesses @16212192 -system.cpu4: completed 50000 read accesses @16217948 -system.cpu3: completed 50000 read accesses @16256632 -system.cpu1: completed 50000 read accesses @16263536 -system.cpu5: completed 50000 read accesses @16271570 -system.cpu6: completed 50000 read accesses @16283656 -system.cpu0: completed 60000 read accesses @19290853 -system.cpu2: completed 60000 read accesses @19315578 -system.cpu7: completed 60000 read accesses @19378042 -system.cpu1: completed 60000 read accesses @19380549 -system.cpu4: completed 60000 read accesses @19394866 -system.cpu3: completed 60000 read accesses @19403114 -system.cpu6: completed 60000 read accesses @19417031 -system.cpu5: completed 60000 read accesses @19417566 -system.cpu2: completed 70000 read accesses @22372583 -system.cpu0: completed 70000 read accesses @22441747 -system.cpu1: completed 70000 read accesses @22499937 -system.cpu6: completed 70000 read accesses @22512662 -system.cpu5: completed 70000 read accesses @22534921 -system.cpu7: completed 70000 read accesses @22545974 -system.cpu3: completed 70000 read accesses @22559233 -system.cpu4: completed 70000 read accesses @22609844 -system.cpu2: completed 80000 read accesses @25417738 -system.cpu0: completed 80000 read accesses @25565987 -system.cpu1: completed 80000 read accesses @25571759 -system.cpu5: completed 80000 read accesses @25633062 -system.cpu6: completed 80000 read accesses @25674790 -system.cpu7: completed 80000 read accesses @25684920 -system.cpu3: completed 80000 read accesses @25708114 -system.cpu4: completed 80000 read accesses @25737082 -system.cpu2: completed 90000 read accesses @28501358 -system.cpu1: completed 90000 read accesses @28680540 -system.cpu0: completed 90000 read accesses @28689988 -system.cpu6: completed 90000 read accesses @28771148 -system.cpu5: completed 90000 read accesses @28782038 -system.cpu7: completed 90000 read accesses @28806422 -system.cpu3: completed 90000 read accesses @28840020 -system.cpu4: completed 90000 read accesses @28843088 -system.cpu2: completed 100000 read accesses @31633980 +system.cpu4: completed 10000 read accesses @3654068 +system.cpu1: completed 10000 read accesses @3658672 +system.cpu6: completed 10000 read accesses @3667702 +system.cpu0: completed 10000 read accesses @3693712 +system.cpu2: completed 10000 read accesses @3695692 +system.cpu7: completed 10000 read accesses @3702934 +system.cpu3: completed 10000 read accesses @3713843 +system.cpu5: completed 10000 read accesses @3747976 +system.cpu4: completed 20000 read accesses @6783252 +system.cpu6: completed 20000 read accesses @6788574 +system.cpu1: completed 20000 read accesses @6811444 +system.cpu2: completed 20000 read accesses @6811575 +system.cpu7: completed 20000 read accesses @6823208 +system.cpu3: completed 20000 read accesses @6833412 +system.cpu0: completed 20000 read accesses @6842332 +system.cpu5: completed 20000 read accesses @6892128 +system.cpu4: completed 30000 read accesses @9900552 +system.cpu6: completed 30000 read accesses @9919466 +system.cpu7: completed 30000 read accesses @9934195 +system.cpu3: completed 30000 read accesses @9940524 +system.cpu2: completed 30000 read accesses @9940526 +system.cpu0: completed 30000 read accesses @9949032 +system.cpu1: completed 30000 read accesses @10008962 +system.cpu5: completed 30000 read accesses @10013847 +system.cpu0: completed 40000 read accesses @12997824 +system.cpu3: completed 40000 read accesses @13026659 +system.cpu4: completed 40000 read accesses @13029141 +system.cpu6: completed 40000 read accesses @13053052 +system.cpu7: completed 40000 read accesses @13057445 +system.cpu2: completed 40000 read accesses @13075320 +system.cpu5: completed 40000 read accesses @13152513 +system.cpu1: completed 40000 read accesses @13163064 +system.cpu3: completed 50000 read accesses @16170822 +system.cpu0: completed 50000 read accesses @16183660 +system.cpu4: completed 50000 read accesses @16197183 +system.cpu6: completed 50000 read accesses @16212971 +system.cpu7: completed 50000 read accesses @16214970 +system.cpu5: completed 50000 read accesses @16230286 +system.cpu2: completed 50000 read accesses @16247930 +system.cpu1: completed 50000 read accesses @16329114 +system.cpu3: completed 60000 read accesses @19272882 +system.cpu7: completed 60000 read accesses @19345830 +system.cpu4: completed 60000 read accesses @19346068 +system.cpu6: completed 60000 read accesses @19382538 +system.cpu0: completed 60000 read accesses @19393516 +system.cpu2: completed 60000 read accesses @19397285 +system.cpu5: completed 60000 read accesses @19426724 +system.cpu1: completed 60000 read accesses @19469424 +system.cpu3: completed 70000 read accesses @22377862 +system.cpu4: completed 70000 read accesses @22461180 +system.cpu2: completed 70000 read accesses @22521889 +system.cpu6: completed 70000 read accesses @22522406 +system.cpu5: completed 70000 read accesses @22529566 +system.cpu7: completed 70000 read accesses @22543033 +system.cpu0: completed 70000 read accesses @22547582 +system.cpu1: completed 70000 read accesses @22584856 +system.cpu3: completed 80000 read accesses @25551111 +system.cpu4: completed 80000 read accesses @25606550 +system.cpu6: completed 80000 read accesses @25616752 +system.cpu2: completed 80000 read accesses @25647434 +system.cpu5: completed 80000 read accesses @25665443 +system.cpu0: completed 80000 read accesses @25669616 +system.cpu1: completed 80000 read accesses @25693304 +system.cpu7: completed 80000 read accesses @25704210 +system.cpu3: completed 90000 read accesses @28724260 +system.cpu6: completed 90000 read accesses @28724466 +system.cpu5: completed 90000 read accesses @28743404 +system.cpu4: completed 90000 read accesses @28745769 +system.cpu2: completed 90000 read accesses @28803478 +system.cpu0: completed 90000 read accesses @28806136 +system.cpu1: completed 90000 read accesses @28823872 +system.cpu7: completed 90000 read accesses @28858910 +system.cpu3: completed 100000 read accesses @31871402 hack: be nice to actually delete the event here diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/simout b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/simout index 6bc6a5644..17519e7a0 100755 --- a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/simout +++ b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/simout @@ -1,5 +1,3 @@ -Redirecting stdout to build/ALPHA_SE/tests/fast/quick/50.memtest/alpha/linux/memtest-ruby/simout -Redirecting stderr to build/ALPHA_SE/tests/fast/quick/50.memtest/alpha/linux/memtest-ruby/simerr M5 Simulator System Copyright (c) 2001-2008 @@ -7,11 +5,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Aug 7 2009 11:05:15 -M5 revision e34c4d587f38 6440 default qtip qbase tip tushar/ruby-data_msg_size-bug-fix -M5 started Aug 7 2009 11:05:38 -M5 executing on ca2h0439 +M5 compiled Aug 5 2009 13:36:56 +M5 revision 26abdfe2d980+ 6439+ default tip +M5 started Aug 5 2009 13:37:49 +M5 executing on clover-02.cs.wisc.edu command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/50.memtest/alpha/linux/memtest-ruby -re tests/run.py build/ALPHA_SE/tests/fast/quick/50.memtest/alpha/linux/memtest-ruby Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 31633980 because maximum number of loads reached +Exiting @ tick 31871402 because maximum number of loads reached diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/stats.txt b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/stats.txt index 258ba3b94..2c9df6517 100644 --- a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/stats.txt +++ b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/stats.txt @@ -1,34 +1,34 @@ ---------- Begin Simulation Statistics ---------- -host_mem_usage 1507500 # Number of bytes of host memory used -host_seconds 3347.37 # Real time elapsed on the host -host_tick_rate 9450 # Simulator tick rate (ticks/s) +host_mem_usage 1538648 # Number of bytes of host memory used +host_seconds 1657.04 # Real time elapsed on the host +host_tick_rate 19234 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_seconds 0.000032 # Number of seconds simulated -sim_ticks 31633980 # Number of ticks simulated +sim_ticks 31871402 # Number of ticks simulated system.cpu0.num_copies 0 # number of copy accesses completed -system.cpu0.num_reads 99389 # number of read accesses completed -system.cpu0.num_writes 53397 # number of write accesses completed +system.cpu0.num_reads 99819 # number of read accesses completed +system.cpu0.num_writes 53816 # number of write accesses completed system.cpu1.num_copies 0 # number of copy accesses completed -system.cpu1.num_reads 99316 # number of read accesses completed -system.cpu1.num_writes 52916 # number of write accesses completed +system.cpu1.num_reads 99606 # number of read accesses completed +system.cpu1.num_writes 53868 # number of write accesses completed system.cpu2.num_copies 0 # number of copy accesses completed -system.cpu2.num_reads 100000 # number of read accesses completed -system.cpu2.num_writes 53389 # number of write accesses completed +system.cpu2.num_reads 99741 # number of read accesses completed +system.cpu2.num_writes 53973 # number of write accesses completed system.cpu3.num_copies 0 # number of copy accesses completed -system.cpu3.num_reads 98794 # number of read accesses completed -system.cpu3.num_writes 53127 # number of write accesses completed +system.cpu3.num_reads 100000 # number of read accesses completed +system.cpu3.num_writes 53819 # number of write accesses completed system.cpu4.num_copies 0 # number of copy accesses completed -system.cpu4.num_reads 98918 # number of read accesses completed -system.cpu4.num_writes 53609 # number of write accesses completed +system.cpu4.num_reads 99858 # number of read accesses completed +system.cpu4.num_writes 53805 # number of write accesses completed system.cpu5.num_copies 0 # number of copy accesses completed -system.cpu5.num_reads 99006 # number of read accesses completed -system.cpu5.num_writes 53467 # number of write accesses completed +system.cpu5.num_reads 99895 # number of read accesses completed +system.cpu5.num_writes 53573 # number of write accesses completed system.cpu6.num_copies 0 # number of copy accesses completed -system.cpu6.num_reads 99283 # number of read accesses completed -system.cpu6.num_writes 53587 # number of write accesses completed +system.cpu6.num_reads 99989 # number of read accesses completed +system.cpu6.num_writes 53856 # number of write accesses completed system.cpu7.num_copies 0 # number of copy accesses completed -system.cpu7.num_reads 99099 # number of read accesses completed -system.cpu7.num_writes 53320 # number of write accesses completed +system.cpu7.num_reads 99668 # number of read accesses completed +system.cpu7.num_writes 53858 # number of write accesses completed ---------- End Simulation Statistics ---------- |