diff options
Diffstat (limited to 'tests/quick/50.memtest')
4 files changed, 15 insertions, 115 deletions
diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest/config.ini b/tests/quick/50.memtest/ref/alpha/linux/memtest/config.ini index 05eb91461..363cb64d4 100644 --- a/tests/quick/50.memtest/ref/alpha/linux/memtest/config.ini +++ b/tests/quick/50.memtest/ref/alpha/linux/memtest/config.ini @@ -1,48 +1,7 @@ [root] type=Root children=system -checkpoint= -clock=1000000000000 -max_tick=0 -output_file=cout -progress_interval=0 - -[exetrace] -intel_format=false -legion_lockstep=false -pc_symbol=true -print_cpseq=false -print_cycle=true -print_data=true -print_effaddr=true -print_fetchseq=false -print_iregs=false -print_opclass=true -print_thread=true -speculative=true -trace_system=client - -[serialize] -count=10 -cycle=0 -dir=cpt.%012d -period=0 - -[stats] -descriptions=true -dump_cycle=0 -dump_period=0 -dump_reset=false -ignore_events= -mysql_db= -mysql_host= -mysql_password= -mysql_user= -project_name=test -simulation_name=test -simulation_sample=0 -text_compat=true -text_file=m5stats.txt +dummy=0 [system] type=System @@ -610,12 +569,3 @@ responder_set=false width=16 port=system.l2c.cpu_side system.cpu0.l1c.mem_side system.cpu1.l1c.mem_side system.cpu2.l1c.mem_side system.cpu3.l1c.mem_side system.cpu4.l1c.mem_side system.cpu5.l1c.mem_side system.cpu6.l1c.mem_side system.cpu7.l1c.mem_side -[trace] -bufsize=0 -cycle=0 -dump_on_exit=false -file=cout -flags= -ignore= -start=0 - diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest/config.out b/tests/quick/50.memtest/ref/alpha/linux/memtest/config.out index b8ae04bc0..b3f4ec871 100644 --- a/tests/quick/50.memtest/ref/alpha/linux/memtest/config.out +++ b/tests/quick/50.memtest/ref/alpha/linux/memtest/config.out @@ -1,9 +1,6 @@ [root] type=Root -clock=1000000000000 -max_tick=0 -progress_interval=0 -output_file=cout +dummy=0 [system.physmem] type=PhysicalMemory @@ -524,51 +521,3 @@ clock=2 width=16 responder_set=false -[trace] -flags= -start=0 -cycle=0 -bufsize=0 -file=cout -dump_on_exit=false -ignore= - -[stats] -descriptions=true -project_name=test -simulation_name=test -simulation_sample=0 -text_file=m5stats.txt -text_compat=true -mysql_db= -mysql_user= -mysql_password= -mysql_host= -events_start=-1 -dump_reset=false -dump_cycle=0 -dump_period=0 -ignore_events= - -[random] -seed=1 - -[exetrace] -speculative=true -print_cycle=true -print_opclass=true -print_thread=true -print_effaddr=true -print_data=true -print_iregs=false -print_fetchseq=false -print_cpseq=false -print_reg_delta=false -pc_symbol=true -intel_format=false -legion_lockstep=false -trace_system=client - -[statsreset] -reset_cycle=0 - diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest/m5stats.txt b/tests/quick/50.memtest/ref/alpha/linux/memtest/m5stats.txt index a65b235b0..285ab3702 100644 --- a/tests/quick/50.memtest/ref/alpha/linux/memtest/m5stats.txt +++ b/tests/quick/50.memtest/ref/alpha/linux/memtest/m5stats.txt @@ -1,8 +1,8 @@ ---------- Begin Simulation Statistics ---------- -host_mem_usage 435124 # Number of bytes of host memory used -host_seconds 28.46 # Real time elapsed on the host -host_tick_rate 202211 # Simulator tick rate (ticks/s) +host_mem_usage 303680 # Number of bytes of host memory used +host_seconds 32.50 # Real time elapsed on the host +host_tick_rate 177110 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_seconds 0.000006 # Number of seconds simulated sim_ticks 5755736 # Number of ticks simulated @@ -887,15 +887,15 @@ system.l2c.ReadReq_mshr_misses 66414 # nu system.l2c.ReadReq_mshr_uncacheable 78703 # number of ReadReq MSHR uncacheable system.l2c.ReadResp_avg_mshr_uncacheable_latency inf # average ReadResp mshr uncacheable latency system.l2c.ReadResp_mshr_uncacheable_latency 420484 # number of ReadResp MSHR uncacheable cycles -system.l2c.WriteReqNoAck|Writeback_accesses 86614 # number of WriteReqNoAck|Writeback accesses(hits+misses) -system.l2c.WriteReqNoAck|Writeback_hits 18299 # number of WriteReqNoAck|Writeback hits -system.l2c.WriteReqNoAck|Writeback_miss_rate 0.788729 # miss rate for WriteReqNoAck|Writeback accesses -system.l2c.WriteReqNoAck|Writeback_misses 68315 # number of WriteReqNoAck|Writeback misses -system.l2c.WriteReqNoAck|Writeback_mshr_miss_rate 0.788729 # mshr miss rate for WriteReqNoAck|Writeback accesses -system.l2c.WriteReqNoAck|Writeback_mshr_misses 68315 # number of WriteReqNoAck|Writeback MSHR misses system.l2c.WriteReq_mshr_uncacheable 42661 # number of WriteReq MSHR uncacheable system.l2c.WriteResp_avg_mshr_uncacheable_latency inf # average WriteResp mshr uncacheable latency system.l2c.WriteResp_mshr_uncacheable_latency 298282 # number of WriteResp MSHR uncacheable cycles +system.l2c.Writeback_accesses 86614 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_hits 18299 # number of Writeback hits +system.l2c.Writeback_miss_rate 0.788729 # miss rate for Writeback accesses +system.l2c.Writeback_misses 68315 # number of Writeback misses +system.l2c.Writeback_mshr_miss_rate 0.788729 # mshr miss rate for Writeback accesses +system.l2c.Writeback_mshr_misses 68315 # number of Writeback MSHR misses system.l2c.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.l2c.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked system.l2c.avg_refs 1.277186 # Average number of references to valid blocks. diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest/stdout b/tests/quick/50.memtest/ref/alpha/linux/memtest/stdout index 3d3289d71..ea4812a6d 100644 --- a/tests/quick/50.memtest/ref/alpha/linux/memtest/stdout +++ b/tests/quick/50.memtest/ref/alpha/linux/memtest/stdout @@ -5,9 +5,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 6 2007 20:30:01 -M5 started Tue Feb 6 21:04:07 2007 -M5 executing on vm1 +M5 compiled Apr 21 2007 21:50:58 +M5 started Sat Apr 21 21:51:15 2007 +M5 executing on zamp.eecs.umich.edu command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/50.memtest/alpha/linux/memtest tests/run.py quick/50.memtest/alpha/linux/memtest warning: overwriting port funcmem.functional value cpu1.functional with cpu2.functional warning: overwriting port funcmem.functional value cpu2.functional with cpu3.functional @@ -15,4 +15,5 @@ warning: overwriting port funcmem.functional value cpu3.functional with cpu4.fun warning: overwriting port funcmem.functional value cpu4.functional with cpu5.functional warning: overwriting port funcmem.functional value cpu5.functional with cpu6.functional warning: overwriting port funcmem.functional value cpu6.functional with cpu7.functional +Global frequency set at 1000000000000 ticks per second Exiting @ tick 5755736 because Maximum number of loads reached! |