diff options
Diffstat (limited to 'tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt')
| -rw-r--r-- | tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt | 482 |
1 files changed, 241 insertions, 241 deletions
diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt index b45122ce6..046013e55 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt @@ -4,167 +4,167 @@ sim_seconds 1.870336 # Nu sim_ticks 1870335522500 # Number of ticks simulated final_tick 1870335522500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 2870976 # Simulator instruction rate (inst/s) -host_op_rate 2870973 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 85025108641 # Simulator tick rate (ticks/s) -host_mem_usage 298608 # Number of bytes of host memory used -host_seconds 22.00 # Real time elapsed on the host +host_inst_rate 4061827 # Simulator instruction rate (inst/s) +host_op_rate 4061823 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 120292600618 # Simulator tick rate (ticks/s) +host_mem_usage 301032 # Number of bytes of host memory used +host_seconds 15.55 # Real time elapsed on the host sim_insts 63154034 # Number of instructions simulated sim_ops 63154034 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu0.inst 855168 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 67882688 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 761216 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 66693056 # Number of bytes read from this memory system.physmem.bytes_read::tsunami.ide 2649600 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 139840 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 770176 # Number of bytes read from this memory -system.physmem.bytes_read::total 72297472 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 855168 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 139840 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 995008 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 10452352 # Number of bytes written to this memory -system.physmem.bytes_written::total 10452352 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.inst 13362 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 1060667 # Number of read requests responded to by this memory +system.physmem.bytes_read::cpu1.inst 110976 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 668672 # Number of bytes read from this memory +system.physmem.bytes_read::total 70883520 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 761216 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 110976 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 872192 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7861504 # Number of bytes written to this memory +system.physmem.bytes_written::total 7861504 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.inst 11894 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 1042079 # Number of read requests responded to by this memory system.physmem.num_reads::tsunami.ide 41400 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 2185 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 12034 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1129648 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 163318 # Number of write requests responded to by this memory -system.physmem.num_writes::total 163318 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.inst 457227 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 36294391 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_reads::cpu1.inst 1734 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 10448 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1107555 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 122836 # Number of write requests responded to by this memory +system.physmem.num_writes::total 122836 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.inst 406994 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 35658338 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::tsunami.ide 1416644 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 74767 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 411785 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 38654814 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 457227 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 74767 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 531994 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 5588490 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 5588490 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 5588490 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 457227 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 36294391 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 59335 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 357514 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 37898826 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 406994 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 59335 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 466329 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 4203259 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 4203259 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 4203259 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 406994 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 35658338 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::tsunami.ide 1416644 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 74767 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 411785 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 44243304 # Total bandwidth to/from this memory (bytes/s) -system.l2c.replacements 1051788 # number of replacements -system.l2c.tagsinuse 34117.721410 # Cycle average of tags in use -system.l2c.total_refs 2341203 # Total number of references to valid blocks. -system.l2c.sampled_refs 1087985 # Sample count of references to valid blocks. -system.l2c.avg_refs 2.151871 # Average number of references to valid blocks. -system.l2c.warmup_cycle 990121000 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 23831.931773 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.inst 3683.485712 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.data 6336.188239 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.inst 152.381317 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.data 113.734368 # Average occupied blocks per requestor -system.l2c.occ_percent::writebacks 0.363646 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.inst 0.056206 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.data 0.096683 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.inst 0.002325 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.data 0.001735 # Average percentage of cache occupancy -system.l2c.occ_percent::total 0.520595 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu0.inst 871618 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 748887 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 101445 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 35685 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1757635 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 811846 # number of Writeback hits -system.l2c.Writeback_hits::total 811846 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 134 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 39 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 173 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 15 # number of SCUpgradeReq hits +system.physmem.bw_total::cpu1.inst 59335 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 357514 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 42102084 # Total bandwidth to/from this memory (bytes/s) +system.l2c.replacements 1000626 # number of replacements +system.l2c.tagsinuse 65381.922680 # Cycle average of tags in use +system.l2c.total_refs 2464692 # Total number of references to valid blocks. +system.l2c.sampled_refs 1065768 # Sample count of references to valid blocks. +system.l2c.avg_refs 2.312597 # Average number of references to valid blocks. +system.l2c.warmup_cycle 838081000 # Cycle when the warmup percentage was hit. +system.l2c.occ_blocks::writebacks 56158.702580 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.inst 4894.236968 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.data 4134.601551 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.inst 174.423287 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.data 19.958294 # Average occupied blocks per requestor +system.l2c.occ_percent::writebacks 0.856914 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.inst 0.074680 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.data 0.063089 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu1.inst 0.002661 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu1.data 0.000305 # Average percentage of cache occupancy +system.l2c.occ_percent::total 0.997649 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::cpu0.inst 873086 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 763047 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 101896 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 36724 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1774753 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 816766 # number of Writeback hits +system.l2c.Writeback_hits::total 816766 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0.data 133 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 36 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 169 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu0.data 14 # number of SCUpgradeReq hits system.l2c.SCUpgradeReq_hits::cpu1.data 9 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 24 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 164417 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 14126 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 178543 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.inst 871618 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 913304 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 101445 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 49811 # number of demand (read+write) hits -system.l2c.demand_hits::total 1936178 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.inst 871618 # number of overall hits -system.l2c.overall_hits::cpu0.data 913304 # number of overall hits -system.l2c.overall_hits::cpu1.inst 101445 # number of overall hits -system.l2c.overall_hits::cpu1.data 49811 # number of overall hits -system.l2c.overall_hits::total 1936178 # number of overall hits -system.l2c.ReadReq_misses::cpu0.inst 13362 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 943555 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 2185 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 2326 # number of ReadReq misses -system.l2c.ReadReq_misses::total 961428 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 2441 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 567 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 3008 # number of UpgradeReq misses +system.l2c.SCUpgradeReq_hits::total 23 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 166157 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 14260 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 180417 # number of ReadExReq hits +system.l2c.demand_hits::cpu0.inst 873086 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 929204 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 101896 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 50984 # number of demand (read+write) hits +system.l2c.demand_hits::total 1955170 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.inst 873086 # number of overall hits +system.l2c.overall_hits::cpu0.data 929204 # number of overall hits +system.l2c.overall_hits::cpu1.inst 101896 # number of overall hits +system.l2c.overall_hits::cpu1.data 50984 # number of overall hits +system.l2c.overall_hits::total 1955170 # number of overall hits +system.l2c.ReadReq_misses::cpu0.inst 11894 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.data 926761 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.inst 1734 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.data 908 # number of ReadReq misses +system.l2c.ReadReq_misses::total 941297 # number of ReadReq misses +system.l2c.UpgradeReq_misses::cpu0.data 2442 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 570 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 3012 # number of UpgradeReq misses system.l2c.SCUpgradeReq_misses::cpu0.data 65 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu1.data 101 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 166 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 117481 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 9826 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 127307 # number of ReadExReq misses -system.l2c.demand_misses::cpu0.inst 13362 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 1061036 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 2185 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 12152 # number of demand (read+write) misses -system.l2c.demand_misses::total 1088735 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.inst 13362 # number of overall misses -system.l2c.overall_misses::cpu0.data 1061036 # number of overall misses -system.l2c.overall_misses::cpu1.inst 2185 # number of overall misses -system.l2c.overall_misses::cpu1.data 12152 # number of overall misses -system.l2c.overall_misses::total 1088735 # number of overall misses +system.l2c.SCUpgradeReq_misses::cpu1.data 100 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::total 165 # number of SCUpgradeReq misses +system.l2c.ReadExReq_misses::cpu0.data 115706 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 9662 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 125368 # number of ReadExReq misses +system.l2c.demand_misses::cpu0.inst 11894 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 1042467 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.inst 1734 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.data 10570 # number of demand (read+write) misses +system.l2c.demand_misses::total 1066665 # number of demand (read+write) misses +system.l2c.overall_misses::cpu0.inst 11894 # number of overall misses +system.l2c.overall_misses::cpu0.data 1042467 # number of overall misses +system.l2c.overall_misses::cpu1.inst 1734 # number of overall misses +system.l2c.overall_misses::cpu1.data 10570 # number of overall misses +system.l2c.overall_misses::total 1066665 # number of overall misses system.l2c.ReadReq_accesses::cpu0.inst 884980 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.data 1692442 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.data 1689808 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::cpu1.inst 103630 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.data 38011 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 2719063 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 811846 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 811846 # number of Writeback accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.data 37632 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 2716050 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 816766 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 816766 # number of Writeback accesses(hits+misses) system.l2c.UpgradeReq_accesses::cpu0.data 2575 # number of UpgradeReq accesses(hits+misses) system.l2c.UpgradeReq_accesses::cpu1.data 606 # number of UpgradeReq accesses(hits+misses) system.l2c.UpgradeReq_accesses::total 3181 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu0.data 80 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu1.data 110 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 190 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 281898 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 23952 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 305850 # number of ReadExReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu0.data 79 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu1.data 109 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::total 188 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0.data 281863 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 23922 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 305785 # number of ReadExReq accesses(hits+misses) system.l2c.demand_accesses::cpu0.inst 884980 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 1974340 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 1971671 # number of demand (read+write) accesses system.l2c.demand_accesses::cpu1.inst 103630 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 61963 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 3024913 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 61554 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 3021835 # number of demand (read+write) accesses system.l2c.overall_accesses::cpu0.inst 884980 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 1974340 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 1971671 # number of overall (read+write) accesses system.l2c.overall_accesses::cpu1.inst 103630 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 61963 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 3024913 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu0.inst 0.015099 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.data 0.557511 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.inst 0.021085 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.data 0.061193 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.353588 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.947961 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 0.935644 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.945615 # miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.812500 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.918182 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::total 0.873684 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.416750 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.410237 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.416240 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu0.inst 0.015099 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.537413 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.021085 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.196117 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.359923 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.inst 0.015099 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.537413 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.021085 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.196117 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.359923 # miss rate for overall accesses +system.l2c.overall_accesses::cpu1.data 61554 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 3021835 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::cpu0.inst 0.013440 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.data 0.548442 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.inst 0.016733 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.data 0.024128 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.346568 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::cpu0.data 0.948350 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1.data 0.940594 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.946872 # miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.822785 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.917431 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::total 0.877660 # miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 0.410504 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 0.403896 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.409987 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::cpu0.inst 0.013440 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.528723 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.016733 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.171719 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.352986 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0.inst 0.013440 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.528723 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.016733 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.171719 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.352986 # miss rate for overall accesses system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -173,8 +173,8 @@ system.l2c.avg_blocked_cycles::no_mshrs nan # av system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 121798 # number of writebacks -system.l2c.writebacks::total 121798 # number of writebacks +system.l2c.writebacks::writebacks 81316 # number of writebacks +system.l2c.writebacks::total 81316 # number of writebacks system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate system.iocache.replacements 41695 # number of replacements system.iocache.tagsinuse 0.435437 # Cycle average of tags in use @@ -451,39 +451,39 @@ system.cpu0.icache.cache_copies 0 # nu system.cpu0.icache.writebacks::writebacks 95 # number of writebacks system.cpu0.icache.writebacks::total 95 # number of writebacks system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.replacements 1978962 # number of replacements -system.cpu0.dcache.tagsinuse 504.827058 # Cycle average of tags in use -system.cpu0.dcache.total_refs 13123502 # Total number of references to valid blocks. -system.cpu0.dcache.sampled_refs 1979474 # Sample count of references to valid blocks. -system.cpu0.dcache.avg_refs 6.629793 # Average number of references to valid blocks. +system.cpu0.dcache.replacements 1978686 # number of replacements +system.cpu0.dcache.tagsinuse 507.129778 # Cycle average of tags in use +system.cpu0.dcache.total_refs 13123753 # Total number of references to valid blocks. +system.cpu0.dcache.sampled_refs 1979198 # Sample count of references to valid blocks. +system.cpu0.dcache.avg_refs 6.630844 # Average number of references to valid blocks. system.cpu0.dcache.warmup_cycle 10840000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.occ_blocks::cpu0.data 504.827058 # Average occupied blocks per requestor -system.cpu0.dcache.occ_percent::cpu0.data 0.985990 # Average percentage of cache occupancy -system.cpu0.dcache.occ_percent::total 0.985990 # Average percentage of cache occupancy -system.cpu0.dcache.ReadReq_hits::cpu0.data 7298106 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 7298106 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 5462265 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 5462265 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 172138 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 172138 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 186635 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 186635 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 12760371 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 12760371 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 12760371 # number of overall hits -system.cpu0.dcache.overall_hits::total 12760371 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 1683563 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 1683563 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 285996 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 285996 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 16159 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 16159 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 703 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 703 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 1969559 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 1969559 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 1969559 # number of overall misses -system.cpu0.dcache.overall_misses::total 1969559 # number of overall misses +system.cpu0.dcache.occ_blocks::cpu0.data 507.129778 # Average occupied blocks per requestor +system.cpu0.dcache.occ_percent::cpu0.data 0.990488 # Average percentage of cache occupancy +system.cpu0.dcache.occ_percent::total 0.990488 # Average percentage of cache occupancy +system.cpu0.dcache.ReadReq_hits::cpu0.data 7298337 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 7298337 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 5462263 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 5462263 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 172144 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 172144 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 186624 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 186624 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 12760600 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 12760600 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 12760600 # number of overall hits +system.cpu0.dcache.overall_hits::total 12760600 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 1683332 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 1683332 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 285998 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 285998 # number of WriteReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 16153 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 16153 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 714 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 714 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 1969330 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 1969330 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 1969330 # number of overall misses +system.cpu0.dcache.overall_misses::total 1969330 # number of overall misses system.cpu0.dcache.ReadReq_accesses::cpu0.data 8981669 # number of ReadReq accesses(hits+misses) system.cpu0.dcache.ReadReq_accesses::total 8981669 # number of ReadReq accesses(hits+misses) system.cpu0.dcache.WriteReq_accesses::cpu0.data 5748261 # number of WriteReq accesses(hits+misses) @@ -496,18 +496,18 @@ system.cpu0.dcache.demand_accesses::cpu0.data 14729930 system.cpu0.dcache.demand_accesses::total 14729930 # number of demand (read+write) accesses system.cpu0.dcache.overall_accesses::cpu0.data 14729930 # number of overall (read+write) accesses system.cpu0.dcache.overall_accesses::total 14729930 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.187444 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.187444 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.049753 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.049753 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.085817 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.085817 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.003753 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.003753 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.133711 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.133711 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.133711 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.133711 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.187419 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.187419 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.049754 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.049754 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.085785 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.085785 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.003811 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.003811 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.133696 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.133696 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.133696 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.133696 # miss rate for overall accesses system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -516,8 +516,8 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 771740 # number of writebacks -system.cpu0.dcache.writebacks::total 771740 # number of writebacks +system.cpu0.dcache.writebacks::writebacks 775641 # number of writebacks +system.cpu0.dcache.writebacks::total 775641 # number of writebacks system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dtb.fetch_hits 0 # ITB hits system.cpu1.dtb.fetch_misses 0 # ITB misses @@ -687,42 +687,42 @@ system.cpu1.icache.avg_blocked_cycles::no_mshrs nan system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.writebacks::writebacks 15 # number of writebacks -system.cpu1.icache.writebacks::total 15 # number of writebacks +system.cpu1.icache.writebacks::writebacks 18 # number of writebacks +system.cpu1.icache.writebacks::total 18 # number of writebacks system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.dcache.replacements 62338 # number of replacements -system.cpu1.dcache.tagsinuse 391.951263 # Cycle average of tags in use -system.cpu1.dcache.total_refs 1834544 # Total number of references to valid blocks. -system.cpu1.dcache.sampled_refs 62657 # Sample count of references to valid blocks. -system.cpu1.dcache.avg_refs 29.279155 # Average number of references to valid blocks. -system.cpu1.dcache.warmup_cycle 1851267520500 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.occ_blocks::cpu1.data 391.951263 # Average occupied blocks per requestor -system.cpu1.dcache.occ_percent::cpu1.data 0.765530 # Average percentage of cache occupancy -system.cpu1.dcache.occ_percent::total 0.765530 # Average percentage of cache occupancy -system.cpu1.dcache.ReadReq_hits::cpu1.data 1109315 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 1109315 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 707444 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 707444 # number of WriteReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 15129 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 15129 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 15613 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 15613 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 1816759 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 1816759 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 1816759 # number of overall hits -system.cpu1.dcache.overall_hits::total 1816759 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 41650 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 41650 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 25861 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 25861 # number of WriteReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 1289 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 1289 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 732 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 732 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 67511 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 67511 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 67511 # number of overall misses -system.cpu1.dcache.overall_misses::total 67511 # number of overall misses +system.cpu1.dcache.replacements 62044 # number of replacements +system.cpu1.dcache.tagsinuse 421.562730 # Cycle average of tags in use +system.cpu1.dcache.total_refs 1836054 # Total number of references to valid blocks. +system.cpu1.dcache.sampled_refs 62382 # Sample count of references to valid blocks. +system.cpu1.dcache.avg_refs 29.432432 # Average number of references to valid blocks. +system.cpu1.dcache.warmup_cycle 1851115552500 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.occ_blocks::cpu1.data 421.562730 # Average occupied blocks per requestor +system.cpu1.dcache.occ_percent::cpu1.data 0.823365 # Average percentage of cache occupancy +system.cpu1.dcache.occ_percent::total 0.823365 # Average percentage of cache occupancy +system.cpu1.dcache.ReadReq_hits::cpu1.data 1109521 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 1109521 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 707457 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 707457 # number of WriteReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 15133 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 15133 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 15610 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 15610 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 1816978 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 1816978 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 1816978 # number of overall hits +system.cpu1.dcache.overall_hits::total 1816978 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 41444 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 41444 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 25848 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 25848 # number of WriteReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 1285 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 1285 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 735 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 735 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 67292 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 67292 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 67292 # number of overall misses +system.cpu1.dcache.overall_misses::total 67292 # number of overall misses system.cpu1.dcache.ReadReq_accesses::cpu1.data 1150965 # number of ReadReq accesses(hits+misses) system.cpu1.dcache.ReadReq_accesses::total 1150965 # number of ReadReq accesses(hits+misses) system.cpu1.dcache.WriteReq_accesses::cpu1.data 733305 # number of WriteReq accesses(hits+misses) @@ -735,18 +735,18 @@ system.cpu1.dcache.demand_accesses::cpu1.data 1884270 system.cpu1.dcache.demand_accesses::total 1884270 # number of demand (read+write) accesses system.cpu1.dcache.overall_accesses::cpu1.data 1884270 # number of overall (read+write) accesses system.cpu1.dcache.overall_accesses::total 1884270 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.036187 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.036187 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.035266 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.035266 # miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.078511 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.078511 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.044784 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.044784 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.035829 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.035829 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.035829 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.035829 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.036008 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.036008 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.035249 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.035249 # miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.078268 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.078268 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.044968 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.044968 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.035713 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.035713 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.035713 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.035713 # miss rate for overall accesses system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -755,8 +755,8 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 39996 # number of writebacks -system.cpu1.dcache.writebacks::total 39996 # number of writebacks +system.cpu1.dcache.writebacks::writebacks 41012 # number of writebacks +system.cpu1.dcache.writebacks::total 41012 # number of writebacks system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- |