diff options
Diffstat (limited to 'tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual')
-rw-r--r-- | tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt | 834 |
1 files changed, 417 insertions, 417 deletions
diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt index f73eb8157..41f61bd3d 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt @@ -1,76 +1,76 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 1.869358 # Number of seconds simulated -sim_ticks 1869358498000 # Number of ticks simulated -final_tick 1869358498000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 1869357988000 # Number of ticks simulated +final_tick 1869357988000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1016587 # Simulator instruction rate (inst/s) -host_op_rate 1016586 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 29236138105 # Simulator tick rate (ticks/s) -host_mem_usage 314344 # Number of bytes of host memory used -host_seconds 63.94 # Real time elapsed on the host -sim_insts 65000470 # Number of instructions simulated -sim_ops 65000470 # Number of ops (including micro ops) simulated +host_inst_rate 1993950 # Simulator instruction rate (inst/s) +host_op_rate 1993950 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 57344769220 # Simulator tick rate (ticks/s) +host_mem_usage 333724 # Number of bytes of host memory used +host_seconds 32.60 # Real time elapsed on the host +sim_insts 64999904 # Number of instructions simulated +sim_ops 64999904 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu0.inst 758272 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.data 66535616 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 105984 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 106112 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.data 766336 # Number of bytes read from this memory system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 68167168 # Number of bytes read from this memory +system.physmem.bytes_read::total 68167296 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu0.inst 758272 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 105984 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 864256 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7836224 # Number of bytes written to this memory -system.physmem.bytes_written::total 7836224 # Number of bytes written to this memory +system.physmem.bytes_inst_read::cpu1.inst 106112 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 864384 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7836352 # Number of bytes written to this memory +system.physmem.bytes_written::total 7836352 # Number of bytes written to this memory system.physmem.num_reads::cpu0.inst 11848 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.data 1039619 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 1656 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 1658 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.data 11974 # Number of read requests responded to by this memory system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1065112 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 122441 # Number of write requests responded to by this memory -system.physmem.num_writes::total 122441 # Number of write requests responded to by this memory +system.physmem.num_reads::total 1065114 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 122443 # Number of write requests responded to by this memory +system.physmem.num_writes::total 122443 # Number of write requests responded to by this memory system.physmem.bw_read::cpu0.inst 405632 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 35592753 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 56695 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 35592763 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 56764 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.data 409946 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::tsunami.ide 514 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 36465540 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 36465619 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu0.inst 405632 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 56695 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 462328 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 4191932 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 4191932 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 4191932 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 56764 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 462396 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 4192002 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 4192002 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 4192002 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.inst 405632 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 35592753 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 56695 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 35592763 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 56764 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.data 409946 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::tsunami.ide 514 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 40657473 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 40657621 # Total bandwidth to/from this memory (bytes/s) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu0.dtb.fetch_hits 0 # ITB hits system.cpu0.dtb.fetch_misses 0 # ITB misses system.cpu0.dtb.fetch_acv 0 # ITB acv system.cpu0.dtb.fetch_accesses 0 # ITB accesses -system.cpu0.dtb.read_hits 7758839 # DTB read hits +system.cpu0.dtb.read_hits 7758808 # DTB read hits system.cpu0.dtb.read_misses 7155 # DTB read misses system.cpu0.dtb.read_acv 152 # DTB read access violations system.cpu0.dtb.read_accesses 531148 # DTB read accesses -system.cpu0.dtb.write_hits 4740268 # DTB write hits +system.cpu0.dtb.write_hits 4740251 # DTB write hits system.cpu0.dtb.write_misses 732 # DTB write misses system.cpu0.dtb.write_acv 102 # DTB write access violations system.cpu0.dtb.write_accesses 201714 # DTB write accesses -system.cpu0.dtb.data_hits 12499107 # DTB hits +system.cpu0.dtb.data_hits 12499059 # DTB hits system.cpu0.dtb.data_misses 7887 # DTB misses system.cpu0.dtb.data_acv 254 # DTB access violations system.cpu0.dtb.data_accesses 732862 # DTB accesses -system.cpu0.itb.fetch_hits 3525737 # ITB hits +system.cpu0.itb.fetch_hits 3525726 # ITB hits system.cpu0.itb.fetch_misses 3572 # ITB misses system.cpu0.itb.fetch_acv 127 # ITB acv -system.cpu0.itb.fetch_accesses 3529309 # ITB accesses +system.cpu0.itb.fetch_accesses 3529298 # ITB accesses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.read_acv 0 # DTB read access violations @@ -83,36 +83,36 @@ system.cpu0.itb.data_hits 0 # DT system.cpu0.itb.data_misses 0 # DTB misses system.cpu0.itb.data_acv 0 # DTB access violations system.cpu0.itb.data_accesses 0 # DTB accesses -system.cpu0.numCycles 3738723791 # number of cpu cycles simulated +system.cpu0.numCycles 3738722771 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu0.kern.inst.arm 0 # number of arm instructions executed system.cpu0.kern.inst.quiesce 6794 # number of quiesce instructions executed -system.cpu0.kern.inst.hwrei 150436 # number of hwrei instructions executed +system.cpu0.kern.inst.hwrei 150435 # number of hwrei instructions executed system.cpu0.kern.ipl_count::0 51398 40.00% 40.00% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::21 243 0.19% 40.18% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::21 243 0.19% 40.19% # number of times we switched to this ipl system.cpu0.kern.ipl_count::22 1907 1.48% 41.67% # number of times we switched to this ipl system.cpu0.kern.ipl_count::30 514 0.40% 42.07% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::31 74447 57.93% 100.00% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::total 128509 # number of times we switched to this ipl +system.cpu0.kern.ipl_count::31 74446 57.93% 100.00% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::total 128508 # number of times we switched to this ipl system.cpu0.kern.ipl_good::0 51050 48.97% 48.97% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good::21 243 0.23% 49.20% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good::22 1907 1.83% 51.03% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good::30 514 0.49% 51.52% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good::31 50536 48.48% 100.00% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good::total 104250 # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_ticks::0 1853222948500 99.14% 99.14% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::0 1853222721000 99.14% 99.14% # number of cycles we spent at this ipl system.cpu0.kern.ipl_ticks::21 20110000 0.00% 99.14% # number of cycles we spent at this ipl system.cpu0.kern.ipl_ticks::22 82001000 0.00% 99.14% # number of cycles we spent at this ipl system.cpu0.kern.ipl_ticks::30 57621500 0.00% 99.15% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::31 15975609500 0.85% 100.00% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::total 1869358290500 # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::31 15975327000 0.85% 100.00% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::total 1869357780500 # number of cycles we spent at this ipl system.cpu0.kern.ipl_used::0 0.993229 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::31 0.678818 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::total 0.811227 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::31 0.678828 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::total 0.811234 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.syscall::2 6 2.63% 2.63% # number of syscalls executed system.cpu0.kern.syscall::3 20 8.77% 11.40% # number of syscalls executed system.cpu0.kern.syscall::4 2 0.88% 12.28% # number of syscalls executed @@ -152,7 +152,7 @@ system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.46% # nu system.cpu0.kern.callpal::swpctx 2743 2.02% 2.47% # number of callpals executed system.cpu0.kern.callpal::tbi 39 0.03% 2.50% # number of callpals executed system.cpu0.kern.callpal::wrent 7 0.01% 2.51% # number of callpals executed -system.cpu0.kern.callpal::swpipl 121669 89.51% 92.02% # number of callpals executed +system.cpu0.kern.callpal::swpipl 121668 89.51% 92.02% # number of callpals executed system.cpu0.kern.callpal::rdps 6149 4.52% 96.54% # number of callpals executed system.cpu0.kern.callpal::wrkgp 1 0.00% 96.54% # number of callpals executed system.cpu0.kern.callpal::wrusp 3 0.00% 96.54% # number of callpals executed @@ -161,44 +161,44 @@ system.cpu0.kern.callpal::whami 2 0.00% 96.55% # nu system.cpu0.kern.callpal::rti 4175 3.07% 99.62% # number of callpals executed system.cpu0.kern.callpal::callsys 369 0.27% 99.89% # number of callpals executed system.cpu0.kern.callpal::imb 146 0.11% 100.00% # number of callpals executed -system.cpu0.kern.callpal::total 135930 # number of callpals executed +system.cpu0.kern.callpal::total 135929 # number of callpals executed system.cpu0.kern.mode_switch::kernel 6593 # number of protection mode switches -system.cpu0.kern.mode_switch::user 1174 # number of protection mode switches +system.cpu0.kern.mode_switch::user 1173 # number of protection mode switches system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches -system.cpu0.kern.mode_good::kernel 1173 -system.cpu0.kern.mode_good::user 1174 +system.cpu0.kern.mode_good::kernel 1172 +system.cpu0.kern.mode_good::user 1173 system.cpu0.kern.mode_good::idle 0 -system.cpu0.kern.mode_switch_good::kernel 0.177916 # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good::kernel 0.177764 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good::total 0.302176 # fraction of useful protection mode switches -system.cpu0.kern.mode_ticks::kernel 1868349657500 99.95% 99.95% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks::user 1008632000 0.05% 100.00% # number of ticks spent at the given mode +system.cpu0.kern.mode_switch_good::total 0.301957 # fraction of useful protection mode switches +system.cpu0.kern.mode_ticks::kernel 1868349152500 99.95% 99.95% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::user 1008627000 0.05% 100.00% # number of ticks spent at the given mode system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode system.cpu0.kern.swap_context 2744 # number of times the context was actually changed -system.cpu0.committedInsts 49478313 # Number of instructions committed -system.cpu0.committedOps 49478313 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 46202260 # Number of integer alu accesses +system.cpu0.committedInsts 49477745 # Number of instructions committed +system.cpu0.committedOps 49477745 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 46201705 # Number of integer alu accesses system.cpu0.num_fp_alu_accesses 197598 # Number of float alu accesses -system.cpu0.num_func_calls 1124639 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 6043708 # number of instructions that are conditional controls -system.cpu0.num_int_insts 46202260 # number of integer instructions +system.cpu0.num_func_calls 1124633 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 6043603 # number of instructions that are conditional controls +system.cpu0.num_int_insts 46201705 # number of integer instructions system.cpu0.num_fp_insts 197598 # number of float instructions -system.cpu0.num_int_register_reads 64004164 # number of times the integer registers were read -system.cpu0.num_int_register_writes 34834852 # number of times the integer registers were written +system.cpu0.num_int_register_reads 64003225 # number of times the integer registers were read +system.cpu0.num_int_register_writes 34834421 # number of times the integer registers were written system.cpu0.num_fp_register_reads 97440 # number of times the floating registers were read system.cpu0.num_fp_register_writes 98967 # number of times the floating registers were written -system.cpu0.num_mem_refs 12536155 # number of memory refs -system.cpu0.num_load_insts 7783785 # Number of load instructions -system.cpu0.num_store_insts 4752370 # Number of store instructions -system.cpu0.num_idle_cycles 3689240240.665401 # Number of idle cycles -system.cpu0.num_busy_cycles 49483550.334599 # Number of busy cycles +system.cpu0.num_mem_refs 12536107 # number of memory refs +system.cpu0.num_load_insts 7783754 # Number of load instructions +system.cpu0.num_store_insts 4752353 # Number of store instructions +system.cpu0.num_idle_cycles 3689239788.666409 # Number of idle cycles +system.cpu0.num_busy_cycles 49482982.333591 # Number of busy cycles system.cpu0.not_idle_fraction 0.013235 # Percentage of non-idle cycles system.cpu0.idle_fraction 0.986765 # Percentage of idle cycles -system.cpu0.Branches 7530941 # Number of branches fetched -system.cpu0.op_class::No_OpClass 2589824 5.23% 5.23% # Class of executed instruction -system.cpu0.op_class::IntAlu 33436514 67.57% 72.80% # Class of executed instruction -system.cpu0.op_class::IntMult 50547 0.10% 72.90% # Class of executed instruction +system.cpu0.Branches 7530826 # Number of branches fetched +system.cpu0.op_class::No_OpClass 2589816 5.23% 5.23% # Class of executed instruction +system.cpu0.op_class::IntAlu 33436017 67.57% 72.80% # Class of executed instruction +system.cpu0.op_class::IntMult 50540 0.10% 72.90% # Class of executed instruction system.cpu0.op_class::IntDiv 0 0.00% 72.90% # Class of executed instruction system.cpu0.op_class::FloatAdd 27840 0.06% 72.96% # Class of executed instruction system.cpu0.op_class::FloatCmp 0 0.00% 72.96% # Class of executed instruction @@ -226,18 +226,18 @@ system.cpu0.op_class::SimdFloatMisc 0 0.00% 72.96% # Cl system.cpu0.op_class::SimdFloatMult 0 0.00% 72.96% # Class of executed instruction system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 72.96% # Class of executed instruction system.cpu0.op_class::SimdFloatSqrt 0 0.00% 72.96% # Class of executed instruction -system.cpu0.op_class::MemRead 7945621 16.06% 89.02% # Class of executed instruction -system.cpu0.op_class::MemWrite 4758309 9.62% 98.63% # Class of executed instruction -system.cpu0.op_class::IprAccess 675566 1.37% 100.00% # Class of executed instruction +system.cpu0.op_class::MemRead 7945590 16.06% 89.02% # Class of executed instruction +system.cpu0.op_class::MemWrite 4758292 9.62% 98.63% # Class of executed instruction +system.cpu0.op_class::IprAccess 675558 1.37% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 49486454 # Class of executed instruction -system.cpu0.dcache.tags.replacements 1781373 # number of replacements -system.cpu0.dcache.tags.tagsinuse 506.187448 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 10705809 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 1781885 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 6.008137 # Average number of references to valid blocks. +system.cpu0.op_class::total 49485886 # Class of executed instruction +system.cpu0.dcache.tags.replacements 1781371 # number of replacements +system.cpu0.dcache.tags.tagsinuse 506.187328 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 10705763 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 1781883 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 6.008118 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 10840000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 506.187448 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu0.data 506.187328 # Average occupied blocks per requestor system.cpu0.dcache.tags.occ_percent::cpu0.data 0.988647 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_percent::total 0.988647 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id @@ -245,56 +245,56 @@ system.cpu0.dcache.tags.age_task_id_blocks_1024::0 446 system.cpu0.dcache.tags.age_task_id_blocks_1024::1 62 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::2 4 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 51822236 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 51822236 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 6068914 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 6068914 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 4360098 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 4360098 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 127591 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 127591 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 132845 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 132845 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 10429012 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 10429012 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 10429012 # number of overall hits -system.cpu0.dcache.overall_hits::total 10429012 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 1560067 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 1560067 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 236542 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 236542 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 12627 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 12627 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 6925 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 6925 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 1796609 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 1796609 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 1796609 # number of overall misses -system.cpu0.dcache.overall_misses::total 1796609 # number of overall misses -system.cpu0.dcache.ReadReq_accesses::cpu0.data 7628981 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 7628981 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 4596640 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 4596640 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.tags.tag_accesses 51822042 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 51822042 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 6068881 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 6068881 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 4360085 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 4360085 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 127592 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 127592 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 132849 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 132849 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 10428966 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 10428966 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 10428966 # number of overall hits +system.cpu0.dcache.overall_hits::total 10428966 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 1560069 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 1560069 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 236538 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 236538 # number of WriteReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 12626 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 12626 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 6921 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 6921 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 1796607 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 1796607 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 1796607 # number of overall misses +system.cpu0.dcache.overall_misses::total 1796607 # number of overall misses +system.cpu0.dcache.ReadReq_accesses::cpu0.data 7628950 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 7628950 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 4596623 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 4596623 # number of WriteReq accesses(hits+misses) system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 140218 # number of LoadLockedReq accesses(hits+misses) system.cpu0.dcache.LoadLockedReq_accesses::total 140218 # number of LoadLockedReq accesses(hits+misses) system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 139770 # number of StoreCondReq accesses(hits+misses) system.cpu0.dcache.StoreCondReq_accesses::total 139770 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 12225621 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 12225621 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 12225621 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 12225621 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.204492 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.204492 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.051460 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.051460 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.090053 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.090053 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.049546 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.049546 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.146954 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.146954 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.146954 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.146954 # miss rate for overall accesses +system.cpu0.dcache.demand_accesses::cpu0.data 12225573 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 12225573 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 12225573 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 12225573 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.204493 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.204493 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.051459 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.051459 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.090046 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.090046 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.049517 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.049517 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.146955 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.146955 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.146955 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.146955 # miss rate for overall accesses system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -303,16 +303,16 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 632988 # number of writebacks -system.cpu0.dcache.writebacks::total 632988 # number of writebacks +system.cpu0.dcache.writebacks::writebacks 633127 # number of writebacks +system.cpu0.dcache.writebacks::total 633127 # number of writebacks system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.icache.tags.replacements 618298 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.240646 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 48867509 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 618810 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 78.970135 # Average number of references to valid blocks. +system.cpu0.icache.tags.replacements 618292 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.240644 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 48866947 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 618804 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 78.969992 # Average number of references to valid blocks. system.cpu0.icache.tags.warmup_cycle 9786048500 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.240646 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.240644 # Average occupied blocks per requestor system.cpu0.icache.tags.occ_percent::cpu0.inst 0.998517 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_percent::total 0.998517 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id @@ -320,26 +320,26 @@ system.cpu0.icache.tags.age_task_id_blocks_1024::0 63 system.cpu0.icache.tags.age_task_id_blocks_1024::1 116 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::2 333 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 50105399 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 50105399 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 48867509 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 48867509 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 48867509 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 48867509 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 48867509 # number of overall hits -system.cpu0.icache.overall_hits::total 48867509 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 618945 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 618945 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 618945 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 618945 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 618945 # number of overall misses -system.cpu0.icache.overall_misses::total 618945 # number of overall misses -system.cpu0.icache.ReadReq_accesses::cpu0.inst 49486454 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 49486454 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 49486454 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 49486454 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 49486454 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 49486454 # number of overall (read+write) accesses +system.cpu0.icache.tags.tag_accesses 50104825 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 50104825 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 48866947 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 48866947 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 48866947 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 48866947 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 48866947 # number of overall hits +system.cpu0.icache.overall_hits::total 48866947 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 618939 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 618939 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 618939 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 618939 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 618939 # number of overall misses +system.cpu0.icache.overall_misses::total 618939 # number of overall misses +system.cpu0.icache.ReadReq_accesses::cpu0.inst 49485886 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 49485886 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 49485886 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 49485886 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 49485886 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 49485886 # number of overall (read+write) accesses system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.012507 # miss rate for ReadReq accesses system.cpu0.icache.ReadReq_miss_rate::total 0.012507 # miss rate for ReadReq accesses system.cpu0.icache.demand_miss_rate::cpu0.inst 0.012507 # miss rate for demand accesses @@ -354,14 +354,14 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs nan system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.writebacks::writebacks 618298 # number of writebacks -system.cpu0.icache.writebacks::total 618298 # number of writebacks +system.cpu0.icache.writebacks::writebacks 618292 # number of writebacks +system.cpu0.icache.writebacks::total 618292 # number of writebacks system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dtb.fetch_hits 0 # ITB hits system.cpu1.dtb.fetch_misses 0 # ITB misses system.cpu1.dtb.fetch_acv 0 # ITB acv system.cpu1.dtb.fetch_accesses 0 # ITB accesses -system.cpu1.dtb.read_hits 2831558 # DTB read hits +system.cpu1.dtb.read_hits 2831559 # DTB read hits system.cpu1.dtb.read_misses 3191 # DTB read misses system.cpu1.dtb.read_acv 58 # DTB read access violations system.cpu1.dtb.read_accesses 198160 # DTB read accesses @@ -369,7 +369,7 @@ system.cpu1.dtb.write_hits 2101673 # DT system.cpu1.dtb.write_misses 412 # DTB write misses system.cpu1.dtb.write_acv 55 # DTB write access violations system.cpu1.dtb.write_accesses 90619 # DTB write accesses -system.cpu1.dtb.data_hits 4933231 # DTB hits +system.cpu1.dtb.data_hits 4933232 # DTB hits system.cpu1.dtb.data_misses 3603 # DTB misses system.cpu1.dtb.data_acv 113 # DTB access violations system.cpu1.dtb.data_accesses 288779 # DTB accesses @@ -389,7 +389,7 @@ system.cpu1.itb.data_hits 0 # DT system.cpu1.itb.data_misses 0 # DTB misses system.cpu1.itb.data_acv 0 # DTB access violations system.cpu1.itb.data_accesses 0 # DTB accesses -system.cpu1.numCycles 3738297607 # number of cpu cycles simulated +system.cpu1.numCycles 3738296587 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu1.kern.inst.arm 0 # number of arm instructions executed @@ -405,11 +405,11 @@ system.cpu1.kern.ipl_good::22 1906 2.99% 51.49% # nu system.cpu1.kern.ipl_good::30 616 0.97% 52.46% # number of times we switched to this ipl from a different ipl system.cpu1.kern.ipl_good::31 30319 47.54% 100.00% # number of times we switched to this ipl from a different ipl system.cpu1.kern.ipl_good::total 63776 # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_ticks::0 1856124001500 99.30% 99.30% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::0 1856123490500 99.30% 99.30% # number of cycles we spent at this ipl system.cpu1.kern.ipl_ticks::22 81958000 0.00% 99.31% # number of cycles we spent at this ipl system.cpu1.kern.ipl_ticks::30 70736500 0.00% 99.31% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::31 12870742500 0.69% 100.00% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::total 1869147438500 # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::31 12870743500 0.69% 100.00% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::total 1869146928500 # number of cycles we spent at this ipl system.cpu1.kern.ipl_used::0 0.967808 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl @@ -461,32 +461,32 @@ system.cpu1.kern.mode_switch_good::kernel 0.434066 # f system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu1.kern.mode_switch_good::idle 0.177356 # fraction of useful protection mode switches system.cpu1.kern.mode_switch_good::total 0.358625 # fraction of useful protection mode switches -system.cpu1.kern.mode_ticks::kernel 5986367000 0.32% 0.32% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::kernel 5986368000 0.32% 0.32% # number of ticks spent at the given mode system.cpu1.kern.mode_ticks::user 456602000 0.02% 0.34% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::idle 1862102855500 99.66% 100.00% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::idle 1862102404500 99.66% 100.00% # number of ticks spent at the given mode system.cpu1.kern.swap_context 2507 # number of times the context was actually changed -system.cpu1.committedInsts 15522157 # Number of instructions committed -system.cpu1.committedOps 15522157 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 14295542 # Number of integer alu accesses +system.cpu1.committedInsts 15522159 # Number of instructions committed +system.cpu1.committedOps 15522159 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 14295544 # Number of integer alu accesses system.cpu1.num_fp_alu_accesses 198941 # Number of float alu accesses system.cpu1.num_func_calls 493140 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 1540067 # number of instructions that are conditional controls -system.cpu1.num_int_insts 14295542 # number of integer instructions +system.cpu1.num_conditional_control_insts 1540068 # number of instructions that are conditional controls +system.cpu1.num_int_insts 14295544 # number of integer instructions system.cpu1.num_fp_insts 198941 # number of float instructions -system.cpu1.num_int_register_reads 19514287 # number of times the integer registers were read -system.cpu1.num_int_register_writes 10457599 # number of times the integer registers were written +system.cpu1.num_int_register_reads 19514289 # number of times the integer registers were read +system.cpu1.num_int_register_writes 10457600 # number of times the integer registers were written system.cpu1.num_fp_register_reads 101734 # number of times the floating registers were read system.cpu1.num_fp_register_writes 104129 # number of times the floating registers were written -system.cpu1.num_mem_refs 4961785 # number of memory refs -system.cpu1.num_load_insts 2849089 # Number of load instructions +system.cpu1.num_mem_refs 4961786 # number of memory refs +system.cpu1.num_load_insts 2849090 # Number of load instructions system.cpu1.num_store_insts 2112696 # Number of store instructions -system.cpu1.num_idle_cycles 3722774671.474094 # Number of idle cycles -system.cpu1.num_busy_cycles 15522935.525906 # Number of busy cycles +system.cpu1.num_idle_cycles 3722773649.474793 # Number of idle cycles +system.cpu1.num_busy_cycles 15522937.525207 # Number of busy cycles system.cpu1.not_idle_fraction 0.004152 # Percentage of non-idle cycles system.cpu1.idle_fraction 0.995848 # Percentage of idle cycles -system.cpu1.Branches 2214162 # Number of branches fetched +system.cpu1.Branches 2214163 # Number of branches fetched system.cpu1.op_class::No_OpClass 856043 5.51% 5.51% # Class of executed instruction -system.cpu1.op_class::IntAlu 9156765 58.98% 64.49% # Class of executed instruction +system.cpu1.op_class::IntAlu 9156766 58.98% 64.49% # Class of executed instruction system.cpu1.op_class::IntMult 25065 0.16% 64.65% # Class of executed instruction system.cpu1.op_class::IntDiv 0 0.00% 64.65% # Class of executed instruction system.cpu1.op_class::FloatAdd 12426 0.08% 64.73% # Class of executed instruction @@ -515,68 +515,68 @@ system.cpu1.op_class::SimdFloatMisc 0 0.00% 64.74% # Cl system.cpu1.op_class::SimdFloatMult 0 0.00% 64.74% # Class of executed instruction system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 64.74% # Class of executed instruction system.cpu1.op_class::SimdFloatSqrt 0 0.00% 64.74% # Class of executed instruction -system.cpu1.op_class::MemRead 2937015 18.92% 83.66% # Class of executed instruction +system.cpu1.op_class::MemRead 2937016 18.92% 83.66% # Class of executed instruction system.cpu1.op_class::MemWrite 2113897 13.62% 97.27% # Class of executed instruction system.cpu1.op_class::IprAccess 423253 2.73% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 15525873 # Class of executed instruction -system.cpu1.dcache.tags.replacements 201756 # number of replacements -system.cpu1.dcache.tags.tagsinuse 497.613037 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 4718402 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 202064 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 23.351027 # Average number of references to valid blocks. +system.cpu1.op_class::total 15525875 # Class of executed instruction +system.cpu1.dcache.tags.replacements 201757 # number of replacements +system.cpu1.dcache.tags.tagsinuse 497.601960 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 4718401 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 202065 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 23.350907 # Average number of references to valid blocks. system.cpu1.dcache.tags.warmup_cycle 15869420000 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 497.613037 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.971900 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.971900 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_blocks::cpu1.data 497.601960 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.971879 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.971879 # Average percentage of cache occupancy system.cpu1.dcache.tags.occ_task_id_blocks::1024 308 # Occupied blocks per task id system.cpu1.dcache.tags.age_task_id_blocks_1024::2 306 # Occupied blocks per task id system.cpu1.dcache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id system.cpu1.dcache.tags.occ_task_id_percent::1024 0.601562 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 20020602 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 20020602 # Number of data accesses -system.cpu1.dcache.ReadReq_hits::cpu1.data 2632689 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 2632689 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 1954642 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 1954642 # number of WriteReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 61099 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 61099 # number of LoadLockedReq hits +system.cpu1.dcache.tags.tag_accesses 20020608 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 20020608 # Number of data accesses +system.cpu1.dcache.ReadReq_hits::cpu1.data 2632688 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 2632688 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 1954643 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 1954643 # number of WriteReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 61098 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 61098 # number of LoadLockedReq hits system.cpu1.dcache.StoreCondReq_hits::cpu1.data 64210 # number of StoreCondReq hits system.cpu1.dcache.StoreCondReq_hits::total 64210 # number of StoreCondReq hits system.cpu1.dcache.demand_hits::cpu1.data 4587331 # number of demand (read+write) hits system.cpu1.dcache.demand_hits::total 4587331 # number of demand (read+write) hits system.cpu1.dcache.overall_hits::cpu1.data 4587331 # number of overall hits system.cpu1.dcache.overall_hits::total 4587331 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 140883 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 140883 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 78318 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 78318 # number of WriteReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 10999 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 10999 # number of LoadLockedReq misses +system.cpu1.dcache.ReadReq_misses::cpu1.data 140885 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 140885 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 78317 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 78317 # number of WriteReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 11000 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 11000 # number of LoadLockedReq misses system.cpu1.dcache.StoreCondReq_misses::cpu1.data 7305 # number of StoreCondReq misses system.cpu1.dcache.StoreCondReq_misses::total 7305 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 219201 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 219201 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 219201 # number of overall misses -system.cpu1.dcache.overall_misses::total 219201 # number of overall misses -system.cpu1.dcache.ReadReq_accesses::cpu1.data 2773572 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 2773572 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.demand_misses::cpu1.data 219202 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 219202 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 219202 # number of overall misses +system.cpu1.dcache.overall_misses::total 219202 # number of overall misses +system.cpu1.dcache.ReadReq_accesses::cpu1.data 2773573 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 2773573 # number of ReadReq accesses(hits+misses) system.cpu1.dcache.WriteReq_accesses::cpu1.data 2032960 # number of WriteReq accesses(hits+misses) system.cpu1.dcache.WriteReq_accesses::total 2032960 # number of WriteReq accesses(hits+misses) system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 72098 # number of LoadLockedReq accesses(hits+misses) system.cpu1.dcache.LoadLockedReq_accesses::total 72098 # number of LoadLockedReq accesses(hits+misses) system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 71515 # number of StoreCondReq accesses(hits+misses) system.cpu1.dcache.StoreCondReq_accesses::total 71515 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 4806532 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 4806532 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 4806532 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 4806532 # number of overall (read+write) accesses +system.cpu1.dcache.demand_accesses::cpu1.data 4806533 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 4806533 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 4806533 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 4806533 # number of overall (read+write) accesses system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.050795 # miss rate for ReadReq accesses system.cpu1.dcache.ReadReq_miss_rate::total 0.050795 # miss rate for ReadReq accesses system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.038524 # miss rate for WriteReq accesses system.cpu1.dcache.WriteReq_miss_rate::total 0.038524 # miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.152556 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.152556 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.152570 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.152570 # miss rate for LoadLockedReq accesses system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.102146 # miss rate for StoreCondReq accesses system.cpu1.dcache.StoreCondReq_miss_rate::total 0.102146 # miss rate for StoreCondReq accesses system.cpu1.dcache.demand_miss_rate::cpu1.data 0.045605 # miss rate for demand accesses @@ -591,48 +591,48 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 144531 # number of writebacks -system.cpu1.dcache.writebacks::total 144531 # number of writebacks +system.cpu1.dcache.writebacks::writebacks 144536 # number of writebacks +system.cpu1.dcache.writebacks::total 144536 # number of writebacks system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.icache.tags.replacements 380671 # number of replacements -system.cpu1.icache.tags.tagsinuse 453.133725 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 15144661 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 381183 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 39.730683 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 1859779767500 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 453.133725 # Average occupied blocks per requestor +system.cpu1.icache.tags.replacements 380647 # number of replacements +system.cpu1.icache.tags.tagsinuse 453.133719 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 15144687 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 381159 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 39.733253 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 1859777157500 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 453.133719 # Average occupied blocks per requestor system.cpu1.icache.tags.occ_percent::cpu1.inst 0.885027 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_percent::total 0.885027 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu1.icache.tags.age_task_id_blocks_1024::2 509 # Occupied blocks per task id system.cpu1.icache.tags.age_task_id_blocks_1024::3 3 # Occupied blocks per task id system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 15907085 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 15907085 # Number of data accesses -system.cpu1.icache.ReadReq_hits::cpu1.inst 15144661 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 15144661 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 15144661 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 15144661 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 15144661 # number of overall hits -system.cpu1.icache.overall_hits::total 15144661 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 381212 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 381212 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 381212 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 381212 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 381212 # number of overall misses -system.cpu1.icache.overall_misses::total 381212 # number of overall misses -system.cpu1.icache.ReadReq_accesses::cpu1.inst 15525873 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 15525873 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 15525873 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 15525873 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 15525873 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 15525873 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.024553 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.024553 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.024553 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.024553 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.024553 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.024553 # miss rate for overall accesses +system.cpu1.icache.tags.tag_accesses 15907063 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 15907063 # Number of data accesses +system.cpu1.icache.ReadReq_hits::cpu1.inst 15144687 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 15144687 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 15144687 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 15144687 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 15144687 # number of overall hits +system.cpu1.icache.overall_hits::total 15144687 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 381188 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 381188 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 381188 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 381188 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 381188 # number of overall misses +system.cpu1.icache.overall_misses::total 381188 # number of overall misses +system.cpu1.icache.ReadReq_accesses::cpu1.inst 15525875 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 15525875 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 15525875 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 15525875 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 15525875 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 15525875 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.024552 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.024552 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.024552 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.024552 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.024552 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.024552 # miss rate for overall accesses system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -641,8 +641,8 @@ system.cpu1.icache.avg_blocked_cycles::no_mshrs nan system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.writebacks::writebacks 380671 # number of writebacks -system.cpu1.icache.writebacks::total 380671 # number of writebacks +system.cpu1.icache.writebacks::writebacks 380647 # number of writebacks +system.cpu1.icache.writebacks::total 380647 # number of writebacks system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -687,12 +687,12 @@ system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 26616 system.iobus.pkt_size_system.tsunami.ide.dma::total 2661656 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size::total 2747818 # Cumulative packet size per connected master and slave (bytes) system.iocache.tags.replacements 41699 # number of replacements -system.iocache.tags.tagsinuse 0.434101 # Cycle average of tags in use +system.iocache.tags.tagsinuse 0.434096 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 41715 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. system.iocache.tags.warmup_cycle 1685787163517 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::tsunami.ide 0.434101 # Average occupied blocks per requestor +system.iocache.tags.occ_blocks::tsunami.ide 0.434096 # Average occupied blocks per requestor system.iocache.tags.occ_percent::tsunami.ide 0.027131 # Average percentage of cache occupancy system.iocache.tags.occ_percent::total 0.027131 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id @@ -735,140 +735,140 @@ system.iocache.cache_copies 0 # nu system.iocache.writebacks::writebacks 41520 # number of writebacks system.iocache.writebacks::total 41520 # number of writebacks system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.tags.replacements 999918 # number of replacements -system.l2c.tags.tagsinuse 65320.982415 # Cycle average of tags in use -system.l2c.tags.total_refs 4249962 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 1064968 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 3.990695 # Average number of references to valid blocks. +system.l2c.tags.replacements 999922 # number of replacements +system.l2c.tags.tagsinuse 65337.856722 # Cycle average of tags in use +system.l2c.tags.total_refs 4259784 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 1064972 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 3.999902 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 838081000 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 55992.770808 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 4860.291584 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 4178.146657 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 175.172078 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 114.601288 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.854382 # Average percentage of cache occupancy +system.l2c.tags.occ_blocks::writebacks 55997.404251 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 4860.296117 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 4190.275222 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 175.171528 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 114.709605 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.854453 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.inst 0.074162 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.063753 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.063939 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu1.inst 0.002673 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.001749 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.996719 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.001750 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.996977 # Average percentage of cache occupancy system.l2c.tags.occ_task_id_blocks::1024 65050 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1024::0 768 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1024::1 3271 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 6123 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 5943 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 48945 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 6047 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 5933 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 49031 # Occupied blocks per task id system.l2c.tags.occ_task_id_percent::1024 0.992584 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 46365909 # Number of tag accesses -system.l2c.tags.data_accesses 46365909 # Number of data accesses -system.l2c.WritebackDirty_hits::writebacks 777519 # number of WritebackDirty hits -system.l2c.WritebackDirty_hits::total 777519 # number of WritebackDirty hits -system.l2c.WritebackClean_hits::writebacks 719211 # number of WritebackClean hits -system.l2c.WritebackClean_hits::total 719211 # number of WritebackClean hits -system.l2c.UpgradeReq_hits::cpu0.data 116 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 577 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 693 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 37 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 13 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 50 # number of SCUpgradeReq hits +system.l2c.tags.tag_accesses 46377222 # Number of tag accesses +system.l2c.tags.data_accesses 46377222 # Number of data accesses +system.l2c.WritebackDirty_hits::writebacks 777663 # number of WritebackDirty hits +system.l2c.WritebackDirty_hits::total 777663 # number of WritebackDirty hits +system.l2c.WritebackClean_hits::writebacks 721478 # number of WritebackClean hits +system.l2c.WritebackClean_hits::total 721478 # number of WritebackClean hits +system.l2c.UpgradeReq_hits::cpu0.data 130 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 604 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 734 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu0.data 44 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu1.data 28 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 72 # number of SCUpgradeReq hits system.l2c.ReadExReq_hits::cpu0.data 111475 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 56603 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 168078 # number of ReadExReq hits -system.l2c.ReadCleanReq_hits::cpu0.inst 607076 # number of ReadCleanReq hits -system.l2c.ReadCleanReq_hits::cpu1.inst 379556 # number of ReadCleanReq hits -system.l2c.ReadCleanReq_hits::total 986632 # number of ReadCleanReq hits -system.l2c.ReadSharedReq_hits::cpu0.data 626681 # number of ReadSharedReq hits +system.l2c.ReadExReq_hits::cpu1.data 56605 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 168080 # number of ReadExReq hits +system.l2c.ReadCleanReq_hits::cpu0.inst 607070 # number of ReadCleanReq hits +system.l2c.ReadCleanReq_hits::cpu1.inst 379530 # number of ReadCleanReq hits +system.l2c.ReadCleanReq_hits::total 986600 # number of ReadCleanReq hits +system.l2c.ReadSharedReq_hits::cpu0.data 626719 # number of ReadSharedReq hits system.l2c.ReadSharedReq_hits::cpu1.data 129011 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::total 755692 # number of ReadSharedReq hits -system.l2c.demand_hits::cpu0.inst 607076 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 738156 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 379556 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 185614 # number of demand (read+write) hits -system.l2c.demand_hits::total 1910402 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.inst 607076 # number of overall hits -system.l2c.overall_hits::cpu0.data 738156 # number of overall hits -system.l2c.overall_hits::cpu1.inst 379556 # number of overall hits -system.l2c.overall_hits::cpu1.data 185614 # number of overall hits -system.l2c.overall_hits::total 1910402 # number of overall hits -system.l2c.UpgradeReq_misses::cpu0.data 3006 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 2174 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 5180 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.data 1175 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu1.data 1110 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 2285 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 113874 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 11069 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 124943 # number of ReadExReq misses +system.l2c.ReadSharedReq_hits::total 755730 # number of ReadSharedReq hits +system.l2c.demand_hits::cpu0.inst 607070 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 738194 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 379530 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 185616 # number of demand (read+write) hits +system.l2c.demand_hits::total 1910410 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.inst 607070 # number of overall hits +system.l2c.overall_hits::cpu0.data 738194 # number of overall hits +system.l2c.overall_hits::cpu1.inst 379530 # number of overall hits +system.l2c.overall_hits::cpu1.data 185616 # number of overall hits +system.l2c.overall_hits::total 1910410 # number of overall hits +system.l2c.UpgradeReq_misses::cpu0.data 2989 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 2147 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 5136 # number of UpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu0.data 1165 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu1.data 1095 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::total 2260 # number of SCUpgradeReq misses +system.l2c.ReadExReq_misses::cpu0.data 113871 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 11066 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 124937 # number of ReadExReq misses system.l2c.ReadCleanReq_misses::cpu0.inst 11848 # number of ReadCleanReq misses -system.l2c.ReadCleanReq_misses::cpu1.inst 1656 # number of ReadCleanReq misses -system.l2c.ReadCleanReq_misses::total 13504 # number of ReadCleanReq misses +system.l2c.ReadCleanReq_misses::cpu1.inst 1658 # number of ReadCleanReq misses +system.l2c.ReadCleanReq_misses::total 13506 # number of ReadCleanReq misses system.l2c.ReadSharedReq_misses::cpu0.data 926615 # number of ReadSharedReq misses system.l2c.ReadSharedReq_misses::cpu1.data 1035 # number of ReadSharedReq misses system.l2c.ReadSharedReq_misses::total 927650 # number of ReadSharedReq misses system.l2c.demand_misses::cpu0.inst 11848 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 1040489 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 1656 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 12104 # number of demand (read+write) misses -system.l2c.demand_misses::total 1066097 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 1040486 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.inst 1658 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.data 12101 # number of demand (read+write) misses +system.l2c.demand_misses::total 1066093 # number of demand (read+write) misses system.l2c.overall_misses::cpu0.inst 11848 # number of overall misses -system.l2c.overall_misses::cpu0.data 1040489 # number of overall misses -system.l2c.overall_misses::cpu1.inst 1656 # number of overall misses -system.l2c.overall_misses::cpu1.data 12104 # number of overall misses -system.l2c.overall_misses::total 1066097 # number of overall misses -system.l2c.WritebackDirty_accesses::writebacks 777519 # number of WritebackDirty accesses(hits+misses) -system.l2c.WritebackDirty_accesses::total 777519 # number of WritebackDirty accesses(hits+misses) -system.l2c.WritebackClean_accesses::writebacks 719211 # number of WritebackClean accesses(hits+misses) -system.l2c.WritebackClean_accesses::total 719211 # number of WritebackClean accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 3122 # number of UpgradeReq accesses(hits+misses) +system.l2c.overall_misses::cpu0.data 1040486 # number of overall misses +system.l2c.overall_misses::cpu1.inst 1658 # number of overall misses +system.l2c.overall_misses::cpu1.data 12101 # number of overall misses +system.l2c.overall_misses::total 1066093 # number of overall misses +system.l2c.WritebackDirty_accesses::writebacks 777663 # number of WritebackDirty accesses(hits+misses) +system.l2c.WritebackDirty_accesses::total 777663 # number of WritebackDirty accesses(hits+misses) +system.l2c.WritebackClean_accesses::writebacks 721478 # number of WritebackClean accesses(hits+misses) +system.l2c.WritebackClean_accesses::total 721478 # number of WritebackClean accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0.data 3119 # number of UpgradeReq accesses(hits+misses) system.l2c.UpgradeReq_accesses::cpu1.data 2751 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 5873 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu0.data 1212 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 5870 # number of UpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu0.data 1209 # number of SCUpgradeReq accesses(hits+misses) system.l2c.SCUpgradeReq_accesses::cpu1.data 1123 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 2335 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 225349 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 67672 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 293021 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadCleanReq_accesses::cpu0.inst 618924 # number of ReadCleanReq accesses(hits+misses) -system.l2c.ReadCleanReq_accesses::cpu1.inst 381212 # number of ReadCleanReq accesses(hits+misses) -system.l2c.ReadCleanReq_accesses::total 1000136 # number of ReadCleanReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu0.data 1553296 # number of ReadSharedReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::total 2332 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0.data 225346 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 67671 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 293017 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadCleanReq_accesses::cpu0.inst 618918 # number of ReadCleanReq accesses(hits+misses) +system.l2c.ReadCleanReq_accesses::cpu1.inst 381188 # number of ReadCleanReq accesses(hits+misses) +system.l2c.ReadCleanReq_accesses::total 1000106 # number of ReadCleanReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu0.data 1553334 # number of ReadSharedReq accesses(hits+misses) system.l2c.ReadSharedReq_accesses::cpu1.data 130046 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::total 1683342 # number of ReadSharedReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.inst 618924 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 1778645 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 381212 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 197718 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 2976499 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 618924 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 1778645 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 381212 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 197718 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 2976499 # number of overall (read+write) accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.962844 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 0.790258 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.882002 # miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.969472 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.988424 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::total 0.978587 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.505323 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.163568 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.426396 # miss rate for ReadExReq accesses +system.l2c.ReadSharedReq_accesses::total 1683380 # number of ReadSharedReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0.inst 618918 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 1778680 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 381188 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 197717 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 2976503 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 618918 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 1778680 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 381188 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 197717 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 2976503 # number of overall (read+write) accesses +system.l2c.UpgradeReq_miss_rate::cpu0.data 0.958320 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1.data 0.780443 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.874957 # miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.963606 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.975067 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::total 0.969125 # miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 0.505316 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 0.163526 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.426381 # miss rate for ReadExReq accesses system.l2c.ReadCleanReq_miss_rate::cpu0.inst 0.019143 # miss rate for ReadCleanReq accesses -system.l2c.ReadCleanReq_miss_rate::cpu1.inst 0.004344 # miss rate for ReadCleanReq accesses -system.l2c.ReadCleanReq_miss_rate::total 0.013502 # miss rate for ReadCleanReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.596548 # miss rate for ReadSharedReq accesses +system.l2c.ReadCleanReq_miss_rate::cpu1.inst 0.004350 # miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_miss_rate::total 0.013505 # miss rate for ReadCleanReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.596533 # miss rate for ReadSharedReq accesses system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.007959 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::total 0.551076 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::total 0.551064 # miss rate for ReadSharedReq accesses system.l2c.demand_miss_rate::cpu0.inst 0.019143 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.584990 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.004344 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.061219 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.358171 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.584976 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.004350 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.061204 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.358170 # miss rate for demand accesses system.l2c.overall_miss_rate::cpu0.inst 0.019143 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.584990 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.004344 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.061219 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.358171 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.584976 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.004350 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.061204 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.358170 # miss rate for overall accesses system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -877,91 +877,91 @@ system.l2c.avg_blocked_cycles::no_mshrs nan # av system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 80921 # number of writebacks -system.l2c.writebacks::total 80921 # number of writebacks +system.l2c.writebacks::writebacks 80923 # number of writebacks +system.l2c.writebacks::total 80923 # number of writebacks system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate system.membus.trans_dist::ReadReq 7449 # Transaction distribution -system.membus.trans_dist::ReadResp 948782 # Transaction distribution +system.membus.trans_dist::ReadResp 948784 # Transaction distribution system.membus.trans_dist::WriteReq 14588 # Transaction distribution system.membus.trans_dist::WriteResp 14588 # Transaction distribution -system.membus.trans_dist::WritebackDirty 122441 # Transaction distribution -system.membus.trans_dist::CleanEvict 917844 # Transaction distribution -system.membus.trans_dist::UpgradeReq 19642 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 14180 # Transaction distribution -system.membus.trans_dist::UpgradeResp 8186 # Transaction distribution -system.membus.trans_dist::ReadExReq 126447 # Transaction distribution +system.membus.trans_dist::WritebackDirty 122443 # Transaction distribution +system.membus.trans_dist::CleanEvict 918012 # Transaction distribution +system.membus.trans_dist::UpgradeReq 19594 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 14154 # Transaction distribution +system.membus.trans_dist::UpgradeResp 8111 # Transaction distribution +system.membus.trans_dist::ReadExReq 125245 # Transaction distribution system.membus.trans_dist::ReadExResp 124222 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 941333 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 941335 # Transaction distribution system.membus.trans_dist::InvalidateReq 41552 # Transaction distribution system.membus.trans_dist::InvalidateResp 41552 # Transaction distribution system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 44074 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 3173737 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 3217811 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124995 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 124995 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 3342806 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 3172394 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 3216468 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 125161 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 125161 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 3341629 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 86162 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 73363008 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 73449170 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 73363264 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 73449426 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2668736 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 2668736 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 76117906 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 76118162 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 2205642 # Request fanout histogram +system.membus.snoop_fanout::samples 2204372 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 2205642 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 2204372 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 2205642 # Request fanout histogram -system.toL2Bus.snoop_filter.tot_requests 6035921 # Total number of requests made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_requests 3018741 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_requests 376832 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_fanout::total 2204372 # Request fanout histogram +system.toL2Bus.snoop_filter.tot_requests 6035855 # Total number of requests made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_requests 3018704 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_requests 374458 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.toL2Bus.snoop_filter.tot_snoops 1611 # Total number of snoops made to the snoop filter. system.toL2Bus.snoop_filter.hit_single_snoops 1521 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.toL2Bus.snoop_filter.hit_multi_snoops 90 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.toL2Bus.trans_dist::ReadReq 7449 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2732182 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2732156 # Transaction distribution system.toL2Bus.trans_dist::WriteReq 14588 # Transaction distribution system.toL2Bus.trans_dist::WriteResp 14588 # Transaction distribution -system.toL2Bus.trans_dist::WritebackDirty 777519 # Transaction distribution -system.toL2Bus.trans_dist::WritebackClean 719211 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 1143412 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 19614 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 14230 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 33844 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 295246 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 295246 # Transaction distribution -system.toL2Bus.trans_dist::ReadCleanReq 1000157 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 1724576 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1705094 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 5410979 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 1014431 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 661358 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 8791862 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 69513536 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 155758011 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 40526016 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 23357975 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 289155538 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 1083512 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 7141306 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 0.106198 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.308338 # Request fanout histogram +system.toL2Bus.trans_dist::WritebackDirty 777663 # Transaction distribution +system.toL2Bus.trans_dist::WritebackClean 998939 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 1205465 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 19613 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 14226 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 33839 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 295242 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 295242 # Transaction distribution +system.toL2Bus.trans_dist::ReadCleanReq 1000127 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 1724580 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1856170 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 5450139 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 1143023 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 684385 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 9133717 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 79182784 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 155766779 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 48757440 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 23358423 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 307065426 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 1083516 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 7141244 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 0.105534 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.307488 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 6383457 89.39% 89.39% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 757309 10.60% 99.99% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 6388144 89.45% 89.45% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 752560 10.54% 99.99% # Request fanout histogram system.toL2Bus.snoop_fanout::2 538 0.01% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::3 2 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 7141306 # Request fanout histogram +system.toL2Bus.snoop_fanout::total 7141244 # Request fanout histogram system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA |